Semiconductor structure, manufacturing method of semiconductor structure and image sensor

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method of the semiconductor structure and an image sensor. The semiconductor structure comprises a substrate; the first doped region and the second doped region are formed in the substrate; wherein the first doped region is used for forming a photodiode; the second doped region is used as a floating diffusion region; the transmission grid electrode is used for forming an electron transmission path between the first doped region and the second doped region; wherein the transmission grid electrode comprises a plurality of grid electrode extension parts which are arranged at intervals; the gate extension portion extends from the second doped region to the first doped region. According to the embodiment of the invention, an electron transmission path between the photodiode and the floating diffusion region is increased, the electron transmission rate between the photodiode and the floating diffusion region is accelerated, and the overall performance of the image sensor is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a semiconductor structure, a method for manufacturing a semiconductor structure, and an image sensor. Background Art

[0002] CIS (Complementary Metal Oxide Semiconductor Image Sensor) has been widely used in many fields such as consumer electronics, security monitoring, assisted driving, medical equipment, etc. due to its advantages of low power consumption, high performance, and easy integration. The core of CIS is the pixel array, and the performance of each pixel will directly affect the overall imaging quality and resolution of CIS.

[0003] At present, a single pixel mainly includes a photodiode (PD), a floating diffusion (FD), and a transfer gate (TG). The photodiode is used to capture photons and generate and store electrons, the floating diffusion is used to detect and temporarily store electrons transferred from the photodiode, and the transfer gate is used to control the transfer process of electrons between the photodiode and the floating diffusion.

[0004] As the application scenarios of CIS continue to expand, some scenarios that require high frame rates and fast responses, such as high-definition video recording or high-speed photography, require higher sensitivity and response speed of CIS. In order to output images sensitively and quickly, a faster electron transfer rate is required between the photodiode and the floating diffusion area in each pixel of the CIS. However, in the existing pixel structure, the electron transfer rate between the photodiode and the floating diffusion area is slow. Summary of the invention

[0005] In view of this, multiple embodiments of the present application provide a semiconductor structure, a method for manufacturing the semiconductor structure, and an image sensor to accelerate the electron transfer rate between a photodiode and a floating diffusion region.

[0006] In one aspect, an embodiment of the present application provides a semiconductor structure, comprising: a substrate; a first doped region and a second doped region formed in the substrate; wherein the first doped region is used to form a photodiode; the second doped region is used as a floating diffusion region; a transmission gate; the transmission gate is used to form an electron transmission path between the first doped region and the second doped region; wherein the transmission gate includes a plurality of gate extensions arranged at intervals; the gate extension extends from the second doped region to the first doped region.

[0007] Optionally, the first doping region and the second doping region are distributed in a direction away from the surface of the substrate, and the projections of the first doping region and the second doping region on the surface of the substrate at least partially overlap; the gate extension portion extends from the surface of the substrate through the second doping region to the first doping region.

[0008] Optionally, the transmission gate further includes a gate connecting portion for connecting a plurality of the gate extension portions; wherein the gate connecting portion is formed on the surface of the substrate.

[0009] Optionally, the semiconductor structure also includes: a doped well region formed between the first doped region and the second doped region; wherein a projection of the doped well region on the surface of the substrate at least partially overlaps with a projection of the first doped region on the surface of the substrate, and a projection of the doped well region on the surface of the substrate at least partially overlaps with a projection of the second doped region on the surface of the substrate.

[0010] Optionally, the doping type of the first doping region and the second doping region is the first doping type; the doping type of the doping well region is the second doping type; the first doping type is different from the second doping type; the doping concentration of the second doping region is greater than the doping concentration of the doping well region, and the doping concentration of the second doping region is greater than the doping concentration of the first doping region.

[0011] Optionally, the first doping type is N-type, and the second doping type is P-type.

[0012] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method for manufacturing the semiconductor structure comprising: providing a substrate; forming a first doped region and a second doped region in the substrate to obtain a transition substrate; wherein the first doped region is used to form a photodiode; the second doped region is used as a floating diffusion region; forming a transfer gate on the transition substrate to obtain the semiconductor structure; the transfer gate is used to form an electron transfer path between the first doped region and the second doped region; wherein the transfer gate comprises a plurality of gate extensions arranged at intervals; the gate extension extends from the second doped region to the first doped region.

[0013] Optionally, the first doping region and the second doping region are distributed in a direction away from the surface of the substrate; the semiconductor structure also includes a doped well region formed between the first doping region and the second doping region; wherein the doped well region is used to isolate the first doping region and the second doping region; the step of forming the first doping region and the second doping region in the substrate to obtain a transition substrate comprises: performing a first ion implantation into the substrate to form the first doping region in the substrate; performing a second ion implantation into the substrate to form the doped well region in the substrate; wherein the distance between the doped well region and the surface of the substrate is less than the distance between the first doping region and the surface of the substrate, and the projections of the doped well region and the first doping region on the surface of the substrate at least partially overlap; performing a third ion implantation into the substrate to form the second doping region in the substrate to obtain a transition substrate; wherein the distance between the second doping region and the surface of the substrate is less than the distance between the doped well region and the surface of the substrate, and the projections of the second doping region and the doped well region on the surface of the substrate at least partially overlap.

[0014] Optionally, the doping type of the first doping region and the second doping region is the first doping type; the doping type of the doping well region is the second doping type; the first doping type is different from the second doping type; the doping concentration of the second doping region is greater than the doping concentration of the doping well region, and the doping concentration of the second doping region is greater than the doping concentration of the first doping region.

[0015] Optionally, the step of forming a transmission gate on the transition substrate to obtain the semiconductor structure includes: forming a plurality of spaced-apart gate trenches on the transition substrate; wherein the gate trenches extend from the surface of the transition substrate through the second doping region to the first doping region; growing a gate oxide layer on the surface of the gate trenches to obtain a transition gate trench; filling the transition gate trenches with a gate filling material to form a transmission gate to obtain the semiconductor structure; wherein the transmission gate is used to form an electron transmission path between the first doping region and the second doping region; the transmission gate includes a plurality of spaced-apart gate extensions and a gate connecting portion for connecting the plurality of gate extensions; the gate connecting portion is formed on the surface of the transition substrate.

[0016] In another aspect, an embodiment of the present application provides an image sensor, which includes the semiconductor structure described in the above embodiment or a semiconductor structure manufactured according to the method for manufacturing the semiconductor structure described in the above embodiment.

[0017] In multiple embodiments of the present application, a first doped region and a second doped region distributed in a direction away from the surface of the substrate are formed in a substrate, wherein the first doped region is used to form a photodiode and the second doped region is used to serve as a floating diffusion region, and then a transmission gate including a plurality of spaced-apart gate extensions is formed, wherein the gate extension extends from the second doped region to the first doped region, and unexpected effects are achieved including: an electron transmission path between the photodiode and the floating diffusion region can be formed based on one gate extension, and the electron transmission path between the photodiode and the floating diffusion region is increased by providing a plurality of gate extensions, thereby accelerating the electron transmission rate between the photodiode and the floating diffusion region. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of an existing pixel structure provided for related technology.

[0020] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided for one embodiment of the present application.

[0021] Figure 3 A schematic diagram of forming an isolation trench and an active area on a substrate is provided for one embodiment of the present application.

[0022] Figure 4 A schematic diagram of forming a trench isolation layer on the surface of an isolation trench is provided for one embodiment of the present application.

[0023] Figure 5 A schematic diagram of a substrate provided for one embodiment of the present application.

[0024] Figure 6 A schematic diagram of a process for obtaining a transition substrate is provided for one embodiment of the present application.

[0025] Figure 7 A schematic diagram of forming a first doped region is provided for one embodiment of the present application.

[0026] Figure 8 A schematic diagram of forming a doped well region is provided for one embodiment of the present application.

[0027] Fig. 9 A schematic diagram of forming a second doping region is provided for one embodiment of the present application.

[0028] Fig.10 A schematic diagram of a transition substrate provided for one embodiment of the present application.

[0029] Fig.11 For Figure 1 Schematic diagram of an improved pixel structure obtained by improving the existing pixel structure in .

[0030] Fig.12 A schematic diagram of a process for forming a transmission gate on a transition substrate is provided for one embodiment of the present application.

[0031] Fig.13 A schematic diagram of forming a plurality of spaced-apart gate trenches on a transition substrate is provided for one embodiment of the present application.

[0032] Fig.14 A schematic diagram of forming a gate oxide layer on the surface of a gate trench is provided for one embodiment of the present application.

[0033] Fig.15 A schematic diagram of a transmission gate provided for one embodiment of the present application.

[0034] Fig.16 A schematic diagram of a semiconductor structure provided for one embodiment of the present application.

[0035] Structure number description 100, existing pixel structure; 110, substrate; 120, isolation structure; 121, trench isolation structure; 122, isolation layer; 130, photodiode; 140, gate of transfer transistor; 150, floating diffusion region; 160, oxide layer; 200, improved pixel structure; 110a, improved substrate; 120a, improved isolation structure; 121a, trench filling structure; 122a, trench isolation layer; 130a, photodiode doping region; 140a, improved transfer transistor gate ...150, improved pixel structure; 110a, improved substrate; 120a, improved isolation structure; 121a, trench filling structure; 122a, trench isolation layer; 130a, photodiode doping region; 140a, improved transfer transistor gate; 150, floating diffusion region; 140a, improved transfer transistor gate; 150, floating diffusion region; 140a, improved transfer transistor gate; 150, floating diffusion region; 140a, improved transfer transistor gate; 150, floating diffusion region; 140a, improved transfer transistor gate; 150a, floating diffusion region; 140a 0a, floating diffusion region doping region; 160a, protective layer; 300, substrate; 210, isolation trench; 220, trench isolation layer; 230, shallow trench isolation structure; 240, photoresist layer; 250, first doping region; 260, doped well region; 270, second doping region; 400, transition substrate; 310, gate trench; 320, gate oxide layer; 330, transition gate trench; 340, transfer gate; 341, gate extension; 342, gate connection; 500, semiconductor structure. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0037] The drawings provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complicated.

[0038] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0039] To adapt to the trend of thinner and lighter equipment and miniaturized devices, the size requirements of CIS are constantly shrinking. At the same time, to meet the image quality requirements of more application scenarios, the performance requirements of CIS are constantly increasing. However, the size and performance of CIS manufactured based on the existing pixel structure are difficult to meet the size and performance requirements of current CIS. The specific reasons are analyzed as follows: See also Figure 1 . In the existing pixel structure 100 provided by the related art, the photodiode 130, the floating diffusion region 150 and the isolation structure 120 are formed in the substrate 110, the gate 140 of the transfer transistor is formed on the surface of the substrate 110, and an oxide layer 160 is formed on the surface of the substrate 110 and the surface of the gate 140 of the transfer transistor. Specifically, the isolation structure 120 may include a trench isolation structure 121 and an isolation layer 122. Among them, the trench isolation structure 121 can be used to isolate different pixels, and the isolation layer 122 can be used to isolate the photodiode 130 and the oxide layer 160 on the surface of the substrate 110, and at the same time to isolate the photodiode 130 and the trench isolation structure 121, so as to reduce pixel defects and reduce dark current. The photodiode 130 and the floating diffusion region 150 are respectively formed at positions corresponding to the two sides of the gate 140 of the transfer transistor.

[0040] Depend on Figure 1It can be seen that in order to increase the photosensitive area, in the existing pixel structure 100, the photodiode 130 and the floating diffusion region 150 are distributed in the horizontal direction in the substrate 110, so that the size of a single pixel is larger, resulting in a smaller number of pixels that can be accommodated on a given sensor area, and a lower resolution of the CIS. At the same time, a larger pixel size may further cause problems such as lower sensor space utilization, increased crosstalk between pixels, and increased dark current in the pixel, resulting in a decrease in the overall performance of the CIS manufactured based on larger-sized pixels.

[0041] Therefore, it is necessary to provide a semiconductor structure and a manufacturing method thereof, by forming a first doped region for forming a photodiode and a second doped region for serving as a floating diffusion region in a substrate, and then forming a transmission gate comprising a plurality of gate extensions arranged at intervals, wherein the gate extension extends to the first doped region through the second doped region, and each gate extension is used as an electron transmission path between the photodiode and the floating diffusion region, thereby increasing the number of electron transmission paths between the photodiode and the floating diffusion region, accelerating the electron transmission rate between the photodiode and the floating diffusion region, and improving the overall performance of the CIS.

[0042] See also Figure 2 An embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure may include steps S110, S120, and S130.

[0043] S110: providing a substrate.

[0044] See also Figure 3 . In this embodiment, the substrate 110 can serve as the basis for the formation of a semiconductor structure. Specifically, the substrate 110 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. For example, the substrate 110 can be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), and silicon carbide (SiC). The substrate 110 can be a single-layer structure or a multi-layer structure. In this embodiment, considering factors such as dielectric loss requirements, manufacturing process, and manufacturing cost, a silicon wafer doped with P-type ions prepared by an epitaxy process is used as the substrate 110 to reduce the resistance of the substrate 110.

[0045] In this embodiment, an isolation trench 210 and an active area may be formed on the substrate 110. Specifically, the positions of a plurality of isolation trenches 210 may be defined in the substrate 110, and the substrate material at these positions may be etched away to form a plurality of isolation trenches 210 spaced apart from each other. After the plurality of isolation trenches 210 are formed, ion implantation may be performed in the spaced regions between the plurality of isolation trenches 210 to form an active area (Active Area, AA).

[0046] See also Figure 4 . In the present embodiment, after the isolation trench and the active area are formed, a trench isolation layer 220 may be formed on the surface of the isolation trench by ion implantation. Specifically, each isolation trench may have a bottom surface and two opposite side surfaces. Doping ions may be implanted into the bottom surface and two side surfaces of each isolation trench, thereby forming a trench isolation layer 220 on the bottom surface and two side surfaces of each isolation trench. Specifically, the doping type of the trench isolation layer 220 may be different from the doping type of the first doping region. For example, when the doping type of the first doping region is N-type, the doping type of the trench isolation layer 220 may be P-type, and the doping ions may be boron (B) ions or gallium (Ga) ions. In subsequent processes, the trench isolation layer 220 may be used to achieve isolation between a shallow trench isolation (STI) structure and the first doping region.

[0047] See also Figure 5 In this embodiment, after the trench isolation layer 220 is formed, an isolation material may be filled into the isolation trench whose surface is covered with the trench isolation layer 220 to form a shallow trench isolation structure 230, thereby obtaining a substrate 300. Specifically, the shallow trench isolation structure 230 may be used to achieve isolation between different pixels. The isolation material may be an oxide.

[0048] S120: forming a first doping region and a second doping region in the substrate to obtain a transition substrate.

[0049] In this embodiment, the first doped region can be used to form a photodiode, and the second doped region can be used as a floating diffusion region to detect electrons generated by the photodiode and read corresponding signals.

[0050] In order to allow the electrons between the first doping region and the second doping region to be transmitted only through the transmission gate after the transmission gate is formed, in this embodiment, in addition to the first doping region and the second doping region, a doped well region for isolating the first doping region and the second doping region is formed between the first doping region and the second doping region in the substrate. Specifically, the doping types of the first doping region and the second doping region are both the first doping type, and the doping types of the two are the same, and the doping type of the doped well region is the second doping type, and the first doping type is different from the second doping type, that is, the doped well region is different from the doping type of the first doping region and the second doping region. For example, the first doping region and the second doping region can both be N-type doped, and correspondingly, the doped well region is P-type doped. Alternatively, the first doping region and the second doping region can both be P-type doped, and correspondingly, the doped well region is N-type doped.

[0051] See also Figure 6In this embodiment, forming the first doping region and the second doping region in the substrate to obtain the transition substrate may include steps S121, S122 and S123.

[0052] S121: performing a first ion implantation into the substrate to form a first doped region in the substrate.

[0053] Depend on Figure 1 It can be seen that in the related art, in order to isolate the photodiode 130 from the oxide layer 160 on the surface of the substrate 110, an isolation layer 122 needs to be formed between the photodiode 130 and the oxide layer 160. In order to reduce process complexity and process cost, the first doped region can be formed in the substrate at a position far away from the substrate surface, thereby reducing the contact between the first doped region and the oxide layer on the substrate surface without the need for isolation using an isolation layer, thereby reducing dark current. In addition, since the first doped region is far away from the substrate surface, the damage to the first doped region in subsequent processes can be reduced, thereby protecting the first doped region.

[0054] See also Figure 7 In this embodiment, before performing the first ion implantation, a photoresist layer 240 may be formed on the substrate surface at a position corresponding to the shallow trench isolation structure 230. Specifically, the photoresist layer 240 may serve as a barrier layer to prevent ions from being implanted into the shallow trench isolation structure 230, thereby reducing the impact of subsequent ion implantation processes on the shallow trench isolation structure 230.

[0055] In this embodiment, the doping ions implanted by the first ion implantation may be N-type doping ions, such as phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions.

[0056] S122: performing a second ion implantation into the substrate to form a doped well region in the substrate.

[0057] In this embodiment, the doping ions implanted by the second ion implantation may be P-type doping ions, such as boron (B) ions, aluminum (Al) ions, gallium (Ga) ions, or indium (In) ions.

[0058] Since the doping concentration of the doped well region will have a direct impact on the electron transmission rate between the first doped region and the second doped region, that is, when the doping concentration of the doped well region is high, the PN junction barrier between the first doped region and the second doped region is high, and the electrons need to overcome a large energy barrier to move from the first doped region to the second doped region, resulting in a decrease in the electron transmission rate; when the doping concentration of the doped well region is low, the isolation effect between the first doped region and the second doped region may be weakened, resulting in an increase in crosstalk between adjacent pixels. Therefore, in order to control the doping concentration of the doped well region to be moderate so as to accelerate the electron transmission rate between the first doped region and the second doped region, in some embodiments, P-type doping ions may be evenly distributed in all the remaining areas of the substrate except the first doped region, the second doped region and the shallow trench isolation structure to form a doped well region.

[0059] In order to reduce the difficulty of controlling the doping concentration of the doped well region, reduce process costs, and improve the isolation effect between the first doped region and the second doped region, in this embodiment, the doped well region can be a regular doped region with clear edges.

[0060] See also Figure 8 Since the first doping region 250 and the second doping region are distributed in a direction away from the substrate surface, and the doping well region 260 needs to be located between the first doping region 250 and the second doping region, in this embodiment, the distance between the doping well region 260 and the surface of the substrate is smaller than the distance between the first doping region 250 and the surface of the substrate, and the projections of the doping well region 260 and the first doping region 250 on the surface of the substrate at least partially overlap. Specifically, the projections of the doping well region 260 and the first doping region 250 on the surface of the substrate may partially overlap or completely overlap.

[0061] S123: performing a third ion implantation into the substrate to form a second doping region in the substrate to obtain a transition substrate.

[0062] See also Fig. 9 . In this embodiment, after the first doping region 250 and the doping well region 260 are formed, a third ion implantation may be performed into the substrate to form a second doping region 270. The doping ions implanted by the third ion implantation may be N-type doping ions, such as phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions. Specifically, the N-type doping ions implanted by the third ion implantation may be the same as or different from the N-type doping ions implanted by the first ion implantation. This application does not impose any specific restrictions on this.

[0063] To improve signal readout efficiency and signal transmission speed, in this embodiment, the distance between the second doping region 270 and the surface of the substrate is smaller than the distance between the doped well region 260 and the surface of the substrate. Specifically, the edge of the second doping region 270 may be close to the surface of the substrate.

[0064] In order to realize electron transmission between the first doping region 250 and the second doping region 270, in this embodiment, the projections of the second doping region 270 and the doping well region 260 on the surface of the substrate at least partially overlap, and the projections of the second doping region 270 and the first doping region 250 on the surface of the substrate at least partially overlap, that is, the projections of the second doping region 270, the doping well region 260 and the first doping region 250 on the surface of the substrate at least partially overlap. Specifically, the projections of the second doping region 270, the doping well region 260 and the first doping region 250 on the surface of the substrate may partially overlap or completely overlap.

[0065] In order to reduce the resistance of the floating diffusion region, increase the charge capacity of the floating diffusion region, and enhance the signal reading capability, in this embodiment, the doping concentration of the second doping region 270 can be greater than the doping concentration of the doping well region 260, and the doping concentration of the second doping region 270 can be greater than the doping concentration of the first doping region 250.

[0066] In order to enhance light absorption efficiency, reduce light leakage, and improve the dynamic range of CIS, in this embodiment, the direction away from the substrate surface is used as the thickness direction of each doping region. Along this thickness direction, the thickness of the first doping region 250 is greater than the thickness of the doped well region 260, and the thickness of the first doping region 250 is greater than the thickness of the second doping region 270.

[0067] See also Fig.10 In this embodiment, after the second doping region 270 is formed, the photoresist layer on the surface of the substrate can be removed to obtain the transition substrate 400 .

[0068] S130: forming a transmission gate on the transition substrate to obtain a semiconductor structure.

[0069] See also Fig.11 In order to make CIS meet increasingly stringent size and performance requirements, in some embodiments, researchers have improved the existing pixel structure to form an improved pixel structure 200. In the improved pixel structure 200, the photodiode doping region 130a and the floating diffusion doping region 150a are distributed in the improved substrate 110a along the vertical direction, and the improved transfer transistor gate 140a is formed between the photodiode doping region 130a and the floating diffusion doping region 150a to control electrons to move from the photodiode doping region 130a to the floating diffusion doping region 150a along the vertical direction.

[0070] contrast Figure 1 and Fig.11 It can be seen that, compared with the existing pixel structure 100, the improved pixel structure 200 reduces the size of a single pixel, thereby increasing the number of pixels that can be accommodated in a given sensor area and improving the resolution of the CIS.

[0071] However, after applying the CIS manufactured based on the improved pixel structure to actual devices, the researchers found that for some scenarios with high requirements on the sensitivity and response speed of the CIS, such as night vision and low-light monitoring, high-speed photography, medical imaging, etc., the performance of the CIS manufactured based on the improved pixel structure is still difficult to meet the requirements.

[0072] Please continue reading Fig.11 Further investigation of the reasons why the performance of the CIS manufactured based on the improved pixel structure is not high shows that in the improved pixel structure 200, the principle of electron transmission between the photodiode doping region 130a and the floating diffusion doping region 150a is as follows: during the exposure process, the improved transfer transistor gate 140a is closed, and the photoelectric conversion is completed in the photodiode doping region 130a to generate electrons for transmitting signals; after the exposure is completed, the improved transfer transistor gate 140a is opened, and an electron transmission path is formed between the photodiode doping region 130a and the floating diffusion doping region 150a with the help of the improved transfer transistor gate 140a, and the improved transfer transistor gate 140a controls the electrons to move from the photodiode doping region 130a to the floating diffusion doping region 150a through the electron transmission path. However, in the improved pixel structure 200, since only one electron transmission path is formed between the photodiode doping region 130a and the floating diffusion doping region 150a, all electrons generated by the photodiode doping region 130a need to be transmitted to the floating diffusion doping region 150a through this electron transmission path. Therefore, the electron transmission rate between the photodiode doping region 130a and the floating diffusion doping region 150a is slow, resulting in a lower sensitivity and a slower response speed of the CIS manufactured based on the improved pixel structure 200.

[0073] Therefore, in order to increase the electron transmission path between the first doping region and the second doping region and speed up the electron transmission rate between the first doping region and the second doping region, in this embodiment, the transmission gate may include a plurality of gate extensions arranged at intervals. Among them, the gate extension may extend from the surface of the substrate through the second doping region to the first doping region. Specifically, the projection of the gate extension on the substrate surface may be located in the overlapping area of ​​the projection of the first doping region, the doped well region and the second doping region on the substrate surface, so that an electron transmission path between the first doping region and the second doping region may be formed with the help of each gate extension.

[0074] See also Fig.12 In this embodiment, forming a transmission gate on a transition substrate to obtain a semiconductor structure may include steps S131, S132, and S133.

[0075] S131: forming a plurality of spaced-apart gate trenches on a transition substrate.

[0076] See also Fig.13 . In order to improve the signal control effect, in the present embodiment, a plurality of spaced gate trenches 310 may be etched by dry etching process in the overlapping areas of the projections of the first doping region 250, the doping well region 260 and the second doping region 270 on the substrate surface, and the gate trenches 310 may extend from the surface of the transition substrate through the second doping region 270 to the first doping region 250. Specifically, the extension direction of the gate trench 310 may be used as the depth direction of the gate trench 310. The depth of the gate trench 310 extending into the first doping region 250 along the depth direction may be determined according to the thickness of the first doping region 250 along the thickness direction and the process requirements for signal transmission. The dry etching process parameters used for etching the gate trench 310 are etching process parameters commonly used in related technologies and will not be described in detail here.

[0077] In order to match the size of the pixel and increase the number of image sensors that can be accommodated per unit area, in this embodiment, the number of gate grooves 310 may fall within the range of 2 to 4. Specifically, the number of gate grooves 310 may be determined according to the design size of a single pixel. For example, when the design size of a single pixel is medium, the number of gate grooves 310 may be 3. When the design size of a single pixel is large, the number of gate grooves 310 may be 4 to further accelerate the electron transmission rate between the first doping region 250 and the second doping region 270. When the design size of a single pixel is small, the number of gate grooves 310 may be 2, so that the electron transmission rate between the first doping region 250 and the second doping region 270 can be accelerated while saving the pixel area.

[0078] In order to make the potential distribution inside the semiconductor structure uniform, and at the same time, to reduce the crosstalk between different electron transmission paths, and to improve the effect of electron transmission between the first doping region 250 and the second doping region 270, in this embodiment, the spacing distance between any two adjacent gate trenches 310 can fall within the range of 100nm to 300nm. For example, the spacing distance between any two adjacent gate trenches 310 can be 100nm, 150nm, 200nm, 250nm or 300nm.

[0079] S132: growing a gate oxide layer on the surface of the gate trench to obtain a transition gate trench.

[0080] See also Fig.14 In this embodiment, after etching the gate trench, a gate oxide layer 320 may be grown on the surface of the gate trench. The gate oxide layer 320 may be used to prevent direct electrical contact between the transmission gate and each doped region, and may also be used to form an electric field to control electron transmission.

[0081] S133: Filling the transition gate trench with a gate filling material to form a transmission gate, thereby obtaining a semiconductor structure.

[0082] See also Fig.15 . In this embodiment, the transmission gate 340 may include a gate connection portion 342 and a plurality of spaced-apart gate extension portions 341. Among them, the gate extension portion 341 may be used to control the electron transmission between the first doping region and the second doping region. Specifically, each gate extension portion 341 controls the conduction between the first doping region and the second doping region to form a channel, and the electrons generated by the first doping region for transmitting signals are transmitted to the second doping region through the channel. Therefore, the number of electron transmission paths between the first doping region and the second doping region is equal to the number of gate extension portions 341. The gate connection portion 342 may be used to connect multiple gate extension portions 341. Specifically, the gate connection portion 342 may be formed on the surface of the transition substrate. The gate connection portion 342 may have a first surface close to the surface of the transition substrate and a second surface away from the surface of the transition substrate. Among them, the first surface may be connected to the plurality of gate extension portions 341, and the second surface may be connected to the electrode, so the plurality of gate extension portions 341 may be connected to the same electrode through the gate connection portion 342, that is, the potentials of the voltage signals connected to the plurality of gate extension portions 341 are equal.

[0083] In this embodiment, the gate filling material may be polysilicon (Poly). Specifically, polysilicon may be filled into the transition gate trench until the transition gate trench is full and a polysilicon layer having a certain thickness is formed on the surface of the transition substrate. Subsequently, the polysilicon layer on the surface of the transition substrate may be planarized, and then the planarized polysilicon layer may be etched to retain portions that match the dimensions of the multiple transition gate trenches and remove the remaining portions to obtain the transmission gate 340. The polysilicon located in the transition gate trench forms a gate extension portion 341, and the polysilicon located on the surface of the transition substrate forms a gate connection portion 342.

[0084] See also Fig.16 An embodiment of the present application provides a semiconductor structure 500 , which may include a substrate, a first doping region 250 and a second doping region 270 formed in the substrate, and a transmission gate 340 .

[0085] In this embodiment, the first doping region 250 can be used to form a photodiode, and the second doping region 270 can be used as a floating diffusion region. To reduce the size of a single pixel, the first doping region 250 and the second doping region 270 are distributed in a direction away from the surface of the substrate, and the projections of the first doping region 250 and the second doping region 270 on the surface of the substrate at least partially overlap.

[0086] In order to increase the electron transmission path between the first doping region 250 and the second doping region 270, speed up the electron transmission rate between the first doping region 250 and the second doping region 270, and improve the sensitivity and response speed of the CIS, in this embodiment, the transmission gate 340 may include a plurality of gate extensions arranged at intervals. The gate extensions may extend from the surface of the substrate through the second doping region 270 to the first doping region 250.

[0087] In order to control the potential of the voltage signals connected to the multiple gate extensions to be equal and improve the control effect of the multiple gate extensions, in this embodiment, the transmission gate 340 may also include a gate connection portion for connecting the multiple gate extensions. The gate connection portion may be formed on the surface of the substrate.

[0088] In order to save pixel area and speed up the electron transmission rate between the first doping region 250 and the second doping region 270 when the size of a single pixel is small, in this embodiment, the number of the gate extensions may fall within the range of 2 to 4. For example, the number of the gate extensions may be 2, 3, or 4.

[0089] In order to optimize the potential distribution within a single pixel and reduce the interference between different electron transmission paths, in this embodiment, the spacing distance between any two adjacent gate extensions can fall within the range of 100nm to 300nm. For example, the spacing distance between any two adjacent gate extensions can be 100nm, 150nm, 200nm, 250nm or 300nm.

[0090] In order to improve the electron transmission effect between the first doping region 250 and the second doping region 270, in the present embodiment, the semiconductor structure 500 may further include a doped well region 260 formed between the first doping region 250 and the second doping region 270. Specifically, the projection of the doped well region 260 on the surface of the substrate at least partially overlaps with the projection of the first doping region 250 on the surface of the substrate, and the projection of the doped well region 260 on the surface of the substrate at least partially overlaps with the projection of the second doping region 270 on the surface of the substrate. The doping type of the doped well region 260 is different from the doping type of the first doping region 250 and the second doping region 270. Specifically, the doping type of the first doping region 250 and the second doping region 270 may be N-type, and the doping type of the doped well region 260 may be P-type.

[0091] In an embodiment of the present application, a first doped region for forming a photodiode and a second doped region for serving as a floating diffusion region are formed in a substrate, and the first doped region and the second doped region are distributed in a direction away from the substrate surface, and their projections on the substrate surface at least partially overlap, and then a transmission gate including a plurality of spaced-apart gate extensions is formed, wherein the gate extension extends from the substrate surface through the second doped region to the first doped region, and the unexpected effects achieved include: an electron transmission path between a photodiode and a floating diffusion region can be formed based on one gate extension, and the electron transmission path between the photodiode and the floating diffusion region is increased by setting a plurality of gate extensions, thereby accelerating the electron transmission rate between the photodiode and the floating diffusion region when the size of a single pixel is small, thereby improving the overall performance of the CIS manufactured based on the semiconductor structure.

[0092] Still another embodiment of the present application provides an image sensor, which may include the semiconductor structure described in the above embodiment, or may include a semiconductor structure manufactured by the method for manufacturing the semiconductor structure described in the above embodiment.

[0093] Regarding the technical effects of the image sensor described in the above embodiment, reference can be made to other embodiments of the present application for comparative explanation and no further details will be given here.

[0094] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0095] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0096] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0097] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are the same as the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include majority forms, unless the context clearly indicates other meanings.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed semiconductor structure and image sensor can be implemented in other ways. For example, the embodiments of the semiconductor structure and image sensor described above are merely illustrative.

[0099] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A first doped region and a second doped region are formed in the substrate; wherein the first doped region is used to form a photodiode; and the second doped region is used as a floating diffusion region; A transmission gate; the transmission gate is used to form an electron transmission path between the first doping region and the second doping region; wherein the transmission gate includes a plurality of gate extensions arranged at intervals; the gate extensions extend from the second doping region to the first doping region.

2. The semiconductor structure according to claim 1, characterized in that: The first doping region and the second doping region are distributed in a direction away from the surface of the substrate, and projections of the first doping region and the second doping region on the surface of the substrate at least partially overlap; The gate extension portion extends from the surface of the substrate through the second doping region to the first doping region.

3. The semiconductor structure according to claim 1, characterized in that: The transmission gate further includes a gate connection portion for connecting a plurality of the gate extension portions; wherein the gate connection portion is formed on a surface of the substrate.

4. The semiconductor structure according to claim 1, characterized in that: Also includes: A doped well region formed between the first doped region and the second doped region; wherein the doped well region is used to isolate the first doped region and the second doped region; The projection of the doped well region on the surface of the substrate at least partially overlaps with the projection of the first doped region on the surface of the substrate, and the projection of the doped well region on the surface of the substrate at least partially overlaps with the projection of the second doped region on the surface of the substrate.

5. The semiconductor structure according to claim 4, characterized in that: The doping types of the first doping region and the second doping region are the first doping type; the doping type of the doping well region is the second doping type; the first doping type is different from the second doping type; the doping concentration of the second doping region is greater than the doping concentration of the doping well region, and the doping concentration of the second doping region is greater than the doping concentration of the first doping region.

6. The semiconductor structure according to claim 5, characterized in that: The first doping type is N-type, and the second doping type is P-type.

7. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: providing a substrate; A first doping region and a second doping region are formed in the substrate to obtain a transition substrate; wherein the first doping region is used to form a photodiode; and the second doping region is used as a floating diffusion region; A transmission gate is formed on the transition substrate to obtain the semiconductor structure; the transmission gate is used to form an electron transmission path between the first doping region and the second doping region; wherein the transmission gate includes a plurality of gate extensions arranged at intervals; the gate extensions extend from the second doping region to the first doping region.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The first doping region and the second doping region are distributed in a direction away from the surface of the substrate; the semiconductor structure further comprises a doped well region formed between the first doping region and the second doping region; wherein the doped well region is used to isolate the first doping region and the second doping region; the step of forming the first doping region and the second doping region in the substrate to obtain a transition substrate comprises: Performing a first ion implantation on the substrate to form the first doped region in the substrate; Performing a second ion implantation on the substrate to form the doped well region in the substrate; wherein the distance between the doped well region and the surface of the substrate is smaller than the distance between the first doped region and the surface of the substrate, and the projections of the doped well region and the first doped region on the surface of the substrate at least partially overlap; A third ion implantation is performed on the substrate to form the second doped region in the substrate to obtain a transition substrate; wherein the distance between the second doped region and the surface of the substrate is smaller than the distance between the doped well region and the surface of the substrate, and the projections of the second doped region and the doped well region on the surface of the substrate at least partially overlap.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The doping types of the first doping region and the second doping region are the first doping type; the doping type of the doping well region is the second doping type; the first doping type is different from the second doping type; the doping concentration of the second doping region is greater than the doping concentration of the doping well region, and the doping concentration of the second doping region is greater than the doping concentration of the first doping region.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The step of forming a transmission gate on the transition substrate to obtain the semiconductor structure includes: Forming a plurality of spaced-apart gate trenches on the transition substrate; wherein the gate trenches extend from the surface of the transition substrate through the second doping region to the first doping region; Growing a gate oxide layer on the surface of the gate trench to obtain a transition gate trench; The transition gate trench is filled with a gate filling material to form a transmission gate to obtain the semiconductor structure; wherein the transmission gate is used to form an electron transmission path between the first doping region and the second doping region; the transmission gate includes a plurality of spaced-apart gate extensions and a gate connection portion for connecting the plurality of gate extensions; the gate connection portion is formed on the surface of the transition substrate.

11. An image sensor, characterized in that: The image sensor comprises the semiconductor structure according to any one of claims 1 to 6 or a semiconductor structure manufactured according to the method for manufacturing the semiconductor structure according to any one of claims 7 to 10.

Images