Display device and method for manufacturing same

Abstract

A display device and a method of manufacturing the same are disclosed. The display device includes a planarization layer including a first planarization portion on a substrate, and a second planarization portion and a third planarization portion on the first planarization portion; a first pad electrode on the second planarization portion and a second pad electrode on the third planarization portion; an organic pattern layer on the first pad electrode and the second pad electrode; a light emitting element on the organic pattern layer; a partition wall; a reflective layer on a side surface of the partition wall and the first planarization portion; a first auxiliary connection electrode connecting the second semiconductor layer and the first pad electrode; and a second auxiliary connection electrode connecting the first semiconductor layer and the second pad electrode, and the planarization layer has an undercut shape.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0119576 filed in the Korean Intellectual Property Office on September 8, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0003] As multimedia develops, display devices are becoming more and more important. In response to this, various types of display devices such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs) are being used.

[0004] The device for displaying an image of the display device includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among them, the light-emitting display panel may include a light-emitting element. For example, a light-emitting diode (LED) includes an organic light-emitting diode using an organic material as a light-emitting material, an inorganic light-emitting diode using an inorganic material as a light-emitting material, and the like. Summary of the invention

[0005] According to aspects of an embodiment of the present disclosure, a display device and a manufacturing method for the display device are provided, in which the auxiliary connection electrode and the reflective layer can be electrically separated from each other by adopting an undercut structure, and in the manufacturing method for the display device, the auxiliary connection electrode and the reflective layer are formed by the same material layer in a single process.

[0006] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure provided below.

[0007] According to one or more embodiments, a display device includes: a planarization layer including a first planarization portion on a substrate and a second planarization portion and a third planarization portion on the first planarization portion; a first pad electrode and a second pad electrode, the first pad electrode being on the second planarization portion and the second pad electrode being on the third planarization portion; an organic pattern layer on the first pad electrode and the second pad electrode; a light emitting element on the organic pattern layer and including a first semiconductor layer, an active layer and a second semiconductor layer; a partition wall on a surface of the first planarization portion and defining a space around the light emitting element; a reflective layer on a side of the partition wall and the first planarization portion within the space; a first auxiliary connection electrode connecting the second semiconductor layer and the first pad electrode; and a second auxiliary connection electrode connecting the first semiconductor layer and the second pad electrode, and the planarization layer has an undercut shape in which a side surface of the second planarization portion is recessed toward a center of the first pad electrode and a side surface of the third planarization portion is recessed toward a center of the second pad electrode.

[0008] In one or more embodiments, the reflective layer includes a first reflective layer disposed on a side of the partition wall and a second reflective layer disposed on an upper portion of the first planarization portion, wherein the second reflective layer extends from the first reflective layer and is disconnected from the first auxiliary connection electrode and the second auxiliary connection electrode by a bottom cut shape.

[0009] In one or more embodiments, the first auxiliary connection electrode and the second auxiliary connection electrode include the same material as the reflective layer.

[0010] In one or more embodiments, the first pad electrode and the second pad electrode are spaced apart from each other on the same plane and protrude outward from the light emitting element.

[0011] In one or more embodiments, the light emitting element further includes: an element reflective layer, which is disposed on the bottom surface of the first semiconductor layer; an element insulating layer, which is around the side of the element reflective layer, the side of the first semiconductor layer, the side of the active layer, and the side of the second semiconductor layer (for example, surrounding the side of the element reflective layer, the side of the first semiconductor layer, the side of the active layer, and the side of the second semiconductor layer); and a pad connecting electrode, which is disposed on the bottom surface of the element reflective layer, and the first end of the pad connecting electrode is in direct contact with the second auxiliary connecting electrode.

[0012] In one or more embodiments, the first auxiliary connection electrode includes a first end portion disposed on a top surface of the second semiconductor layer, extending along a side surface of the light emitting element and a side surface of the organic pattern layer, and further includes a second end portion disposed on a side surface of the first pad electrode, wherein the second auxiliary connection electrode has a first end portion disposed on a side surface of the light emitting element, extending along a side surface of the light emitting element, a first end portion of the pad connection electrode, and a side surface of the organic pattern layer, and further includes a second end portion disposed on a side surface of the second pad electrode.

[0013] In one or more embodiments, the display device further includes a via layer and a wavelength conversion layer sequentially arranged in the space, wherein a height of the second auxiliary connection electrode is equal to or lower than a height of the via layer.

[0014] In one or more embodiments, the light emitting element further includes: a base substrate disposed on the second semiconductor layer; a first contact electrode disposed on the first surface of the second semiconductor layer; and a second contact electrode disposed on the first surface of the first semiconductor layer, and wherein the first contact electrode and the second contact electrode are arranged to be spaced apart from each other and bonded to the organic pattern layer.

[0015] In one or more embodiments, the first auxiliary connection electrode includes a first end portion disposed on a side of the light emitting element, extends along a side of the light emitting element, a first end portion of the first contact electrode, and a side of the organic pattern layer, and also includes a second end portion disposed on a side of the first pad electrode, wherein the second auxiliary connection electrode includes a first end portion disposed on a side of the light emitting element, extends along a side of the light emitting element, a first end portion of the second contact electrode, and a side of the organic pattern layer, and also includes a second end portion disposed on a side of the second pad electrode.

[0016] In one or more embodiments, the display device further includes a via layer and a wavelength conversion layer sequentially disposed in the space, wherein a height of the first auxiliary connection electrode and a height of the second auxiliary connection electrode are equal to or less than a height of the via layer.

[0017] In one or more embodiments, the display device further includes: a via layer and a wavelength conversion layer, which are sequentially disposed in the space; and a cover layer, an overcoat layer, and a color filter layer, which are sequentially disposed on the wavelength conversion layer and the partition wall.

[0018] According to one or more embodiments, a display device includes: a planarization layer including a first planarization portion disposed on a substrate and a second planarization portion and a third planarization portion disposed on the first planarization portion; a first pad electrode and a second pad electrode, the first pad electrode being disposed on the second planarization portion and the second pad electrode being disposed on the third planarization portion; a bank covering a portion of the first pad electrode and a portion of the second pad electrode; a first auxiliary connection electrode including a first end portion contacting the first pad electrode and a second end portion disposed on a top surface of the bank; a second auxiliary connection electrode including a first end portion contacting the second pad electrode and a second end portion disposed on a top surface of the bank; an insulating organic layer overlapping the first pad electrode and the second pad electrode, and covers a portion of the first auxiliary connection electrode and a portion of the second auxiliary connection electrode; a light emitting element is provided on the insulating organic layer and has a first contact electrode and a second contact electrode on a top surface; and a first lead and a second lead, respectively connecting the first contact electrode to the first auxiliary connection electrode and connecting the second contact electrode to the second auxiliary connection electrode, wherein the second planarizing portion has an undercut shape in which a side surface of the second planarizing portion is recessed toward a center of the first pad electrode, the third planarizing portion has an undercut shape in which a side surface of the third planarizing portion is recessed toward a center of the second pad electrode, and a horizontal reflective layer is located between the second planarizing portion and the third planarizing portion.

[0019] In one or more embodiments, the horizontal reflective layer is disposed between the first and second auxiliary connection electrodes and is disconnected from the first and second auxiliary connection electrodes by the undercut shapes of the second and third planarizing portions.

[0020] In one or more embodiments, the horizontal reflective layer includes the same material as the first auxiliary connection electrode and the second auxiliary connection electrode.

[0021] In one or more embodiments, the light emitting element further includes a first semiconductor layer, an active layer, a second semiconductor layer and an element insulation layer, wherein the element insulation layer surrounds the side of the first semiconductor layer, the side of the active layer and the side of the second semiconductor layer, wherein the first contact electrode contacts the first semiconductor layer, and the second contact electrode contacts the second semiconductor layer.

[0022] In one or more embodiments, the first end of the first lead is disposed on the first contact electrode, and the second end of the first lead is disposed on the first auxiliary connection electrode, and the first end of the second lead is disposed on the second contact electrode, and the second end of the second lead is disposed on the second auxiliary connection electrode.

[0023] According to one or more embodiments, a method for manufacturing a display device includes the following steps: providing a first planarizing portion and a second planarizing portion and a third planarizing portion on the first planarizing portion; providing a first pad electrode and a second pad electrode on the second planarizing portion and the third planarizing portion; etching the second planarizing portion and the third planarizing portion to expose the first planarizing portion; forming an undercut shape in which side surfaces of the second planarizing portion and the third planarizing portion are recessed toward centers of the first pad electrode and the second pad electrode; providing an organic pattern layer and a light emitting element on the first pad electrode and the second pad electrode; forming a partition wall on the first planarizing portion to surround the light emitting element (e.g., surround the light emitting element); depositing a reflective material layer to cover both the partition wall and the light emitting element; forming a via layer in a space defined by the partition wall; forming a photoresist mask pattern to cover a portion of the light emitting element; and forming a reflective layer and a first auxiliary connection electrode and a second auxiliary connection electrode by etching the reflective material layer on the via layer and the photoresist mask pattern.

[0024] In one or more embodiments, the reflective layer includes a first reflective layer disposed on a side of the partition wall and a second reflective layer disposed on an upper portion of the first planarization portion, wherein the second reflective layer is disposed to extend from the first reflective layer and is disconnected from the first auxiliary connection electrode and the second auxiliary connection electrode by a bottom cut shape.

[0025] In one or more embodiments, the step of disposing an organic pattern layer and a light emitting element on the first pad electrode and the second pad electrode includes: coating (e.g., completely coating) an organic pattern material layer on the substrate to cover the first planarization portion, the second planarization portion, the third planarization portion, the first pad electrode, and the second pad electrode; disposing a light emitting element to overlap with the first pad electrode and the second pad electrode on the organic pattern material layer; bonding the light emitting element by curing the organic pattern material layer; and forming the organic pattern layer by ashing a portion of the organic pattern material layer that does not overlap with the light emitting element.

[0026] In one or more embodiments, the method further includes the steps of: forming a wavelength conversion layer in a space defined by the partition wall; and forming an overcoat layer and a color filter layer, the overcoat layer and the color filter layer being sequentially disposed on the partition wall and the wavelength conversion layer.

[0027] The display device according to the embodiment may form the auxiliary connection electrode and the reflective layer in a single process using the same material layer, and the auxiliary connection electrode and the reflective layer may be electrically separated from each other by the undercut structure.

[0028] Furthermore, the display device according to the embodiment can improve light output efficiency and prevent (prevent or substantially prevent) color mixing by forming a reflector on a partition wall surrounding a light emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a perspective view showing a display device according to an embodiment.

[0030] Figure 2 and Figure 3 is a plan view showing a display device according to an embodiment.

[0031] Figure 4 is a circuit diagram showing a first sub-pixel of a display panel according to an embodiment.

[0032] Figure 5 is a circuit diagram showing a first sub-pixel of a display panel according to another embodiment.

[0033] Figure 6 is a cross-sectional view schematically showing a display device according to an embodiment.

[0034] Figure 7 is schematically shown with reference to Figure 6 An enlarged view of the first light emitting region is depicted.

[0035] Figure 8 yes Figure 7 Magnified view of area "A".

[0036] Fig. 9 It is a reference Figure 7 A plan view and a cross-sectional view of a light emitting element portion according to the described embodiment correspond to each other.

[0037] Fig.10 is an enlarged view of a light emitting element according to an embodiment.

[0038] Fig.11 is a schematic diagram showing a method for performing a Figure 7 An enlarged view of the first light-emitting area corresponding to the area.

[0039] Fig.12 is a cross-sectional view schematically showing a display device according to another embodiment.

[0040] Fig.13 is schematically shown with reference to Fig.12 An enlarged view of the first light emitting region is depicted.

[0041] Fig.14 It is a reference Fig.13 A plan view of the light-emitting area explained.

[0042] Fig.15 is included in Fig.13 An enlarged view of the light-emitting element in FIG.

[0043] Fig.16is a cross-sectional view schematically showing a display device according to another embodiment.

[0044] Fig.17 is schematically shown with reference to Fig.16 An enlarged view of the first light emitting region is depicted.

[0045] Fig.18 It is a reference Fig.16 A plan view of the light-emitting area explained.

[0046] Fig.19 is included in Fig.17 An enlarged view of the light-emitting element in FIG.

[0047] Figures 20 to 38 is a diagram for illustrating a method of manufacturing a display device according to an embodiment.

[0048] Figure 39 to Figure 43 is a diagram for illustrating a method of manufacturing a display device according to another embodiment.

[0049] Figures 44 to 50 is a diagram for illustrating a method of manufacturing a display device according to another embodiment.

[0050] Fig.51 is a diagram schematically showing an example of a virtual reality device including a display device according to an embodiment.

[0051] Fig.52 is a diagram schematically illustrating an example of a smart device including a display device according to an embodiment.

[0052] Fig.53 is a diagram schematically showing an example of a vehicle including a display device according to an embodiment.

[0053] Fig.54 is a diagram schematically showing an example of a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION

[0054] Some embodiments will now be described more fully herein with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting the present disclosure. Throughout the disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0055] In order to more clearly describe the embodiments of the present disclosure, descriptions of some components that are not related to the description may not be provided.

[0056] It will be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or one or more intervening layers may also be present. Conversely, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

[0057] In addition, the phrase "in a plan view" refers to when the target portion is viewed from above, and the phrase "in a schematic cross-sectional view" refers to when the schematic cross-section taken by vertically cutting the target portion is viewed from the side. The term "superimposed" or its variants means that the first target can be above or below or on one side of the second target, and vice versa. In addition, the term "superimposed" may include stacking, stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-superimposed" includes the meaning of any other suitable equivalent such as "spaced apart from" or "biased from" or "offset from" and as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" mean that the first target can be directly or indirectly opposite to the second target. In the case where the third target is placed between the first target and the second target, although the first target and the second target face each other, it can be understood to be indirectly opposite to each other.

[0058] For ease of description, spatially relative terms such as "below", "under", "below", "above", "on", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, where the device shown in the figure is flipped, a device that is "below" or "below" another device may be "above" another device. Thus, the exemplary term "below" may include both lower and upper positions. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0059] When an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or electrically connected or coupled to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms "comprises," "having," and / or "comprising," and variations thereof, are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0060] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element, or for convenience of description and explanation. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be named in a similar manner without departing from the teachings herein.

[0061] As used herein, the term "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0062] In the specification and claims, for the purpose of its meaning and description, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and description, the phrase "at least one of..." is intended to include the meaning of "at least one of the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0063] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in the specification.

[0064] Here, some example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0065] Figure 1 is a perspective view showing a display device according to an embodiment.

[0066] Reference Figure 1The display device 10 is a device for displaying video or still images, and can be used as a display screen of any of portable electronic devices (such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation and ultra mobile PCs (UMPCs)) and various products (such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices).

[0067] The display device 10 may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a miniaturized light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Here, the description provided focuses on the display device 10 as a micro light-emitting display device, but the present disclosure is not limited thereto. In addition, for ease of explanation, an ultra-small light-emitting diode is described herein as a micro light-emitting diode.

[0068] In an embodiment, the display device 10 includes a display panel 100 , a display driving circuit 250 , and a circuit board 300 .

[0069] In an embodiment, the display panel 100 may be formed to have a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a curvature (e.g., a predetermined curvature), or may be formed to be a right angle. However, the planar shape of the display panel 100 is not limited to a rectangle, and may be formed to be other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 may be formed to be flat, but is not limited thereto. For example, the display panel 100 may be formed to include a curved portion having a constant curvature or a variable curvature at its left and right ends. In addition, the display panel 100 may be formed to be flexible, such as being formed to be able to bend, bend, fold, or curl.

[0070] The substrate of the display panel 100 may include a main area MA and a sub area SBA.

[0071] The main area MA may include a display area DA that displays an image and a non-display area NDA that is a peripheral area of ​​the display area DA. The display area DA may include a plurality of pixels that display an image. For example, a pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0072] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2. Figure 1The sub-region SBA is shown as being expanded, but the sub-region SBA may be bent, and in this case, the sub-region SBA may be disposed on the bottom surface of the display panel 100. When the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the third direction DR3 which is the thickness direction of the display panel 100. The display driving circuit 250 may be disposed in the sub-region SBA.

[0073] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and may be attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 using a chip on film (COF) method.

[0074] The circuit board 300 may be attached to the end of the sub-area SBA of the display panel 100. As such, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0075] Figure 2 and Figure 3 is a plan view showing a display device according to an embodiment. Figure 2 The sub-area SBA is shown unfolded without being bent. Figure 3 It is shown that the sub-area SBA is bent.

[0076] Reference Figure 2 and Figure 3 , the display panel 100 may include a main area MA and a sub-area SBA.

[0077] The main area MA may include a display area DA displaying an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be located at the center of the main area MA.

[0078] The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. In an embodiment, the non-display area NDA may be arranged to surround the display area DA. In an embodiment, the non-display area NDA may be an edge area of ​​the display panel 100.

[0079] The first scan driving unit SDC1 and the second scan driving unit SDC2 may be disposed in the non-display area NDA. The first scan driving unit SDC1 is disposed on a side (e.g., a left side) of the display panel 100, and the second scan driving unit SDC2 is disposed on the other side (e.g., a right side) of the display panel 100. However, the present disclosure is not limited thereto. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may receive a scan control signal from the display driving circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0080] The sub-region SBA may protrude from the side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be disposed at a lower portion of the display panel 100. In this case, the sub-region SBA may overlap the main region MA in the third direction DR3.

[0081] The sub-area SBA may include a connection area CA, a pad (also called a “bonding pad” or a “pad”) area PA, and a bending area BA.

[0082] The connection area CA is an area protruding from the side of the main area MA in the second direction DR2. A side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0083] The pad area PA is an area where the pad PD and the display driving circuit 250 are provided. The display driving circuit 250 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The side of the pad area PA may be in contact with the bending area BA.

[0084] The bending area BA is a bent or bendable area. When the bending area BA is bent, the pad area PA may be disposed below the connection area CA and below the main area MA. The bending area BA may be disposed between the connection area CA and the pad area PA. A side of the bending area BA may contact the connection area CA, and the other side of the bending area BA may contact the pad area PA.

[0085] Figure 4is a circuit diagram showing a first sub-pixel of a display panel according to an embodiment.

[0086] Reference Figure 4 , the first subpixel SPX1 according to the embodiment can be connected to the scan lines GWL, GIL, GCL and GBL, the emission line EL and the data line DL. For example, the first subpixel SPX1 can be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission line EL and the data line DL.

[0087] The first subpixel SPX1 according to the embodiment includes a driving transistor DT, a switching element, a capacitor C1 and a first light emitting element LE1. The switching element includes first, second, third, fourth, fifth and sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6.

[0088] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (Ids, referred to herein as “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0089] In an embodiment, the first light emitting element LE1 may be a micro light emitting diode.

[0090] The first light emitting element LE1 emits light according to the driving current (Ids). The amount of light emitted from the first light emitting element LE1 may be proportional to the driving current (Ids). The anode electrode of the first light emitting element LE1 may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode thereof may be connected to the second power line VSL to which the second power voltage is applied.

[0091] The capacitor C1 is formed between the second electrode of the driving transistor DT and the first power line VDL to which the first power voltage is applied. The first power voltage may be at a higher level than the second power voltage. An electrode of the capacitor C1 may be connected to the second electrode of the driving transistor DT, and another electrode thereof may be connected to the first power line VDL.

[0092] In an embodiment, Figure 4 As shown in , the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may all be formed as p-type MOSFETs. In an embodiment, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may be formed of polysilicon or an oxide semiconductor.

[0093] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. In an embodiment, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, and may be turned on when a scan signal of a gate low voltage and an emission signal are applied to the control scan line GCL, the write scan line GWL, the initialization scan line GIL, the bias scan line GBL, and the light emitting line EL, respectively. The electrode of the third transistor ST3 and the electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0094] Figure 5 is a circuit diagram showing a first sub-pixel of a display panel according to another embodiment.

[0095] Reference Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed of n-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as n-type MOSFETs may be formed of oxide semiconductors. In this case, transistors formed of polysilicon and transistors formed of oxide semiconductors may be arranged in different layers.

[0096] Since the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal with a gate high voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal is applied to the initialization scan line GIL. In contrast, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, and can be turned on when a scan signal with a gate low voltage and an emission signal are applied to the write scan line GWL, the bias scan line GBL, and the light emitting line EL, respectively.

[0097] In another embodiment, Figure 4The fourth transistor ST4 in the embodiment may be formed by an n-type MOSFET. In this case, the active layer of the fourth transistor ST4 may be formed by an oxide semiconductor. When the fourth transistor ST4 is formed by an n-type MOSFET, the fourth transistor ST4 may be turned on when a bias scan signal of a gate high voltage is applied to the bias scan line GBL.

[0098] In another embodiment, although Figure 4 and Figure 5 Although not shown, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 and the driving transistor DT may all be formed as n-type MOSFETs.

[0099] In an embodiment, the circuit diagram of the second sub-pixel and the third sub-pixel according to the embodiment is combined with Figure 4 and Figure 5 The circuit diagram of the first sub-pixel SPX1 described is substantially the same, and further description thereof will be omitted.

[0100] Figure 6 is a cross-sectional view schematically showing a display device according to an embodiment.

[0101] Reference Figure 6 , the display device 10 may include a substrate 110 , a light emitting element portion LEP, and a color filter layer CFL.

[0102] The substrate 110 may be an insulating substrate. The substrate 110 may include a transparent material. For example, the substrate 110 may include a transparent insulating material such as glass, quartz, etc. The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto, and may include a plastic such as polyimide, and may have a flexible property that allows it to bend, bend, fold, or curl. A plurality of light emitting areas EA1, EA2, and EA3 and a non-light emitting area NEA may be defined in the substrate 110.

[0103] The switching elements T1, T2, and T3 may be located on the substrate 110. In an embodiment, the first switching element T1 may be located in the first light emitting area EA1 of the substrate 110, the second switching element T2 may be located in the second light emitting area EA2, and the third switching element T3 may be located in the third light emitting area EA3. However, the present disclosure is not limited thereto, and in another embodiment, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be located in the non-light emitting area NEA.

[0104] In an embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 may each be a thin film transistor including amorphous silicon, polycrystalline silicon, or an oxide semiconductor. Although not shown in the drawings, a plurality of signal lines (e.g., gate lines, data lines, power lines, etc.) transmitting signals to each switching element may be further located on the substrate 110.

[0105] Each of the switching elements T1 , T2 , and T3 may include a semiconductor layer 65 , a gate electrode 75 , a source electrode 85 a , and a drain electrode 85 b .

[0106] The buffer layer 60 may be disposed on the substrate 110. The buffer layer 60 may be disposed to cover the entire surface of the substrate 110. The buffer layer 60 may include silicon nitride, silicon oxide, or silicon oxynitride, and may be made of a single layer or a double layer thereof.

[0107] The semiconductor layer 65 may be disposed on the buffer layer 60. The semiconductor layer 65 may form a channel for each of the switching elements T1, T2, and T3. The semiconductor layer 65 may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the oxide semiconductor may include a binary compound (AB) containing, for example, indium, zinc, gallium, tin, titanium, aluminum, hafnium, zirconium, magnesium, etc. x ), ternary compounds (AB x C y ) or quaternary compounds (AB x C y D z In an embodiment, the semiconductor layer 65 may include indium gallium zinc oxide (IGZO).

[0108] The gate insulating layer 70 may be disposed on the semiconductor layer 65. The gate insulating layer 70 may include a silicon compound, a metal oxide, etc. For example, the gate insulating layer 70 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. In an embodiment, the gate insulating layer 70 may include silicon oxide.

[0109] The gate electrode 75 may be disposed on the gate insulating layer 70. The gate electrode 75 may be disposed to overlap the semiconductor layer 65. The gate electrode 75 may include a conductive material. The gate electrode 75 may include a metal oxide (such as ITO, IZO, ITZO, In 2 O 3 ) or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni). For example, the gate electrode 75 may be made of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0110] The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be disposed on the gate electrode 75. The first interlayer insulating layer 80 may be disposed directly on the gate electrode 75, and the second interlayer insulating layer 82 may be disposed directly on the first interlayer insulating layer 80. The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may each include an inorganic insulating material such as any one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, etc. However, the present disclosure is not limited thereto, and the second interlayer insulating layer 82 may include an organic insulating material capable of flattening a lower level difference. In the embodiment, two interlayer insulating layers (the first interlayer insulating layer 80 and the second interlayer insulating layer 82) are shown and described, but the present disclosure is not limited thereto, and in the embodiment, only one interlayer insulating layer may be provided.

[0111] The source electrode 85a and the drain electrode 85b may be disposed on the second interlayer insulating layer 82. The source electrode 85a and the drain electrode 85b may contact the semiconductor layer 65 through contact holes passing through the first interlayer insulating layer 80, the second interlayer insulating layer 82, and the gate insulating layer 70, respectively. The source electrode 85a and the drain electrode 85b may include a metal oxide (such as ITO, IZO, ITZO, In 2 O 3 ) or a metal such as any one of copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), and nickel (Ni). For example, the source electrode 85a and the drain electrode 85b may be composed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0112] The first planarization layer 120 may be disposed on the first switching element T1, the second switching element T2, and the third switching element T3. The first planarization layer 120 may include an organic material. For example, the first planarization layer 120 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, etc. In an embodiment, the first planarization layer 120 may include a positive photosensitive material or a negative photosensitive material.

[0113] The pixel connection electrode 125 may be disposed on the first planarization layer 120. The pixel connection electrode 125 is disposed to correspond to each of the first switching element T1, the second switching element T2, and the third switching element T3, and may be electrically connected to each of the first switching element T1, the second switching element T2, and the third switching element T3. The pixel connection electrode 125 may connect a pixel electrode described later to the switching elements T1, T2, and T3 described above. The pixel connection electrode 125 may contact the switching elements T1, T2, and T3 through a contact hole penetrating the first planarization layer 120.

[0114] The second planarization layer 130 may be disposed on the first planarization layer 120 and the pixel connection electrode 125. The second planarization layer 130 planarizes the lower level difference, and may include the same material as the first planarization layer 120 described above.

[0115] The light emitting element part LEP may be disposed on the second planarization layer 130. The light emitting element part LEP may include a first pad electrode CPD, a second pad electrode APD, an organic pattern layer BOL, a plurality of light emitting elements LE, a first auxiliary connection electrode SCT, a second auxiliary connection electrode SAT, a partition wall PW, a reflective layer RF, a via layer VIA, and a wavelength conversion layer QDL.

[0116] The first pad electrode CPD may be supplied with a first power supply voltage as a low potential voltage, and may be a cathode electrode. The second pad electrode APD may be directly connected to the pixel connection electrode 125 through a contact hole penetrating the second planarization layer 130, and may be electrically connected to each of the switching elements T1, T2, and T3 through the pixel connection electrode 125. The second pad electrode APD may be an anode electrode. The first pad electrode CPD and the second pad electrode APD may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In some embodiments, the first pad electrode CPD and the second pad electrode APD may have a double-layer structure of Ti / Al or a triple-layer structure of Ti / Al / Ti. In some embodiments, each of the first pad electrode CPD and the second pad electrode APD may include a transparent conductive layer to increase adhesion. The transparent conductive layer may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0117] The organic pattern layer BOL may be disposed on the first pad electrode CPD and the second pad electrode APD. The organic pattern layer BOL may expose at least a portion of the first pad electrode CPD and the second pad electrode APD.

[0118] In an embodiment, the organic pattern layer BOL may be arranged in each of the emission regions EA1, EA2, and EA3 in an island pattern shape. For example, the organic pattern layer BOL disposed in each of the emission regions EA1, EA2, and EA3 may be arranged to be spaced apart from the organic pattern layer BOL disposed in the adjacent emission regions EA1, EA2, and EA3.

[0119] In an embodiment, the thickness of the plurality of organic pattern layers BOL may be about 2 μm or less, but is not limited thereto.

[0120] The plurality of organic pattern layers BOL may include an organic material. The organic material may be, for example, a photosensitive organic insulating material, but is not limited thereto. In an embodiment, the organic material may include epoxy resin, acrylic resin, cardo resin, or imide resin.

[0121] The plurality of organic pattern layers BOL may be formed by various methods such as an organic imprint method, an inkjet printing method, an electrospray method, or a stamping method.

[0122] In a high-resolution display panel such as the display device 10 in the embodiment, it is difficult to replace the organic pattern layer BOL with an anisotropic conductive film (ACF).

[0123] The light emitting element LE may be disposed on the organic pattern layer BOL. The light emitting element LE may be an inorganic light emitting element made of an inorganic material such as GaN.

[0124] The light emitting element LE may be disposed in each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. The light emitting element LE may be a vertical light emitting diode element that extends long in the third direction DR3. That is, the length of the light emitting element LE in the third direction DR3 may be greater than its length in the horizontal direction. The length in the horizontal direction refers to the length in the first direction DR1 or the length in the second direction DR2. For example, the length of the light emitting element LE in the first direction DR1 or the length in the second direction DR2 may be approximately 7 μm to 10 μm, but is not limited thereto. In an embodiment, the length of the light emitting element LE in the third direction DR3 may be approximately 1 μm to 5 μm. However, the present disclosure is not limited thereto, and the length of the light emitting element LE in the third direction DR3 may be equal to or less than its length in the horizontal direction.

[0125] The light emitting element LE may be a micro light emitting diode element.

[0126] A partition wall PW and a via layer VIA that divide each of the light emitting areas EA1 , EA2 , and EA3 may be further disposed on the second planarization layer 130 .

[0127] The partition wall PW may divide the plurality of light emitting areas EA1, EA2, and EA3. The partition wall PW is arranged to extend in the first direction DR1 and the second direction DR2, and may be formed in a grid-like pattern throughout the display area DA. In an embodiment, the partition wall PW may not overlap the plurality of light emitting areas EA1, EA2, and EA3, and may overlap the non-light emitting area NEA.

[0128] The partition wall PW may provide a space for forming the wavelength conversion layer QDL. The partition wall PW may be made relatively thick to provide a space in which the wavelength conversion layer QDL is formed. The partition wall PW may include an organic insulating material so that the partition wall PW is made thick. The organic insulating material may include, for example, an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0129] In an embodiment, the partition wall PW may block the transmission of light in the non-light emitting area NEA. The partition wall PW may also include a light blocking material, and may include a dye or pigment having a light blocking property. For example, the partition wall PW may be a black matrix. External light incident from the outside of the display device 10 may cause the problem of color gamut distortion of the light emitting element part LEP. According to an embodiment, the partition wall PW including a light blocking material is disposed in the light emitting element part LEP so that at least a portion of the external light can be absorbed by the light blocking member. Therefore, the color distortion caused by the reflection of external light can be reduced. In addition, the partition wall PW including a light blocking material can prevent or substantially prevent color mixing due to light entering between adjacent light emitting areas, thereby further improving color reproduction. In an embodiment, the partition wall PW is formed as a single layer, but the present disclosure is not limited thereto, and the partition wall PW may be formed as a double-layer structure. The height of the partition wall PW may be higher than the height of the light emitting element LE. In an embodiment, the height of the partition wall PW may be about 8 μm to 14 μm. The height of the partition wall PW may refer to the length from the top of the second planarization layer 130 in the third direction DR3.

[0130] In an embodiment, the partition wall PW is formed of a negative photoresist and may have an inverse tapered shape.

[0131] The reflective layer RF may be disposed between the partition wall PW and the space formed by the partition wall PW. The reflective layer RF may be disposed on the side of the partition wall PW and on the bottom surface between the partition walls PW that is not overlapped with the light emitting element LE, the first pad electrode CPD, and the second pad electrode APD. The reflective layer RF may include an opening formed in a region overlapping with the first pad electrode CPD, the second pad electrode APD, and the light emitting element LE. In an embodiment, the reflective layer RF may include a metal material having a high light reflectivity. For example, the reflective layer RF may include aluminum or silver, or an alloy thereof.

[0132] The first auxiliary connection electrode SCT is disposed along the side of the light emitting element LE and connects a second semiconductor layer SEM2 and a first pad electrode CPD of the light emitting element LE to be described later. The first auxiliary connection electrode SCT includes a conductive material and may directly contact the second semiconductor layer SEM2 and the first pad electrode CPD.

[0133] The second auxiliary connection electrode SAT is disposed along the side of the light emitting element LE and connects the pad connection electrode PCE and the second pad electrode APD of the light emitting element LE. The second auxiliary connection electrode SAT includes a conductive material and directly contacts the pad connection electrode PCE and the second pad electrode APD. Fig. 9 , the pad connection electrode PCE and the second pad electrode APD are arranged to be spaced apart from each other.

[0134] The via layer VIA may be disposed in each of the light emitting areas EA1, EA2, and EA3 divided by the partition wall PW. The via layers VIA disposed in each of the light emitting areas EA1, EA2, and EA3 may be disposed to be spaced apart from each other. The via layer VIA may be disposed in a space between each of a plurality of sub-pixels, thereby forming an island pattern spaced apart from each other. In other words, the via layer VIA may be disposed on the second planarization layer 130. The via layer VIA may not surround the entire light emitting element LE, but may be disposed to cover the first pad electrode CPD and the second pad electrode APD protruding to the outside of the light emitting element LE.

[0135] The via layer VIA may be formed to be lower than the height of the light emitting element LE. In an embodiment, the height of the via layer VIA may be the same as the height of the second auxiliary connection electrode SAT. The height of the via layer VIA may be higher than the height of the second auxiliary connection electrode SAT.

[0136] The via layer VIA may be formed of an organic film such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0137] The wavelength conversion layer QDL may be disposed on the via layer VIA. The wavelength conversion layer QDL may convert or shift the peak wavelength of the incident light into light of another specific peak wavelength and emit the light. The wavelength conversion layer QDL may convert the blue first light emitted by the light emitting element LE into the red second light, convert the blue first light into the green third light, or transmit the blue first light as is.

[0138] The wavelength conversion layer QDL may be disposed in each of the light emitting areas EA1, EA2, and EA3 divided by the partition wall PW, and may be disposed to be spaced apart from each other. That is, the wavelength conversion layer QDL may be formed into an island pattern spaced apart from each other. The wavelength conversion layer QDL may be disposed to overlap the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, respectively. In an embodiment, each of the wavelength conversion layers QDL may completely overlap the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0139] The wavelength conversion layer QDL includes a first wavelength conversion pattern WCL1 overlapping the first light emitting area EA1 , a second wavelength conversion pattern WCL2 overlapping the second light emitting area EA2 , and a light-transmitting pattern TPL overlapping the third light emitting area EA3 .

[0140] The first wavelength conversion pattern WCL1 may be disposed to overlap the first light emitting area EA1. The first wavelength conversion pattern WCL1 may convert or shift the peak wavelength of the incident light into light of another specific peak wavelength and emit the light. In an embodiment, the first wavelength conversion pattern WCL1 may convert the blue first light emitted from the light emitting element LE of the first light emitting area EA1 into the second light, which is red light having a single peak wavelength in the range of about 610 nm to about 650 nm, and emit the second light.

[0141] The first wavelength conversion pattern WCL1 may include a first base resin BRS1, first wavelength conversion particles WCP1, and scatterers SCP. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include epoxy resin, acrylic resin, cardo resin, or imide resin.

[0142] The first wavelength conversion particle WCP1 may convert the first light incident from the light emitting element LE into the second light. For example, the first wavelength conversion particle WCP1 may convert the light in the blue band into the light in the red band. The first wavelength conversion particle WCP1 may be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material. For example, a quantum dot may be a particle material that emits a specific color when an electron transitions from a conduction band to a valence band.

[0143] Quantum dots can be semiconductor nanocrystal materials. Depending on their composition and size, quantum dots can have a specific band gap to absorb light and emit light with a unique wavelength. Examples of semiconductor nanocrystals of quantum dots include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, or combinations thereof.

[0144] In an embodiment, the II-VI compound is a binary compound (selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS) and mixtures thereof, a ternary compound (selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZ nS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS) and mixtures thereof and quaternary compounds (selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe) and mixtures thereof.

[0145] In an embodiment, the III-V compound is a binary compound (selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb) and mixtures thereof, a ternary compound (selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb) and mixtures thereof and a quaternary compound (selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb) and mixtures thereof.

[0146] In an embodiment, the IV-VI compound may be selected from the group consisting of binary compounds (selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe) and mixtures thereof, ternary compounds (selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe) and mixtures thereof, and quaternary compounds (selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe) and mixtures thereof. The IV group element may be selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe and mixtures thereof.

[0147] The binary, ternary or quaternary compound may be present in a particle at a uniform concentration, or may be present in the same particle at a partially different concentration distribution. The quantum dot may also have a core-shell structure in which a quantum dot surrounds another quantum dot. The interface of the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0148] In an embodiment, the quantum dot may have a core-shell structure comprising a core comprising a nanocrystal as described above and a shell surrounding the core. The shell of the quantum dot may act as a protective layer to prevent or substantially prevent chemical denaturation of the core to maintain semiconductor properties and / or act as a charge layer to impart electrophoretic properties to the quantum dot. The shell may be monolayer or multilayer. Examples of shells for quantum dots include metal or nonmetal oxides, semiconductor compounds, or combinations thereof.

[0149] For example, the metal or non-metal oxide may be, for example, a binary compound (such as SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 , NiO) or ternary compounds (such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 、CoMn 2 O 4 ), but the present disclosure is not limited thereto.

[0150] In an embodiment, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but is not limited thereto.

[0151] The second wavelength conversion pattern WCL2 may be disposed to overlap the second light emitting area EA2. The second wavelength conversion pattern WCL2 may emit light by converting or shifting the peak wavelength of the incident light into light of another specific peak wavelength. In an embodiment, the second wavelength conversion pattern WCL2 converts the blue first light emitted from the light emitting element LE of the second light emitting area EA2 into a green third light having a peak wavelength in the range of about 510 nm to 550 nm, and emits the light.

[0152] The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2 and scatterers SCP dispersed in the second base resin BRS2.

[0153] The second base resin BRS2 may be made of a material having high light transmittance, may be made of the same material as the first base resin BRS1, or may include at least one of the materials described as examples as a constituent material.

[0154] The second wavelength conversion particles WCP2 may convert or shift the peak wavelength of the incident light to another specific peak wavelength. In an embodiment, the second wavelength conversion particles WCP2 may convert the blue first light provided from the light emitting element LE into a green third light having a peak wavelength in the range of about 510 nm to 550 nm, and emit the light. Examples of the second wavelength conversion particles WCP2 include quantum dots, quantum rods, or phosphors. The second wavelength conversion particles WCP2 may be substantially the same or similar to those described above in the description of the first wavelength conversion particles WCP1, and thus further description thereof will be omitted.

[0155] The light-transmitting pattern TPL may be arranged to overlap with the third light-emitting area EA3. The light-transmitting pattern TPL may transmit incident light. The light-transmitting pattern TPL may directly transmit the blue first light emitted from the light-emitting element LE disposed in the third light-emitting area EA3. The light-transmitting pattern TPL may include a third base resin BRS3 and a scatterer SCP dispersed in the third base resin BRS3. The third base resin BRS3 may be substantially the same as or similar to the first base resin BRS1 described above, and thus further description thereof will be omitted.

[0156] Reference Figure 7 and Figure 8 The light emitting element portion LEP is described in further detail.

[0157] First light, second light, and third light emitted from the light emitting element portion LEP described below may be transmitted through the color filter layer CFL described herein to realize full color.

[0158] The capping layer CAP may be disposed on the partition wall PW and the wavelength conversion layer QDL, and may be included in the light emitting element portion LEP. The capping layer CAP covers the wavelength conversion layer QDL below to protect the wavelength conversion layer QDL below from moisture or debris. In an embodiment, the capping layer CAP may include an inorganic material. For example, the capping layer CAP may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The accompanying drawings show that the capping layer CAP is formed as a single layer, but the present disclosure is not limited thereto. For example, the capping layer CAP may be formed as a plurality of layers stacked with alternating inorganic layers, the alternating inorganic layers including at least one of the materials exemplified as the materials that the capping layer CAP may include. In an embodiment, the thickness of the capping layer CAP may be in the range of 0.05 μm to 2 μm, but is not limited thereto.

[0159] The color filter layer CFL may be disposed on the light emitting element part LEP. The color filter layer CFL may include a first overcoat layer OC1, a first color filter CF1, a second color filter CF2, a third color filter CF3, and a second overcoat layer OC2.

[0160] The first overcoat layer OC1 may be disposed on the light emitting element portion LEP. In an embodiment, the first overcoat layer OC1 may be disposed directly on the cover layer CAP of the light emitting element portion LEP. In an embodiment, the first overcoat layer OC1 may be disposed entirely in the display area DA and may have a flat surface. The first overcoat layer OC1 may facilitate the formation of the color filter layer CFL by flattening a step formed by the wavelength conversion layer QDL below.

[0161] The first overcoat layer OC1 may include a light-transmitting organic material. For example, the first overcoat layer OC1 may include epoxy resin, acrylic resin, cardo resin, or imide resin. In the embodiment, the first overcoat layer OC1 is shown as a single layer, but is not limited thereto, and may be arranged to be stacked in multiple layers.

[0162] First, second, and third color filters CF1, CF2, and CF3 may be disposed on the first overcoat layer OC1. The first, second, and third color filters CF1, CF2, and CF3 may be disposed in the first, second, and third emission regions EA1, EA2, and EA3, respectively.

[0163] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant such as a dye or pigment that absorbs wavelengths other than the corresponding color wavelength. The first color filter CF1 may selectively transmit the second light (e.g., red light) and block or absorb the first light (e.g., blue light) and the third light (e.g., green light). The second color filter CF2 may selectively transmit the third light (e.g., green light) and block or absorb the first light (e.g., blue light) and the second light (e.g., red light). The third color filter CF3 may selectively transmit the first light (e.g., blue light) and block or absorb the second light (e.g., red light) and the third light (e.g., green light). For example, the first color filter CF1 may be a red filter, the second color filter CF2 may be a green filter, and the third color filter CF3 may be a blue filter.

[0164] In an embodiment, light incident on the first color filter CF1 may be light converted into second light in the first wavelength conversion pattern WCL1, light incident on the second color filter CF2 may be light converted into third light in the second wavelength conversion pattern WCL2, and light incident on the third color filter CF3 may be first light transmitted through the light-transmitting pattern TPL. As a result, the second light transmitted through the first color filter CF1, the third light transmitted through the second color filter CF2, and the first light transmitted through the third color filter CF3 may be emitted toward the top of the substrate 110 to achieve full color.

[0165] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb a portion of light entering from the outside of the display device 10 to reduce reflected light caused by the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent or substantially prevent color distortion due to reflection of external light.

[0166] The plane area of ​​the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be larger than the plane area of ​​the corresponding light-emitting area in the plurality of light-emitting areas EA1, EA2, and EA3. For example, the first color filter CF1 may be larger than the plane area of ​​the first light-emitting area EA1, the second color filter CF2 may be larger than the plane area of ​​the second light-emitting area EA2, and the third color filter CF3 may be larger than the plane area of ​​the third light-emitting area EA3. However, the present disclosure is not limited thereto, and for example, the plane area of ​​the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be equal to the plane area of ​​the corresponding light-emitting area in the plurality of light-emitting areas EA1, EA2, and EA3.

[0167] The second overcoat layer OC2 may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. In an embodiment, the second overcoat layer OC2 may be disposed directly on the first color filter CF1, the second color filter CF2, and the third color filter CF3. In an embodiment, the second overcoat layer OC2 may be disposed entirely in the display area DA and may have a flat surface. The second overcoat layer OC2 may flatten the steps formed by the first color filter CF1, the second color filter CF2, and the third color filter CF3 below. The second overcoat layer OC2 may include a light-transmitting organic material and may be substantially the same or similar to the first overcoat layer OC1 described above.

[0168] As described above, the display device 10 according to the embodiment can improve the light emission efficiency of the light emitting element LE by forming the reflective layer RF on the substrate 110 on the side of the partition wall PW and in the area not overlapping the light emitting element LE between the partition wall PW and another partition wall PW.

[0169] Figure 7 is schematically shown with reference to Figure 6 An enlarged view of the first light emitting region is depicted. Figure 8 yes Figure 7 Magnified view of area "A". Fig. 9 It is a reference Figure 7 A plan view and a cross-sectional view of a light emitting element portion according to the described embodiment correspond to each other. Fig.10 is an enlarged view of a light emitting element according to an embodiment.

[0170] Reference Figures 7 to 9 , the second planarization layer 130 may have an undercut structure in a portion overlapping the first pad electrode CPD and the second pad electrode APD. For example, the second planarization layer 130 includes a first planarization portion 130-1 disposed on the substrate 110, a second planarization portion 130-2 disposed on the first planarization portion 130-1, and a third planarization portion 130-3 disposed on the first planarization portion 130-1. The second planarization portion 130-2 and the third planarization portion 130-3 may be arranged to be spaced apart from each other on the same plane. The second planarization portion 130-2 may overlap the first pad electrode CPD, and the third planarization portion 130-3 may overlap the second pad electrode APD.

[0171] The second planarizing layer 130 has an undercut shape in which a side surface of the second planarizing portion 130 - 2 is located inward from a side surface of the first pad electrode CPD and a side surface of the third planarizing portion 130 - 3 is located inward from a side surface of the second pad electrode APD.

[0172] The organic pattern layer BOL is disposed between the first pad electrode CPD and the second pad electrode APD and may cover a portion of the first pad electrode CPD and a portion of the second pad electrode APD. The organic pattern layer BOL may be disposed between the first pad electrode CPD and the second pad electrode APD to fill a space between the second planarization portion 130-2 and the third planarization portion 130-3 having an undercut structure.

[0173] The light emitting element LE may be disposed on the organic pattern layer BOL. In an embodiment, a side surface of the organic pattern layer BOL may be disposed to be aligned with a side surface of the light emitting element LE.

[0174] The light emitting element LE may include a pad connection electrode PCE.

[0175] The pad connection electrode PCE may be disposed on the bottom surface of the light emitting element LE. The pad connection electrode PCE is disposed on the bottom surface of the light emitting element LE and may be disposed to be equal to or smaller than the width of the light emitting element LE. One side of the pad connection electrode PCE may be disposed to be aligned with one side of the light emitting element LE. The pad connection electrode PCE may be disposed in a region overlapping with the second pad electrode APD. One side of the pad connection electrode PCE may be disposed to be aligned with one side of the organic pattern layer BOL.

[0176] The pad connection electrode PCE may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), but is not limited thereto.

[0177] The first auxiliary connection electrode SCT connecting the top of the light emitting element LE and the first pad electrode CPD may be disposed along the side of the light emitting element LE. One end of the first auxiliary connection electrode SCT is disposed on the top surface of the light emitting element LE, and the other end of the first auxiliary connection electrode SCT is disposed on the side of the first pad electrode CPD. When the side of the first pad electrode CPD protrudes outward from the side of the light emitting element LE, the first auxiliary connection electrode SCT may be disposed on the top surface and the side of the first pad electrode CPD protruding outward from the side of the light emitting element LE. Therefore, the contact area between the first auxiliary connection electrode SCT and the first pad electrode CPD may be wider. In this way, the first auxiliary connection electrode SCT extends from the top surface of the light emitting element LE along the side of the light emitting element LE and the side of the organic pattern layer BOL, and is disposed along at least a portion of the top surface and the side of the first pad electrode CPD.

[0178] Although the first auxiliary connection electrode SCT is disposed on a portion of the top surface of the light emitting element LE, as shown in FIG. Fig. 9It can be seen that the first auxiliary connection electrode SCT covers a relatively small portion of the top surface of the light emitting element LE, so that the use of the transparent electrode does not significantly affect the light emitting effect of the light emitting element LE.

[0179] The first pad electrode CPD may be supplied with a low potential power voltage. The light emitting element LE may receive the power voltage input through the first pad electrode CPD through the first auxiliary connection electrode SCT.

[0180] The second auxiliary connection electrode SAT connecting the pad connection electrode PCE and the second pad electrode APD may be disposed at the other side of the light emitting element LE. The second auxiliary connection electrode SAT and the first auxiliary connection electrode SCT may be arranged to face each other with the light emitting element LE therebetween, but is not limited thereto.

[0181] One end of the second auxiliary connection electrode SAT is disposed on a side of the light emitting element LE, and the other end of the second auxiliary connection electrode SAT is disposed on a side of the second pad electrode APD. That is, the second auxiliary connection electrode SAT extends from the side of the light emitting element LE, along the side of the organic pattern layer BOL, and along at least a portion of the top surface and the side of the second pad electrode APD to the end of the second pad electrode APD. The height of the second auxiliary connection electrode SAT may be the same as the height of the via layer VIA. When the side of the second pad electrode APD protrudes outward from the side surface of the light emitting element LE, the second auxiliary connection electrode SAT may be disposed on the top surface and the side of the second pad electrode APD protruding outward from the side of the light emitting element LE. Therefore, the contact area of ​​the second auxiliary connection electrode SAT with the second pad electrode APD may be larger.

[0182] The second pad electrode APD may be supplied with a pixel voltage or an anode voltage.

[0183] The pad connection electrode PCE may be supplied with a pixel voltage or an anode voltage input through the second pad electrode APD through the second auxiliary connection electrode SAT. The light emitting element LE may emit light with a brightness (eg, predetermined brightness) according to a voltage difference between the pixel voltage and the power supply voltage.

[0184] As will be described later, the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be formed by the same process as the reflective layer RF disposed on the side of the partition wall PW. Therefore, the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may include the same material as the reflective layer RF. For example, the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may include aluminum or silver as a metal material having high light reflectivity, or may include an alloy thereof.

[0185] The reflective layer RF may include a first reflective layer RF1 around (eg, surrounding) a side of the partition wall PW and a second reflective layer RF2 disposed on a flat surface between the partition wall PW and the light emitting element LE. In an embodiment, the first reflective layer RF1 and the second reflective layer RF2 may be continuously connected.

[0186] The reflective layer RF is disposed to be spaced apart from the first and second pad electrodes CPD and APD by the second and third planarizing portions 130-2 and 130-3 having an undercut structure. In addition, the reflective layer RF is spaced apart from the first and second auxiliary connection electrodes SCT and SAT by the second and third planarizing portions 130-2 and 130-3 having an undercut structure.

[0187] The via layer VIA and the wavelength conversion layer QDL may be sequentially disposed in the space formed by the partition wall PW.

[0188] The via layer VIA may be disposed on the second reflective layer RF2 disposed on the first planarization part 130 - 1 .

[0189] The height of the via layer VIA may be less than the height of the light emitting element LE, and the thickness of the via layer VIA may be less than the thickness of the wavelength conversion layer QDL. The height of the via layer VIA may refer to the length from the top surface of the second reflective layer RF2 in the third direction DR3. The thickness of the via layer VIA may refer to the length from the bottom surface to the top surface of the via layer VIA. Similarly, the thickness of the wavelength conversion layer QDL may refer to the length from the bottom surface to the top surface of the wavelength conversion layer QDL.

[0190] like Fig.10 As shown in the figure, in the embodiment, the light emitting element LE includes a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT and a second semiconductor layer SEM2 in the third direction DR3. The first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT and the second semiconductor layer SEM2 may be sequentially stacked in the third direction DR3.

[0191] The first semiconductor layer SEM1 may be doped with a first conductive type dopant such as Mg, Zn, Ca, Sr, or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. In an embodiment, a thickness Tsem1 of the first semiconductor layer SEM1 may be approximately 30 nm to 200 nm.

[0192] The electron blocking layer EBL may be disposed on the first semiconductor layer SEM1. The electron blocking layer EBL may be a layer for suppressing or preventing (preventing or substantially preventing) excessive electrons from flowing into the active layer MQW. For example, the electron blocking layer EBL may be p-AlGaN doped with p-type Mg. In an embodiment, the thickness Tebl of the electron blocking layer EBL may be approximately 10 nm to 50 nm. However, in an embodiment, the electron blocking layer EBL may be omitted.

[0193] The active layer MQW may be disposed on the electron blocking layer EBL. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light (ie, light in a blue band) having a central wavelength range of 450 nm to 495 nm.

[0194] The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. In an embodiment, the thickness of the well layer may be approximately 1 nm to 4 nm, and the thickness of the barrier layer may be approximately 3 nm to 10 nm.

[0195] In another embodiment, the active layer MQW may have a structure in which a semiconductor material having a high energy band gap and a semiconductor material having a low energy band gap are alternately stacked, and may include other group III to group V semiconductor materials according to the wavelength range of the emitted light. The light emitted from the active layer MQW is not limited to the first light (light in the blue band), and may be the second light (light in the green band) or the third light (light in the red band) in some cases. In an embodiment, the thickness Tmqw of the active layer MQW may be approximately 10 nm to 25 nm.

[0196] The superlattice layer SLT may be disposed on the active layer MQW. The superlattice layer SLT may be a layer for alleviating stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer SLT may be formed of InGaN or GaN. In an embodiment, the thickness Tslt of the superlattice layer SLT may be approximately 50 nm to 200 nm. However, in an embodiment, the superlattice layer SLT may be omitted.

[0197] The second semiconductor layer SEM2 may be disposed on the superlattice layer SLT. The second semiconductor layer SEM2 may be doped with a second conductive type dopant such as Si, Se, Ge, or Sn. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. In an embodiment, the thickness Tsem2 of the second semiconductor layer SEM2 may be approximately 500 nm to 1 μm.

[0198] In an embodiment, the light emitting element LE may further include an element reflective layer RFO, an insulating layer INS, and a pad connection electrode PCE.

[0199] The element reflection layer RFO may be disposed on the bottom surface of the first semiconductor layer SEM1. In an embodiment, the element reflection layer RFO may be in direct contact with the first semiconductor layer SEM1. The element reflection layer RFO reflects light emitted from the active layer MQW of the light emitting element LE toward the element reflection layer RFO to improve the light emitting efficiency of the light emitting element LE.

[0200] The insulating layer INS may be disposed on the side surface of each light emitting element LE and the bottom surface of the light emitting element LE. The insulating layer INS may not be disposed on the top surface of each light emitting element LE. The insulating layer INS may be disposed on the bottom surface of the element reflection layer RFO. The insulating layer INS may include an opening OP. The insulating layer INS may expose the element reflection layer RFO through the opening OP.

[0201] The pad connection electrode PCE may be disposed on the bottom of the insulating layer INS disposed on the bottom of the light emitting element LE. The pad connection electrode PCE is disposed to cover the opening OP of the insulating layer INS and may contact the element reflection layer RFO exposed through the opening OP. The side of the pad connection electrode PCE may be disposed to be aligned with the side of the light emitting element LE. The insulating layer INS may be made of, for example, silicon oxide (SiO 2 )、Alumina(Al 2 O 3 ) or hafnium oxide (HfO x ) is formed by an inorganic film, but is not limited to this.

[0202] Fig.11 is a schematic diagram showing a method for performing a Figure 7 An enlarged view of the first light-emitting area corresponding to the area.

[0203] Fig.11 The embodiment and above Figures 6 to 10 The embodiment of FIG. 1 is different in that the organic pattern layer BOL protrudes outward from the side of the light emitting element LE. Here, the description overlapping with the embodiment described above may be omitted, and the differences will be described.

[0204] Reference Fig.11, the width of the organic pattern layer BOL may be greater than the width of the light emitting element LE. Therefore, the side surface of the organic pattern layer BOL may protrude outward from the light emitting element LE. In addition, the organic pattern layer BOL may be disposed inward from the outer edges of the first pad electrode CPD and the second pad electrode APD. When viewed from the side, the light emitting element LE, the organic pattern layer BOL, and the first pad electrode CPD (or the second pad electrode APD) may have a stepped shape having steps different from each other.

[0205] Fig.12 is a cross-sectional view schematically showing a display device according to another embodiment. Fig.13 is schematically shown with reference to Fig.12 An enlarged view of the first light emitting region is depicted. Fig.14 It is a reference Fig.13 A plan view of the light-emitting area explained. Fig.15 is included in Fig.13 An enlarged view of the light-emitting element in FIG.

[0206] Figures 12 to 15 Examples and Figures 6 to 10 The embodiment of is different in that the light emitting element LE is a flip chip type. Here, the description overlapping with the embodiment described above may be omitted, and the differences will be described.

[0207] Reference Figures 12 to 15 , the light emitting element part LEP may be disposed on the second planarization layer 130. The light emitting element part LEP may include a first pad electrode CPD, a second pad electrode APD, an organic pattern layer BOL, a light emitting element LE, a first auxiliary connection electrode SCT, a second auxiliary connection electrode SAT, a partition wall PW, a reflective layer RF, a via layer VIA, a flip-chip type light emitting element PLE, and a wavelength conversion layer QDL.

[0208] The flip-chip light emitting element PLE may include first and second contact electrodes CTE1 and CTE2. In an embodiment, the first and second contact electrodes CTE1 and CTE2 are electrodes disposed to correspond to the first and second pad electrodes CPD and APD, and may be a flip-chip micro LED.

[0209] The flip-chip light emitting element PLE may be an inorganic light emitting element made of an inorganic material such as GaN. In an embodiment, the flip-chip light emitting element PLE may have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of several μm to several hundred μm, respectively. For example, the flip-chip light emitting element PLE may have a size of 10 μm×25 μm, but is not limited thereto.

[0210] The flip-chip type light emitting element PLE may be a light emitting structure including a base substrate PSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE2.

[0211] In the embodiment, the base substrate PSUB of the flip-chip type light emitting element PLE may be a sapphire substrate, but is not limited thereto.

[0212] The n-type semiconductor NSEM of the flip chip type light emitting element PLE may be disposed on the surface of the base substrate PSUB. For example, the n-type semiconductor NSEM may be disposed on the bottom surface of the base substrate PSUB. The n-type semiconductor NSEM may be made of GaN doped with an n-type conductive dopant such as Si, Ge, or Sn. Figures 6 to 10 The described second semiconductor layer SEM2 of the light emitting element LE corresponds.

[0213] The active layer MQW of the flip-chip light emitting element PLE may be disposed on a portion of the surface of the n-type semiconductor NSEM. The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. In an embodiment, the active layer MQW includes a material having a multiple quantum well structure, and may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto.

[0214] In another embodiment, the active layer MQW may be a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a low energy band gap are alternately stacked, or may include other Group III to Group V semiconductor materials according to the wavelength of light to be emitted.

[0215] The p-type semiconductor PSEM may be disposed on the surface of the active layer MQW. The p-type semiconductor PSEM may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Sr, Ba, etc. The p-type semiconductor PSEM is similar to the reference Figures 6 to 10 The described first semiconductor layer SEM1 of the light emitting element LE corresponds.

[0216] The second contact electrode CTE2 may be disposed on the surface of the p-type semiconductor PSEM, and the first contact electrode CTE1 may be disposed on another portion of the surface of the n-type semiconductor NSEM. The first contact electrode CTE1 and the second contact electrode CTE2 may not be in direct contact with each other. Another portion of the surface of the n-type semiconductor NSEM on which the first contact electrode CTE1 is disposed may be disposed to be spaced apart from a portion of the surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

[0217] The first auxiliary connection electrode SCT is disposed along the side of the flip-chip type light emitting element PLE and connects the first contact electrode CTE1 and the first pad electrode CPD. The first auxiliary connection electrode SCT includes a conductive material and may directly contact the first contact electrode CTE1 and the first pad electrode CPD.

[0218] One end portion of the first auxiliary connection electrode SCT is disposed on a side surface of the flip-chip type light emitting element PLE, and the other end portion of the first auxiliary connection electrode SCT is disposed on a side surface of the first pad electrode CPD.

[0219] That is, the first auxiliary connection electrode SCT extends from the side of the light emitting element LE along the side of the first contact electrode CTE1 and along the side of the organic pattern layer BOL, and is disposed along at least a portion of the top surface and side of the first pad electrode CPD.

[0220] The second auxiliary connection electrode SAT is disposed along the side of the light emitting element LE and may extend along the side of the second contact electrode CTE2, the side of the organic pattern layer BOL, and the top surface and the side of the second pad electrode APD. The second auxiliary connection electrode SAT connects the second contact electrode CTE2 of the light emitting element LE and the second pad electrode APD. In an embodiment, the second auxiliary connection electrode SAT includes a conductive material and directly contacts the second contact electrode CTE2 and the second pad electrode APD.

[0221] In an embodiment, the heights of the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be the same as that of the via layer VIA, or may be lower than that of the via layer VIA.

[0222] As will be described later, the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be formed by the same process as the reflective layer RF disposed on the side of the partition wall PW. Therefore, the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may include the same material as the reflective layer RF. For example, the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may include aluminum or silver as a metal material with high light reflectivity, or may include an alloy thereof.

[0223] The reflective layer RF may include a first reflective layer RF1 around (eg, surrounding) a side of the partition wall PW and a second reflective layer RF2 disposed on a flat surface between the partition wall PW and the light emitting element LE. In an embodiment, the first reflective layer RF1 and the second reflective layer RF2 may be continuously connected.

[0224] The flip-chip type light emitting element PLE may be formed by growing on a semiconductor substrate such as a silicon wafer. In an embodiment, each of the flip-chip type light emitting elements PLE may be directly transferred from the silicon wafer to the first pad electrode CPD and the second pad electrode APD of the substrate 110. In another embodiment, each of the flip-chip type light emitting elements PLE may be transferred to the first pad electrode CPD and the second pad electrode APD of the substrate 110 by an electrostatic method using an electrostatic head or by a stamping method using an elastic polymer material such as PDMS or silicone as a transfer substrate.

[0225] In an embodiment, the first contact electrode CTE1 and the first pad electrode CPD and the second contact electrode CTE2 and the second pad electrode APD may be bonded to each other by a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). In another embodiment, the first contact electrode CTE1 and the first pad electrode CPD may be bonded to each other by a welding process.

[0226] Fig.16 is a cross-sectional view schematically showing a display device according to another embodiment. Fig.17 is schematically shown with reference to Fig.16 An enlarged view of the first light emitting region is depicted. Fig.18 It is a reference Fig.16 A plan view of the light-emitting area explained. Fig.19 is an enlarged view of the light emitting element included in 17.

[0227] Figures 16 to 19 Examples and Figures 6 to 10 The embodiment of is different in that the light emitting element is a lateral type light emitting element. Here, the description overlapping with the embodiment described above may be omitted, and the differences will be described.

[0228] Reference Figures 16 to 19 , the light emitting element part LEP may be disposed on the second planarization layer 130. The light emitting element part LEP may include a first pad electrode CPD, a second pad electrode APD, a bank PDL, an organic pattern layer BOL, a lateral light emitting element LLE, a first auxiliary connection electrode SCT, a second auxiliary connection electrode SAT, a horizontal reflective layer RFM, a via layer VIA, a partition wall PW, and a wavelength conversion layer QDL.

[0229] The second planarization layer 130 may have an undercut structure in a portion overlapping the first pad electrode CPD and the second pad electrode APD. For example, the second planarization layer 130 includes a first planarization portion 130-1 disposed on the substrate 110, a second planarization portion 130-2 disposed on the first planarization portion 130-1, and a third planarization portion 130-3 disposed on the first planarization portion 130-1. In an embodiment, the second planarization portion 130-2 and the third planarization portion 130-3 may be arranged to be spaced apart from each other on the same plane. The second planarization portion 130-2 may overlap the first pad electrode CPD, and the third planarization portion 130-3 may overlap the second pad electrode APD.

[0230] The first pad electrode CPD, the second pad electrode APD, and the bank PDL may be formed on the second planarization layer 130. For example, the first pad electrode CPD may be disposed on the second planarization portion 130-2, and the second pad electrode APD may be disposed on the third planarization portion 130-3. The first pad electrode CPD and the second pad electrode APD may be arranged to be spaced apart from each other.

[0231] The bank PDL may be formed to cover a portion of the first pad electrode CPD and the second pad electrode APD. The bank PDL may be formed to cover edges of the first pad electrode CPD and the second pad electrode APD. In an embodiment, the bank PDL may include an inclined portion and a flat portion, the inclined portion overlapping the edges of the first pad electrode CPD and the second pad electrode APD and having a slope (e.g., a predetermined slope), and the flat portion extending from the inclined portion and having a flat plane.

[0232] The first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be disposed on the first pad electrode CPD and the second pad electrode APD, respectively. For example, the first auxiliary connection electrode SCT may be disposed on the first pad electrode CPD, and the second auxiliary connection electrode SAT may be disposed on the second pad electrode APD. The first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be disposed to be spaced apart from each other, and each of the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be disposed on a top surface of the bank PDL along the bank PDL. One end of each of the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be disposed on a flat portion of the bank PDL.

[0233] The horizontal reflective layer RFM may be disposed on the first planarizing portion 130-1 between the second planarizing portion 130-2 and the third planarizing portion 130-3. In an embodiment, the horizontal reflective layer RFM includes the same material as the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT. The horizontal reflective layer RFM may be disposed between the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT, and may be disconnected from the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT by the undercut shape of the second planarizing layer 130.

[0234] The organic pattern layer BOL may be disposed to cover a portion of the first and second auxiliary connection electrodes SCT and SAT and the horizontal reflective layer RFM.

[0235] The lateral light emitting element LLE is disposed on the organic pattern layer BOL.

[0236] The lateral light emitting element LLE may include a first contact electrode CTE1 and a second contact electrode CTE2. In an embodiment, as an example, the first contact electrode CTE1 and the second contact electrode CTE2 may be disposed on a top surface of the lateral light emitting element LLE, and the lateral light emitting element LLE may be a lateral chip type micro LED.

[0237] In an embodiment, the lateral light emitting element LLE may be an inorganic light emitting element made of an inorganic material such as GaN. The lateral light emitting element LLE may have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of several μm to several hundred μm, respectively. For example, the lateral light emitting element LLE may have a size of 10 μm×25 μm, but is not limited thereto.

[0238] The lateral light emitting element LLE may be a light emitting structure including a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, a first contact electrode CTE1, and a second contact electrode CTE2.

[0239] The second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1 of the lateral light emitting element LLE are similar to those of the reference Fig.10 The second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 of the described light emitting element LE correspond, and thus, redundant description will be omitted. The lateral light emitting element LLE may further include a transparent conductive layer TCO on the first semiconductor layer SEM1. The transparent conductive layer TCO may be formed to be transparent to emit light. The transparent conductive layer TCO may be formed of a transparent conductive oxide such as any one of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0240] The lateral light emitting element LLE further includes an element insulating layer INSO. The element insulating layer INSO may be formed around the side surfaces of the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the transparent conductive layer TCO, and the top surface of the transparent conductive layer TCO (for example, formed to surround the side surfaces of the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the transparent conductive layer TCO, and the top surface of the transparent conductive layer TCO). In an embodiment, the element insulating layer INSO has two openings. For example, the element insulating layer INSO includes a first opening OP-L1 and a second opening OP-L2.

[0241] The first contact electrode CTE1 and the second contact electrode CTE2 are disposed in two openings. For example, the first contact electrode CTE1 may be disposed in the first opening OP-L1 and contact the first semiconductor layer SEM1. The second contact electrode CTE2 may be disposed in the second opening OP-L2 and contact the second semiconductor layer SEM2. The lateral light emitting element LLE may further include a recess overlapping the second opening OP-L2. The second semiconductor layer SEM2 may be exposed through the recess. In an embodiment, the second opening OP-L2 may have a diameter wider than the first opening OP-L1.

[0242] The element insulating layer INSO may be disposed to cover the side surface of the recess overlapping the second opening OP-L2. The first and second contact electrodes CTE1 and CTE2 may be formed of a transparent conductive oxide such as any one of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0243] The via layer VIA may be provided to support the lead line LDL connecting the first and second contact electrodes CTE1 and CTE2 with the first and second auxiliary connection electrodes SCT and SAT.

[0244] The lead LDL may be included in the light emitting element portion LEP, and may include a first lead LDL1 connecting the first contact electrode CTE1 with the first auxiliary connection electrode SCT and a second lead LDL2 connecting the second contact electrode CTE2 with the second auxiliary connection electrode SAT.

[0245] The first semiconductor layer SEM1, the first contact electrode CTE1, the first lead LDL1, the first auxiliary connection electrode SCT, and the first pad electrode CPD may be electrically connected, and the second semiconductor layer SEM2, the second contact electrode CTE2, the second lead LDL2, the second auxiliary connection electrode SAT, and the second pad electrode APD may be electrically connected.

[0246] The shape of the via layer VIA is not limited as long as it can support the lead LDL.

[0247] The partition wall PW may be formed on the via layer VIA. The partition wall PW overlaps the bank PDL and does not overlap the lateral light emitting element LLE. The wavelength conversion layer QDL may be disposed in a space formed by the partition wall PW.

[0248] Figures 20 to 38 is a diagram for illustrating a method of manufacturing a display device according to an embodiment.

[0249] Figures 20 to 38 The formation order of the structure of each layer of the display device 10 is shown in cross-sectional views. Figures 20 to 38 It is shown that it can be roughly compared with Figures 6 to 8 and Fig.10 The cross-sectional view of FIG. 1 corresponds to a manufacturing process of the light emitting element portion LEP. In addition, the first light emitting area EA1 of the display device 10 is described below.

[0250] Reference Figure 20 to Figure 24 , a plurality of light emitting elements LE are formed on the base substrate BSUB.

[0251] In an embodiment, a base substrate BSUB is prepared. The base substrate BSUB may be Al 2 O 3 However, the present disclosure is not limited thereto, and in the embodiments, a case in which the base substrate BSUB is a sapphire substrate will be described as an example.

[0252] A plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L are formed on the base substrate BSUB. In an embodiment, a plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L grown by an epitaxial method may be formed by growing a seed crystal. Methods for forming the semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), and the like, and in an embodiment, the semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L are formed by metal organic chemical vapor deposition (MOCVD). However, the present disclosure is not limited thereto.

[0253] The precursor material used to form the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L is not particularly limited within the range that can be conventionally selected for forming the target material. In an example, the precursor material may be a metal precursor including an alkyl group such as a methyl group or an ethyl group. For example, the precursor material may be a metal precursor such as trimethylgallium (Ga(CH 3 ) 3 ), trimethylaluminum (Al(CH3 ) 3 ), triethyl phosphate ((C 2 H 5 ) 3 PO 4 ) compounds, but not limited thereto.

[0254] In an embodiment, a third semiconductor material layer SEM3L is formed on the base substrate BSUB. Although the drawings show a single-layer third semiconductor material layer SEM3L, the present disclosure is not limited thereto, and the third semiconductor material layer SEM3L may be formed as a plurality of layers. The third semiconductor material layer SEM3L may be provided to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer SEM3L may include an undoped semiconductor that may be an n-type or p-type undoped material. In an embodiment, the third semiconductor material layer SEM3L may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0255] In an embodiment, the second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L by using the method described above.

[0256] Next, a reflective material layer RFOL is formed on the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L. The reflective material layer RFOL may be formed to cover all of the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L. In an embodiment, the reflective material layer RFOL may include aluminum (Al) or silver (Ag), or may be an alloy thereof.

[0257] Then, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL are etched.

[0258] In an embodiment, a plurality of first mask patterns MP1 are formed on the reflective material layer RFOL. The first mask pattern MP1 may be a hard mask including an inorganic material or a photoresist mask including an organic material. The first mask pattern MP1 prevents or substantially prevents the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL below from being etched. Next, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, SEM1L and a portion of the reflective material layer RFOL are etched (first etching) using the plurality of first mask patterns MP1 as a mask.

[0259] like Fig.21As shown in the figure, on the base substrate BSUB, portions of the plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L and the reflective material layer RFOL that do not overlap with the first mask pattern MP1 are etched and removed, and portions of the plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L and the reflective material layer RFOL that overlap with the first mask pattern MP1 and are not etched can be formed into a plurality of light emitting elements LE.

[0260] The plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL may be etched by conventional methods. For example, the process of etching the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL may be performed by any one of dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of a dry etching method, anisotropic etching that may be suitable for vertical etching is possible. When the etching method described above is used, the etchant may be Cl 2 or 2 However, the present disclosure is not limited thereto.

[0261] The portions of the plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L and the reflective material layer RFOL overlapping the first mask pattern MP1 are not etched but formed into a plurality of light emitting elements LE and an element reflective layer RFO. Thus, a plurality of light emitting elements LE including the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1 are formed.

[0262] Next, refer to Fig. 22 and Fig.23 , an insulating material layer INSL having an opening OP is formed on the base substrate BSUB on which the light emitting element LE is formed.

[0263] An insulating material layer INSL is formed on the outer surfaces of the plurality of light emitting elements LE. In an embodiment, the insulating material layer INSL may be formed on the entire surface of the base substrate BSUB, and may be formed not only on the light emitting elements LE but also on the top surface of the base substrate BSUB exposed by the light emitting elements LE.

[0264] Then, a second etching is performed to partially remove the insulating material layer INSL to form the insulating material layer INSL having the opening OP on the top surface of the light emitting element LE.

[0265] A second etching process of partially removing the insulating material layer INSL so that the insulating material layer INSL exposes the top surface of the light emitting element LE but surrounds the side of the light emitting element LE may be performed. In this process, a portion of the insulating material layer INSL may be removed to expose at least a portion of the top surface of the element reflective layer RFO of the light emitting element LE. The process of partially removing the insulating material layer INSL may be performed by a mask process.

[0266] Reference Fig.24 , the light emitting element LE can be formed by forming the pad connection electrode PCE on the light emitting element LE.

[0267] For example, the pad connection electrode PCE covering the opening OP of the light emitting element LE is formed by stacking a pad connection electrode material layer on the base substrate BSUB and then etching the pad connection electrode material layer by an etching process. The pad connection electrode material layer is formed of a conductive material and may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the pad connection electrode material layer may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy (SAC305) of copper, silver, and tin.

[0268] Next, refer to Fig.25 Attach the support film SPF1 to Fig.24 Multiple light-emitting elements LE are formed on the base substrate BSUB prepared in the process.

[0269] Specifically, the support film SPF1 is attached to the plurality of light emitting elements LE. The support film SPF1 may be aligned on the plurality of light emitting elements LE and attached to each pad connection electrode PCE of the plurality of light emitting elements LE. The plurality of light emitting elements LE may be arranged in large quantities so that they are attached to the support film SPF1 without being separated from the support film SPF1.

[0270] In an embodiment, the support film SPF1 may be composed of a support layer S2 and an adhesive layer S1 disposed on the support layer S2. The support layer S2 may be made of a material that is transparent and mechanically stable to allow light to pass therethrough. For example, the support layer S2 may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The adhesive layer S1 may include an adhesive material for bonding the light emitting element LE. For example, the adhesive material may include any one of urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material may be a material whose adhesive strength changes when ultraviolet light (UV) or heat is applied, and therefore, the adhesive layer S1 may be easily separated from the light emitting element LE.

[0271] Next, refer to Fig.26, laser (first laser) is irradiated to the base substrate BSUB to separate the light emitting element LE from the base substrate BSUB. The base substrate BSUB is separated from the third semiconductor layer SEM3 of the plurality of light emitting elements LE.

[0272] The process of separating the base substrate BSUB may be performed using a laser lift-off (LLO) process. The laser lift-off process uses laser, and in an embodiment, a KrF excimer laser (248 nm wavelength) may be used as a light source. In an embodiment, the energy density of the excimer laser is about 550 mJ / cm 2 Up to 950mJ / cm 2 The range of illumination can be 50×50μm 2 Up to 1×1cm 2 By irradiating the base substrate BSUB with laser light, the base substrate BSUB can be separated from the light emitting element LE.

[0273] Next, refer to Fig. 27 , the relay substrate SPF2 is attached to the plurality of light emitting elements LE separated from the base substrate BSUB.

[0274] A plurality of light emitting elements LE disposed on the support film SPF1 are aligned on the relay substrate SPF2, and laser LS is irradiated on the support film SPF1. The light emitting elements LE irradiated by the laser LS may be separated from the support film SPF1 and transferred to the relay substrate SPF2. Like the support film SPF1 described above, the relay substrate SPF2 may include a support layer and an adhesive layer to bond and support the plurality of light emitting elements LE.

[0275] Next, refer to Fig.28 , the support film SPF1 is separated from the plurality of light emitting elements LE. By irradiation with the laser LS, the adhesive strength of the adhesive layer S1 of the support film SPF1 may be reduced, and the support film SPF1 may be separated physically or naturally.

[0276] Next, refer to Fig.29 , forming a second planarization layer 130 having an undercut structure.

[0277] Specifically, a substrate 110 is prepared. Figure 6 As described, the substrate 110 may be a substrate on which the second planarization layer 130 , the first pad electrode CPD, and the second pad electrode APD are formed.

[0278] The second planarization layer 130 may include a first planarization portion 130 - 1 disposed on the substrate 110 , and a second planarization portion 130 - 2 and a third planarization portion 130 - 3 formed on the first planarization portion 130 - 1 .

[0279] The side surface of the second planarizing portion 130-2 is etched to have an undercut structure that is recessed from the side surface of the first pad electrode CPD toward the center portion thereof. In addition, the side surface of the third planarizing portion 130-3 is etched to have an undercut structure that is recessed from the side surface of the second pad electrode APD toward the center portion thereof. For example, the etching process is performed by supplying an etchant to the second planarizing layer 130. The second planarizing portion 130-2 and the third planarizing portion 130-3 coated with the etchant are selectively etched. In an embodiment, the etchant processing time includes not only a first processing time for completely removing a portion of the second planarizing layer 130 that is not overlapped with the first pad electrode CPD and the second pad electrode APD and is located at the same level as the second planarizing portion 130-2 and the third planarizing portion 130-3, but also a second processing time for forming the undercut structure of the second planarizing portion 130-2 and the third planarizing portion 130-3 in the region overlapping with the first pad electrode CPD and the second pad electrode APD. For example, if the first process time is approximately 60 seconds and the second process time is α seconds, the etchant process is performed for a time of (60 seconds + α seconds).

[0280] After the first treatment time, a portion of the second planarizing layer 130 in a region not overlapping the first pad electrode CPD and the second pad electrode APD and located at the same level as the second planarizing portion 130-2 and the third planarizing portion 130-3 is removed to expose the first planarizing portion 130-1, and the side surfaces of the second planarizing portion 130-2 and the third planarizing portion 130-3 in a region overlapping the first pad electrode CPD and the second pad electrode APD are exposed. After the second treatment time, the side surfaces of the second planarizing portion 130-2 and the third planarizing portion 130-3 have an undercut-like shape having an inward depression.

[0281] Then, refer to Fig.30 and Fig.31 , the plurality of light emitting elements LE arranged on the relay substrate SPF2 are transferred to the substrate 110 .

[0282] In an embodiment, an organic pattern material layer BOLL is entirely coated on the second planarization layer 130 on which the first pad electrode CPD and the second pad electrode APD are disposed. In an embodiment, the organic pattern material layer BOLL may be coated to a thickness of about 2 μm, but is not limited thereto. At this stage, the organic pattern material layer BOLL is not cured but is in a fluid state, which may be referred to as a pseudo adhesive layer.

[0283] Next, the relay substrate SPF2 is aligned on the substrate 110. The pad connection electrode PCE of the light emitting element LE grown on the relay substrate SPF2 is aligned to be disposed on the second pad electrode APD of the substrate 110 with the organic pattern material layer BOLL interposed therebetween.

[0284] Next, the substrate 110 is bonded to the relay substrate SPF2. The pad connection electrode PCE of the light emitting element LE to which the relay substrate SPF2 is attached is attached and in contact with the organic pattern material layer BOLL. Next, heat and pressure are applied to the organic pattern material layer BOLL to cure the organic pattern material layer BOLL. As a result, the light emitting element LE and the organic pattern material layer BOLL can be bonded to each other. In this way, the heat and pressure of the process of curing the organic pattern material layer BOLL to bond the light emitting element LE are lower than the heat and pressure of the eutectic bonding process. For example, when the eutectic bonding process is a relatively high temperature process of about 200 to 400 degrees Celsius, the organic material curing process can be a relatively low temperature process of 80 to 200 degrees Celsius. Therefore, compared with the eutectic bonding process, the light emitting element LE can be bonded to the substrate 110 at a relatively low temperature and pressure.

[0285] At this time, the relay substrate SPF2 is separated from the plurality of light emitting elements LE. After applying ultraviolet rays or heat to the relay substrate SPF2 to reduce the adhesive strength of the adhesive layer of the relay substrate SPF2, the relay substrate SPF2 may be physically or naturally separated from the plurality of light emitting elements LE.

[0286] Next, refer to Fig.32 , the organic pattern layer BOL overlapping the light emitting element LE may be formed by ashing the portion of the organic pattern material layer BOLL that does not overlap the light emitting element LE. When the portion of the organic pattern material layer BOLL that does not overlap the light emitting element LE is ashed, the side surface PCE-S of the pad connection electrode PCE disposed on the side surface of the light emitting element LE may be exposed. In an embodiment, the third semiconductor layer SEM3 of the light emitting element LE has low conductivity and may be removed so that the second semiconductor layer SEM2 is connected to the first auxiliary connection electrode SCT. The third semiconductor layer SEM3 may be removed by a chemical polishing process, an etching process, or the like.

[0287] Next, refer to Fig.33 , a partition wall PW is formed on the second planarization layer 130 .

[0288] In an embodiment, a negative photoresist is used to form the partition wall PW on the second planarization layer 130. Since a portion of the negative photoresist that does not receive light is dissolved, the partition wall PW may be formed in an inverted tapered shape having a width that narrows downward.

[0289] Next, refer to Fig.34 In an embodiment, a reflective material layer RFL is deposited on the entire surface of the substrate 110 on which the partition wall PW is formed. The reflective material layer RFL may be formed to cover both the partition wall PW and the light emitting element LE.

[0290] The reflective material layer RFL is formed on the top and side of the partition wall PW, the top and side of the light emitting element LE, and the bottom (top surface of the second planarization layer 130) between the light emitting element LE and the partition wall PW. The reflective material layer RFL is disposed along the side of the light emitting element LE, the side PCE-S of the pad connection electrode PCE, the side of the organic pattern layer BOL, the first pad electrode CPD, and the second pad electrode APD, and is disconnected by the undercut-like structure of the second planarization portion 130-2 and the third planarization portion 130-3 of the second planarization layer 130. The reflective material layer RFL disposed along the side of the light emitting element LE, the side PCE-S of the pad connection electrode PCE, the side of the organic pattern layer BOL, the first pad electrode CPD, and the second pad electrode APD is disposed discontinuously with the reflective material layer RFL deposited on the bottom surface SB of the space S formed by the partition wall PW. The reflective material layer RFL disposed along the side of the light emitting element LE, the side PCE-S of the pad connection electrode PCE, the side of the organic pattern layer BOL, the first pad electrode CPD, and the second pad electrode APD may be spaced apart from the reflective material layer RFL deposited on the bottom surface SB of the space S formed by the partition wall PW. The reflective material layer RFL may include, for example, aluminum (Al) or silver (Ag), or may be an alloy thereof.

[0291] Next, refer to Fig.35 , a via layer VIA is formed in the space S formed by the partition wall PW. The via layer VIA may be coated using a solution process such as spin coating or inkjet printing. The via layer VIA may be formed to be lower than the height of the light emitting element LE. For example, the top surface of the light emitting element LE may be set higher than the via layer VIA.

[0292] Reference Fig.36 and Fig.37 , a portion of the reflective material layer RFL is removed to form the reflective layer RF on the side of the partition wall PW, and the first and second auxiliary connection electrodes SCT and SAT are formed.

[0293] For example, refer to Fig.36 , a photoresist mask pattern PR is formed on a portion of the top surface of the light emitting element LE overlapping the first pad electrode CPD.

[0294] A second etching that partially removes the reflective material layer RFL is performed to form the reflective layer RF, the first auxiliary connection electrode SCT, and the second auxiliary connection electrode SAT.

[0295] In an embodiment, a second etching process may be performed to partially remove a portion of the reflective material layer RFL so that the reflective material layer RFL exposes the top surface of the light emitting element LE but surrounds the side of the light emitting element LE. At this time, a portion of the reflective material layer RFL overlapping the photoresist mask pattern PR, a portion of the reflective material layer RFL covered by the via layer VIA, and a portion of the reflective material layer RFL located on the side surface of the partition wall PW are not etched.

[0296] Reference Fig.38 , a wavelength conversion layer QDL is formed in a space formed in the partition wall PW.

[0297] For example, a solution mixed with the first matrix resin BRS1, the first wavelength conversion particles WCP1, and the scatterer SCP may be dropped in the space formed in the partition wall PW by a solution process such as inkjet printing, stamping, etc., but is not limited thereto. Each wavelength conversion layer QDL may be formed in a plurality of openings and may be formed to overlap a plurality of light emitting regions.

[0298] Then, if Figure 6 As shown in FIG, a capping layer CAP, a first overcoat layer OC1, a color filter, and a second overcoat layer OC2 are formed on the partition wall PW and the wavelength conversion layer QDL.

[0299] In an embodiment, the color filter may be formed by a photolithography process. In an embodiment, the thickness of the color filter may be 1 μm or less, but is not limited thereto. Similarly, other color filters are formed by a patterning process to overlap with the respective openings.

[0300] Figure 39 to Figure 43 is a diagram for illustrating a method of manufacturing a display device according to another embodiment.

[0301] Figure 39 to Figure 43 The structure of each layer of the display device 10 is shown in a cross-sectional view. Figure 39 to Figure 43 Focus on Fig.13 The cross-sectional view of FIG. 1 basically corresponds to the manufacturing process of the light emitting element portion LEP. In addition, the following description will focus on the first light emitting area EA1 of the display device 10.

[0302] First, the flip-chip light emitting element PLE is bonded onto the second planarization layer 130 having the undercut structure through the organic pattern layer BOL.

[0303] Reference Fig.29 The method of forming the second planarization layer 130 having an undercut-like structure is described, and the method of bonding the flip-chip type light emitting element PLE through the organic pattern layer BOL can be compared with the reference Figure 30 to Figure 32 The method of bonding the light emitting element LE through the organic pattern layer BOL is the same, and a redundant description thereof will be omitted.

[0304] Next, refer to Fig.39 , a partition wall PW is formed on the second planarization layer 130 on which the flip-chip type light emitting element PLE is disposed.

[0305] In an embodiment, a negative photoresist is used to form the partition wall PW on the second planarization layer 130. A portion of the negative photoresist that does not receive light is dissolved, and the partition wall PW may be formed in an inverse tapered shape having a width that narrows downward.

[0306] Next, refer to Fig.40 In an embodiment, a reflective material layer RFL is deposited on the entire surface of the substrate 110 on which the partition wall PW is formed. The reflective material layer RFL may be formed to cover both the partition wall and the light emitting element LE.

[0307] The reflective material layer RFL is formed on the top and side surfaces of the partition wall PW, the top and side surfaces of the light emitting element LE, and the bottom (top surface of the second planarization layer 130) between the flip-chip type light emitting element PLE and the partition wall PW. The reflective material layer RFL is disposed along the side surface of the flip-chip type light emitting element PLE, the side surface of the first contact electrode CTE1, the side surface of the second contact electrode CTE2, the side surface of the organic pattern layer BOL, the side surface of the first pad electrode CPD, and the side surface of the second pad electrode APD, but is cut by the undercut-like structure of the second planarization portion 130-2 and the third planarization portion 130-3 of the second planarization layer 130. The reflective material layer RFL disposed along the side surface of the light emitting element LE, the side surface of the first contact electrode CTE1, the side surface of the second contact electrode CTE2, the side surface of the organic pattern layer BOL, the side surface of the first pad electrode CPD, and the side surface of the second pad electrode APD is disposed discontinuously with the reflective material layer RFL deposited on the bottom surface SB of the space S formed by the partition wall PW. The reflective material layer RFL disposed along the side surface of the light emitting element LE, the side surface of the first contact electrode CTE1, the side surface of the second contact electrode CTE2, the side surface of the organic pattern layer BOL, the side surface of the first pad electrode CPD, and the side surface of the second pad electrode APD may be spaced apart from the reflective material layer RFL deposited on the bottom surface SB of the space S formed by the partition wall PW. The reflective material layer RFL may include, for example, aluminum (Al) or silver (Ag), or may be an alloy thereof.

[0308] Next, refer to Fig.41 , a via layer VIA is formed in the space formed by the partition wall PW. The via layer VIA may be coated using a solution process such as spin coating or inkjet printing. The via layer VIA may be formed to be lower than the height of the light emitting element LE. For example, the top surface of the light emitting element LE may be higher than the via layer VIA.

[0309] Reference Fig.42 , a portion of the reflective material layer RFL is removed to form the reflective layer RF on the side of the partition wall PW, and the first and second auxiliary connection electrodes SCT and SAT are formed.

[0310] A second etching that partially removes the reflective material layer RFL is performed to form the reflective layer RF, the first auxiliary connection electrode SCT, and the second auxiliary connection electrode SAT.

[0311] For example, a portion of the reflective material layer RFL that is on the flip-chip type light emitting element PLE and that protrudes above the via layer VIA may be removed.

[0312] Reference Fig.43 , a wavelength conversion layer QDL is formed in a space formed in the partition wall PW.

[0313] For example, a solution mixed with the first matrix resin BRS1, the first wavelength conversion particles WCP1, and the scatterer SCP may be dropped in the space formed in the partition wall PW by a solution process such as inkjet printing, stamping, etc., but is not limited thereto. Each wavelength conversion layer QDL may be formed in a plurality of openings and may be formed to overlap a plurality of light emitting regions.

[0314] Then, if Fig.12 As shown in FIG, a capping layer CAP, a first overcoat layer OC1, a color filter, and a second overcoat layer OC2 are formed on the partition wall PW and the wavelength conversion layer QDL.

[0315] The color filter may be formed by a photolithography process. In an embodiment, the thickness of the color filter may be 1 μm or less, but is not limited thereto. Similarly, other color filters are also formed by a patterning process to overlap each opening.

[0316] Figures 44 to 50 is a diagram for illustrating a method of manufacturing a display device according to another embodiment.

[0317] Figures 44 to 50 Cross-sectional views of the structure of each layer of the display device 10 are respectively shown in the order of formation. Figures 44 to 50 Focus on Fig.17 The cross-sectional view of FIG. 1 basically corresponds to the manufacturing process of the light emitting element portion LEP. In addition, the following description will focus on the first light emitting area EA1 of the display device 10.

[0318] Reference Fig.44 , forming a second planarization layer 130 having an undercut structure. The second planarization layer 130 having an undercut structure can be formed with reference Fig.29 The second planarization layer 130 described is the same and further description thereof will be omitted.

[0319] Reference Fig.45 , a bank PDL may be formed on the second planarization layer 130. In an embodiment, the bank PDL may be formed by a photolithography process. The bank PDL may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0320] The bank PDL may be formed to cover edges of the first pad electrode CPD and the second pad electrode APD. The bank PDL may include an inclined portion overlapping the edges of the first pad electrode CPD and the second pad electrode APD and having a slope (eg, a predetermined inclination), and a flat portion extending from the inclined portion and having a flat plane.

[0321] Next, refer to Fig.46 and Fig.47 , a first auxiliary connection electrode SCT, a second auxiliary connection electrode SAT, and a horizontal reflective layer RFM may be formed on the bank PDL and the first pad electrode CPD and the second pad electrode APD. The first auxiliary connection electrode SCT, the second auxiliary connection electrode SAT, and the horizontal reflective layer RFM may be formed by the same process, and the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be disconnected from the horizontal reflective layer RFM by an undercut structure. An organic pattern material layer BOL may be formed, and a lateral light emitting element LLE may be bonded.

[0322] The organic pattern material layer BOL is formed to cover the first pad electrode CPD and the second pad electrode APD, and is disposed on the lateral light emitting element LLE on the organic pattern material layer BOL. The lateral light emitting element LLE is disposed on the organic pattern material layer BOL so that the first contact electrode CTE1 and the second contact electrode CTE2 face upward. The first contact electrode CTE1 may be disposed close to the first pad electrode CPD, and the second contact electrode CTE2 may be disposed close to the second pad electrode APD. Then, the lateral light emitting element LLE may be bonded to the second planarization layer 130 by curing the organic pattern material layer BOL.

[0323] Next, refer to Fig.48 A via layer VIA partially exposing the first auxiliary connection electrode SCT and the second auxiliary connection electrode SAT may be formed. In an embodiment, a height of the via layer VIA may be formed to be higher than a height of the lateral light emitting element LLE, but is not limited thereto.

[0324] Reference Fig.49, forming a first lead LDL1 connecting the first contact electrode CTE1 of the lateral light emitting element LLE and the first auxiliary connection electrode SCT, and forming a second lead LDL2 connecting the second contact electrode CTE2 and the second auxiliary connection electrode SAT. One end of the first lead LDL1 is disposed on the first contact electrode CTE1 and disposed along the via layer VIA, and the other end is disposed on the first auxiliary connection electrode SCT. One end of the second lead LDL2 is disposed on the second contact electrode CTE2 and disposed along the via layer VIA, and the other end is disposed on the second auxiliary connection electrode SAT.

[0325] Reference Fig.50 , a partition wall PW and a wavelength conversion layer QDL are formed on the via layer VIA.

[0326] In an embodiment, a negative photoresist is used to form the partition wall PW on the second planarization layer 130. A portion of the negative photoresist that does not receive light is dissolved, and the partition wall PW may be formed in an inverse tapered shape having a width that narrows downward.

[0327] The wavelength conversion layer QDL is formed in the space formed in the partition wall PW. For example, a solution mixed with the first matrix resin BRS1, the first wavelength conversion particles WCP1 and the scatterer SCP may be dropped into the space formed in the partition wall PW by a solution process such as inkjet printing, embossing, etc., but is not limited thereto. Each wavelength conversion layer QDL may be formed in a plurality of openings and may be formed to overlap with a plurality of light emitting regions.

[0328] Fig.51 is a diagram illustrating an example of a virtual reality device including a display device according to an embodiment. Fig.51 A virtual reality device 1 including a display device 10 according to an embodiment is shown.

[0329] Reference Fig.51 The virtual reality device 1 according to the embodiment may be a device in the form of glasses. The virtual reality device 1 according to the embodiment may include a display device 10, a left eye lens 10a, a right eye lens 10b, a support frame 20, a left leg 30a and a right leg 30b, a reflective member 40, and a display device housing 50.

[0330] Fig.51 The virtual reality device 1 including two legs 30a and 30b is shown. However, the disclosure is not limited thereto. For example, the virtual reality device 1 according to the embodiment may be used in a head mounted display including a headband that can be worn on the head instead of the legs 30a and 30b. For example, the virtual reality device 1 according to the embodiment may not be limited to Fig.51 The examples shown in and can be applied to various electronic devices in various forms.

[0331] The display device housing 50 can accommodate the display device 10 and the reflective member 40. The image displayed on the display device 10 can be reflected from the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user can watch the virtual reality image displayed on the display device 10 through the right eye.

[0332] Fig.51 It is shown that the display device housing 50 is disposed at the right end of the supporting frame 20. However, the disclosed embodiments are not limited thereto. For example, the display device housing 50 may be disposed at the left end of the supporting frame 20. In this case, the image displayed on the display device 10 may be reflected from the reflective member 40 and provided to the user's left eye via the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10 via the left eye. As another example, the display device housing 50 may be disposed at each of the left end and the right end of the supporting frame 20. In this case, the user can view the virtual reality image displayed on the display device 10 via both the left eye and the right eye.

[0333] Fig.52 is a diagram illustrating an example of a smart device including a display device according to an embodiment.

[0334] Reference Fig.52 , the display device 10 according to the embodiment may be applied to a smart watch 2 as an example of a smart device.

[0335] Fig.53 is a diagram showing an example of a vehicle including a display device according to an embodiment. Fig.53 A vehicle in which display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to the embodiment are included is shown.

[0336] Reference Fig.53 The display devices 10_a, 10_b, and 10_c according to the embodiment may be applied to a dashboard of a vehicle, to a center console panel of a vehicle, or to a central information display (CID) provided on a dashboard of a vehicle. In addition, each of the display devices 10_d and 10_e according to the embodiment may be applied to an interior mirror display replacing each of the side mirrors of the vehicle.

[0337] Fig.54 is a diagram showing an example of a transparent display device including a display device according to an embodiment.

[0338] Reference Fig.54, the display device 10 according to the embodiment can be applied to a transparent display device. The transparent display device can transmit light therethrough while displaying an image IM thereon. Therefore, a user located in front of the transparent display device can view not only the image IM displayed on the display device 10, but also a target RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 6 The substrate 110 of the display device 10 shown in FIG. 1 may include a light-transmitting portion through which light may be transmitted, or may be made of a material through which light may be transmitted.

[0339] Although some embodiments have been described in the above detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles of the disclosure. Therefore, the disclosed embodiments disclosed herein may be understood to be used in a general and descriptive sense rather than for purposes of limitation.

Claims

1. A display device, comprising: A planarization layer, comprising a first planarization portion on a substrate, and a second planarization portion and a third planarization portion on the first planarization portion; a first pad electrode and a second pad electrode, the first pad electrode being on the second planarized portion, and the second pad electrode being on the third planarized portion; an organic pattern layer on the first pad electrode and the second pad electrode; A light emitting element, on the organic pattern layer, comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a partition wall on a surface of the first planarized portion and defining a space around the light emitting element; a reflective layer on the side surface of the partition wall and the first planarized portion in the space; a first auxiliary connection electrode, connecting the second semiconductor layer and the first pad electrode; as well as a second auxiliary connection electrode, connecting the first semiconductor layer and the second pad electrode, The planarization layer has an undercut shape in which a side surface of the second planarization portion is recessed toward a center of the first pad electrode, and a side surface of the third planarization portion is recessed toward a center of the second pad electrode.

2. The display device according to claim 1, wherein: The reflective layer includes a first reflective layer on a side surface of the partition wall and a second reflective layer on an upper portion of the first planarized portion, The second reflective layer extends from the first reflective layer and is disconnected from the first auxiliary connecting electrode and the second auxiliary connecting electrode by the undercut shape.

3. The display device according to claim 2, wherein: The first auxiliary connection electrode and the second auxiliary connection electrode include the same material as the reflective layer.

4. The display device according to claim 2, wherein: The first pad electrode and the second pad electrode are spaced apart from each other on the same plane and protrude outward from the light emitting element.

5. The display device according to claim 4, wherein: The light emitting element further comprises: an element reflection layer on the bottom surface of the first semiconductor layer; an element insulating layer around a side surface of the element reflective layer, a side surface of the first semiconductor layer, a side surface of the active layer, and a side surface of the second semiconductor layer; and A pad connection electrode, on the bottom surface of the element reflection layer, a first end portion of the pad connection electrode is in direct contact with the second auxiliary connection electrode.

6. The display device according to claim 5, wherein: The first auxiliary connection electrode includes a first end portion on a top surface of the second semiconductor layer, extends along a side surface of the light emitting element and a side surface of the organic pattern layer, and also includes a second end portion on a side surface of the first pad electrode, The second auxiliary connection electrode includes a first end on the side of the light-emitting element, extends along the side of the light-emitting element, the first end of the pad connection electrode and the side of the organic pattern layer, and also includes a second end on the side of the second pad electrode.

7. The display device according to claim 6, further comprising a via layer and a wavelength conversion layer sequentially arranged in the space, in, The height of the second auxiliary connection electrode is equal to or lower than the height of the via layer.

8. The display device according to claim 4, wherein: The light emitting element further comprises: a base substrate, on the second semiconductor layer; a first contact electrode on the first surface of the second semiconductor layer; and a second contact electrode on the first surface of the first semiconductor layer, and The first contact electrode and the second contact electrode are arranged to be spaced apart from each other and bonded to the organic pattern layer.

9. The display device according to claim 8, wherein: The first auxiliary connection electrode includes a first end portion on a side of the light emitting element, extends along the side of the light emitting element, the first end portion of the first contact electrode and a side of the organic pattern layer, and also includes a second end portion on a side of the first pad electrode, The second auxiliary connection electrode includes a first end on a side of the light emitting element, extends along the side of the light emitting element, the first end of the second contact electrode and a side of the organic pattern layer, and also includes a second end on a side of the second pad electrode.

10. The display device according to claim 9, further comprising a via layer and a wavelength conversion layer sequentially arranged in the space, in, A height of the first auxiliary connection electrode and a height of the second auxiliary connection electrode are equal to or smaller than a height of the via layer.

11. The display device according to claim 3, further comprising: The via layer and the wavelength conversion layer are sequentially arranged in the space; as well as A cover layer, an overcoat layer and a color filter layer are sequentially arranged on the wavelength conversion layer and the partition wall.

12. A display device, comprising: A planarization layer, comprising a first planarization portion on a substrate, and a second planarization portion and a third planarization portion on the first planarization portion; a first pad electrode and a second pad electrode, the first pad electrode being on the second planarized portion, and the second pad electrode being on the third planarized portion; a bank covering a portion of the first pad electrode and a portion of the second pad electrode; a first auxiliary connection electrode including a first end portion contacting the first pad electrode and a second end portion on a top surface of the bank; a second auxiliary connection electrode including a first end portion contacting the second pad electrode and a second end portion on the top surface of the bank; an insulating organic layer overlapping the first pad electrode and the second pad electrode and covering a portion of the first auxiliary connection electrode and a portion of the second auxiliary connection electrode; a light emitting element on the insulating organic layer and including a first contact electrode and a second contact electrode on a top surface thereof; as well as a first lead and a second lead, connecting the first contact electrode to the first auxiliary connection electrode and connecting the second contact electrode to the second auxiliary connection electrode, respectively; The second planarization portion has an undercut shape in which a side surface of the second planarization portion is recessed toward a center of the first pad electrode, the third planarization portion has an undercut shape in which a side surface of the third planarization portion is recessed toward a center of the second pad electrode, and a horizontal reflective layer is located between the second planarization portion and the third planarization portion.

13. The display device according to claim 12, wherein: The horizontal reflective layer is located between the first auxiliary connection electrode and the second auxiliary connection electrode, and is disconnected from the first auxiliary connection electrode and the second auxiliary connection electrode by the undercut shape of the second planarizing portion and the undercut shape of the third planarizing portion.

14. The display device according to claim 13, wherein: The horizontal reflective layer includes the same material as the first auxiliary connection electrode and the second auxiliary connection electrode.

15. The display device according to claim 12, wherein: The light emitting element further comprises a first semiconductor layer, an active layer, a second semiconductor layer and an element insulating layer. The element insulating layer surrounds the side surface of the first semiconductor layer, the side surface of the active layer and the side surface of the second semiconductor layer. The first contact electrode contacts the first semiconductor layer, and the second contact electrode contacts the second semiconductor layer.

16. The display device according to claim 15, wherein: A first end of the first lead is on the first contact electrode, and a second end of the first lead is on the first auxiliary connection electrode, and The first end of the second lead is on the second contact electrode, and the second end of the second lead is on the second auxiliary connection electrode.

17. A method for manufacturing a display device, the method comprising the following steps: Disposing a first planarizing portion and a second planarizing portion and a third planarizing portion on the first planarizing portion; disposing a first pad electrode and a second pad electrode on the second planarizing portion and the third planarizing portion respectively; etching the second planarization portion and the third planarization portion to expose the first planarization portion; forming an undercut shape in which side surfaces of the second planarizing portion and the third planarizing portion are recessed toward centers of the first pad electrode and the second pad electrode, respectively; Disposing an organic pattern layer and a light emitting element on the first pad electrode and the second pad electrode; forming a partition wall on the first planarized portion to surround the light emitting element; depositing a layer of reflective material to cover both the partition wall and the light emitting element; forming a via layer in a space defined by the partition wall; forming a photoresist mask pattern to cover a portion of the light emitting element; as well as A reflective layer and a first auxiliary connection electrode and a second auxiliary connection electrode are formed by etching a reflective material layer on the via layer and the photoresist mask pattern.

18. The method according to claim 17, wherein: The reflective layer includes a first reflective layer on a side surface of the partition wall and a second reflective layer on an upper portion of the first planarized portion, The second reflective layer is configured to extend from the first reflective layer and is disconnected from the first auxiliary connection electrode and the second auxiliary connection electrode by the undercut shape.

19. The method according to claim 17, wherein the step of providing the organic pattern layer and the light emitting element on the first pad electrode and the second pad electrode comprises: coating an organic pattern material layer on a substrate to cover the first planarization portion, the second planarization portion, the third planarization portion, the first pad electrode, and the second pad electrode; disposing the light emitting element to overlap with the first pad electrode and the second pad electrode on the organic pattern material layer; bonding the light emitting element by curing the organic pattern material layer; as well as The organic pattern layer is formed by ashing a portion of the organic pattern material layer that does not overlap the light emitting element.

20. The method according to claim 17, further comprising the steps of: forming a wavelength conversion layer in the space defined by the partition wall; as well as An overcoat layer and a color filter layer are formed, the overcoat layer and the color filter layer being sequentially disposed on the partition wall and the wavelength conversion layer.

Images