Display panel and wearable display device

By setting curved and extended anti-crack grooves in the display panel and combining them with a flat layer of organic and inorganic materials, the cracking problem of small display devices is solved, achieving a balance between anti-crack effect and structural adaptability.

CN119630194BActive Publication Date: 2026-03-17WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-11-29
Publication Date
2026-03-17

AI Technical Summary

Technical Problem

Smaller display devices, such as smartwatches and fitness trackers, are prone to cracking when their display panels are curved. Existing anti-crack groove designs have inherent defects and are difficult to effectively prevent cracking.

Method used

Multiple spaced, curved, extended anti-crack grooves are set in the display panel, and these grooves are filled with a planarization layer. The planarization layer and the insulating layer are designed alternately, using a combination of organic and inorganic materials to balance the width-to-thickness ratio of the anti-crack grooves and enhance the bonding strength.

Benefits of technology

It effectively prevents cracks from forming at the edges of the display panel in smaller display devices, while also taking into account structural adaptability and bonding strength, making it suitable for smaller wearable display devices.

✦ Generated by Eureka AI based on patent content.

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Abstract

This application discloses a display panel and a wearable display device. The display panel includes: a substrate; an insulating layer with multiple spaced, curved, extending anti-crack grooves; and a planarization layer that fills at least to the anti-crack grooves. The width of the anti-crack grooves is W1 μm; the thickness of the planarization layer is H1 μm; and the ratio of W1 to H1 is between 1.25 and 2.5. This application, through a balanced setting of the width of the anti-crack grooves and the thickness of the planarization layer, effectively prevents the formation of crack curves at the edges of the display panel of a small-sized wearable display device.
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Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a wearable display device. Background Technology

[0002] In related technologies, display panels with curved edges are prone to cracking. Anti-crack grooves can be set on the display panels of larger display devices to prevent cracks from forming.

[0003] However, this is more pronounced on smaller display devices (such as smartwatches and fitness trackers), especially when the anti-crack grooves themselves are designed with an arc shape to fit the panel, the anti-crack grooves themselves may also develop crack defects. Summary of the Invention

[0004] As a first aspect of this application, an embodiment of this application provides a display panel, the display panel comprising: a substrate; an insulating layer having a plurality of spaced, curved, extending anti-crack grooves; a planarization layer filling at least to the anti-crack grooves; wherein the width of the anti-crack grooves is W1μm; the thickness of the planarization layer is H1μm; and the ratio of W1 to H1 ranges from 1.25 to 2.5.

[0005] Optionally, in some embodiments of this application, the display panel further includes: an organic layer disposed on the surface opposite to the substrate; and a touch layer disposed between the planarization layer and the organic layer.

[0006] Optionally, in some embodiments of this application, the display panel further includes a buffer layer disposed between the substrate and the insulating layer and / or the planarization layer.

[0007] Optionally, in some embodiments of this application, the insulating layer includes a gate insulating layer and an interlayer dielectric layer.

[0008] Optionally, in some embodiments of this application, the gate insulating layer is disposed between the buffer layer and the interlayer dielectric layer.

[0009] Optionally, in some embodiments of this application, the interlayer dielectric layer is disposed between the gate insulating layer and the planarization layer.

[0010] Optionally, in some embodiments of this application, the gate insulating layer and / or the interlayer dielectric layer are made of inorganic insulating material, and the planarization layer is made of organic insulating material; the anti-crack trench is disposed between the stacked structures formed by the two gate insulating layers and the interlayer dielectric layer.

[0011] Optionally, in some embodiments of this application, the thickness of the portion of the planarization layer extending beyond the insulating layer ranges from 1.16 μm to 2.34 μm.

[0012] Optionally, in some embodiments of this application, the thickness of the portion of the planarization layer extending beyond the insulating layer is H2 μm; the values ​​of W1 and H2 range from 2.93 to 5.87.

[0013] Optionally, in some embodiments of this application, the distance between the anti-crack grooves ranges from 3.45 μm to 6.9 μm.

[0014] Optionally, in some embodiments of this application, the distance between the anti-crack grooves is W2μm, and the ratio of W1 to W2 ranges from 0.99 to 1.99.

[0015] Optionally, in some embodiments of this application, as a second aspect of this application, embodiments of this application provide a wearable display device, including the aforementioned display panel.

[0016] The beneficial effects provided by the embodiments of this application include at least the following:

[0017] By balancing the width of the anti-crack groove and the thickness of the flattening layer, the structure can be adapted to smaller panel sizes while preventing crack formation.

[0018] Other beneficial effects of the embodiments of this application will be further explained in the following specific embodiments. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a display panel provided in some embodiments of this application;

[0020] Figure 2 This is a schematic diagram of a portion of the structure of a display panel provided in some embodiments of this application;

[0021] Figure 3 This is a schematic diagram of another part of the structure of a display panel provided in some embodiments of this application;

[0022] Figure 4 This is a schematic diagram of the extension of the anti-crack groove of a display panel provided in some embodiments of this application;

[0023] Figure 5 This is a schematic diagram of the structure of a wearable display device provided in an optional embodiment of this application.

[0024] Meaning of the reference numerals in the attached figures:

[0025] 100, Display panel; 110, Substrate; 110a, Substrate edge;

[0026] 120. Insulating layer; 120a. Crack-resistant trench; 121. Gate insulating layer; 122. Interlayer dielectric layer;

[0027] 130. Planarization layer; 140. Organic layer; 150. Touch layer; 160. Buffer layer;

[0028] C1, the dividing line. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0030] Furthermore, in the embodiments of this application, "multiple" refers to two or more. The terms "first" and "second," etc., in the embodiments of this application are used to distinguish different technical features and do not indicate any order, quantity, or importance.

[0031] The directional terms used in this application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", and "side", are only for the directions shown in the accompanying drawings. The directional terms used herein are for the purpose of explaining and illustrating this application, and not for limiting the scope of protection of this application.

[0032] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and this application does not limit the dimensions and thicknesses of each component.

[0033] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0034] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0035] Reference Figures 1 to 4 As shown, the display panel 100 of this application includes: a substrate 110, an insulating layer 120, and a planarization layer 130. Of course, other functional layers such as a light-emitting layer (not shown in the figure) may also be provided.

[0036] The substrate 110 provides the base for the panel, and the substrate 110 may be constructed using a barrier layer (PB layer, not shown in the figure).

[0037] In some embodiments of this application, the gate insulating layer 121 and / or the interlayer dielectric layer 122 are made of inorganic insulating material, and the planarization layer 130 is made of organic insulating material; the anti-crack trench 120a is disposed between the stacked structures formed by the two gate insulating layers 121 and the interlayer dielectric layer 122.

[0038] A unified "insulating layer" is formed by alternating planarization layer 130 and insulating layer 120. From a structural perspective, they are combined in a "dam" and "groove" manner, and from a material perspective, they are combined in an "organic" and "inorganic" manner. This avoids the need for additional film layer structures and utilizes the interface difference between organic and inorganic layers to block the extension of cracks. In addition, the inward shrinkage of the touch layer 150 covered on the planarization layer 130, which is made of inorganic material, and the contact between the organic layer 140, which is made of organic material, and the planarization layer 130, both improve the longitudinal interlayer bonding ability of the display panel 100 and prevent the generation of cracks in the longitudinal direction.

[0039] The insulating layer 120 has multiple spaced, curved, extending anti-crack grooves 120a; the planarization layer 130 fills at least to the anti-crack grooves 120a; the width of the anti-crack grooves 120a is W1μm; the thickness of the planarization layer 130 is H1μm; and the ratio of W1 to H1 ranges from 1.25 to 2.5.

[0040] By adopting this solution, the anti-crack groove 120a at the edge of the display panel of a smaller wearable display device can effectively prevent the generation of crack curves by balancing the width of the anti-crack groove 120a and the thickness of the flattening layer 130.

[0041] This balances the anti-crack effect of the anti-crack groove 120a with the bonding effect of the flat layer 130.

[0042] More specifically, the ratio of W1 to H1 can be in the range of 1.5 to 2.25, 1.8 to 2, etc., or the ratio of W1 to H1 can be in the range of 1.25 to 1.5, 1.6 to 2, 2 to 2.25, 2.25 to 2.5, etc.

[0043] Reference Figures 1 to 4 As shown, in some embodiments of this application, the display panel 100 further includes an organic layer 140 and a touch layer 150. The organic layer 140 is disposed on the surface opposite to the substrate 110; the touch layer 150 is disposed between the planarization layer 130 and the organic layer 140.

[0044] In some embodiments of this application, the display panel 100 further includes a buffer layer 160. The buffer layer 160 is disposed between the substrate 110 and the insulating layer 120 and / or the planarization layer 130.

[0045] In some embodiments of this application, the insulating layer 120 includes a gate insulating layer 121 and an interlayer dielectric layer 122. The gate insulating layer 121 is disposed between the buffer layer 160 and the interlayer dielectric layer 122. The interlayer dielectric layer 122 is disposed between the gate insulating layer 121 and the planarization layer 130.

[0046] Reference Figures 1 to 4 As shown, in some embodiments of this application, the thickness of the portion of the planarization layer 130 extending beyond the insulating layer 120 ranges from 1.16 μm to 2.34 μm.

[0047] More specifically, the thickness of the portion of the planarization layer 130 extending beyond the insulating layer 120 may be in the range of 1.3 μm to 2.3 μm, 1.4 μm to 2.2 μm, 1.5 μm to 2.1 μm, 1.6 μm to 2 μm, etc.; or, the thickness of the portion of the planarization layer 130 extending beyond the insulating layer 120 may be in the range of 1.16 μm to 1.2 μm, 1.2 μm to 1.7 μm, 1.8 μm to 2.1 μm, 2.1 μm to 2.3 μm, etc.

[0048] Reference Figures 1 to 4 As shown, in some embodiments of this application, the thickness of the portion of the planarization layer 130 extending beyond the insulating layer 120 is H2 μm; the values ​​of W1 and H2 range from 2.93 to 5.87.

[0049] This further ensures the bonding strength.

[0050] More specifically, the values ​​of W1 and H2 can also be 3 to 5.7, 3.02 to 5.6, 3.1 to 5.5, 3.5 to 5, 3.7 to 4.6, 4.1 to 4.5, etc.; or, the values ​​of W1 and H2 can also be 2.93 to 3.2, 3.3 to 3.8, 3.8 to 4.2, 4.4 to 5.1, 5.1 to 5.45, 5.5 to 5.87, etc.

[0051] Reference Figures 1 to 4 As shown, in some embodiments of this application, the distance between the anti-crack grooves 120a ranges from 3.45μm to 6.9μm.

[0052] Reference Figures 1 to 4As shown, in some embodiments of this application, the distance between the anti-crack grooves 120a is W2μm, and the ratio of W1 to W2 ranges from 0.99 to 1.99.

[0053] More specifically, the ratio of W1 to W2 can also be in the range of 1 to 1.9, 1.2 to 1.8, 1.3 to 1.7, 1.4 to 1.6, 1.45 to 1.55, 0.99 to 1.99, etc., or the ratio of W1 to W2 can also be in the range of 0.99 to 1.99, 0.99 to 1.99, 0.99 to 1.99, 0.99 to 1.99, 0.99 to 1.99, etc.

[0054] This allows for a further balance between crack prevention and the emphasis on integration.

[0055] Reference Figures 1 to 4 As shown, in some embodiments of this application, the distance between the midpoint C1 of the anti-crack trench 120a and the edge 110a of the substrate is defined as the outer edge distance D; the curvature of the midpoint C1 of the anti-crack trench 120a is defined as the extension curvature K; the extension curvature K increases as the outer edge distance D increases.

[0056] In some embodiments of this application, the extension curvature K and the outer edge distance D satisfy a linear relationship.

[0057] In some embodiments of this application, the width of the anti-crack groove 120a is defined as the groove width W; the groove width W decreases as the outer edge distance D increases.

[0058] In some embodiments of this application, the distance between the anti-crack grooves 120a is defined as the groove distance V; the groove distance V decreases as the outer edge distance D increases.

[0059] This allows the size of the anti-leakage groove to be adjusted according to its distance from the edge, thereby achieving a better anti-crack effect while reducing the space occupied.

[0060] In some embodiments of this application, the width of the anti-crack groove 120a ranges from 4.9 μm to 9.8 μm; the distance between the anti-crack grooves 120a ranges from 3.45 μm to 6.9 μm.

[0061] Reference Figure 5 As shown, another embodiment of this application also provides a wearable display device 200, including the display panel 100 described in any of the above embodiments.

[0062] Wearable display device 200 can be: smartwatch, wristband, portable PDA, etc.

[0063] In some embodiments, the aforementioned display panel 100 of this application can also be applied to the following display devices: mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, navigators, and any other products or components with display functions.

[0064] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, The display panel includes: substrate; An insulating layer is provided with multiple spaced, curved, extending anti-crack grooves. The distance between the midline of the anti-crack groove and the edge of the substrate is defined as the outer edge distance D. The curvature of the midline of the anti-crack groove is defined as the extension curvature K. The extension curvature K increases as the outer edge distance D increases. A flattening layer, filling at least to the crack-resistant trench; Wherein, the width of the anti-crack groove is W1μm; the thickness of the flattening layer is H1μm; and the ratio of W1 to H1 ranges from 1.25 to 1.

5. The insulating layer includes: a gate insulating layer and an interlayer dielectric layer; the gate insulating layer and / or the interlayer dielectric layer are made of inorganic insulating material, and the planarization layer is made of organic insulating material; the anti-crack trench is disposed between the stacked structures formed by the two gate insulating layers and the interlayer dielectric layers.

2. The display panel according to claim 1, characterized in that, The display panel also includes: An organic layer is disposed on the surface opposite to the substrate; A touch layer is disposed between the planar layer and the organic layer.

3. The display panel according to claim 2, characterized in that, The display panel also includes: A buffer layer is disposed between the substrate and the insulating layer and / or the planarization layer.

4. The display panel according to claim 3, characterized in that, in, The gate insulating layer is disposed between the buffer layer and the interlayer dielectric layer; the interlayer dielectric layer is disposed between the gate insulating layer and the planarization layer.

5. The display panel according to any one of claims 1 to 4, characterized in that, in, The thickness of the portion of the planarization layer extending beyond the insulating layer ranges from 1.16 μm to 2.34 μm; the thickness of the portion of the planarization layer extending beyond the insulating layer is H2 μm; and the values ​​of W1 and H2 range from 2.93 to 5.

87.

6. The display panel according to claim 5, characterized in that, in, The distance between the anti-crack grooves ranges from 3.45 μm to 6.9 μm.

7. The display panel according to claim 6, characterized in that, in, The distance between the anti-crack grooves is W2μm, and the ratio of W1 to W2 ranges from 0.99 to 1.

99.

8. A wearable display device, characterized in that, Includes the display panel as described in any one of claims 1 to 7.

Citation Information

Patent Citations

  • Display panel and display device

    CN214753840U