System and method for configuring coordinated PWM generator

Abstract

A system (200) and method are provided. The system comprises: a first pulse width modulation (PWM) generator circuit (210) comprising a first timer (211) for generating a first cycle count, a first configuration register (212) for defining a characteristic of a first electrical pulse (213) to be generated, and a trigger cycle count specifying a timing of a first trigger signal (216); and a first load enable input (214) for loading a new configuration value into the first configuration register (212); a second PWM generator circuit (220) comprising a second timer (221) for generating a second cycle count, a second configuration register (222) for defining a characteristic of a second electrical pulse (223) to be generated, a second load enable input (224) for loading a new configuration value into the second configuration register (222); and a load enable selector (227) for selectively driving the second load enable input (224) based on the first trigger signal (216).

Description

[0001] Related patent applications

[0002] This application claims priority to U.S. Provisional Application Serial No. 63 / 432,894, filed on December 15, 2022, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to pulse width modulation (PWM) devices, and more particularly to configuration coordinated PWM generators. Background Art

[0004] To control the generation of the PWM signal, a control loop is typically used.For some PWM applications using 4-16 independent PWM signal generators running in parallel, the inventors of the disclosed examples have found that the computational demands for the control of such generators are very high.

[0005] The operation of complex power converter topologies, such as multiphase LLC resonant converters with synchronous rectifier stages, requires a very specific scheme for updating timing values ​​that are led by one channel and then followed by all other channels. The update triggers must be daisy-chained and kept in a fixed, stable, and reliable sequence. Even if the leading trigger is out of its timing base, the subsequent triggering of the daisy-chained PWM generators and the associated configuration updates must be performed in the order specified by the microprocessor.

[0006] The flexibility of existing PWM modules may be limited to standard time-based triggering.

[0007] Examples of the present disclosure can address these issues by improving the efficiency of PWM signaling. This efficiency can include more advanced intelligent synchronization and updated trigger management. Summary of the invention

[0008] In some examples, a circuit is provided, the circuit comprising: a first pulse width modulation (PWM) generator circuit, the first PWM generator circuit comprising a first timer for generating a first cycle count, a first configuration register for defining the characteristics of a first electrical pulse to be generated, and a trigger cycle count for specifying the timing of a first trigger signal; and a first load enable input, the first load enable input for loading a new configuration value into the first configuration register; a second PWM generator circuit, the second PWM generator circuit comprising a second timer for generating a second cycle count, a second configuration register for defining the characteristics of a second electrical pulse to be generated, and a second load enable input for loading a new configuration value into the second configuration register; and a load enable selector, the load enable selector for selectively driving the second load enable input based on the first trigger signal. In some examples, the circuit comprises: a buffer for defining the characteristics of a third electrical pulse to be generated, wherein when the second load enable input is asserted, the second PWM generator circuit is used to load the second configuration register from the buffer content and load the buffer with the characteristics of a fourth electrical pulse to be generated. In some examples, the circuit includes a first buffer and a second buffer, the first buffer being used to define the characteristics of a third electrical pulse to be generated, and the second buffer being used to define the characteristics of a fourth electrical pulse to be generated, wherein when the second load enable input is asserted, the second PWM generator circuit loads the second configuration register from the first buffer content, loads the first buffer content from the second buffer, and loads the second buffer with the characteristics of the fifth electrical pulse to be generated. In some examples, the characteristics of the second electrical pulse to be generated include the specification of the clock cycle of the period of the second electrical pulse, the timing of the clock cycle of the rising edge of the second electrical pulse, and the timing of the clock cycle of the falling edge of the second electrical pulse. In some examples, the circuit includes: a first configuration buffer, the first configuration buffer being used to load the first configuration register when the first load enable input is asserted; and a second configuration buffer, the second configuration buffer being used to load the second configuration register when the second load enable input is asserted. In some examples, the circuit includes: a first configuration register, the first configuration register being used to define the timing of the second trigger signal; and a load enable selector, the load enable selector selectively driving the second load enable input based on the second trigger signal. In some examples, a first configuration register defining characteristics of a first electrical pulse to be generated includes specifications for a period of the first electrical pulse, specifications for a phase of the first electrical pulse, specifications for a duty cycle of the first electrical pulse, and specifications for dead time compensation of the first electrical pulse.

[0009] In some examples, a circuit is provided, the circuit comprising: a first PWM generator circuit, the first PWM generator circuit comprising a first timer, a first program enabler for enabling loading of a first program register, a first trigger input for activating the first timer, and a first plurality of trigger outputs; and a second PWM generator circuit, the second PWM generator circuit comprising a second timer, a second program enable input for enabling loading of a second program register, a second trigger input for activating the second timer, and a second trigger input selector for selectively driving the second trigger input based on one of the first plurality of trigger outputs; a first memory access channel, the first memory access channel for loading the first program register; and a second memory access channel, the second memory access channel for loading the second program register. In some examples, the circuit comprises: a third PWM generator circuit, the third PWM generator circuit comprising a third timer, a third program enabler for enabling loading of a third program register, a third trigger input for activating the third timer; and a third trigger input selector, the third trigger input selector for selectively driving the third trigger input based on one of the first plurality of trigger outputs or one of the second plurality of trigger outputs. In some examples, the first program register defines a period, a phase, and a duty cycle. In some examples, the first program enabler and the second program enabler can be asserted simultaneously. In some examples, the first program register and the second program register are coupled to the same memory access controller. In some examples, the first memory access controller reads a value from the first buffer into the first program register, and the second memory access controller reads a value from the second buffer into the second program register.

[0010] In some examples, a method is provided, the method comprising: in response to a first load enable signal received at a first PWM generator, loading a first configuration register with a value defining a characteristic of a first electrical pulse to be generated and a first trigger time, and determining a start time of the first electrical pulse; and in response to a first trigger signal on a first trigger input, enabling a first timer to start counting, generating a first trigger output signal on a first trigger output in response to the first timer counting to the first trigger time, generating the first electrical pulse in response to the first timer counting to the start time of the first electrical pulse, selecting a second load enable input of a second PWM generator from a plurality of selectable inputs including the first trigger output, and in response to a second load enable input signal received at the second load enable input, loading a second configuration register of a second PWM generator with a value defining a characteristic of a second electrical pulse to be generated. In some examples, the method comprises: in response to the first timer counting to the second trigger time, generating a second trigger signal, enabling a second timer of the second PWM generator to start counting in response to the second trigger signal. In some examples, the method includes: selecting a first trigger input as a second load enable input of a second PWM generator, and in response to the first trigger input signal, loading a second configuration register with a value defining a characteristic of a second electrical pulse to be generated. In some examples, loading the first configuration register receives the configuration value from a first buffer, and loading the second configuration register receives the configuration value from a second buffer. In some examples, loading the first configuration register receives the configuration value from a first direct memory access (DMA) channel, and loading the second configuration register receives the configuration value from a second DMA channel. In some examples, the first PWM generator operates in a first cycle, and the second PWM generator operates in a second cycle, and the method includes: a processor stores in a memory a value defining a plurality of characteristics of a first electrical pulse to be generated and a value defining a characteristic of a second electrical pulse to be generated; and at the beginning of the first cycle, triggering a DMA controller to retrieve a value defining a plurality of characteristics of the first electrical pulse to be generated, and at the beginning of the second cycle, triggering the DMA controller to retrieve a value defining a characteristic of the second electrical pulse to be generated. In some examples, triggering the DMA controller in each instance occurs independently of execution of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram of a PWM generator according to certain examples of the present disclosure.

[0012] Figure 2 is a diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0013] Figure 3 is a diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0014] Figure 4 is a diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0015] Figure 5 is a diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0016] Figure 6 is an illustration of a method for controlling a PWM generator according to certain examples of the present disclosure.

[0017] Figure 7 is an illustration of a method for controlling a PWM generator according to certain examples of the present disclosure.

[0018] Figure 8 is an illustration of an arrangement of a PWM generator controlling a 4-level FLMC totem-pole bridgeless PFV stage according to certain examples of the present disclosure.

[0019] Fig. 9 is an illustration of an application of a PWM generator according to certain examples of the present disclosure.

[0020] Fig.10 is an illustration of a timing diagram for a PWM generator according to certain examples of the present disclosure.

[0021] Fig.11 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0022] Fig.12 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0023] Fig.13 is an illustration of a timing diagram for a PWM generator according to certain examples of the present disclosure.

[0024] Fig.14 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0025] Fig.15 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0026] Fig.16 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0027] Fig.17 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure.

[0028] Fig.18 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure. DETAILED DESCRIPTION

[0029] Examples of the present disclosure may allow a single control loop to support multi-phase PWM implementations. Examples of the present disclosure may include no restrictions on sharing data values ​​between PWM generators, no timing restrictions on register programming on any of the PWM generators, and no restrictions on total offset between PWM generators.

[0030] Examples of the present disclosure may include two independent architectures. These examples may include a pipeline architecture and a direct memory access (DMA) assisted architecture. A given device may use one or both of these architectures. Each architecture may be implemented by analog circuits, digital circuits, programmable logic, programmable circuits, application specific integrated devices, field programmable gate arrays, instructions executed by a processor, or any suitable combination thereof.

[0031] The pipeline architecture utilizes one or more additional data buffers, making them fully independent to achieve design goals.

[0032] The DMA-assisted architecture takes advantage of available DMA and memory resources to simplify its design and implementation while still achieving its design goals.

[0033] The pipelined architecture utilizes a triple-deep FIFO to achieve its goals. By adding another layer of data buffers, new data values ​​can be programmed before or after previously programmed values ​​are used. The hardware is responsible for tracking the programmed timing (from the control loop) in relation to the PWM timing to properly manage its FIFO pointers and data movement. This also makes total excursions greater than 360 degrees possible. However, due to its increased cost, this architecture may be better suited for larger and more general-purpose devices.

[0034] On the other hand, the DMA-assisted architecture does not require these additional buffers or design modifications. All goals can be achieved with some increase in software complexity by utilizing the already available DMA channels and some pre-allocated internal system memory space in a timely manner. However, this architecture takes away some system resources that may be delayed or unavailable due to competing demands; especially during some critical execution cycles (depending on the application). Therefore, it can be suitable for more specialized devices where more DMA channels are dedicated to PWM purposes and the bus utilization is low for other functions.

[0035] It should be noted that both architectures employ design modifications to ensure that hardware updates maintain order (offset relationships between all PWM generators).

[0036] Each PWM typically requires a dedicated control loop to support it. This greatly increases the need for CPU intervention, making it difficult or impractical to support multi-phase PWM implementations with a large number of PWM generators using a low-cost microcontroller or processor.

[0037] To the extent that examples of the present disclosure are able to achieve all of their goals, more computational work can be accomplished with the same performance (ie, MIPS), thereby allowing a greater number of generators in a multi-phase PWM implementation without having to upgrade to a higher CPU platform.

[0038] Figure 1 1 is a diagram of a PWM generator according to some examples of the present disclosure. A PWM generator is a circuit that generates a pulse with a specific rising edge and a falling edge. The PWM generator can repeat the pulse in each cycle of a defined cycle rate or period. The PWM generator 100 can be based on an edge timer 101. The edge timer 101 provides a current count of clock cycles when enabled. The current count of clock cycles can be used to determine when a part of the PWM generator circuit takes action. The edge timer 101 can be enabled or disabled by a trigger logic 102 fed by a trigger input (internal and / or external to the PWM generator 100). The trigger logic 102 can receive information about the current cycle period (from a period comparator 111, as described below) and / or one or more trigger inputs. The selector 103 can receive a set of program control input (PCI) synchronization signals 107 from a source such as other PWM generator trigger outputs. The PCI bypass source selection 108 can select the output of a specific PWM generator to pass to the OR gate 104 for input to the trigger logic 102. The trigger input selector 105 may select a trigger input specified by input 109 from a source including an internal trigger driven by a period comparator 111, a microprocessor, or other signal lines 106. Other signal lines may include trigger outputs from other PWM generators, or may capture information about, for example, sensor events or external (PWM) control signals. For example, a motor controller incorporating the PWM generator 100 may receive input from a user to begin powering a motor.

[0039] The PWM generator 100 generates PWM pulses based on the current count of the edge timer 100. When the edge timer 100 reaches the rising edge count, the PWM output is turned on, and when the edge timer 100 reaches the falling edge count, the PWM output is turned off. In this example, the edge timer 101 counts at a rate defined by the clock input 108 and provides the current cycle count 110 to the comparators 111, 112 and 113 to compare the current cycle count 110 with the period register 114, the rising edge register 115 and the falling edge register 116 respectively. The period comparator 111 determines when the current cycle count 110 reaches the end of the predefined period for PWM generation and feeds the trigger logic 102, and can directly or indirectly drive the cycle end 131. The cycle end 131 is the output of the trigger logic 102. The rising edge comparator 112 determines when the current cycle count 110 is greater than or equal to the predetermined rising edge time defined in the rising edge register 115. When this condition is true, rising edge comparator 117 asserts the set input of flip-flop 117, causing PWM output 118 to be asserted. Falling edge comparator 113 determines when the current cycle count 110 is greater than or equal to the predetermined falling edge time defined in falling edge register 116. When this condition is true, edge comparator 113 is called to assert the reset input of flip-flop 117, causing PWM output 118 to be de-asserted. Timer capture register 130 may be used to capture the current cycle count 110 of edge timer 101 when a trigger or other event occurs.

[0040] The period, rising edge count, and falling edge count may be determined by a set of control inputs set by the microprocessor. The edge time calculation logic 120 may generate values ​​for the period register 114, the rising edge register 115, and the falling edge register 116 based on the following inputs. The PGxPER register 121 may define the period in clock cycles. The PGxPHASE 122 may define the start time of a pulse using clock cycles. The PGxDC 123 may define the duty cycle or pulse width in clock cycles. The PGxDCA 124 may define the duty cycle adjustment value. In the duty cycle adjustment mode, the edge time calculation logic 120 may add the duty cycle adjustment value from the PGxDCA 124 to the end of the duty cycle. In some examples, a pulse of a PWM generator may be delayed to avoid simultaneous switching of power devices controlled by the PWM generator. The PGxDT 125 may store a falling time adjustment value that will be added to the rising edge register 115 by the edge calculation logic 120 to delay the rising edge of the pulse, thereby avoiding simultaneous switching of power devices controlled by the PWM generator. Configuration register PGxSTAT 127 may allow additional control or programmability of the PWM generator.

[0041] In addition to generating the PWM output 118, the PWM generator 100 also generates one or more trigger signals to, for example, coordinate with other PWM generators 100 and other electronic components in the circuit. Registers 141-146 (labeled PGxTRIGA to PGxTRIGF, respectively) allow the microprocessor to set one or more clock cycle counts to define the trigger timing. The trigger register 140 can store the current / active values ​​of these trigger definitions for comparison with the current cycle count at the comparator 132. For example, if trigger A has been defined at a specific count, when the current cycle time 110 equals the trigger A count, the trigger A signal will be provided to the event selector 133. The event selector 133 allows the microprocessor to select which events will be output on various trigger and / or interrupt lines. The PG trigger 134 can be connected to the trigger input of the next downstream PWM generator in the sequence. The ADC trigger 1 (135) and ADC trigger 2 (136) can be used to initiate analog-to-digital conversion sampling. The PCI trigger 127 can be fed to the downstream PWM generator to trigger, for example, the update of the configuration settings. The DAC trigger 138 can initiate the digital-to-analog conversion circuit. The interrupt event 139 may send an interrupt signal to a microprocessor (not shown) to provide feedback to the processor.

[0042] In some examples, configuration registers 121-125, 127, and 141-146 can be implemented as buffers with two levels of depth, which are used in some examples to provide configuration of a set of working registers and a first set of future values ​​to be loaded upon a triggering event. In some examples, an internal trigger (such as one of triggers A, B, C, D, or E) can be used to trigger the transfer of configuration values ​​from the first set of future values ​​to the set of working registers. In some examples, an external trigger such as one of signal lines 106 can trigger the transfer of configuration values ​​from the first set of future values ​​to the set of working registers.

[0043] In some examples, configuration registers 121-125, 127, and 141-146 can be implemented as buffers with three levels of depth, which are used in some examples to provide a set of working configuration registers and first and second sets of future values ​​to be loaded upon a triggering event. In some examples, an internal trigger (such as one of triggers A, B, C, D, or E) can be used to trigger the transfer of configuration values ​​from the first set of future values ​​to a set of working registers, and from the second set of future values ​​to the first set of future values. In some examples, an external trigger such as one of signal lines 106 can trigger the transfer of configuration values ​​from the first set of future values ​​to a set of working registers, and from the second set of future values ​​to the first set of future values.

[0044] Daisy chaining may require the PWM generator to use its independent time base using an independent edge timer in the absence of a master timer. The leading PWM generator can be set up to manually update its timing registers. This may require setting the update request bit of PGxSTAT. Depending on the configuration, the timing register updates will be propagated immediately, or (sometimes recommended) at the start of the next cycle.

[0045] The daisy chain trigger PGxTRIGC 143 can be updated with all other registers of that generator. This may change the phase shift to the next PWM generator which will then apply its individual timing when deploying on itself and all other subsequent generators. It may be advisable to disable all other automatic PWM update modes in the triggered PWM generator. In some examples, new timing values ​​can be written independently and asynchronously to the registers generated by the PWM. When the lead PWM generator is set for start of cycle (SOC) update, an update request for that generator can be set at any time, triggering the daisy chain deployment of all channels.

[0046] Conventional power supply circuits sometimes take advantage of new FETs and other technologies to increase switching frequencies. More and more switches are used. As a result, the PWM patterns to be generated become more complex and higher in frequency. Conventional microprocessor control of cascaded PWM generators may not be able to update and / or coordinate the PWM generators, and may exhaust resources trying to do so. In some examples of the present disclosure, the software control loop can operate asynchronously with the hardware control. At some point, the PWM channel can be updated with new parameters. New parameters for the PWM channel can be added to the pipeline. Each PWM has its own PWM cycle and can set content for other channels. When the first channel starts a cycle, an update signal can be provided to other channels, which can then load their parameters when the new signal for the next channel starts.

[0047] Figure 2 2 is a diagram of an arrangement of a PWM generator according to some examples of the present disclosure. Circuit 200 includes two PWM generators. PWM generator 210 is arranged upstream of PWM generator 220. PWM generator 210 includes a setting load enabler 214, which allows settings to be loaded into a configuration register 212 of PWM generator 210, which defines the characteristics of the electrical pulse to be generated (including the start time and the end time of the electrical pulse) and the time to generate a trigger. Trigger input 215 can be used to start timer 211 of PWM generator 210. PWM generator 210 generates a PWM signal on PWM output 213. When the current count of timer 211 reaches a predefined trigger time (e.g., defined in configuration register 212), PWM generator 210 can assert trigger output 216.

[0048] The PWM generator 220 is arranged downstream of the PWM generator 210. The PWM generator 220 includes a setting load enabler 224 that allows settings to be loaded into a configuration register 222 of the PWM generator 220, which defines the characteristics of the electrical pulse to be generated (including the start time and the end time of the electrical pulse). The trigger input 225 can be used to start the timer 221 of the PWM generator 220. The PWM generator 220 generates a PWM signal on the PWM output 223. When the current count of the timer 221 reaches a predefined trigger time (e.g., defined in the configuration register 222), the PWM generator 210 can assert the trigger output 226. The load enable selector 227 can select the trigger output 216 to provide a load enable signal.

[0049] Figure 3 3 is a diagram of an arrangement of a PWM generator according to some examples of the present disclosure. Circuit 300 includes two PWM generators. PWM generator 310 is arranged upstream of PWM generator 320. PWM generator 310 includes a setting load enabler 314, which allows settings to be loaded into a configuration register 312 of PWM generator 310. Trigger input 315 can be used to start a timer 311 of PWM generator 310. PWM generator 310 generates a PWM signal on PWM output 313. When the current count of timer 311 reaches a predefined trigger time (e.g., defined in configuration register 312), PWM generator 310 can assert trigger output 316.

[0050] The PWM generator 320 is arranged downstream of the PWM generator 310. The PWM generator 320 includes a setting load enabler 324 that allows settings to be loaded into a configuration register 322 of the PWM generator 320. A trigger input 325 can be used to start a timer 321 of the PWM generator 320. The PWM generator 320 generates a PWM signal on a PWM output 323. When the current count of the timer 321 reaches a predefined trigger time (e.g., defined in the configuration register 322), the PWM generator 310 can assert a trigger output 326. A trigger selector 327 can select the trigger output 316 to provide a trigger input for the PWM generator 320.

[0051] Buffer 330 and buffer 331 provide temporary storage of configuration register values ​​for PWM generators 310 and 320, respectively. In some examples, buffer 330 and buffer 331 each store one set of configuration register values. In some examples, buffer 330 and buffer 331 each store two sets of configuration register values.

[0052] Figure 4 4 is a diagram of an arrangement of PWM generators according to certain examples of the present disclosure. Circuit 400 includes three PWM generators. PWM generator 450 is arranged upstream of PWM generator 460. PWM generator 450 includes a setting load enabler 453, which allows settings to be loaded to configure the settings of PWM generator 450. Trigger input 455 can be used to start a timer of PWM generator 450 clocked by clock signal 408. PWM generator 450 generates a PWM signal on PWM output 451. When the current count of the internal timer of PWM generator 450 reaches a predefined trigger time (e.g., defined in the configuration settings when setting load enabler 453 is asserted), PWM generator 450 can assert one of trigger outputs 452. At other predefined trigger times, PWM generator 450 can assert other trigger outputs 452.

[0053] PWM generator 460 is arranged downstream of PWM generator 450. PWM generator 460 includes a setting load enabler 463 that allows settings to be loaded to configure the settings of PWM generator 460. Load enable selector 464 can select one of trigger outputs 452 as load enable input 463. Trigger input 465 can be used to start a timer of PWM generator 460 clocked by clock signal 408. Trigger selector 466 can select one of trigger outputs 452 as trigger input 465. In this arrangement, PWM generator 450 can control when PWM generator 460 loads new configuration settings and when PWM generator 460 is triggered. PWM generator 460 generates a PWM signal on PWM output 461. When the current count of the timer of PWM generator 460 reaches a predefined trigger time (e.g., defined in the configuration settings when setting load enabler 463 is asserted), PWM generator 460 can assert trigger output 462. At other predefined trigger times, the PWM generator 460 may assert other trigger outputs 462 .

[0054] PWM generator 470 is arranged downstream of PWM generator 460. PWM generator 460 includes a setting load enabler 473 that allows settings to be loaded to configure the settings of PWM generator 470. Load enable selector 474 can select one of trigger output 452 or trigger output 462 as load enable input 473. Trigger input 475 can be used to start a timer of PWM generator 470 clocked by clock signal 408. Trigger selector 476 can select one of trigger output 452 or one of trigger output 462 as trigger input 475. In this arrangement, PWM generator 450 or 460 can control when PWM generator 470 loads new configuration settings and when PWM generator 470 is triggered. PWM generator 470 generates a PWM signal on PWM output 471. When the current count of the timer of the PWM generator 470 reaches a predefined trigger time (e.g., defined in the configuration settings when the setting load enabler 473 is asserted), the PWM generator 470 can assert the trigger output 472. At other predefined trigger times, the PWM generator 470 can assert other trigger outputs 472.

[0055] In these examples, a microprocessor may provide configuration settings to a set of PWM generators, and the PWM generators may run one or more cycles autonomously or nearly autonomously.

[0056] Figure 5 5 is a diagram of an arrangement of a PWM generator according to some examples of the present disclosure. Circuit 500 includes a PWM generator 501 coupled to a memory 503 via a data port 502. The memory 503 may be, for example, a buffer, a RAM, or a DMA channel to a main memory. Circuit 500 also includes a PWM generator 511 coupled to a memory 513 via a data port 512. The memory 513 may be, for example, a buffer, a RAM, or a DMA channel to a main memory. In this arrangement, configuration settings may be provided to data ports 502 and 512 simultaneously, thereby allowing each PWM generator to be configured independently. PWM generator 501 may have a trigger output 504 connected to a setting load enabler 516 of PWM generator 511. In one example, memories 503 and 513 may each be a buffer storing four sets of configuration values. The microprocessor may store multiple sets of configuration settings in memories 503 and 513. PWM generator 501 may load a set of settings from memory 503, and trigger PWM generator 511 to load a set of settings from memory 513 via trigger output 504. The PWM generator can load new configuration settings within a certain number of cycles without intervention by the microprocessor, freeing up microprocessor and memory access resources for other tasks.

[0057] Figure 6 is an illustration of a method for controlling a PWM generator according to certain examples of the present disclosure. Method 600 begins at block 602, where a first PWM generator receives a load enable signal. At block 604, the first PWM generator loads a value including characteristics of a first pulse and a first trigger time to a first configuration register. In an example, the characteristics of the first pulse may include a period, a rising edge start time, and a falling edge time. In another example, the characteristics of the first pulse may include a period, a phase, and a duty cycle. In some examples, the first configuration register may store configuration settings that enable an output trigger and select an input trigger.

[0058] At block 606, the first PWM generator determines a start time for a first pulse to be generated. In some examples, block 606 may result in copying a preset start time from a configuration setting into an internal register for comparison with a current timer. In some examples, block 606 may include adding a period and a dead time compensation value to determine a start time for the pulse, and saving the start time in an internal register.

[0059] At block 608, the first PWM generator receives a trigger signal. At block 610, in response to the trigger signal, a first timer, i.e., a timer of the first PWM generator, is initiated. The first timer may begin counting at a clock frequency greater than the period of the PWM output. A higher clock frequency may enable higher resolution control of the timing of pulse edges and trigger events.

[0060] At block 612, a comparator of the first PWM generator indicates a match between the first trigger time and the current clock cycle count, i.e., reaching the first trigger time. At block 614, in response to the match indication at block 612, i.e., in response to reaching the time of the first trigger timer, the PWM generator generates a first trigger output signal.

[0061] At block 616, the comparator of the first PWM generator indicates a match of the start time of the first pulse with the current clock cycle count, i.e., the start time of the first pulse is reached. At block 618, in response to the match indication at block 616, i.e., in response to the start time of the first pulse being reached, the PWM generator generates a first electrical pulse and maintains the first electrical pulse for a predetermined duration.

[0062] At block 620, the selector selects a load enable input of the second PWM generator. In some examples, the load enable input can be coupled to a trigger output of the first PWM generator to provide control by the first PWM generator when the second PWM generator loads configuration settings.

[0063] At block 622, the second PWM generator receives a load enable signal. At block 624, in response to the load enable signal received at the second PWM generator, the second PWM generator loads a second configuration register, i.e., a configuration register of the second PWM generator, with a value including characteristics of the first pulse to be generated by the second PWM generator. In an example, the characteristics of the first pulse from the second PWM generator may include a period, a rising edge start time, and a falling edge time. In another example, the characteristics of the second pulse may include a period, a phase, and a duty cycle. In some examples, the second configuration register may store configuration settings that enable an output trigger and select an input trigger.

[0064] In some examples, the blocks are not performed in the order shown.

[0065] Figure 7 is a diagram of a method for controlling a PWM generator according to certain examples of the present disclosure. The method 700 includes reference Figure 6 The block described in the embodiment of the present invention includes the following contents. At block 710 (which may be after block 608 and before block 620), the comparator indicates that the current clock cycle count of the first PWM generator matches the second trigger time defined by the configuration value, that is, the time of the second trigger timer is reached. At block 712, in response to the indication of block 710, that is, in response to reaching the second trigger time, the first PWM generator generates a second trigger output signal. At block 714 (which may be after block 622), the second PWM generator receives the second trigger output signal generated at block 712. At block 716, in response to the trigger received at block 714, the second PWM generator enables its internal timer, that is, enables the second timer.

[0066] Figure 8 890 is a diagram of an arrangement of PWM generators controlling a 4-level FLMC (Fuzzy Logic Motor Controller) totem pole bridgeless PFC (Power Factor Compensation) stage according to certain examples of the present disclosure. Circuit 890 includes a 4-level FLMC totem pole bridgeless PFC stage 891 and PWM generators 800, 810, 820, 830, 840, and 850. Circuit 891 improves the performance of an electrical load by regulating the power supplied to the electrical load.

[0067] The switches Q1-Q6 may have a specific sequence that allows for specific other components (such as capacitor C F2 , C F1 and C Dc ) for charging. Input voltage V IN and the series inductor L IN The circuit is powered and switches Q7 and Q8 are controlled by other PWM generators not shown. Capacitor C F2 , C F1and C DC The charging and discharging can be synchronized and can be based on the input voltage V IN and the output voltage at terminal OUT. Three complementary PWM signals are generated to control switches Q1-Q6.

[0068] PWM generator 800 operates as a pilot PWM generator. PWM generator 800 generates a PWM signal at output 802 to control switch Q1. PWM generator is configured via configuration enable input 803 and initiated via trigger input 804. PWM generator 800 generates a trigger signal at trigger output 805. PWM generator 850 generates a PWM signal output to control switch Q6, the PWM signal of which is complementary to the PWM control signal of control switch Q1. PWM generator 850 is configured via configuration enable input 853 and initiated via trigger input 854.

[0069] PWM generator 810 generates a PWM signal at output 812 to control switch Q2. PWM generator 810 is configured via configuration enable input 813 and initiated via trigger input 814. PWM generator 810 generates a trigger signal at trigger output 815. PWM generator 840 generates a PWM signal output to control switch Q5, which is complementary to the PWM control signal controlling switch Q2. PWM generator 840 is configured via configuration enable input 843 and initiated via trigger input 844. PWM generator 840 generates a trigger signal at trigger output 845.

[0070] PWM generator 820 generates a PWM signal at output 822 to control switch Q3. PWM generator 820 is configured via configuration enable input 823 and initiated via trigger input 804. PWM generator 801 generates a trigger signal at trigger output 805. PWM generator 830 generates a complementary PWM signal output to control switch Q4, which is complementary to the PWM control signal controlling switch Q3. PWM generator 830 is configured via configuration enable input 833 and initiated via trigger input 834. PWM generator 830 generates a trigger signal at trigger output 835.

[0071] In some examples, the trigger output signals 805, 815, 825, 835, and 845 are available via input selectors 816, 826, 836, 846, 856 to enable configuration updates on PWM generators 810, 820, 830, 840, and 850. In some examples, the trigger output signals 805, 815, 825, 835, and 845 are available via input selectors 817, 827, 837, 847, 857 to trigger counting in PWM generators 810, 820, 830, 840, and 850.

[0072] Fig. 9 is an illustration of an application of a PWM generator according to certain examples of the present disclosure. Switches 901, 903, 905, 907, 909, and 911 are connected to the high side of a bridge circuit including transformers 935, 936, and 937 and capacitors 934a-e. Switches 902, 904, 906, 908, 910, and 912 are connected to the low side of the bridge circuit. Switch 901 is controlled by a first PWM generator (PG1-H), which is designated as a leading PWM generator and operates on the first phase of a three-phase circuit. Switches 903 and 905 operate on the other two phases of the three-phase circuit. PWM generators PG3-H and PG5-H follow and control switches 903 and 905, respectively. Similarly, switches 902, 904, 906, 908, 910, and 912 are controlled by PWM generators PG1-L to PG6-L. PG1-H is updated first and leads the update. Update triggers PG1TRIGC to PG5TRIGC are shown as arrows between switches 901, 903, 905, 907, 909 and 911. The update triggers PG1TRIGC to PG5TRIGC may not be limited to the order shown. PG1TRIGC can be generated during the PG1-H cycle and is defined by the configuration register. PG1-H generates PG1TRIGC when the timer internal to PG1-H reaches the count defined for this trigger.

[0073] In this example, the three phases on each side of the bridge are each offset by 60 degrees. In some examples, the phases can be offset by 120 degrees. In some examples, the phase offset programmed into the PWM generator can be greater or less than 60 degrees. In some examples, the cumulative offset value of a group of PWM generators can be greater than 360 degrees.

[0074] Fig.10 1 is an illustration of a timing diagram of a PWM generator according to certain examples of the present disclosure. Timing diagram 1000 illustrates a PWM signal on the y-axis and time (t) on the x-axis. Signal 1010 may be a first PWM signal referred to as PWMxH. Signal 1011 may be a second PWM signal referred to as PWMxL. These signals may operate in a complementary manner.

[0075] In some examples, the timer operates with a resolution of 250 picoseconds. In some examples, each PWM trigger generates three triggers. PGxTRIGA may have enhanced options. For example, PGxTRIGA may be delayed and shifted within multiple PWM cycles. In some examples, PGxTRIGA, PGxTRIGB, and PGxTRIGC can be used as analog-to-digital conversion triggers. In some examples, PGxTRIGA, PGxTRIGB, and PGxTRIGC can be used for PWM synchronization. In some examples, PGxTRIGA, PGxTRIGB, and PGxTRIGC can be placed independently across cycles. In some examples, configuration values ​​PGxDTH, PGxDC, PGxDTL, PGxTRIGA, PGxTRIGB, PGxTRIGC, and PGxPER can be defined in a configuration register and set when a configuration load enable signal is applied to the PWM generator. PGxDTH can specify multiple "dead time" cycles for the PWMxH signal. The "dead time" can be configured to prevent the high-power switches controlled by the PWM generator from switching at the same time. PGxDC can specify multiple duty cycles or cycles to assert the PWMxH signal. PGxDTL can specify a number of "dead time" cycles for the PWMxL signal. PGxTRIGA, PGxTRIGB, and PGxTRIGC can specify each of the three trigger cycle counts that define when each of the three triggers will be asserted. PGxPER can specify the number of cycles of the PWM generator repetition period.

[0076] At time 1001, the PWM generator timer starts counting. Time 1001 may be referred to as START_OF_CYCLE, and the counter may be reset to zero. At time 1002, the signal PWMxH may begin to rise to an asserted level. Time 1002 may be PGxDTH clock cycles from the start. In some examples, time 1002 may be the sum of the register value PGxPHASE 122 and the PGxDTH clock cycles from the start. At time 1003, the signal PWMxH may begin to fall to an unasserted level. Time 1003 may be a PGxDC clock cycle from the start. At time 1004, the signal PWMxL may begin to rise to an asserted level. Time 1003 may be a PGxDC plus PGxDTL clock cycle from the start. At time 1005, the trigger TRIGA may be asserted. Time 1005 may be a PGxTRIGA clock cycle from the start. At time 1006, the trigger labeled TRIGB may be asserted. Time 1006 may be PGxTRIGB clock cycles from the start. At time 1007, the trigger labeled TRIGC may be asserted. Time 1007 may be PGxTRIGC clock cycles from the start. At time 1008, signal PWMxL may begin to fall. Time 1008 may be PGxPER clock cycles from the start. At time 1008, the counter may be reset to zero and a new cycle may begin. At time 1009, signal PWM 1010 may begin to rise again after PGxDTH cycles from time 1008.

[0077] In some examples, PGxPER is a limited window in which triggers and events can be generated for the PWM generator. In some examples, the PWM generator can include a second timer to allow triggers and events in multiple PWM cycles.

[0078] Fig.11is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure. At time 1101, PWM1 may be configured by a microprocessor and may be self-triggered as a pilot PWM generator to begin its cycle of generating complementary PWM signals 1110 and 1111. At time 1102, PWM1 may assert a trigger PG1TRIGC to initiate PWM2 to generate complementary PWM signals 1112 and 1113, which may differ by 60 degrees from PWM signals 1110 and 1111. At time 1103, PWM2 may assert a trigger PG2TRIGC to initiate PWM3 to generate complementary PWM signals 1114 and 1115, which may differ by 60 degrees from PWM signals 1112 and 1113. At time 1104, PWM3 may assert a trigger PG3TRIGC to initiate PWM4 to generate complementary PWM signals 1116 and 1117, which may differ by 60 degrees from PWM signals 1114 and 1115. At time 1105, PWM4 may assert trigger PG4TRIGC to initiate other downstream PWM generators. In some examples, when the last channel is triggered, the first channel may have been updated.

[0079] Fig.12 1 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure. In some examples, a synchronous rectifier PWM channel may be utilized to control the circuit. A set of primary and secondary half-bridge drive PWM channels may be synchronized with a synchronous rising edge. In this example, the trigger cycle count of the TRIGC of the primary PWM may be set to zero (or close to zero, as shown) to trigger the secondary PWM at the beginning of the cycle. At time 1201, the last phase of the last PWM in a set of daisy-chained PWMs begins a cycle, and the primary PWM generator stops asserting the complementary PWM signal 1221. At time 1202, the last PWM triggers the primary PWM. At time 1203, which may be the same as time 1202, the primary PWM asserts the trigger PG1TRIGC. In some examples, the delay between the primary PWM and the secondary PWM may be achieved by a dead time configuration, rather than delaying the PG1TRIGC to synchronize the primary PWM generator and the secondary PWM generator. At time 1204, the primary PWM asserts signal 1220. At time 1205, the secondary PWM generator asserts signal 1222. At time 1206 , the secondary PWM may assert trigger PT2TRIGC to shift the next power converter phase by 60 degrees. At time 1207 , the subsequent primary PWM channel asserts signal 1224 .

[0080] In some examples, the primary PWM trigger can be used to perform phase shifting. In these examples, the secondary PGxTRIGC trigger value can reduce the count of the phase shift delay. Using the dead time register to change the pulse timing is sometimes simpler than triggering the delay. This is illustrated using pulse delays 1205 and 1208 that delay the pulses PGxDTH and PGxDTL, respectively.

[0081] Fig.13 1 is an illustration of a timing diagram for a PWM generator according to certain examples of the present disclosure. Timing diagram 1300 illustrates the timing for programming and operation of a single channel PWM generator. Signal 1301 is a PWM output signal. Timing line 1302 illustrates three defined time periods A1, B1, and C1. Timing line 1304 illustrates three time periods programmed with values ​​for the defined time periods. Timing line 1306 illustrates three time periods for operating the PWM generator.

[0082] During time period 1320 (labeled "A1"), the PWM generator operates with the configuration settings associated with A1 during time period 1340 (labeled "Operation [A1]") to generate PWM signal 1301. During time period 1330 (labeled "Programming [B1]"), the PWM generator loads new configuration settings for time period 1321 (labeled "B1"). During windows 1310 and 1311, the microprocessor performs a control loop execution cycle in which the microprocessor calculates the next set of program values. The beginning of window 1310 (or 1311) is the period boundary between periods A1 and B1 (or B1 and C1), and is the time when the working registers within the PWM generator are updated based on the programmed values ​​of period B1. The end of period 1310 (or 1311) is the time when the microprocessor updates the programming registers with the configuration of period B1 (or C1).

[0083] Fig.14 1400 is an illustration of a timing diagram of an arrangement of PWM generators according to certain examples of the present disclosure. Timing diagram 1400 illustrates the timing of a multi-phase PWM, where each PWM generator is cascaded from the first generator, performing programming on cycle boundaries, such as Fig.13 shown.

[0084] Timing lines 1402, 1408, 1414, and 1420 provide markers for the operating time periods of PWM generators PG1, PG2, PG3, and PG4, respectively. Timing lines 1404 and 1406 illustrate timing lines for programming and operation of the first PWM generator PG1. Timing lines 1410 and 1412 illustrate timing lines for programming and operation of the second PWM generator PG2. Timing lines 1416 and 1418 illustrate timing lines for programming and operation of the third PWM generator PG3. Timing lines 1422 and 1424 illustrate timing lines for programming and operation of the fourth PWM generator PG4.

[0085] PG1 (the pilot PWM generator) triggers the operation of PG2, which in turn triggers the operation of PG3, and so on. In this example, the programming steps in lines 1404, 1410, 1416, and 1422 are interleaved to allow the microprocessor to execute four separate control loops for sequential programming. The working steps in lines 1406, 1412, 1418, and 1424 are also interleaved to follow the programming steps in the same time frame. This interleaving of programming steps and working steps may be overly restrictive in some applications and may require more control execution time than some examples of the present disclosure.

[0086] Fig.15 is an illustration of a timing diagram of an arrangement of PWM generators according to certain examples of the present disclosure. Timing diagram 1500 illustrates a non-interleaved programming process in which programming steps B1, B2 B3, and B4 are simultaneous or nearly simultaneous and can be performed by a single control loop. Working phases B1, B2, B3, and B4 can be staged with cascade triggers from PG1 to PG2, PG2 to PG3, and PG3 to PG4. The sequence must be executed carefully to avoid programming PG4 with the value of window B4 before A4 work is completed. In some examples, the values ​​can be loaded into a buffer on each PWM generator by the control loop and programmed into the operating register at the end of the current working window (i.e., at the end of the cycle).

[0087] In some examples, new configuration values ​​are stored in pre-allocated memory during control loop 1550 if earlier than the furthest trigger boundary. In these examples, PG4 can trigger DMA at the boundary time (as shown by the dashed arrow) to upload register values ​​and program PWM generators PG1-PG4 with the values ​​previously stored in pre-allocated memory. Because the total offset is within 360 degrees, one trigger per loop iteration is sufficient (i.e., cycles B1 and B4 overlap).

[0088] Fig.16is an illustration of a timing diagram of an arrangement of PWM generators according to certain examples of the present disclosure. Timing diagram 1600 illustrates an interleaved programming and triggering sequence. At each control loop execution, the program configuration of PWM generator PG1 is directly loaded, while the program configurations of PG2-PG4 are stored in memory. At each timing boundary, the previous PWM generator triggers DMA to introduce a program for the next PWM generator. For example, during control loop 1650, the microprocessor programs PG1 using program configuration C1. At some later time, as shown in timing line 1410, PG2 triggers DMA to load PG2 configuration registers using program configuration C2. In line 1416, PG3 triggers DMA to load PG3 configuration registers using program configuration C3. In line 1420, PG4 triggers DMA to load PG4 configuration registers using program configuration C4. In this example timing, PG4 cannot be responsible for triggering the program configurations of PG1-PG3 because PG4 operates at a position more than 360 degrees after PG1 and nearly 360 degrees after PG2. In these examples, the microprocessor can perform other tasks while the daisy-chained PWM generators independently load and execute a set of three program configurations.

[0089] Fig.17 is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure. Timing diagram 1700 shows a PWM with a second working layer. The second working layer in each PWM can be enabled by including an additional set of working registers. In some examples, additional buffer layers are provided to pipeline the configuration and operation of the PWM. In line 1420, the A4 operating window is consistent with a request to load the B4 program configuration. In order to enable the program timing, an additional configuration buffer layer can be provided to allow the B4 program configuration settings to be stored during execution under the A4 program configuration settings. At the end of the A4 cycle, the hardware within PG4 will automatically shift the B4 settings into the working registers when line 1424 transitions to the working [B4] time window.

[0090] exist Fig.17 In the example shown, a single control loop 1750 simultaneously writes programs PG1-PG4 using the C1-C4 configuration. In parallel with the control loop 1750, PG1 shifts the execution of its B1 configuration to its second execution time slot. After phase shifting, each daisy-chained PWM generator shifts the execution of its B1 configuration to the second internal execution time slot. The same process is repeated for the control loop 1752. This pipeline architecture provides additional timing flexibility for loading configurations.

[0091] Fig.18is an illustration of a timing diagram of an arrangement of a PWM generator according to certain examples of the present disclosure. Timing diagram 1800 illustrates an example where the offset can be greater than 360 degrees. Control loop 1850 loads PG1-PG4 with program configurations C1-C4. During this time, time windows PG1 and PG2 begin to execute under C1 and C2, respectively. PG3 begins executing C3 outside the time window of control loop 1850 but before control loop 1852. The pipeline architecture implemented with additional layers of configuration buffers supports operation with offsets greater than 360 degrees.

[0092] Although examples have been described above, the present disclosure may have other variations and examples without departing from the spirit and scope of these examples.

Claims

1. A circuit, comprising: A first pulse width modulation (PWM) generator circuit, wherein the first PWM generator circuit comprises: a first timer, the first timer being used to generate a first cycle count, A first configuration register, wherein the first configuration register is used to define: the characteristics of the first electrical pulse to be generated, and a trigger cycle count that specifies the timing of the first trigger signal, and a first load enable input for loading a new configuration value into the first configuration register; A second PWM generator circuit, wherein the second PWM generator circuit comprises: a second timer, the second timer being used to generate a second cycle count, The second configuration register is used to define: The characteristics of the second electrical pulse to be generated, a second load enable input for loading a new configuration value into the second configuration register; and A load enable selector is configured to selectively drive the second load enable input based on the first trigger signal.

2. The circuit according to claim 1, comprising: a buffer for defining characteristics of a third electrical pulse to be generated, wherein when the second load enable input is asserted, the second PWM generator circuit is configured to: load the second configuration register from the buffer contents, and The buffer is loaded with the characteristics of a fourth electrical pulse to be generated.

3. The circuit according to any one of claims 1 to 2, comprising: a first buffer for defining characteristics of a third electrical pulse to be generated and a second buffer for defining characteristics of a fourth electrical pulse to be generated, wherein when the second load enable input is asserted, the second PWM generator circuit is configured to: load the second configuration register from the first buffer content, load the first buffer contents from the second buffer, and The second buffer is loaded with the characteristics of a fifth electrical pulse to be generated.

4. The circuit according to any one of claims 1 to 3, wherein: The characteristics of the second electrical pulse to be generated include specifications of a clock cycle of a period of the second electrical pulse, timing of a clock cycle of a rising edge of the second electrical pulse, and timing of a clock cycle of a falling edge of the second electrical pulse.

5. The circuit according to any one of claims 1 to 4, comprising: a first configuration buffer for loading the first configuration register when the first load enable input is asserted, and A second configuration buffer is provided for loading the second configuration register when the second load enable input is asserted.

6. The circuit according to any one of claims 1 to 5, comprising: the first configuration register, the first configuration register defining the timing of the second trigger signal, and The load enable selector selectively drives the second load enable input based on the second trigger signal.

7. The circuit according to any one of claims 1 to 6, wherein: The first configuration register for defining the characteristics of the first electrical pulse to be generated comprises: The specification of the period of the first electric pulse, The specification of the phase of the first electrical pulse, the specification of the duty cycle of the first electrical pulse, and Specifications for dead time compensation of the first electrical pulse.

8. A circuit, comprising: A first PWM generator circuit, wherein the first PWM generator circuit comprises: First timer, a first program enabler, the first program enabler being used to enable loading of a first program register, a first trigger input for activating the first timer, and The first of multiple trigger outputs, and A second PWM generator circuit, wherein the second PWM generator circuit comprises: Second timer, a second program enable input for enabling loading of a second program register, a second trigger input, the second trigger input being used to activate the second timer, and a second trigger input selector, the second trigger input selector being configured to selectively drive the second trigger input based on one of the first plurality of trigger outputs, a first memory access channel, the first memory access channel being used to load the first program register, and A second memory access channel, wherein the second memory access channel is used to load the second program register.

9. The circuit according to claim 8, comprising: A third PWM generator circuit, the third PWM generator circuit comprising: The third timer, a third program enabler, the third program enabler being used to enable loading of a third program register, a third trigger input for activating the third timer, and A third trigger input selector is configured to selectively drive a third trigger input based on one of the first plurality of trigger outputs or one of the second plurality of trigger outputs.

10. The circuit according to any one of claims 8 to 9, wherein: The first program register defines the period, phase and duty cycle.

11. A circuit according to any one of claims 8 to 10, wherein: The first program enabler and the second program enabler can be asserted simultaneously.

12. A circuit according to any one of claims 8 to 11, wherein: The first program register and the second program register are coupled to a memory bus.

13. A circuit according to any one of claims 8 to 12, wherein: The first memory access controller reads a value from a first buffer into the first program register, and the second memory access controller reads a value from a second buffer into the second program register.

14. A method comprising: In response to a first load enable signal received at the first PWM generator: The first configuration register is loaded with values ​​defining: the characteristics of the first electrical pulse to be generated, and First trigger time, and determining the start time of the first electrical pulse, and In response to a first trigger signal on a first trigger input, enabling a first timer to start counting, generating a first trigger output signal on a first trigger output in response to the first timer counting to the first trigger time, generating a first electrical pulse in response to the first timer counting to the start time of the first electrical pulse, selecting a second load enable input of a second PWM generator from a plurality of selectable inputs including the first trigger output, and In response to a second load enable input signal received at the second load enable input, a second configuration register of the second PWM generator is loaded with values ​​defining characteristics of a second electrical pulse to be generated.

15. The method according to claim 14, comprising: In response to the first timer counting to a second trigger time, generating a second trigger signal, In response to the second trigger signal, a second timer of the second PWM generator is enabled to start counting.

16. The method according to any one of claims 14 to 15, comprising: selecting the first trigger input as the second load enable input of the second PWM generator, and In response to the first trigger input signal, the second configuration register is loaded with a value defining a characteristic of a second electrical pulse to be generated.

17. The method according to claim 16, wherein: Loading the first configuration register receives a configuration value from a first buffer, and loading the second configuration register receives a configuration value from a second buffer.

18. The method according to any one of claims 16 to 17, wherein: Loading the first configuration register receives a configuration value from a first direct memory access (DMA) channel, and loading the second configuration register receives a configuration value from a second DMA channel.

19. The method according to any one of claims 14 to 18, wherein: The first PWM generator operates in a first period, and the second PWM generator operates in a second period, and the method includes: The processor stores in memory: defining said values ​​of said plurality of characteristics of said first electrical pulse to be generated, and defining said value of a characteristic of a second electrical pulse to be generated, and at the beginning of said first cycle, triggering a DMA controller to retrieve said values ​​defining said plurality of characteristics of said first electrical pulse to be generated, At the beginning of the second cycle, the DMA controller is triggered to retrieve the value defining the characteristic of the second electrical pulse to be generated.

20. The method according to claim 19, wherein: Triggering the DMA controller in each instance occurs independently of execution of the processor.

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