Silicon-based display device and manufacturing method thereof

Abstract

According to the silicon-based display device and the manufacturing method thereof, the contact plug with the RC delay smaller than that of the tungsten plug is adopted to replace the tungsten plug, lower resistance is achieved, and therefore lower RC delay performance is achieved. In the manufacturing method, the second dielectric layer is deposited after the optical mirror surface electrode array is formed, and the isolation of the optical mirror surface electrode array is realized by performing CMP on the second dielectric layer and then performing wet etching, so that the manufacturing cost is lower, the problems of recesses, micro scratches, oxidation and the like caused by direct grinding of the CMP on the top surface of the optical mirror surface electrode can be avoided, and the reliability of the optical mirror surface electrode array is improved. Therefore, the optical mirror electrode array has a smooth and flat top surface, the reflectivity of the optical mirror electrode array is improved, the consistency of arrangement and thickness of subsequently filled liquid crystals is improved, and light distortion is avoided. In addition, the metal connection structure and the contact plug can be formed by adopting a dual damascene + single damascene process, so that the manufacturing cost is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of display device manufacturing, and in particular to a silicon-based display device and a manufacturing method thereof. Background Art

[0002] Liquid Crystal On Silicon (LCOS) display device is a reflective liquid crystal display device. It is different from ordinary liquid crystal display devices. Please refer to Figure 1 CMOS devices are directly manufactured on a silicon wafer 100 using a CMOS process. The CMOS devices are led upward through a multi-layer metal connection structure 101, and further a process such as aluminum plating is used to form an optical mirror electrode array 102 (composed of a number of Al electrodes spaced from each other and arranged in an array), thereby forming a CMOS silicon substrate. The CMOS silicon substrate is then bonded to a glass cover plate 105 formed with a transparent electrode 104, and filled with liquid crystal 103. The CMOS device in the CMOS silicon substrate provides an electric potential to the optical mirror electrode array 102 from the bottom to achieve control of the reflected light path.

[0003] The existing silicon-based display devices and manufacturing methods thereof still have defects and need further improvement. Summary of the invention

[0004] The object of the present invention is to provide a silicon-based display device and a manufacturing method thereof, which can enable an optical mirror electrode array to have lower RC delay performance, lower process cost, and avoid problems such as dents, micro scratches and oxidation on the metal surface of the optical mirror electrode array caused by a chemical mechanical polishing (CMP) process.

[0005] To achieve the above object, a method for manufacturing a silicon-based display device is characterized by comprising:

[0006] Providing a silicon substrate having a CMOS device, a metal connection structure and an interlayer dielectric layer, wherein the metal connection structure is electrically connected to the CMOS device and is formed in the interlayer dielectric layer;

[0007] Forming a first dielectric layer and a contact plug having an RC delay smaller than that of a tungsten plug on the interlayer dielectric layer and the metal connection structure, wherein the contact plug penetrates the first dielectric layer and the bottom thereof is in electrical contact with the metal connection structure, and the top surface of the first dielectric layer is flat and exposes the top surface of the contact plug;

[0008] Depositing an optical mirror electrode material layer on the first dielectric layer, and etching the optical mirror electrode material layer to the first dielectric layer to form an optical mirror electrode array, wherein the bottom of each optical mirror electrode in the optical mirror electrode array is in electrical contact with the corresponding contact plug, and adjacent optical mirror electrodes are separated by isolation grooves;

[0009] Depositing a second dielectric layer on the optical mirror electrode array and the first dielectric layer and in the isolation trench;

[0010] The second dielectric layer is flattened and thinned by a chemical mechanical polishing process, and the optical mirror electrode array is still buried in the remaining second dielectric layer after the top surface is flattened and thinned;

[0011] The remaining second dielectric layer is wet-etched to expose the top surface of each of the optical mirror electrodes.

[0012] Optionally, a multi-layer copper interconnect structure is formed at least on the top by using a copper dual damascene process as the metal connection structure, and a copper plug is formed on the interlayer dielectric layer by using a copper single damascene process as the contact plug.

[0013] Optionally, the step of forming a copper plug as the contact plug on the interlayer dielectric layer by using a copper single damascene process includes:

[0014] Depositing the first dielectric layer on the interlayer dielectric layer and the metal connection structure, and etching the first dielectric layer to the top surface of the top copper interconnect structure of the metal interconnect structure to form a contact through hole exposing the top surface of the top copper interconnect structure;

[0015] Copper is deposited to fill the contact through hole, and the deposited copper is planarized by a chemical mechanical polishing process until the top surface of the first dielectric layer is exposed, thereby forming a copper plug as the contact plug.

[0016] Optionally, when the remaining second dielectric layer is wet-etched, the second dielectric layer is overetched after the top surface of each of the optical mirror electrodes is exposed, so that the second dielectric layer retained in the isolation trench forms a second groove.

[0017] Optionally, when the second dielectric layer is deposited on the optical mirror electrode array and the first dielectric layer and in the isolation groove, the deposited second dielectric layer conformally forms a first groove at the isolation groove, and after the second dielectric layer is flattened and thinned by the chemical mechanical polishing process, the first groove is partially retained or removed; or, when the second dielectric layer is deposited on the optical mirror electrode array and the first dielectric layer and in the isolation groove, the deposited second dielectric layer fills the isolation groove and has a flat top surface.

[0018] Optionally, the manufacturing method includes at least one of the following parameter settings:

[0019] (1) The line width of the contact plug is 0.3 μm to 0.5 μm;

[0020] (2) The height of the contact plug is

[0021] (3) The material of the optical mirror electrode includes Al, and the thickness of the optical mirror electrode is

[0022]

[0023] (4) The optical mirror electrode is a rectangle with a single side of more than 0.5 μm;

[0024] (5) The spacing between the optical mirror electrodes in the optical mirror electrode array is 0.1 μm to 0.5 μm;

[0025] (6) After the second dielectric layer is flattened and thinned by chemical mechanical polishing, the second dielectric layer has a coverage thickness of 1000 nm on the top surface of the optical mirror electrode.

[0026] (7) The depth of the second groove relative to the top surface of the optical mirror electrode is

[0027] Optionally, after depositing the optical mirror surface electrode material layer and before etching the optical mirror surface electrode material layer, or after etching the optical mirror surface electrode material layer and before depositing the second dielectric layer, a surface barrier layer is further deposited on the optical mirror surface electrode material layer.

[0028] Optionally, after wet-etching the remaining second dielectric layer, the method further includes: forming a display material layer on the second dielectric layer and the optical mirror electrode array.

[0029] Optionally, the display material layer includes a liquid crystal layer, and the step of forming the display material layer includes: bonding a glass cover plate having a transparent electrode formed on one side to the silicon substrate, so that the optical mirror electrode array is sandwiched between the transparent electrode and the first dielectric layer, and further filling liquid crystal in the space between the transparent electrode and the optical mirror electrode array;

[0030] Alternatively, the display material layer includes a luminescent material layer, and the step of forming the display material layer includes: depositing the luminescent material layer on the second dielectric layer and the optical mirror electrode array.

[0031] Based on the same inventive concept, the present invention also provides a silicon-based display device, comprising:

[0032] A silicon substrate having a CMOS device, a metal connection structure and an interlayer dielectric layer, wherein the metal connection structure is electrically connected to the CMOS device and is formed in the interlayer dielectric layer;

[0033] A first dielectric layer and a contact plug having a smaller RC delay than the tungsten plug are formed on the interlayer dielectric layer and the metal connection structure, the contact plug penetrates the first dielectric layer and the bottom is in electrical contact with the metal connection structure, and the top surface of the first dielectric layer is flat and exposes the top surface of the contact plug;

[0034] An optical mirror electrode array is formed on the first dielectric layer, the bottom of each optical mirror electrode in the optical mirror electrode array is in electrical contact with the corresponding contact plug, and adjacent optical mirror electrodes are separated by isolation grooves;

[0035] A second dielectric layer is filled in the isolation trench to expose the top surface of each of the optical mirror electrodes;

[0036] The display material layer is formed on the second medium layer and the optical mirror electrode.

[0037] Optionally, the metal connection structure is a multilayer copper interconnect structure formed at least at the top by a copper dual damascene process, and the top copper interconnect structure electrically contacts the optical mirror electrode array in the metal connection structure, and the contact plug is a copper plug formed by a copper single damascene process.

[0038] Optionally, the optical mirror surface electrode is a single-layer film or includes an optical mirror surface electrode material layer and a surface barrier layer stacked on the optical mirror surface electrode material layer.

[0039] Optionally, the second dielectric layer conformally covers the inner surface of the isolation trench and forms a groove, and the bottom surface of the groove is lower than the top surface of the optical mirror electrode.

[0040] Optionally, the silicon-based display device includes at least one of the following parameter settings:

[0041] (1) The line width of the contact plug is 0.3 μm to 0.5 μm;

[0042] (2) The height of the contact plug is

[0043] (3) The material of the optical mirror electrode includes Al, and the thickness of the optical mirror electrode is

[0044]

[0045] (4) The optical mirror electrode is a rectangle with a single side of more than 0.5 μm;

[0046] (5) The spacing between the optical mirror electrodes in the optical mirror electrode array is 0.1 μm to 0.5 μm;

[0047] (6) The depth of the bottom surface of the groove relative to the top surface of the optical mirror electrode is

[0048]

[0049] Optionally, the display material layer includes a liquid crystal or a light-emitting material layer; or, the silicon-based display device further includes a glass cover plate and a transparent electrode, one side of the glass cover plate is bonded to the silicon substrate, and the transparent electrode is formed between the glass cover plate and the display material layer.

[0050] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0051] 1. Using a contact plug (such as copper) with a smaller RC delay than the tungsten plug to replace the tungsten plug has a lower resistance and thus has a lower RC delay performance.

[0052] 2. After forming the optical mirror electrode array, a second dielectric layer is deposited, and the second dielectric layer is first subjected to CMP and then wet-etched to achieve isolation of the optical mirror electrode array. Compared with the method of photolithography combined with etching of the dielectric layer on the optical mirror electrode array in the prior art, the manufacturing cost is lower. Moreover, after the second dielectric layer is first subjected to CMP to retain a certain thickness on the top surface of the optical mirror electrode, and then wet-etched to expose the top surface of the optical mirror electrode, it can avoid the problems of depression, micro scratches and oxidation caused by CMP directly grinding on the top surface of the optical mirror electrode, so that the optical mirror electrode array has a smooth and flat top surface, improves the reflectivity of the optical mirror electrode array, and is conducive to improving the consistency of the arrangement and thickness of the liquid crystal filled subsequently, avoiding light distortion.

[0053] 3. The contact plug formed is a copper plug, and the metal connection structure formed is a multi-layer copper interconnection structure, thereby making the contact plug low in resistance and making the contact plug compatible with the metal connection structure of the previous layer, thus preventing metal contamination.

[0054] 4. At least the top of the metal connection structure on the silicon substrate is formed by a copper dual damascene process, and the contact plug used to realize the electrical connection between the metal connection structure and the optical mirror electrode array is formed by a copper single damascene process. Therefore, the "dual damascene + single damascene" process can be used to replace the single damascene process used in the prior art to form the metal connection structure and the contact plug, which can save manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0056] Figure 1 It is a schematic diagram of the cross-sectional structure of an existing silicon-based display device.

[0057] Figure 2 It is a schematic diagram of a device cross-sectional structure in an existing method for manufacturing a silicon-based display device.

[0058] Figure 3 It is a schematic flow chart of a method for manufacturing a silicon-based display device according to a specific embodiment of the present invention.

[0059] Figure 4 yes Figure 3 A schematic diagram of the device cross-sectional structure in the manufacturing method of a silicon-based display device is shown.

[0060] Figure 5 It is a schematic diagram of the cross-sectional structure of a silicon-based display device according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0061] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] Please refer to Figure 2 The existing method for manufacturing an optical mirror electrode array 102 of a silicon-based display device on a platform of 0.18 μm to 0.11 μm comprises the following steps:

[0063] First, please refer to Figure 2 As shown in (A) in FIG. 1 , a silicon substrate (not shown) on which a CMOS device is manufactured is provided, and then a multi-layer metal connection structure (not shown) consisting of Al (aluminum) wires and W (tungsten) plugs is formed on the silicon substrate by a single damascene process, and two adjacent layers of Al wires are insulated and isolated by an interlayer dielectric layer (not shown). Afterwards, an Al layer 102a and a silicon oxide layer 201 for manufacturing an optical mirror electrode array are sequentially deposited on the top W plug and the interlayer dielectric layer.

[0064] Next, please refer to Figure 2 As shown in (B), a bottom anti-reflection layer 202 is deposited on the silicon oxide layer 201 and a first photoresist layer 203 is coated, and the first photoresist layer 203 is exposed and developed to define a pattern of the optical mirror electrode array 102 in the first photoresist layer 203, and further, using the remaining first photoresist layer 203 as a mask, the bottom anti-reflection layer 202, the silicon oxide layer 201 and the Al layer 102a are etched in sequence until the interlayer dielectric layer under the Al layer 102a is exposed to form a groove 200, whereby the remaining Al layer is the optical mirror electrode array 102.

[0065] Next, please refer to Figure 2 As shown in (C) to (D) in the figure, the remaining first photoresist layer 203 and the bottom anti-reflective layer 202 are removed, and an isolation dielectric layer 204 is deposited to fill the groove 200, a second photoresist layer 205 is coated on the isolation dielectric layer 204, and the second photoresist layer 205 is exposed and developed to define the pattern of the isolation dielectric layer 204 between the optical mirror electrode array 102 in the second photoresist layer 205.

[0066] Then, please refer to Figure 2 As shown in (E) to (F) in the figure, the isolation dielectric layer 204 is etched using the remaining second photoresist layer 205 as a mask to reduce the height of the isolation dielectric layer 204 on the top of the optical mirror electrode array 102 to a required height, and then the remaining second photoresist layer 205 is removed, thereby forming the isolation dielectric layer 204 between the optical mirror electrode arrays 102 to achieve isolation between the optical mirror electrode arrays 102.

[0067] The above solution is usually applied on the platform of 0.18um to 0.11um, and has the following defects:

[0068] 1. A method of photolithography combined with etching (litho+etching) is required to form the isolation dielectric layer 204 between the optical mirror electrode arrays 102, and the manufacturing process cost is high.

[0069] 2. The bottom of the optical mirror electrode array 102 contacts a tungsten plug, which results in a large RC delay, affecting the performance of the display device.

[0070] Based on the above-mentioned problems in the prior art, the present invention provides a silicon-based display device and a manufacturing method thereof, which uses a contact plug (such as copper) with an RC delay less than that of a tungsten plug to replace a tungsten plug, and has a lower resistance, and therefore has a lower RC delay performance. In addition, in the manufacturing method of the present invention, a second dielectric layer is deposited after forming an optical mirror electrode array, and the second dielectric layer is first CMPed and then wet-etched to achieve isolation of the optical mirror electrode array, which has a lower manufacturing cost than the method of photolithography combined with etching of the dielectric layer on the optical mirror electrode array in the prior art. Among them, the second dielectric layer is first CMPed to retain a certain thickness on the top surface of the optical mirror electrode, and then wet-etched to expose the top surface of the optical mirror electrode, which can avoid the problems of depression, micro scratches and oxidation caused by CMP directly grinding on the top surface of the optical mirror electrode, so that the optical mirror electrode array has a smooth and flat top surface, improves the reflectivity of the optical mirror electrode array, and is conducive to improving the consistency of the arrangement and thickness of the liquid crystal filled subsequently, avoiding light distortion.

[0071] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0072] Please refer to Figure 3 An embodiment of the present invention further provides a method for manufacturing a silicon-based display device, which comprises the following steps:

[0073] S1, providing a silicon substrate formed with a CMOS device, a metal connection structure and an interlayer dielectric layer, wherein the metal connection structure is electrically connected to the CMOS device and formed in the interlayer dielectric layer;

[0074] S2, forming a first dielectric layer and a contact plug having an RC delay smaller than that of the tungsten plug on the interlayer dielectric layer, wherein the contact plug penetrates the first dielectric layer and the bottom thereof is in electrical contact with the metal connection structure, and the top surface of the first dielectric layer is flat and exposes the top surface of the contact plug;

[0075] S3, depositing an optical mirror electrode material layer on the first dielectric layer, and etching the optical mirror electrode material layer to the first dielectric layer to form an optical mirror electrode array, wherein the bottom of each optical mirror electrode in the optical mirror electrode array is in electrical contact with the corresponding contact plug, and adjacent optical mirror electrodes are separated by isolation grooves;

[0076] S4, depositing a second dielectric layer on the optical mirror electrode array and the first dielectric layer and in the isolation trench;

[0077] S5, flattening and thinning the top surface of the second dielectric layer by a chemical mechanical polishing process, wherein the remaining second dielectric layer after the top surface flattening and thinning still buries the optical mirror electrode array;

[0078] S6, wet-etching the remaining second dielectric layer to expose the top surface of each of the optical mirror electrodes.

[0079] Please refer to Figure 4 In step (A), in step S1, a silicon substrate having a CMOS device (not shown), a metal connection structure 301 and an interlayer dielectric layer 300 is provided, wherein the CMOS device can refer to Figure 1As shown in the MOS in FIG. 1 , it can be formed in a silicon substrate using a CMOS process, and the CMOS process may include a well ion implantation process, a device isolation process (such as a local oxidation LOCOS process or a shallow trench isolation STI process), a gate process, a source-drain process, a capacitor process, a resistor process, etc. The CMOS process is a conventional process in the art and will not be described in detail herein.

[0080] As an example, the metal connection structure 301 and the interlayer dielectric layer 300 are formed by at least part of a copper dual damascene process, and the copper dual damascene process generally includes: depositing a corresponding interlayer dielectric layer and etching the interlayer dielectric layer, forming an interconnection line trench (trench) located at the top and an interconnection via (Via) located at the bottom and connected to the corresponding interconnection line trench in the interlayer dielectric layer, and depositing copper filling in the interconnection line trench and the interconnection via at the same time. Therefore, the metal connection structure 301 is a multi-layer copper interconnection structure, which includes a multi-layer copper interconnection line and an interconnection via electrically connecting the corresponding two layers of copper interconnection lines, and the adjacent two layers of copper interconnection lines are insulated and isolated by the interlayer dielectric layer 300, that is, the interlayer dielectric layer 300 of this example is formed by stacking multiple layers of dielectric materials, and the metal connection structure 301 is formed in the interlayer dielectric layer 300, and the interlayer dielectric layer 300 exposes a part of the top surface of the top copper interconnection structure of the metal connection structure 301.

[0081] It should be understood that the copper dual damascene process is divided into three methods according to the etching order of interconnection vias and interconnection line grooves: etching the interconnection line grooves first and then etching the interconnection vias, etching the interconnection vias first and then etching the interconnection line grooves, and etching the interconnection vias and interconnection line grooves together.

[0082] As an example, no matter which copper dual damascene process is used, the top layer of the metal connection structure 301 is a metal interconnection line (top metal), and its line width is 0.3μm to 0.5μm. As an example, the top layer of the top copper interconnection structure is a copper interconnection line (top metal), and the bottom surface of the contact plug formed in the subsequent step S2 is electrically in contact with the top surface of the top copper interconnection line.

[0083] As another example, the top interconnection via below the top copper interconnection line in the metal connection structure 301 may be a circular hole or a square hole, and its size is 0.3 μm to 0.5 μm.

[0084] Please refer to Figure 4(B) and (C), in step S2, a first dielectric layer 302 and a copper plug with an RC delay smaller than that of the tungsten plug are formed on the interlayer dielectric layer 300 and the metal connection structure 301 by a copper single damascene process, the first dielectric layer 302 covers the interlayer dielectric layer 300 and the metal connection structure 301, the copper plug serves as a contact plug 303 and is surrounded by the first dielectric layer 302, penetrates the first dielectric layer 302, and the bottom is electrically contacted with the top surface of the metal connection structure 301, the top surface of the first dielectric layer 302 is flat and the top surface of the contact plug 303 is exposed.

[0085] As an example, the contact plug 303 may be a circular hole or a square hole, with a size of 0.3 μm to 0.5 μm and a height range of The upper surface of the contact plug 303 has no filled hole.

[0086] Among them, the metal connection structure 301 is a multi-layer copper interconnection structure, and the contact plug 303 is a copper plug. On the one hand, it can achieve compatibility between the two and avoid the problem of metal contamination. On the other hand, by utilizing the advantages of copper having lower resistivity than metals such as aluminum and tungsten and being less prone to electromigration, it can reduce delays and achieve faster device speeds and higher device reliability.

[0087] As an example, the first dielectric layer 302 and the contact plug 303 are formed by using a copper single damascene process, and the specific process includes:

[0088] First, a first dielectric layer 302 is deposited on the interlayer dielectric layer 300 and the metal connection structure 301 by using a suitable process such as chemical vapor deposition. The material of the first dielectric layer 302 can be any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride or tetraethyl orthosilicate.

[0089] Next, a photolithography-etching process is used to etch the first dielectric layer 302 to the top surface of the metal interconnection structure 301 , thereby forming a contact hole 302 a exposing the top surface of the metal interconnection structure 301 .

[0090] Then, copper is deposited by electroplating or other processes to fill the contact through hole 302 a, and the deposited copper is further planarized on the top by chemical mechanical polishing to remove excess copper on the top surface of the first dielectric layer 302 , thereby forming a copper plug filled in the contact through hole 302 a as the contact plug 303 , and the top surface of the first dielectric layer 302 is substantially flush with the top surface of the contact plug 303 .

[0091] In this example, the contact plug 303 is made of Cu, which has the effects of low resistance and good compatibility with the metal connection structure 301 of the previous layer.

[0092] Please refer to Figure 4 (D) and (E) in step S3, first, a physical vapor deposition or chemical vapor deposition process such as evaporation or sputtering or plasma jet deposition is used to deposit an optical mirror electrode material layer (for example, a highly reflective metal material such as aluminum, copper-aluminum alloy and silver) on the top surface of the first dielectric layer 302 and the contact plug 303; then, a photolithography combined with etching process is used to etch the optical mirror electrode material layer to the top surface of the first dielectric layer 302 or to a certain depth at the top of the first dielectric layer 302, thereby forming an optical mirror electrode array 304, wherein the optical mirror electrodes in the optical mirror electrode array 304 are separated from each other by isolation grooves 304a, the depth of the isolation grooves 304a is the thickness of the optical mirror electrode, and the line width of the isolation grooves 304a is the spacing between the optical mirror electrodes in the optical mirror electrode array 304.

[0093] As an example, the thickness of the optical mirror electrode in the optical mirror electrode array 304 is That is, the depth of the isolation trench 304a is

[0094] As an example, the optical mirror electrodes in the optical mirror electrode array 304 are rectangular with a single side of more than 0.5 μm, and the line width of the isolation groove 304 a (ie, the spacing between the optical mirror electrodes) is 0.1 μm to 0.5 μm.

[0095] Optionally, in step S3, before depositing the optical mirror electrode material layer, a surface barrier layer is first deposited on the top surface of the first dielectric layer 302 and the contact plug 303; or after depositing the optical mirror electrode material layer and before etching the deposited optical mirror electrode material layer to form the optical mirror electrode array 304, a surface barrier layer (not shown) is deposited on the surface of the optical mirror electrode array 304; or, after etching the deposited optical mirror electrode material layer to form the optical mirror electrode array 304 and before performing step S4 (i.e., depositing a second dielectric layer 305 in the optical mirror electrode array 304 and the isolation trench 304a), a surface barrier layer (not shown) is deposited on the surface of the optical mirror electrode array 304.

[0096] The thickness of the surface barrier layer is, for example, The material thereof may include Ti or TiN or Ta or TaN or a composite laminated material thereof. The surface barrier layer is used to block metal diffusion in the optical mirror electrode.

[0097] It should be understood that the metal connection structure 301 , the contact plugs 303 and the optical mirror electrodes in the optical mirror electrode array 304 should be aligned from top to bottom, so the contact plugs 303 should also be arranged in an array.

[0098] Please refer to Figure 4 In (F), in step S4, a second dielectric layer 305 is deposited on the surface of the optical mirror electrode array 304 and the isolation groove 304a by using a process such as chemical vapor deposition. Whether the thickness of the deposited second dielectric layer 305 can fill the isolation groove 304a depends on the size of the isolation groove 304a, the thickness of the second dielectric layer 305 that needs to be retained, and other parameters.

[0099] As an example, in step S4, the second dielectric layer 305 is conformally deposited on the surface of the optical mirror electrode array 304 and the isolation groove 304a, and the deposited second dielectric layer 305 not only covers the top surface of each optical mirror electrode and the sidewall and bottom surface of the isolation groove 304a, but also conformally forms a first groove 306 with a large depth and a bottom surface higher or lower than the top surface of the optical mirror electrode at the isolation groove 304a. For example, the deposited second dielectric layer 305 is relatively thick and can fill the isolation groove 304a, so that the top surface of the portion of the second dielectric layer 305 covering the bottom surface of the isolation groove 304a is higher than the top surface of the optical mirror electrode (that is, the bottom surface of the first groove 306 is higher than the top surface of the optical mirror electrode), thereby forming a first groove 306 with a relatively large depth above the top surface of the optical mirror electrode at the isolation groove 304a after subsequent CMP. For another example, the deposited second dielectric layer 305 is relatively thin, conformally covers the sidewalls and bottom surface of the isolation trench 304a and does not fill the isolation trench 304a (i.e., has a filled gap), so that the top surface of the portion covering the bottom surface of the isolation trench 304a is lower than the top surface of the optical mirror electrode (i.e., the bottom surface of the first groove 306 is lower than the top surface of the optical mirror electrode), thereby forming a first groove 306 with a larger depth after subsequent CMP in the isolation trench 304a. The second dielectric layer 305 can be any suitable insulating dielectric material, such as tetraethyl orthosilicate (TEOS), high-density plasma silicon dioxide SiO 2 Or oxygen-rich silica (SRO), etc.

[0100] In another example, the deposited second dielectric layer 305 not only fills up the isolation trench 304 a , but also has a flat top surface at the end of the deposition due to the flow characteristics of the material itself during the deposition process.

[0101] Please refer to Figure 4 (G) in step S5, a chemical mechanical polishing (CMP) process is used to flatten and thin the top surface of the second dielectric layer 305, and the remaining second dielectric layer 305 not only covers the isolation groove 304a, but also covers a certain thickness on the top surface of each optical mirror electrode of the optical mirror electrode array 304, so as to avoid the problem of polishing defects such as depression, micro scratches and oxidation on the top surface of each optical mirror electrode when the chemical mechanical polishing process is polished to expose the top surface of the optical mirror electrode.

[0102] As an example, after the second dielectric layer 305 is conformally deposited on the surface of the optical mirror electrode array 304 and the isolation groove 304a in step S4 and the first groove 306 is formed in the second dielectric layer 305, the chemical mechanical polishing (CMP) process in step S5 grinds and consumes the second dielectric layer 305, and the upper part of the first groove 306 is grinded and consumed accordingly, thereby the second dielectric layer 305 on the side wall of the isolation groove 304a gradually becomes lower, and then the depth of the first groove 306 gradually decreases as the chemical mechanical polishing process proceeds, but the height of the bottom surface of the first groove 306 (i.e., the top surface of the second dielectric layer 305 on the bottom surface of the isolation groove 304a) remains unchanged, maintaining a state of being lower or higher than the top surface of the optical mirror electrode.

[0103] As another example, after the second dielectric layer 305 is conformally deposited on the surface of the optical mirror electrode array 304 and the isolation groove 304a in step S4 and the first groove 306 is formed in the second dielectric layer 305, the chemical mechanical polishing (CMP) process in step S5 grinds and consumes the second dielectric layer 305 and removes the first groove 306, so that the top surface of the second dielectric layer 305 remaining after CMP is flat and the thickness of the second dielectric layer 305 remaining on the top surface of each optical mirror electrode meets the requirements.

[0104] As another example, when the top surface of the second dielectric layer 305 deposited in step S4 is flat, the chemical mechanical polishing (CMP) process in step S5 flattens the top surface of the second dielectric layer 305 until the thickness of the second dielectric layer 305 remaining on the top surface of each optical mirror electrode meets the requirement.

[0105] As an example, after the chemical mechanical polishing process of step S5 is completed, the remaining second dielectric layer 305 covers the top surface of each optical mirror electrode of the optical mirror electrode array 304 with a thickness of

[0106]

[0107] Please refer to Figure 4 In (H), in step S6, a suitable etching solution is selected according to the material of the second dielectric layer, and the second dielectric layer 305 remaining after CMP is wet-etched to remove the second dielectric layer 305 on the top surface of each optical mirror electrode of the optical mirror electrode array 304.

[0108] In one example, when the first groove 306 is formed in the second dielectric layer 305 at the isolation groove after CMP in step S5, during the wet etching process in step S6, the etching liquid accumulates at the first groove 306, and in order to completely remove the second dielectric layer 305 on the top surface of the optical mirror electrode, the second dielectric layer 305 is over-etched after the top surface of each optical mirror electrode is exposed, that is, the over-etching not only completely removes the second dielectric layer 305 on the top surface of the optical mirror electrode, but also over-etches the second dielectric layer 305 at the first groove 306, thereby etching and consuming the second dielectric layer 305 at the first groove 306, making the first groove 306 wider and deeper and finally forming a second groove 306a. After this wet etching, the remaining thickness of the second dielectric layer 305 on the top surface of each optical mirror electrode is A portion of the second dielectric layer 305a remains on the sidewall and bottom surface of the isolation trench 304a, and the top surface of the second dielectric layer 305a on the bottom surface of the isolation trench 304a is lower than the top surface of the optical mirror electrode. (That is, the depth of the second groove 306a is ),For example To ensure the isolation performance between adjacent optical mirror electrodes in the optical mirror electrode array.

[0109] In another example, when the top surface of the second dielectric layer 305 after CMP in step S5 is flat, in the wet etching process in step S6, after the second dielectric layer 305 is wet-etched to expose the top surfaces of each of the optical mirror electrodes, the second dielectric layer 305 continues to be over-etched so that the residual second dielectric layer 305 on the top surface of the optical mirror electrode is completely removed, and at the same time, the second dielectric layer 305 in the isolation groove 304a is wet-etched and consumed, so that the remaining second dielectric layer 305a on the sidewall and bottom surface of the isolation groove 304a forms a second groove 306a.

[0110] As an example, the second dielectric layer 305 is silicon dioxide, and the second dielectric layer 305 after CMP is wet-etched using an HF acid solution or a diluted HF acid solution.

[0111] After CMP and wet etching of the second dielectric layer 305, the surfaces of the optical mirror electrodes of the optical mirror electrode array 304 have no insulating layer and are smooth and flat, thus meeting the reflectivity requirements of the device for the optical mirror electrode array.

[0112] After step S6, any suitable subsequent process may be used to continue to complete the manufacturing of other film layers or structures of the silicon-based display device. For example, a transparent dielectric material is deposited on the surface of the optical mirror electrode array 304 and the remaining second dielectric layer 305a, and a suitable technical means is used to enable the deposited transparent dielectric material to form a planarization layer 307 with a flat top surface. For another example, after the planarization layer 307 is formed, please refer to Figure 5 , a glass cover plate 310 having a transparent electrode 309 formed on one side is bonded to the silicon substrate, so that the optical mirror electrode array 304 is sandwiched between the transparent electrode 309 and the first dielectric layer 302, and further liquid crystal 308 is filled in the space between the transparent electrode 309 and the optical mirror electrode array 304. This situation is applicable to the manufacture of silicon-based liquid crystal display devices, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, in step S6, a luminescent material layer may be deposited on the optical mirror electrode array 304 and the second dielectric layer 305, and a transparent electrode may be further formed on the luminescent material layer, and the glass cover plate 310 may be bonded to the silicon substrate, so that the optical mirror electrode array 304 is sandwiched between the luminescent material layer and the first dielectric layer 302.

[0113] The manufacturing method of the silicon-based display device of this embodiment can replace the tungsten plug with a contact plug (such as copper) with an RC delay less than that of the tungsten plug, which has a lower resistance and thus has a lower RC delay performance. Moreover, after forming the optical mirror electrode array, a second dielectric layer is deposited, and the second dielectric layer is first CMPed and then wet-etched to achieve the isolation of the optical mirror electrode array. Compared with the method of photolithography combined with etching of the dielectric layer on the optical mirror electrode array in the prior art, the manufacturing cost is lower and the process is simpler. Moreover, after the second dielectric layer is first CMPed to retain a certain thickness on the top surface of the optical mirror electrode, it is wet-etched to expose the top surface of the optical mirror electrode, which can avoid the problems of depression, micro scratches and oxidation caused by CMP directly grinding on the top surface of the optical mirror electrode, so that the optical mirror electrode array has a smooth and flat top surface, improves the reflectivity of the optical mirror electrode array, and is conducive to improving the consistency of the arrangement and thickness of the liquid crystal filled subsequently, avoiding light distortion. Furthermore, the metal connection structure in the CMOS driving circuit of the silicon substrate is formed by a copper dual damascene process, and the contact plug used to realize the electrical connection between the metal connection structure and the optical mirror electrode array is formed by a copper single damascene process. Therefore, the "dual damascene + single damascene" process can be used to replace the single damascene process in the prior art to form the metal connection structure and the contact plug, which can save manufacturing costs.

[0114] In addition, please combine Figure 5When the silicon-based display device manufactured by the manufacturing method of the silicon-based display device according to the present embodiment is working, the CMOS device in the silicon substrate is led upward through the metal connection structure 301 and the contact plug 303, thereby providing an electric potential to the optical mirror electrode array 304, and realizing the control of the reflected light path of the light from above the glass cover 310. Since the surface of the optical mirror electrode array 304 is smooth and flat, the problem of light distortion will not occur. Moreover, since the metal connection structure 301 and the contact plug 303 can be formed of copper with a small RC delay, the display performance and response rate of the silicon-based display device are improved.

[0115] Based on the same invention concept, please refer to Figure 5 An embodiment of the present invention provides a silicon-based display device, which can be manufactured by the manufacturing method of the silicon-based display device of the present invention, or by any other suitable method. The silicon-based display device includes:

[0116] A silicon substrate having a CMOS device (not shown), a metal connection structure (301) and an interlayer dielectric layer 300, wherein the metal connection structure 301 is electrically connected to the CMOS device and is formed in the interlayer dielectric layer 300;

[0117] A first dielectric layer 302 and a contact plug 303 having a smaller RC delay than the tungsten plug are formed on the interlayer dielectric layer 300 and the metal connection structure 301. The contact plug 303 penetrates the first dielectric layer 302 and the bottom thereof is in electrical contact with the top of the metal connection structure 301. The top surface of the first dielectric layer 302 is flat and exposes the top surface of the contact plug 303.

[0118] An optical mirror electrode array 304 is formed on the first dielectric layer 302 and the contact plug 303, the bottom of each optical mirror electrode in the optical mirror electrode array 304 is in electrical contact with the corresponding contact plug 303, and adjacent optical mirror electrodes are separated by isolation grooves 304a;

[0119] The second dielectric layer 305a is filled in the isolation trench 304a to expose the top surface of each of the optical mirror electrodes.

[0120] A display material layer (not shown) is formed on the second dielectric layer 305 a and the optical mirror electrode array 304 .

[0121] Optionally, the metal connection structure 301 is a multi-layer copper interconnect structure formed by a copper dual damascene process at least on the top, and the top metal interconnect line is electrically in contact with the optical mirror electrode array 304 in the metal connection structure 301, and the contact plug 303 is a copper plug formed by a copper single damascene process, thereby making the contact plug 303 low in resistance and making the contact plug 303 well compatible with the metal connection structure 301 of the front layer, thereby preventing the problem of metal contamination.

[0122] Optionally, the optical mirror electrode is a single-layer film, or the optical mirror electrode includes a surface barrier layer in addition to the optical mirror electrode material layer, wherein the surface barrier layer can be stacked on the top surface of the optical mirror electrode material layer, or can be formed between the optical mirror electrode material layer and the contact plug. The material of the surface barrier layer can include at least one of Ti, TiN, Ta and TaN, and is used to prevent Al diffusion in the optical mirror electrode material layer.

[0123] Optionally, the second dielectric layer 305a is conformally covered on the inner surface of the isolation groove 304a (i.e., the second dielectric layer 305a covers the sidewalls and the bottom surface of the isolation groove 304a) and forms a groove 306a, and the top surface of the second dielectric layer 305a covered on the bottom surface of the isolation groove 304a is lower than the top surface of the optical mirror electrode in the optical mirror electrode array 304. Further, optionally, the top surface of the second dielectric layer 305a covered on the bottom surface of the isolation groove 304a is lower than the top surface of the optical mirror electrode in the optical mirror electrode array 304. (For example ), that is, the depth of the groove 306a is (For example ).

[0124] Optionally, the display material layer includes liquid crystal or light-emitting material.

[0125] Further optionally, the silicon-based display device further includes a glass cover plate 310 and a transparent electrode 309 , wherein the glass cover plate 310 is bonded to the silicon substrate, and the transparent electrode 309 is formed between the glass cover plate 310 and the display material layer.

[0126] In one example, the silicon-based display device of this embodiment is manufactured using the manufacturing method of the silicon-based display device in the above embodiment, so the material selection and size characteristics of its various structures, film layers, etc. are the same as the material selection and size characteristics when manufacturing the corresponding structures, film layers, etc. in the manufacturing method of the silicon-based display device in the above embodiment, and will not be repeated here. Optionally, the silicon-based display device of this embodiment includes at least one of the following parameter settings:

[0127] (1) The line width of the contact plug 303 is 0.3 μm to 0.5 μm;

[0128] (2) The height of the contact plug 303 is

[0129] (3) The material of the optical mirror electrode includes Al, and the thickness of the optical mirror electrode (ie, the depth of the isolation groove 304a) is

[0130] (4) The optical mirror electrode is a rectangle with a single side of more than 0.5 μm;

[0131] (5) The spacing of the optical mirror electrodes in the optical mirror electrode array (i.e., the line width of the isolation groove 304 a ) is 0.1 μm to 0.5 μm;

[0132] (6) The depth of the top surface of the second dielectric layer 305a covering the bottom surface of the isolation trench 304a relative to the top surface of the optical mirror electrode is That is, the depth of the groove formed by the second dielectric layer 305a in the isolation trench 304a is

[0133] In summary, the silicon-based display device of the present invention has lower resistance due to the use of contact plugs (such as copper) with a smaller RC delay than the tungsten plug to replace the tungsten plug, and therefore has lower RC delay performance. Moreover, when it is manufactured using the manufacturing method of the present invention, its optical mirror electrode array has a smooth and flat top surface, which improves the reflectivity of the optical mirror electrode array and is conducive to improving the consistency of the arrangement and thickness of the subsequently filled liquid crystal, avoiding light distortion. Furthermore, the metal connection structure between the formed contact plug and the silicon substrate is copper, thereby making the contact plug low in resistance while also making the contact plug compatible with the metal connection structure of the front layer, preventing the problem of metal contamination.

[0134] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a silicon-based display device, characterized in that: include: Providing a silicon substrate having a CMOS device, a metal connection structure and an interlayer dielectric layer, wherein the metal connection structure is electrically connected to the CMOS device and is formed in the interlayer dielectric layer; Forming a first dielectric layer and a contact plug having an RC delay smaller than that of a tungsten plug on the interlayer dielectric layer and the metal connection structure, wherein the contact plug penetrates the first dielectric layer and the bottom thereof is in electrical contact with the metal connection structure, and the top surface of the first dielectric layer is flat and exposes the top surface of the contact plug; Depositing an optical mirror electrode material layer on the first dielectric layer, and etching the optical mirror electrode material layer to the first dielectric layer to form an optical mirror electrode array, wherein the bottom of each optical mirror electrode in the optical mirror electrode array is in electrical contact with the corresponding contact plug, and adjacent optical mirror electrodes are separated by isolation grooves; Depositing a second dielectric layer on the optical mirror electrode array and the first dielectric layer and in the isolation trench; The second dielectric layer is flattened and thinned by a chemical mechanical polishing process, and the optical mirror electrode array is still buried in the remaining second dielectric layer after the top surface is flattened and thinned; The remaining second dielectric layer is wet-etched to expose the top surface of each of the optical mirror electrodes.

2. The manufacturing method according to claim 1, characterized in that A multilayer copper interconnection structure is formed at least on the top by using a copper dual damascene process as the metal connection structure, and a copper plug is formed on the interlayer dielectric layer by using a copper single damascene process as the contact plug.

3. The manufacturing method according to claim 2, characterized in that: The step of forming a copper plug as the contact plug on the interlayer dielectric layer by using a copper single damascene process comprises: Depositing the first dielectric layer on the interlayer dielectric layer and the metal connection structure, and etching the first dielectric layer to the top surface of the top copper interconnect structure of the metal interconnect structure to form a contact through hole exposing the top surface of the top copper interconnect structure; Copper is deposited to fill the contact through hole, and the deposited copper is planarized by a chemical mechanical polishing process until the top surface of the first dielectric layer is exposed, thereby forming a copper plug as the contact plug.

4. The manufacturing method according to claim 1, characterized in that: When the remaining second dielectric layer is wet-etched, the second dielectric layer is overetched after the top surface of each of the optical mirror electrodes is exposed, so that the second dielectric layer retained in the isolation trench forms a second groove.

5. The manufacturing method according to claim 4, characterized in that: When the second dielectric layer is deposited on the optical mirror electrode array and the first dielectric layer and in the isolation groove, the deposited second dielectric layer conformally forms a first groove at the isolation groove, and after the second dielectric layer is flattened and thinned by the chemical mechanical polishing process, the first groove is partially retained or removed; or, when the second dielectric layer is deposited on the optical mirror electrode array and the first dielectric layer and in the isolation groove, the deposited second dielectric layer fills the isolation groove and has a flat top surface.

6. The manufacturing method according to claim 4, characterized in that: Include at least one of the following parameter settings: (1) The line width of the contact plug is 0.3 μm to 0.5 μm; (2) The height of the contact plug is (3) The material of the optical mirror electrode includes Al, and the thickness of the optical mirror electrode is (4) The optical mirror electrode is a rectangle with a single side of more than 0.5 μm; (5) The spacing between the optical mirror electrodes in the optical mirror electrode array is 0.1 μm to 0.5 μm; (6) After the second dielectric layer is flattened and thinned by chemical mechanical polishing, the second dielectric layer has a coverage thickness of 1000 nm on the top surface of the optical mirror electrode. (7) The depth of the second groove relative to the top surface of the optical mirror electrode is 7. The manufacturing method according to claim 1, characterized in that: After depositing the optical mirror electrode material layer and before etching the optical mirror electrode material layer, or after etching the optical mirror electrode material layer and before depositing the second dielectric layer, a surface barrier layer is further deposited on the optical mirror electrode material layer.

8. The manufacturing method according to claim 1, characterized in that: After wet etching the remaining second dielectric layer, the method further includes: forming a display material layer on the second dielectric layer and the optical mirror electrode array.

9. The manufacturing method according to claim 8, characterized in that: The display material layer includes a liquid crystal layer, and the steps of forming the display material layer include: bonding a glass cover plate having a transparent electrode formed on one side to the silicon substrate, sandwiching the optical mirror electrode array between the transparent electrode and the first dielectric layer, and further filling the space between the transparent electrode and the optical mirror electrode array with liquid crystal; Alternatively, the display material layer includes a luminescent material layer, and the step of forming the display material layer includes: depositing the luminescent material layer on the second dielectric layer and the optical mirror electrode array.

10. A silicon-based display device, characterized in that: include: A silicon substrate having a CMOS device, a metal connection structure and an interlayer dielectric layer, wherein the metal connection structure is electrically connected to the CMOS device and is formed in the interlayer dielectric layer; A first dielectric layer and a contact plug having a smaller RC delay than the tungsten plug are formed on the interlayer dielectric layer and the metal connection structure, the contact plug penetrates the first dielectric layer and the bottom is in electrical contact with the metal connection structure, and the top surface of the first dielectric layer is flat and exposes the top surface of the contact plug; An optical mirror electrode array is formed on the first dielectric layer, the bottom of each optical mirror electrode in the optical mirror electrode array is in electrical contact with the corresponding contact plug, and adjacent optical mirror electrodes are separated by isolation grooves; A second dielectric layer is filled in the isolation trench to expose the top surface of each of the optical mirror electrodes; The display material layer is formed on the second medium layer and the optical mirror electrode.

11. The silicon-based display device according to claim 10, characterized in that: The metal connection structure is a multilayer copper interconnect structure formed at least at the top by a copper dual damascene process, and the top copper interconnect structure is in electrical contact with the optical mirror electrode array in the metal connection structure. The contact plug is a copper plug formed by a copper single damascene process.

12. The silicon-based display device according to claim 10, wherein: The optical mirror surface electrode is a single-layer film or includes an optical mirror surface electrode material layer and a surface barrier layer stacked on the optical mirror surface electrode material layer.

13. The silicon-based display device according to claim 10, wherein: The second dielectric layer conformally covers the inner surface of the isolation trench and forms a groove, and the bottom surface of the groove is lower than the top surface of the optical mirror electrode.

14. The silicon-based display device according to claim 13, characterized in that: Include at least one of the following parameter settings: (1) The line width of the contact plug is 0.3 μm to 0.5 μm; (2) The height of the contact plug is (3) The material of the optical mirror electrode includes Al, and the thickness of the optical mirror electrode is (4) The optical mirror electrode is a rectangle with a single side of more than 0.5 μm; (5) The spacing between the optical mirror electrodes in the optical mirror electrode array is 0.1 μm to 0.5 μm; (6) The depth of the bottom surface of the groove relative to the top surface of the optical mirror electrode is 15. The silicon-based display device according to claim 10, wherein: The display material layer includes liquid crystal or light-emitting material; or, the silicon-based display device further includes a glass cover plate and a transparent electrode, one side of the glass cover plate is bonded to the silicon substrate, and the transparent electrode is formed between the glass cover plate and the display material layer.

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