A low quiescent current loop adaptive regulation linear voltage regulator

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a low quiescent current loop adaptive regulation linear voltage regulator, which comprises a power detection comparator, an adaptive current source, a loop regulation module, a PMOS tube Mp, an NMOS tube Mc, a gate discharge module, a capacitor Cm, an error operational amplifier, a band gap reference, and three resistors R1, R2 and Rm, and each device is sequentially connected to form the low quiescent current loop adaptive regulation linear voltage regulator. The low quiescent current loop adaptive regulation linear voltage regulator circuit can simultaneously have the characteristics of low quiescent current and fast response, and can be adaptively adjusted when the load current and the input-output voltage difference change, so that the static power consumption is reduced while the response speed is ensured.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a low quiescent current loop adaptive regulation linear voltage regulator. BACKGROUND

[0002] Low dropout regulator (LDO) is widely used in portable electronic devices, wearable applications and system on chip (SOC) fields due to good voltage stability, small size and other characteristics. The traditional LDO needs to consume static current when working, and the low quiescent current LDO chip has the characteristics of energy saving and high efficiency, and can consume less power in the standby or resting state of the whole device, and can be widely used in battery, communication, radar and other long standby devices.

[0003] The existing low quiescent current linear voltage regulator mainly reduces the internal branch current by using high square resistance in the branch to achieve it. Figure 1 As shown in the figure, it is composed of bandgap reference, error amplifier, current source, power tube Mp and control tube Mc, and feedback resistors R1 and R2. Since the bias provided by the current source is fixed, if the current setting is large, the static power consumption increases; if the current setting is small, the loop response speed will be slow when the load changes, and even cannot perform feedback adjustment. But the main defect of this kind of low quiescent current LDO is that the loop internal static current is relatively small, which leads to slow loop feedback speed and long response time. At the same time, under the condition of large load working, there is also the risk of abnormal loop function caused by weak response ability. Therefore, many low quiescent current LDOs cannot further reduce the static power consumption or work under large load current. This also limits the application range of low quiescent current LDO. SUMMARY

[0004] In order to solve the problems existing in the prior art, the application provides a low quiescent current loop adaptive regulation linear voltage regulator, which comprises a power detection comparator, an adaptive current source, a loop regulation module, a PMOS tube Mp, an NMOS tube Mc, a gate discharge module, a capacitor Cm, an error amplifier, a bandgap reference and three resistors R1, R2 and Rm.

[0005] The connection relationship of each device comprises that the output end of the bandgap reference is connected with the positive input end of the error operational amplifier, one end of resistors R1 and R2 is connected with the negative input end of the error operational amplifier, the output end of the error operational amplifier is connected with the output end of the gate discharge module, one end of the resistor Rm and the gate of Mc, the other end of the resistor R2 is grounded, the other end of the resistor R1 is connected with the drain of Mp and the negative input end of the power detection comparator, the positive input end of the power detection comparator is connected with the input end of the adaptive current source and the source of Mp, the first output end of the power detection comparator is connected with the first input end of the loop regulation module, the second output end of the power detection comparator is connected with the input end of the gate discharge module, the output end of the adaptive current source is connected with the second input end of the loop regulation module, the output end of the loop regulation module is connected with the gate of Mp, one end of Cm and the drain of Mc, the other end of Cm is connected with the other end of Rm, the source of Mc is grounded, and the other end of the resistor R2 is grounded.

[0006] The beneficial effects of the present application are as follows:

[0007] The present application can simultaneously have the characteristics of low static current and fast response by designing a low static current loop adaptive regulation linear voltage regulator circuit, and can adaptively adjust when the load current and the input-output voltage difference change, thereby reducing the static power consumption while ensuring a faster response speed. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 It is a structural schematic diagram of a traditional linear voltage regulator;

[0009] Figure 2 It is a structural diagram of a low static current loop adaptive regulation linear voltage regulator circuit of the present application;

[0010] Figure 3 It is a circuit structural diagram of an adaptive current source circuit of the present application;

[0011] Figure 4 It is a circuit structural diagram of a power detection comparator of the present application;

[0012] Figure 5 It is a circuit structural diagram of a loop regulation module of the present application;

[0013] Figure 6 It is a circuit structural diagram of a gate discharge module of the present application;

[0014] Figure 7 It is a comparison simulation diagram of the circuit of the present application and the power-on speed of a traditional LDO;

[0015] Figure 8 It is a comparison simulation diagram of the circuit of the present application and the transient load response of a traditional LDO. DETAILED DESCRIPTION

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] The present invention aims to solve the aforementioned problems of low quiescent current LDO chips by providing a low quiescent current loop adaptive adjustment linear regulator circuit that has lower quiescent power consumption and faster loop response speed.

[0018] A low quiescent current loop adaptive adjustment linear regulator, such as Figure 2 As shown, the circuit includes: a power detection comparator, an adaptive current source, a loop adjustment module, a PMOS transistor Mp, an NMOS transistor Mc, a gate discharge module, a capacitor Cm, an error operational amplifier, a bandgap reference, and three resistors R1, R2, and Rm. The output of the bandgap reference is connected to the positive input of the error operational amplifier. The negative input of the error operational amplifier is connected to one end of resistors R1 and R2, respectively. The output of the error operational amplifier is connected to the output of the gate discharge module, one end of resistor Rm, and the gate of Mc, respectively. The other end of resistor R2 is grounded. The other end of resistor R1 is connected to the drain of Mp and the power... The negative input terminal of the power detection comparator is connected to the input terminal of the adaptive current source and the source of Mp. The first output terminal of the power detection comparator is connected to the first input terminal of the loop adjustment module, and the second output terminal of the power detection comparator is connected to the input terminal of the gate discharge module. The output terminal of the adaptive current source is connected to the second input terminal of the loop adjustment module. The output terminal of the loop adjustment module is connected to the gate of Mp and the output terminal of the loop adjustment module is connected to one end of Cm and the drain of Mc. The other end of Cm is connected to the other end of Rm. The source of Mc is grounded. The other end of resistor R2 is grounded.

[0019] In this embodiment, the adaptive current source detects the difference between the input voltage and the gate voltage of the power transistor, i.e., the Vt of the power transistor. GS When the voltage difference is small, the adaptive current source uses a small current channel, providing only a small quiescent current to maintain loop operation. When the voltage difference exceeds a threshold, the current source activates a large current channel to provide sufficient current for the loop response. The power detection comparator can detect the input and output voltage difference. Depending on the voltage difference, the control loop regulation module and the gate discharge module adjust the control transistor M. c The gate voltage and drain path are regulated and controlled. The loop regulation module receives the output voltage of the power detection comparator and selects and regulates M. cThe current channel of the drain end ensures the matching of the loop response capability; the gate discharge module receives another output voltage of the power detection comparator, controls the output voltage of the error operational amplifier EA, and quickly discharges the voltage when needed to improve the loop response speed. The error operational amplifier and the band gap reference can be selected from the existing common operational amplifier structure and reference structure as the corresponding functional modules in the application. In the linear voltage regulator, the positive input end of the power detection comparator is used as the input end of the entire circuit, and the Vin signal is input into the device; and the drain of Mp is used as the output end of the device.

[0020] As shown in Figure 4 , the power detection comparator comprises 5 NMOS tubes M6-M10, 8 PMOS tubes M4, M5, M11-M16, and 6 resistors R6-R11; one end of the resistor R6 is connected to the source of M11, the source of M12, the source of M13, and the source of M14, and inputs the signal Vin; the other end of the resistor R6 is connected to the source of M4, the gate of M4 is connected to the drain of M4 and one end of R8 respectively; the other end of R8 is connected to the gate of M8 and one end of R9 respectively; the other end of R9 is connected to the drain of M6; the gate of M6 is connected to the gate of M7 and the gate of M10, and the source of M6 is grounded; the source of M7 is grounded, and the drain of M7 is connected to the drain of M5, the gate of M5, and the gate of M9 respectively; the source of M5 is connected to one end of the resistor R7; the other end of R7 inputs the Vout signal; the source of M10 is grounded, and the drain of M10 is connected to the source of M9 and the source of M8 respectively; the drain of M8 is connected to one end of the resistor R10; the other end of R10 is connected to the drain of M11, the gate of M11, and the gate of M13 respectively; the drain of M9 is connected to one end of the resistor R11; the other end of R11 is connected to the drain of M12, the gate of M12, and the gate of M14 respectively; the drain of M13 is connected to the source of M15; the gate of M15 is connected to the gate of M16 and inputs the Vb2 signal, and the drain of M15 is used as the first output end of the power detection comparator; the source of M16 is connected to the drain of M14, and the drain of M16 is used as the second output end of the power detection comparator.

[0021] As shown in Figure 3 , the adaptive current source comprises 1 PMOS tube M1, 2 diodes D1-D2, and 3 resistors R3-R5; the source of M1 is connected to one end of R3 and the positive electrode of D1 after being connected to the signal Vin respectively, the gate of M1 is connected to one end of R5 and the negative electrode of D2 after being connected to the signal Ic respectively, and the drain of M1 is connected to the other end of R3 and one end of R4 respectively; the other end of R4 is connected to the other end of R5, the positive electrode of D2, and the negative electrode of D1 respectively; the gate of M1 is used as the signal output end of the adaptive current source.

[0022] As shown in Figure 5As shown, the loop adjustment module includes: a transistor Q1, three resistors R12-R14, two capacitors C1-C2, and three NMOS transistors M17-M19; the collector of Q1 is connected to the base of Q1, the gate of M17, one end of resistor R13, and one end of capacitor C2; the emitter of Q1 is connected to one end of resistor R12 and one end of capacitor C1; the other ends of resistor R12, capacitor C1, and capacitor C2 are all grounded; the other end of resistor R13 is connected to the source of M17 and the gate of M18; the drain of M17 is connected to the gate of M19; the drain of M18 is connected to one end of resistor R14, and the source of M18 is connected to the source of M19, serving as the output terminal of the loop adjustment module; the other end of resistor R14 is connected to the drain of M19.

[0023] In this embodiment, the collector of transistor Q1 in the loop adjustment module is used as the first input terminal of the loop adjustment module, the drain of M18 is used as the second input terminal of the loop adjustment module, and the drain of M17 is used as the third input terminal of the loop adjustment module.

[0024] like Figure 6 As shown, the gate discharge module includes: nine NMOS transistors M20 to M28, two transistors Q2 to Q3, and one resistor R15; the sources of M20, M21, and M22, the emitter of Q2, the source of M23, and the emitter of Q3 are all grounded; the drain of M20 is connected to the gates of M20, M21, M22, and M23 respectively; the drain of M21 is connected to the collector of Q2, the gate of M24, the gate of M25, and the gate of M28 respectively. The gates of M26, M27, and M28 are connected; the drain of M22 is connected to the base of Q2, the source of M24, the source of M25, the source of M26, and the source of M27; the drain of M24 is connected to the drain of M25, the drain of M26, the drain of M27, and the drain of M28; the source of M28 is connected to one end of resistor R15 and the drain of M23; the other end of R15 is connected to the base of Q3; the collector of Q3 serves as the output terminal of the gate discharge module.

[0025] The adaptive current source, power detection comparator, loop adjustment module, and gate discharge module of this invention are specifically implemented as shown in the appendix. Figure 3 , Figure 4 , Figure 5 , Figure 6 As shown. Figure 3 The adaptive current source of this invention has an input terminal connected to a Vin voltage and an output terminal connected to the gate of a power transistor. Its function is to detect the difference between the input voltage and the gate voltage of the power transistor to adjust the current source current I. cThe size of the module. The module is mainly composed of M1 PMOS tube and D1 diode current control channel, resistance R3, R4, R5 as current distribution resistance, diode D2 as clamping diode. Among them, R3, R4 resistance is much larger than R5. When the load current I D Small, power tube has:

[0026]

[0027] Among them, V GS The gate-source voltage of power tube, I D The load current through the power tube, μ n The electron mobility, C ox The unit area gate oxide capacitance, W is the channel width, L is the channel length, V TH The power tube opening threshold.

[0028] Because I D Small, the pressure difference V GS Also relatively small, M1 tube opens, the current from Vin through M1, R3, R4, R5 output current I c , the size is about

[0029]

[0030] Among them, I c The bias current provided by the current source at this time, R on1 The on-resistance of M1 tube, R3 is the resistance of R3, R4 is the resistance of R4, R5 is the resistance of R5.

[0031] With the increase of load current, due to the negative feedback regulation of LDO loop, the gate voltage of power tube decreases, V GS Increase. At this time, M1 tube is fully open, and diode D1 is turned on, the current from Vin through M1, R3, R4, D1 and R5 output current I c , the current size is about:

[0032]

[0033] Among them, R D1 The on-resistance of diode D1.

[0034] If the load appears larger jump, so that the gate of power tube instantaneously reduces more, at this time V GS Further increase, reach V THD1 +V THD2 , M1, D1, D2 are opened, at this time most of the current directly from D1, D2 through directly provide I c , while D2 constitutes a clamping circuit to prevent VGS The difference is too large. THD1 and V THD2 These are the forward conduction threshold voltages of diodes D1 and D2, respectively.

[0035] In this embodiment, Figure 4 The power detection comparator of the present invention is used to provide control voltage for the loop regulation module and the gate discharge module by detecting the voltage difference between the power supply Vin and the output Vout. It mainly consists of three parts: (1) Input sampling, which is composed of resistors R6, R7, R8, R9, PMOS transistors M4 and M5, and NMOS transistors M6 and M7. R6 and R7 are used to reduce the branch current, R8 and R9 are used to set the sampling voltage of Vin. The sampling ratio is determined by adjusting the ratio of R8 and R9. M6 and M7 provide bias current. This part mainly transmits the voltage changes of Vin and Vout to the next stage comparator; (2) The comparator is composed of NMOS transistors M8, M9, and M10, PMOS transistors M11, M12, M13, M14, M15, and M16, and resistors R10 and R11. R10 and R11 are used to reduce the branch current, M11 and M12 are active loads, M8 and M9 are input differential pair transistors, and M10 provides tail current. M13, M14, M15, and M16 are the second stage common source and common gate structure to amplify the control signal. This part mainly detects the voltage difference change between the sampled voltages of Vin and Vout, outputs the gate discharge signal Vsink and the loop adjustment signal Vc to further control the loop. When the voltage difference increases, the drain voltage of M9 decreases and the drain voltage of M8 increases, which causes the output voltage Vsink of the second-stage Cascode amplifier composed of M14 and M16 to decrease and the drain output voltage Vctrl of M13 and M15 to increase.

[0036] Figure 5 The loop regulation module of this invention has its IC terminal connected to the current provided by the adaptive current source, and its loop regulation output terminal connected to the drain of the control NMOS transistor Mc below. Its function is to receive the loop regulation voltage Vctrl, and use this voltage to control the gate voltages of M18 and M19, thereby controlling the current path flowing into the drain of the Mc transistor. M18 and M19 are high-voltage LDMOS transistors used to withstand the high voltage of the power gate. Q1, R12, and C1 convert the current flowing out of the loop regulation signal Vctrl port into a stable voltage through resistors and capacitors. M17, R13, and C2 are used to control the gate voltage of transistor M18, where M17 is the main voltage control transistor. C2 and R13 provide a stable control voltage to M18 after the loop stabilizes, while avoiding the threshold voltage V of M17. TH7The loss of control voltage. M18, M19 and R14 constitute a loop current path. When the Vctrl signal is low, the M17 source voltage is low, so that the M18 tube is weakly opened, and the current passing through is less, while the M19 tube is controlled by the bias voltage Vb and is in a constant open state, and the loop current only passes through M19 and R14. Since R14 has a large resistance, in this case, the drain current of the control tube Mc is limited, and the overall loop will work with a small static current; when the Vctrl signal becomes larger, Q1 will form a stable voltage through R12 and C1, and the gate voltage of M17 will rise. When Vctrl > V TH17 , the source voltage of M17 rises, and when Vctrl - V TH17 > V GS18 , it makes M18 open to a greater extent, and the current passing through increases. At this time, the loop current flows through two channels at the same time, speeding up the loop response. Then, the source voltage of M17 becomes consistent with Vctrl, and M18 continues to be opened, maintaining stability when transient changes occur in Vctrl.

[0037] In this embodiment, Figure 6 is a gate bleeder module of the application, whose gate bleeder output is connected to the gate of the control tube Mc, and its function is to receive the gate bleeder signal Vsink and control the bleeder NPN tube Q3 to bleed the output voltage of the error amplifier, speeding up the loop response. NMOS tubes M20, M21, M22, M23 constitute a bias circuit for providing the bias current of the module, M24, M25, M26, M27 and Q2 constitute a clamping circuit to prevent the Vsink voltage from being too high momentarily, and M28, R15 and Q3 constitute a bleeder path for bleeding the error amplifier output and reducing the voltage. When Vsink is a low voltage, M24, M25, M26, M27 and M28 are not conductive, and the module does not work. When the Vsink voltage is high, the five NMOS tubes are conductive, the source potential of M28 rises, and at the same time, the current controls the base of Q3, opening the NPN tube Q3, thereby pulling down the output of the error amplifier. When Vsink is momentarily high, since M24, M25, M26 and M27 have stronger current capacity than M28, according to the power tube formula, the Q2 base voltage will be higher than the Q3 base voltage. At this time, if Q2 is conductive, it will pull down the Vsink voltage, preventing the voltage from being too high and causing damage to M28 and Q3.

[0038] The principle of the overall circuit module of the present application is explained as follows: when the input Vin and output Vout voltage difference is small and the load current is small, the adaptive current source outputs a small current Ic, and the power detection module outputs a low loop regulation signal Vctrl and a high gate sink signal Vsink, the Vctrl voltage control loop regulation module only opens the low static current channel, and the Vsink voltage pulls down the error op-amp output through the discharge path, so that the power transistor gate voltage is raised as soon as possible, and the overall LDO is in the lowest static power consumption mode; when the load current becomes large, the adaptive current source opens other channels, thereby outputting a larger current Ic, and the loop regulation signal Vctrl output by the power detection module is raised, and the gate sink signal Vsink is lowered, so that the Vctrl voltage control loop regulation module opens the large static current channel, and the Vsink voltage closes the discharge path to lower the power transistor gate voltage. The overall static current of the LDO increases, improving the response speed of the loop; when the input Vin and output Vout voltage difference is large and the load current is small, the adaptive current source still outputs a small current Ic at this time, and the static current does not increase much, but the loop current channel opens the large current channel, which facilitates rapid feedback response when Ic increases rapidly after the load increases. Figure 7 For the instant power-on simulation diagram of the circuit of the present application and the conventional low-power LDO, it can be seen that the power-on speed of the present application is much faster than that of the conventional LDO due to the existence of the large current channel, and the static current does not increase significantly after stabilization; Figure 8 For the load transient response simulation diagram of the circuit of the present application and the conventional low-power LDO, the response speed of the circuit of the present application is significantly faster than that of the conventional LDO when the load suddenly increases.

[0039] Figure 7 The middle upper part is the output voltage waveform of the conventional low-power LDO during power-on, and the lower part is the output voltage waveform of the present application during power-on. It can be seen that the response speed of the present application is much faster than that of the ordinary LDO circuit under a large Vin, Vout voltage difference.

[0040] Figure 8 The middle upper part is the output voltage waveform of the conventional low-power LDO when the load suddenly changes, and the lower part is the output voltage waveform of the present application when the load suddenly changes. It can be seen that the load transient response speed of the present application is much faster than that of the ordinary LDO circuit.

[0041] The above examples further illustrate the purpose, technical solutions and advantages of the present application. It should be understood that the above examples are only preferred embodiments of the present application and do not limit the present application. Any modification, equivalent replacement, improvement, etc. made to the present application within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A low quiescent current loop adaptive regulated linear voltage regulator, characterized by, It comprises: a power detection comparator, an adaptive current source, a loop regulation module, a PMOS tube Mp, an NMOS tube Mc, a gate discharge module, a capacitor Cm, an error operational amplifier, a bandgap reference, and three resistors R1, R2, and Rm; The output end of the bandgap reference is connected to the positive input end of the error operational amplifier; one end of the resistors R1 and R2 is respectively connected to the negative input end of the error operational amplifier, and the output end of the error operational amplifier is respectively connected to the output end of the gate discharge module, one end of the resistor Rm, and the gate of the Mc; the other end of the resistor R2 is grounded; the other end of the resistor R1 is respectively connected to the drain of the Mp and the negative input end of the power detection comparator; the positive input end of the power detection comparator is connected to the input end of the adaptive current source and the source of the Mp, the first output end of the power detection comparator is connected to the first input end of the loop regulation module, and the second output end of the power detection comparator is connected to the input end of the gate discharge module; the output end of the adaptive current source is connected to the second input end of the loop regulation module; the output end of the loop regulation module is connected to the gate of the Mp and one end of the Cm and the drain of the Mc; the other end of the Cm is connected to the other end of the Rm; the source of the Mc is grounded. The adaptive current source comprises one PMOS tube M1, two diodes D1-D2, and three resistors R3-R5; the source of the M1 is respectively connected to one end of the R3 and the positive pole of the D1 connected to the signal Vin, the gate of the M1 is respectively connected to one end of the resistor R5 and the negative pole of the D2 connected to the signal Ic, and the drain of the M1 is respectively connected to the other end of the resistor R3 and one end of the resistor R4; the other end of the resistor R4 is respectively connected to the other end of the resistor R5, the positive pole of the D2, and the negative pole of the D1; the gate of the M1 is taken as the signal output end of the adaptive current source.

2. The low quiescent current loop adaptive regulated linear voltage stabilizer according to claim 1, wherein, In the linear voltage regulator, the positive input end of the power detection comparator is taken as the input end of the whole circuit, and the Vin signal is input to the device; the drain of the Mp is taken as the output end of the device.

3. The low quiescent current loop adaptive regulated linear voltage stabilizer according to claim 1, wherein, The power detection comparator comprises five NMOS tubes M6-M10, eight PMOS tubes M4, M5, M11-M16 and six resistors R6-R11; one end of the resistor R6 is connected to the source of M11, the source of M12, the source of M13 and the source of M14, and inputs a signal Vin; the other end of the resistor R6 is connected to the source of M4, the gate of M4 is connected to the drain of M4 and one end of R8 respectively; the other end of R8 is connected to the gate of M8 and one end of R9 respectively; the other end of R9 is connected to the drain of M6; the gate of M6 is connected to the gate of M7 and the gate of M10, and the source of M6 is grounded; the source of M7 is grounded, and the drain of M7 is connected to the drain of M5, the gate of M5 and the gate of M9 respectively; the source of M5 is connected to one end of the resistor R7; the other end of R7 inputs a Vout signal; the source of M10 is grounded, and the drain of M10 is connected to the source of M9 and the source of M8 respectively; the drain of M8 is connected to one end of the resistor R10; the other end of R10 is connected to the drain of M11, the gate of M11 and the gate of M13 respectively; the drain of M9 is connected to one end of the resistor R11; the other end of R11 is connected to the drain of M12, the gate of M12 and the gate of M14 respectively; the drain of M13 is connected to the source of M15; the gate of M15 is connected to the gate of M16 and inputs a Vb2 signal, and the drain of M15 is the first output end of the power detection comparator; the source of M16 is connected to the drain of M14, and the drain of M16 is the second output end of the power detection comparator.

4. The low quiescent current, low dropout linear regulator with adaptive loop compensation of claim 1, wherein, The loop regulation module comprises one triode Q1, three resistors R12-R14, two capacitors C1-C2 and three NMOS tubes M17-M19; the collector of Q1 is connected to the base of Q1, the gate of M17, one end of the resistor R13 and one end of the capacitor C2 respectively, and the emitter of Q1 is connected to one end of the resistor R12 and one end of the capacitor C1 respectively; the other end of the resistor R12, the other end of the capacitor C1 and the other end of the capacitor C2 are all grounded; the other end of the resistor R13 is connected to the source of M17 and the gate of M18 respectively; the drain of M17 is connected to the gate of M19; the drain of M18 is connected to one end of the resistor R14, and the source of M18 is connected to the source of M19 and serves as the output end of the loop regulation module; the other end of the resistor R14 is connected to the drain of M19.

5. The low quiescent current, low dropout linear regulator with adaptive loop compensation of claim 4, wherein, The collector of the triode Q1 in the loop regulation module serves as the first input end of the loop regulation module, the drain of M18 serves as the second input end of the loop regulation module, and the drain of M17 serves as the third input end of the loop regulation module.

6. The low quiescent current, low dropout linear regulator with adaptive loop compensation of claim 1, wherein, The gate discharge module comprises 9 NMOS tubes M20-M28, 2 triodes Q2-Q3 and 1 resistor R15; the source of M20, the source of M21, the source of M22, the emitter of Q2, the source of M23 and the emitter of Q3 are grounded; the drain of M20 is connected with the gate of M20, the gate of M21, the gate of M22 and the gate of M23 respectively; the drain of M21 is connected with the collector of Q2, the gate of M24, the gate of M25, the gate of M26, the gate of M27 and the gate of M28 respectively; the drain of M22 is connected with the base of Q2, the source of M24, the source of M25, the source of M26 and the source of M27 respectively; the drain of M24 is connected with the drain of M25, the drain of M26, the drain of M27 and the drain of M28 respectively; the source of M28 is connected with one end of the resistor R15 and the drain of M23 respectively; the other end of R15 is connected with the base of Q3; the collector of Q3 is the output terminal of the gate discharge module.

7. The low quiescent current, low dropout linear regulator with adaptive loop compensation of claim 6, wherein, M20, M21, M22 and M23 in the gate discharge module constitute a bias circuit for providing the bias current of the module; M24, M25, M26, M27 and Q2 constitute a clamping circuit for preventing the transient voltage of the gate discharge signal from increasing; M28, R15 and Q3 constitute a discharge path for discharging the error op-amp output.

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