Verification method and device for design DUT to be tested, equipment and storage medium

Abstract

The invention provides a verification method and device for a to-be-tested design DUT, equipment and a storage medium. The method comprises the following steps: determining target excitation according to the sending times of directional excitation corresponding to each to-be-verified function; arbitrating each to-be-verified function by using an arbiter to obtain an arbitration result corresponding to the first target function; and generating the target excitation corresponding to the first target function according to the arbitration result corresponding to the first target function, and verifying the DUT according to the target excitation corresponding to the first target function. According to the method, sending of the directional excitation corresponding to the to-be-verified function is added on the basis of the random excitation, wrong verification or missed verification of some to-be-verified functions is avoided, and verification effectiveness and verification quality are improved.

Description

Technical Field

[0001] The present application relates to chip verification technology, and in particular to a verification method, device, equipment and storage medium for a designed DUT to be tested. Background Art

[0002] With the rapid development of the Intellectual Property (IP) design and System on Chip (SOC) design industries and the rapid increase in chip application requirements, IP design and SOC design are showing a trend of faster iteration, more functional points, and more complex scenario combinations. Design Under Test (DUT) usually refers to the design to be tested of a chip, IP or SOC.

[0003] Currently, the DUT is verified by using the traditional random injection stimulus verification method. However, the random stimulus verification method is prone to missed verification and false verification, and has poor effectiveness, and can no longer meet current verification needs. Summary of the invention

[0004] The present application provides a verification method, device, equipment and storage medium for a design DUT to be tested, so as to solve the problem that the verification method of random excitation is less effective.

[0005] In a first aspect, the present application provides a verification method for a design DUT to be tested, comprising:

[0006] Determining a target incentive according to the number of times the directional incentives corresponding to each of the functions to be verified are sent;

[0007] Using an arbitrator to arbitrate each of the functions to be verified, and obtaining an arbitration result corresponding to the first target function;

[0008] According to the arbitration result corresponding to the first target function, the target stimulus corresponding to the first target function is generated, and the DUT is verified according to the target stimulus corresponding to the first target function.

[0009] In a possible implementation manner, determining the target incentive according to the number of times the directional incentives corresponding to each of the functions to be verified are sent includes:

[0010] In the case where the number of times that the directional incentive corresponding to at least one of the functions to be verified is sent is less than the first threshold, determining that the target incentive is a directional incentive;

[0011] When the number of times the directional excitations corresponding to all the functions to be verified in the at least one function to be verified are sent is greater than or equal to the second threshold, one of the random excitations and the directional excitations is randomly selected to be determined as the target excitation.

[0012] In a possible implementation manner, before the arbitrating each of the to-be-verified functions by the arbitrator to obtain an arbitration result corresponding to the first target function, the method further includes:

[0013] Performing control operations on each of the functions to be verified to obtain operation results corresponding to each of the functions to be verified; the control operation includes controlling at least one of the following: enabling, priority, and configuration data for generating incentives;

[0014] The using an arbitrator to arbitrate each of the to-be-verified functions to obtain an arbitration result corresponding to the first target function includes:

[0015] In the case where the target excitation is a directional excitation, an arbitrator is used to arbitrate at least one second target function to obtain an arbitration result corresponding to the first target function; the second target function is a function to be verified whose operation result is enabled among the functions to be verified.

[0016] In a possible implementation manner, the using an arbitrator to arbitrate at least one second target function to obtain an arbitration result corresponding to the first target function includes:

[0017] Using the arbitrator to arbitrate the at least one second target function according to the operation result corresponding to the priority and the polling arbitration method, to obtain an arbitration result corresponding to the first target function;

[0018] Generating the target incentive corresponding to the first target function according to the arbitration result corresponding to the first target function includes:

[0019] In the case where the target incentive is a directional incentive, the directional incentive corresponding to the first target function is generated according to the configuration data corresponding to the first target function.

[0020] In a possible implementation manner, the control operation is generated in at least one of the following ways: a random way and a custom way.

[0021] In a possible implementation manner, after determining the target incentive according to the number of times the directional incentives corresponding to each of the functions to be verified are sent, the method further includes:

[0022] sending an arbitration request to the arbitrator, wherein the arbitration request is used to request arbitration for at least one second target function;

[0023] The operation results corresponding to each of the functions to be verified are updated.

[0024] In a second aspect, the present application provides a verification device for a design DUT to be tested, wherein the DUT includes at least one function to be verified, and the device includes:

[0025] A determination module, used to determine a target incentive according to the number of times the directional incentives corresponding to each of the functions to be verified are sent;

[0026] A processing module, configured to use an arbitrator to arbitrate each of the functions to be verified, and obtain an arbitration result corresponding to the first target function;

[0027] The processing module is further configured to generate the target stimulus corresponding to the first target function according to the arbitration result corresponding to the first target function, and verify the DUT according to the target stimulus corresponding to the first target function.

[0028] In a third aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor;

[0029] The memory stores computer-executable instructions;

[0030] The processor executes the computer-executable instructions stored in the memory to implement the verification method of the designed DUT to be tested as described in the first aspect.

[0031] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a computer, they are used to implement the verification method of the designed DUT to be tested as described in the first aspect.

[0032] In a fifth aspect, the present application provides a computer program product, including a computer program, which, when executed by a computer, is used to implement the verification method of the designed DUT to be tested described in the first aspect.

[0033] In a sixth aspect, an embodiment of the present application provides a chip having a computer program stored thereon, wherein when the computer program is executed by the chip, the verification method of the design DUT to be tested described in the first aspect is executed.

[0034] In a possible implementation, the chip is a chip in a chip module.

[0035] In a seventh aspect, an embodiment of the present application provides a module device, wherein the module device includes a power module, a storage module, and a chip module;

[0036] Wherein, the power module is used to provide electrical energy to the module device;

[0037] The storage module is used to store data and instructions;

[0038] The chip module is used to execute the verification method of the designed DUT to be tested described in the first aspect.

[0039] The verification method, apparatus, device and storage medium of the design DUT to be tested provided in the present application determine the target stimulus according to the number of times the directional stimulus corresponding to each function to be verified is sent; use an arbitrator to arbitrate each function to be verified to obtain an arbitration result corresponding to the first target function; further, based on the arbitration result corresponding to the first target function, generate a target stimulus corresponding to the first target function, and verify the DUT according to the target stimulus corresponding to the first target function. In the above scheme, the target stimulus generated subsequently is determined by the number of times the directional stimulus corresponding to each function to be verified is sent, and then the targeted directional stimulus is input into the random stimulus, that is, the sending of the directional stimulus corresponding to the function to be verified is increased on the basis of the random stimulus, so as to avoid false verification or missed verification of some functions to be verified, thereby improving the verification effectiveness and verification quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0041] Figure 1 A flow chart of a verification method for a design DUT to be tested provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of a verification method for a designed DUT to be tested provided in an embodiment of the present application;

[0043] Figure 3 A schematic diagram of the structure of a verification device for a designed DUT to be tested provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0045] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0046] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0047] First, the terms involved in this application are explained:

[0048] Background data stream: refers to a stimulus sequence consisting of random stimuli, simulating the busy state of the DUT.

[0049] Vacant period: refers to the DUT input interface being in an idle state due to discontinuous stimulation.

[0050] Empty test case success: usually refers to the situation in the test report where the test case is executed successfully but there is no actual test result or output.

[0051] This application can be applied to scenarios such as module-level IP verification and SOC-level chip functional verification.

[0052] The traditional simulation verification method of random injection of stimuli is very likely to lead to empty success of use cases due to the uncontrollable stimuli, which in turn makes the product face problems of uncontrollable delivery time and delivery quality. The more complex the DUT functions and the more scenarios there are, the greater the probability of this problem occurring.

[0053] The method of the embodiment of the present application determines the target incentive according to the number of times the targeted incentives corresponding to each function to be verified are sent, and then inputs the targeted targeted incentives into the random incentives to greatly improve the effectiveness of the verification use case, thereby achieving the effect of improving verification efficiency and improving verification quality, and has high versatility.

[0054] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0055] Figure 1 A flow chart of a verification method for a design DUT to be tested provided in an embodiment of the present application is provided. The method can be executed by an electronic device, or by a verification device for the design DUT to be tested set in the electronic device. The device can be a chip or a chip module, etc. Figure 1 , the DUT includes at least one function to be verified, and the method comprises the following steps:

[0056] S101. Determine a target incentive according to the number of times the directional incentive corresponding to each function to be verified is sent.

[0057] In S101, the target incentive to be sent next time is determined according to the number of times the directional incentives corresponding to each function to be verified are sent, that is, the number of times the directional incentives are sent to the function to be verified. For example, if the number of times the directional incentives corresponding to a function to be verified are sent is small, in order to improve the effectiveness of verification, the target incentive can be determined to be a directional incentive, and a targeted directional incentive can be input, thereby improving the effectiveness of verification.

[0058] S102: Utilize an arbitrator to arbitrate each function to be verified, and obtain an arbitration result corresponding to the first target function.

[0059] In S102, an arbitrator is used to arbitrate each function to be verified, and determine the next function to be verified to send a directional stimulus, that is, the first target function. For example, the arbitrator selects a function to be verified from each function to be verified in a certain order, or selects a function to be verified with a higher priority from each function to be verified.

[0060] S103 . Generate a target stimulus corresponding to the first target function according to the arbitration result corresponding to the first target function, and verify the DUT according to the target stimulus corresponding to the first target function.

[0061] In S103, for the first target function selected by the arbitrator, a target stimulus corresponding to the first target function is generated, and the target stimulus corresponding to the first target function is input into the first target function, thereby realizing verification of the DUT.

[0062] The method of the embodiment of the present application determines the target stimulus according to the number of times the directional stimulus corresponding to each function to be verified is sent; uses an arbitrator to arbitrate each function to be verified to obtain an arbitration result corresponding to the first target function; further, based on the arbitration result corresponding to the first target function, a target stimulus corresponding to the first target function is generated, and the DUT is verified according to the target stimulus corresponding to the first target function. In the above scheme, the target stimulus generated subsequently is determined by the number of times the directional stimulus corresponding to each function to be verified is sent, and then the targeted directional stimulus is input into the random stimulus, that is, the sending of the directional stimulus corresponding to the function to be verified is increased on the basis of the random stimulus, so as to avoid false verification or missed verification of certain functions to be verified, thereby improving the verification effectiveness and verification quality.

[0063] In a possible implementation, S101 may be implemented in the following manner:

[0064] In the case where the number of times that the directional incentive corresponding to at least one of the functions to be verified is sent is less than the first threshold, determining that the target incentive is a directional incentive;

[0065] When the number of times the directional excitations corresponding to all the functions to be verified in the at least one function to be verified are sent is greater than or equal to the second threshold, one of the random excitations and the directional excitations is randomly selected to be determined as the target excitation.

[0066] In some embodiments, it is necessary to determine whether the target excitation is a directed excitation or a random excitation based on the number of times the directed excitations corresponding to each function to be verified are sent. Assuming that the number of times a directed excitation corresponding to a function to be verified is less than a first threshold, it means that the number of times the directed excitation corresponding to the function to be verified is sent is small, which may lead to insufficient verification and affect the effectiveness of the verification. In this case, the target excitation to be sent next time is determined to be a directed excitation, thereby improving the effectiveness and quality of the verification.

[0067] Assuming that the number of times the directed incentives corresponding to all the functions to be verified are sent is greater than or equal to the second threshold, it means that the number of times the directed incentives corresponding to all the functions to be verified are sent is large, and multiple targeted verifications have been carried out. Next time, random incentives or directed incentives can be randomly selected to verify as many functions and scenarios as possible.

[0068] Optionally, the first thresholds may be equal or unequal.

[0069] Exemplarily, the DUT includes N functions to be verified, where N is greater than 2. It is assumed that the number of times the directional excitation corresponding to the function 1 to be verified is sent is less than the first threshold, that is, the number of times the directional excitation is sent to the function 1 to be verified is less than the first threshold. If it is less than 1, that is, no directional excitation is sent to the function 1 to be verified, it means that no targeted verification is performed on the function 1 to be verified, which may affect the verification effect. Therefore, the target excitation to be sent next time can be determined as the directional excitation, so as to increase the probability of generating the directional excitation of the function 1 to be verified.

[0070] In some embodiments, Figure 2 As shown in the figure, the stimulus generation module is responsible for generating stimulus, which is divided into directional stimulus generation and random stimulus generation. Random stimulus can be used as the background data stream for verification. After the stimulus is generated, it is sent to the input port of the DUT to complete the process of function arbitration and function corresponding stimulus output.

[0071] like Figure 2 As shown, the incentive selector is responsible for selecting whether the target incentive to be sent next time is a directional incentive or a random incentive. When the selection result is a directional incentive, an arbitration request is sent to the arbitrator at the same time. Otherwise, when the selection result is a random incentive, the corresponding information is sent to the random incentive queue to generate a random incentive.

[0072] Optionally, the stimulus selector can automatically adjust the selection of two stimuli according to the coverage of different functions. For example, in extreme cases, when the simulation verification is about to end, some functions are not covered by the directional stimulus, and the directional stimulus will continue to be selected until all functions are covered by the directional stimulus. The function of this module is to intersperse the directional stimulus of different functions in the background data stream, which is more in line with the actual use scenario of the chip and improves the verification quality.

[0073] The directional stimulus recorder is used to record the number of times the directional stimulus corresponding to each function in the function request queue is sent. It serves as an important basis for the stimulus selector to choose between two stimuli. At the same time, it can provide users with record information to facilitate troubleshooting.

[0074] The directional incentive queue is used to store the information corresponding to the directional incentives to be sent. The incentive generation process is initiated according to the arbitration results. The configuration related to the incentive is directly obtained from the function control module. All relevant configuration data of the function is packaged and then the incentive is output. The function of this module is to generate more effective directional incentives, so that each verification can have incentives that hit the enabled functions, which can improve the verification efficiency and quality at the same time.

[0075] The random stimulus queue is used to store the information corresponding to the random stimulus to be sent. All information in the random stimulus package is randomly generated and is not linked to the function. It has two main functions: first, it can fill the blank time between directional stimuli and reduce the vacuolation period of the DUT; second, it can increase the input pressure of the DUT and improve the robustness of the DUT. The above two points can improve the verification quality.

[0076] In the above implementation, the hit rate of the directional excitation for each function to be verified during the verification process is improved by inserting the directional excitation into the random excitation, and the verification efficiency and verification quality are improved at the same time.

[0077] In a possible implementation manner, the following operations may also be performed before S102:

[0078] Performing control operations on each of the functions to be verified to obtain operation results corresponding to each of the functions to be verified; the control operation includes controlling at least one of the following: enabling, priority, and configuration data for generating incentives;

[0079] S102 is implemented as follows:

[0080] In the case where the target excitation is a directional excitation, an arbitrator is used to arbitrate at least one second target function to obtain an arbitration result corresponding to the first target function; the second target function is a function to be verified whose operation result is enabled among the functions to be verified.

[0081] Specifically, before the arbitrator performs arbitration, control operations may be performed on all functions included in the DUT, and the content of the control operations includes but is not limited to enable control, priority control, and control of configuration data of other related attributes.

[0082] Optionally, the priority can be divided according to the frequency of use, importance, etc. of the function to be verified. For example, a function with a higher frequency of use has a higher priority, and a function with a lower frequency of use has a lower priority; a function with a higher importance has a higher priority, and a function with a lower importance has a lower priority.

[0083] Optionally, the enable control has two main functions: one is to control the opening or closing of the corresponding function in the DUT, and the other is to serve as a basis for the arbitrator to determine whether to add the function to the arbitration queue.

[0084] Optionally, when it is determined that the target excitation is a directional excitation, the arbitrator arbitrates at least one enabled second target function to determine the first target function, that is, obtains an arbitration result corresponding to the first target function.

[0085] Optionally, the embodiment of the present application does not limit the activation time and the number of functions to be verified that can be activated. For example, multiple second target functions can be activated at the same time, or some functions can be activated at random times.

[0086] Optionally, the main function of priority control is to control the probability of the function obtaining arbitration in subsequent arbitration. The purpose of adding this control operation is to assign reasonable input stimulus probabilities to functions of different importance and usage frequency, thereby improving verification efficiency and quality.

[0087] Optionally, the implementation of some functions to be verified is more complicated and requires additional information to complete, so the control operation of configuration data is introduced. This configuration data is used as the data source for generating incentives in the subsequent incentive generation process.

[0088] In the above implementation, through enable control, the enabled functions to be verified are arbitrated and corresponding target stimuli are generated. Based on the random stimuli of traditional simulation, directional stimuli related to the functions that have been turned on by the DUT are automatically injected, and priority judgment is added when the stimuli are generated, so as to improve the verification effectiveness and efficiency.

[0089] Optionally, the control operations of the functions to be verified may be generated in the following ways:

[0090] The first one: random method. Suitable for general verification needs. In this method, the values ​​of all control operations are generated randomly. This method can minimize human intervention on the DUT and improve the effectiveness of verification.

[0091] The second method is custom mode. It is suitable for specific verification requirements. In this mode, users are supported to customize the control operation, such as specifying that one or some functions to be verified are always open, setting the priority of a function to the highest, etc.

[0092] Alternatively, if Figure 2 As shown, the operation results generated by the function random module are packaged according to the function and saved in the form of a queue, that is, Figure 2 The function request queue in the example can be placed in the function request queue in the order in which the control operations of the functions to be verified are completed.

[0093] In the above implementation, as many functions and scenarios as possible can be verified through random methods and / or customized methods, thereby improving the effectiveness and quality of verification.

[0094] In a possible implementation, the step of “using an arbitrator to arbitrate at least one second target function to obtain an arbitration result corresponding to the first target function” may be implemented as follows:

[0095] Using the arbitrator to arbitrate the at least one second target function according to the operation result corresponding to the priority and the polling arbitration method, to obtain an arbitration result corresponding to the first target function;

[0096] Generating the target incentive corresponding to the first target function according to the arbitration result corresponding to the first target function includes:

[0097] In the case where the target incentive is a directional incentive, the directional incentive corresponding to the first target function is generated according to the configuration data corresponding to the first target function.

[0098] Specifically, the arbitrator arbitrates at least one second target function according to the operation result corresponding to the priority and the polling arbitration method, and determines the first target function, that is, the polling arbitration method is adopted, and the priority judgment is added. For example, the second target function with a high priority is selected according to the polling arbitration method, that is, the second target function with a high priority must be arbitrated before the second target function with a low priority, and the second target functions with the same priority are arbitrated in the order of polling. On the basis of ensuring fairness, the weight of the incentive corresponding to the important function can be increased.

[0099] In some embodiments, Figure 2 As shown, for the directional incentive corresponding to the first target function, the realization of the first target function is relatively complex and may require additional information to complete. Therefore, the configuration data related to the target incentive can be directly obtained from the function control module, such as Figure 2 Other configurations in.

[0100] In a possible implementation manner, after S101, the method further includes:

[0101] sending an arbitration request to the arbitrator, wherein the arbitration request is used to request arbitration for at least one second target function;

[0102] The operation results corresponding to each of the functions to be verified are updated.

[0103] Specifically, after determining the target stimulus, for example, after determining that the target stimulus is a directional stimulus, an arbitration request may be sent to the arbitrator to request arbitration for the enabled function to be verified (ie, the second target function).

[0104] Optionally, before each arbitration cycle starts, the operation results corresponding to each function to be verified are updated, that is, the operation results corresponding to the control operation are updated to ensure that functions enabled at different times can enter the arbitrator fairly.

[0105] In the above implementation, by updating the operation results corresponding to the functions to be verified before arbitration, the arbitration hit rate of each function to be verified is improved, thereby improving the effectiveness and quality of verification.

[0106] To sum up, the method of the embodiment of the present application not only retains the advantages of random verification, but also ensures that during the random verification process, directional incentives corresponding to the function are issued, and the probability is controllable, which makes up for the problems of low quality and efficiency of random verification of specific functions, and ultimately achieves the purpose of accelerating chip mass production, reducing chip bugs, and reducing chip costs.

[0107] Figure 3 A schematic diagram of the structure of a verification device for a design DUT to be tested provided in an embodiment of the present application. Figure 3 The device includes: a determination module 31 and a processing module 32.

[0108] A determination module 31, configured to determine a target incentive according to the number of times the directional incentives corresponding to the functions to be verified are sent;

[0109] A processing module 32, configured to use an arbitrator to arbitrate each of the functions to be verified, and obtain an arbitration result corresponding to the first target function;

[0110] The processing module 32 is further configured to generate the target stimulus corresponding to the first target function according to the arbitration result corresponding to the first target function, and verify the DUT according to the target stimulus corresponding to the first target function.

[0111] In a possible implementation manner, the determining module 31 is specifically configured to:

[0112] In the case where the number of times that the directional incentive corresponding to at least one of the functions to be verified is sent is less than the first threshold, determining that the target incentive is a directional incentive;

[0113] When the number of times the directional excitations corresponding to all the functions to be verified in the at least one function to be verified are sent is greater than or equal to the second threshold, one of the random excitations and the directional excitations is randomly selected to be determined as the target excitation.

[0114] In a possible implementation manner, the processing module 32 is further configured to:

[0115] Before using the arbitrator to arbitrate each of the functions to be verified and obtaining the arbitration result corresponding to the first target function, performing a control operation on each of the functions to be verified to obtain the operation result corresponding to each of the functions to be verified; the control operation includes controlling at least one of the following: enabling, priority, and configuration data for generating stimulus;

[0116] The processing module 32 is specifically used for:

[0117] In the case where the target excitation is a directional excitation, an arbitrator is used to arbitrate at least one second target function to obtain an arbitration result corresponding to the first target function; the second target function is a function to be verified whose operation result is enabled among the functions to be verified.

[0118] In a possible implementation manner, the processing module 32 is specifically configured to:

[0119] Using the arbitrator to arbitrate the at least one second target function according to the operation result corresponding to the priority and the polling arbitration method, to obtain an arbitration result corresponding to the first target function;

[0120] Generating the target incentive corresponding to the first target function according to the arbitration result corresponding to the first target function includes:

[0121] In the case where the target incentive is a directional incentive, the directional incentive corresponding to the first target function is generated according to the configuration data corresponding to the first target function.

[0122] In a possible implementation manner, the control operation is generated in at least one of the following ways: a random way and a custom way.

[0123] In a possible implementation manner, the processing module 32 is further configured to:

[0124] After determining the target stimulus according to the number of times the directional stimulus corresponding to each of the functions to be verified is sent, sending an arbitration request to the arbitrator, the arbitration request being used to request arbitration for at least one second target function;

[0125] The operation results corresponding to each of the functions to be verified are updated.

[0126] The device of this embodiment can be used to execute the technical solution of the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0127] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the electronic device may include: at least one processor 41 and a memory 42 .

[0128] The memory 42 is used to store programs. Specifically, the programs may include program codes, and the program codes include computer-executable instructions.

[0129] The memory 42 may include a random access memory (RAM), and may also include a non-volatile memory (Non-volatile Memory), such as at least one disk memory.

[0130] The processor 41 is used to execute the computer-executable instructions stored in the memory 42 to implement the method described in the aforementioned method embodiment. The processor 41 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0131] Optionally, the electronic device may further include: a communication interface 43. In a specific implementation, if the communication interface 43, the memory 42 and the processor 41 are implemented independently, the communication interface 43, the memory 42 and the processor 41 may be interconnected through a bus and communicate with each other. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc., but it does not mean that there is only one bus or one type of bus.

[0132] Optionally, in a specific implementation, if the communication interface 43, the memory 42 and the processor 41 are integrated on a chip, the communication interface 43, the memory 42 and the processor 41 can communicate through an internal interface.

[0133] The electronic device may be a chip, a chip module, a terminal device, a network device, etc.

[0134] The electronic device of this embodiment can be used to execute the technical solution of the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0135] The embodiment of the present application provides a computer-readable storage medium, which may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a RAM, a disk or an optical disk, and other media that can store computer-executable instructions. Specifically, the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a computer, the technical solution shown in the above method embodiment is executed. The specific implementation method and technical effect are similar and will not be repeated here.

[0136] An embodiment of the present application provides a computer program product, including a computer program. When the computer program is executed by a computer, the technical solution shown in the above method embodiment is executed. The specific implementation method and technical effect are similar and will not be repeated here.

[0137] An embodiment of the present application provides a chip having a computer program stored thereon. When the computer program is executed by the chip, the technical solution shown in the above method embodiment is executed.

[0138] In a possible implementation, the chip may also be a chip module.

[0139] The chip of this embodiment can be used to execute the technical solution shown in the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0140] The embodiment of the present application provides a module device, which includes a power module, a storage module and a chip module. The power module is used to provide power to the module device. The storage module is used to store data and instructions.

[0141] The chip module of this embodiment can be used to execute the technical solution shown in the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0142] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0143] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A verification method for a design DUT to be tested, characterized in that: The DUT includes at least one function to be verified, and the method includes: Determining a target incentive according to the number of times the directional incentives corresponding to each of the functions to be verified are sent; Using an arbitrator to arbitrate each of the functions to be verified, and obtaining an arbitration result corresponding to the first target function; According to the arbitration result corresponding to the first target function, the target stimulus corresponding to the first target function is generated, and the DUT is verified according to the target stimulus corresponding to the first target function.

2. The method according to claim 1, characterized in that The determining the target incentive according to the number of times the directional incentives corresponding to the functions to be verified are sent includes: In the case where the number of times that the directional incentive corresponding to at least one of the functions to be verified is sent is less than the first threshold, determining that the target incentive is a directional incentive; When the number of times the directional excitations corresponding to all the functions to be verified in the at least one function to be verified are sent is greater than or equal to the second threshold, one of the random excitations and the directional excitations is randomly selected to be determined as the target excitation.

3. The method according to claim 1 or 2, characterized in that: Before the arbitrating each of the to-be-verified functions by the arbitrator to obtain the arbitration result corresponding to the first target function, the method further includes: Performing control operations on each of the functions to be verified to obtain operation results corresponding to each of the functions to be verified; the control operation includes controlling at least one of the following: enabling, priority, and configuration data for generating incentives; The using an arbitrator to arbitrate each of the to-be-verified functions to obtain an arbitration result corresponding to the first target function includes: In the case where the target excitation is a directional excitation, an arbitrator is used to arbitrate at least one second target function to obtain an arbitration result corresponding to the first target function; the second target function is a function to be verified whose operation result is enabled among the functions to be verified.

4. The method according to claim 3, characterized in that The using the arbitrator to arbitrate at least one second target function to obtain an arbitration result corresponding to the first target function includes: Using the arbitrator to arbitrate the at least one second target function according to the operation result corresponding to the priority and the polling arbitration method, to obtain an arbitration result corresponding to the first target function; Generating the target incentive corresponding to the first target function according to the arbitration result corresponding to the first target function includes: In the case where the target incentive is a directional incentive, the directional incentive corresponding to the first target function is generated according to the configuration data corresponding to the first target function.

5. The method according to claim 3, characterized in that: The generation method of the control operation includes at least one of the following methods: a random method and a custom method.

6. The method according to claim 3, characterized in that: After determining the target incentive according to the number of times the directional incentives corresponding to the functions to be verified are sent, the method further includes: sending an arbitration request to the arbitrator, wherein the arbitration request is used to request arbitration for at least one second target function; The operation results corresponding to each of the functions to be verified are updated.

7. A verification device for a design DUT to be tested, characterized in that: The DUT includes at least one function to be verified, and the device includes: A determination module, used to determine a target incentive according to the number of times the directional incentives corresponding to each of the functions to be verified are sent; A processing module, configured to arbitrate each of the functions to be verified by using an arbitrator to obtain an arbitration result corresponding to the first target function; The processing module is further configured to generate the target stimulus corresponding to the first target function according to the arbitration result corresponding to the first target function, and verify the DUT according to the target stimulus corresponding to the first target function.

8. An electronic device, characterized in that: include: Memory, processor; Memory; a memory for storing instructions executable by the processor; Wherein, the processor is configured to: Determine the target incentive according to the number of times the directional incentive corresponding to each function to be verified is sent; Using an arbitrator to arbitrate each of the functions to be verified, and obtaining an arbitration result corresponding to the first target function; According to the arbitration result corresponding to the first target function, the target stimulus corresponding to the first target function is generated, and the DUT is verified according to the target stimulus corresponding to the first target function.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed by a processor.

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