Tri-exposure multi-terminal wire net wiring method and system based on coloring coding

Abstract

The invention provides a triple exposure multi-terminal wire net wiring method and system based on color coding, and relates to the technical field of circuit wiring, and the method comprises the steps: obtaining to-be-wired information of a chip; determining wiring diagram nodes according to the chip information and the component position information, and constructing a wiring diagram structure of a to-be-wired area; according to the element position information and the wiring design constraint information, setting wiring connection edge weights in the wiring diagram structure in different mask states; initializing coloring codes of nodes of the wiring diagram; setting a coloring code change rule in a line network searching process and a line network updating process; and in combination with the coloring code change rule and the multi-terminal network connection relationship information, performing wiring search on the multi-terminal network to obtain a final wiring scheme. According to the invention, the wiring rate of the triple exposure multi-terminal wire net can be effectively improved, the wiring operation time is reduced, and the wiring efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit wiring, and in particular to a triple-exposure multi-terminal wire mesh wiring method and system based on coloring coding. Background Art

[0002] As the feature size of integrated circuits continues to shrink and the density of layout patterns continues to increase, the multiple exposure lithography process has become a key technology to further improve the success rate of chip manufacturing. The multiple exposure lithography process is to decompose the layout pattern into multiple different masks, and finally form a complete silicon wafer pattern through multiple exposure and etching iterations. The minimum spacing between layout patterns on different masks can be smaller than the minimum spacing between layout patterns on the same mask, which puts forward higher and more complex requirements for integrated circuit design.

[0003] In the design of VLSI chips, wiring is the most time-consuming and important link, which has an extremely significant impact on the performance and power consumption of the chip. In order to meet the multiple exposure lithography process, the wiring needs to be distributed on different masks and meet the minimum spacing requirements of different mask plates or layout patterns on the same mask plate.

[0004] However, existing design methods mainly focus on double exposure technology or two-terminal net design. But with the increase of design scale and complexity, triple exposure technology has gradually become a new design trend. In ultra-large-scale integrated circuit chip design, multi-terminal nets are a common design format. Traditional methods often split them into multiple two-terminal nets, which will lead to suboptimal wiring length output and easily reduce the routing rate. Summary of the invention

[0005] In order to solve the problem that the existing design methods in the prior art mainly focus on double exposure technology or two-end wire net design, but with the increase of design scale and complexity, triple exposure technology has gradually become a new design trend. In the design of ultra-large-scale integrated circuit chips, multi-end wire nets are a common design format. Traditional methods often split them into multiple two-end wire nets. This approach may result in suboptimal output wiring length and easily reduce the technical problem of wiring pass rate. The present invention provides a triple exposure multi-end wire net wiring method and system based on coloring coding.

[0006] The technical solution provided by the embodiment of the present invention is as follows:

[0007] First aspect

[0008] An embodiment of the present invention provides a triple exposure multi-terminal wire mesh wiring method based on color coding, comprising:

[0009] S1: Obtaining the chip's wiring information, wherein the wiring information includes chip information, component location information, wiring design constraint information, and multi-terminal wire network connection relationship information;

[0010] S2: Determine the wiring diagram nodes according to the chip information and component position information, and construct the wiring diagram structure of the area to be wired;

[0011] S3: according to the component position information and the wiring design constraint information, setting the wiring connection edge weights in the wiring diagram structure under different mask states;

[0012] S4: Initialize the coloring code of the wiring diagram nodes;

[0013] S5: Setting the coloring code change rules in the wire mesh search process and the wire mesh update process;

[0014] S6: Combine the coloring code change rules and the multi-terminal wire net connection relationship information to perform a wiring search on the multi-terminal wire net to obtain a final wiring plan.

[0015] Second aspect

[0016] An embodiment of the present invention provides a triple exposure multi-terminal wire mesh wiring system based on color coding, comprising:

[0017] processor;

[0018] A memory having computer-readable instructions stored therein, wherein when the computer-readable instructions are executed by a processor, the color coding-based triple-exposure multi-terminal wire mesh wiring method of the first aspect is implemented.

[0019] The third aspect

[0020] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the coloring-coding-based triple-exposure multi-terminal wire mesh wiring method according to the first aspect is implemented.

[0021] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0022] In the present invention, by directly processing a multi-terminal network, the traditional method of splitting a multi-terminal network into multiple two-terminal networks is avoided, thereby reducing the complexity of the wiring stage and improving the overall wiring efficiency. By using triple exposure technology, the wiring space can be more effectively utilized, the wiring length can be reduced, and the wiring delay and signal transmission loss can be reduced, thereby improving the performance of the chip. By comprehensively considering the connection relationship of the multi-terminal network, the connectivity of the signal path is ensured, thereby significantly improving the routing rate and reducing the risk of failure due to signal interference or path congestion. By setting the weights of the connection edges under different mask states, it is possible to flexibly respond to changes in design constraints, so that the wiring scheme maintains high adaptability and flexibility while following the design rules. Color coding is used to manage the state of the nodes, and the connection state and mask usage of each node are effectively recorded, so that the wiring algorithm can select the path more accurately during the search and optimization process, can handle circuit designs with higher complexity, and adapt to the needs of large-scale integrated circuits, thereby effectively reducing manufacturing costs and material waste, and achieving sustainability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic flow chart of a triple exposure multi-terminal wire mesh wiring method based on color coding provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of the wiring diagram structure provided by an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of a wiring diagram structure with connection edge weights provided by an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of color coding initialization provided by an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of color coding when the first target element is searched for according to an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of color coding after the wire net is updated when the first target element is searched for according to an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of color coding after the wire net is updated when the second target element is searched for according to an embodiment of the present invention;

[0031] Figure 8 A schematic diagram of wiring results provided by an embodiment of the present invention;

[0032] Fig. 9 A schematic structural diagram of a triple-exposure multi-terminal wire mesh wiring system based on color coding is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0034] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0035] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0036] Reference Manual Attached Figure 1 , shows a schematic flow chart of a triple exposure multi-terminal wire mesh wiring method based on color coding provided in an embodiment of the present invention.

[0037] An embodiment of the present invention provides a triple exposure multi-terminal wire mesh wiring method based on color coding, comprising:

[0038] S1: Obtain the chip's information to be wired, wherein the information to be wired includes chip information, component location information, wiring design constraint information, and multi-terminal wire network connection relationship information.

[0039] In one possible implementation, the chip information includes chip size, number of chip layers and chip track distribution; the component position information includes component size, component position and the layer where the component is located; the wiring design constraint information includes the routing width of different chip layers, the spacing between lines of different chip layers and the spacing between lines and components of different chip layers.

[0040] Among them, chip size refers to the physical size of the integrated circuit chip, usually expressed in microns (μm) or square microns (μm²). The number of chip layers refers to the number of layers inside the chip, usually including multiple metal layers, insulating layers and semiconductor layers. The number of layers affects the complexity of wiring and the way signals are transmitted. Chip track distribution refers to the arrangement of metal tracks (conductive paths for wiring) on ​​the chip, including the track position, width and direction of each layer. This distribution determines the effectiveness of the signal transmission path. Component size refers to the physical size of each component (such as resistors, capacitors, transistors, etc.) in the integrated circuit. Component position refers to the specific coordinates or position of the component on the chip, usually expressed in two-dimensional coordinates (x, y). The layer where the component is located refers to the specific level of the component in the multi-layer structure of the chip. Wiring design constraint information refers to the rules and restrictions that need to be followed during the design process to ensure that the wiring meets the manufacturing process requirements. The routing width refers to the width of the metal track used for wiring. Different widths affect the signal transmission capability and wiring density.

[0041] It should be noted that obtaining the chip's wiring information is the basis of the entire wiring process, ensuring that subsequent steps have sufficient data support. By fully understanding chip information, component location information, design constraints and connection relationships, the risk of design errors can be effectively reduced and the accuracy and reliability of wiring can be improved.

[0042] Reference Manual Attached Figure 2 , showing a schematic diagram of the wiring diagram structure provided by an embodiment of the present invention;

[0043] like Figure 2 , is a schematic diagram of the wiring diagram structure. There are wiring connection edges between adjacent wiring diagram nodes in the vertical or horizontal direction. One component (represented by a light gray square) may cover multiple wiring diagram nodes.

[0044] S2: Determine the wiring diagram nodes according to the chip information and component position information, and construct the wiring diagram structure of the area to be wired.

[0045] Among them, the wiring diagram node is the key point in the wiring diagram, usually indicating the connection location of components, intersections or wiring. Each node acts as a decision point for path selection in the wiring algorithm. The area to be wired refers to the area on the chip that has not yet been wired, usually including all components that need to be connected and the connection relationship between them. The wiring diagram structure is a graphical model used to describe wiring nodes and their connection relationships. The wiring diagram structure consists of nodes and edges. The edges represent the connections between nodes or possible wiring paths.

[0046] In a possible implementation, S2 specifically includes:

[0047] S201: Determine, according to chip information, the intersection of chip tracks of different chip layers as a first wiring diagram node.

[0048] It should be noted that determining the track intersections of different chip layers as the first wiring diagram nodes based on the chip information can effectively identify the key connection positions.

[0049] S202: Consider the location of the component as a second wiring diagram node.

[0050] S203: Determine the covering relationship between the first wiring diagram node and the second wiring diagram node according to the component position information.

[0051] The coverage relationship refers to the spatial relationship between the first wiring diagram node and the second wiring diagram node, indicating whether there is overlap or contact between the nodes so that a signal can be transmitted from one node to another.

[0052] Specifically, determining the coverage relationship between the first wiring diagram node and the second wiring diagram node can effectively identify potential connection paths in the wiring. Through a clear coverage relationship, the wiring path can be optimized, the risk of signal interference can be reduced, and the circuit routing rate can be improved. This can reduce redundant connections in the wiring scheme and improve the efficiency and reliability of the overall design.

[0053] S204: adding a wiring connection edge between the second wiring diagram node and the corresponding first wiring diagram node according to the covering relationship to obtain a wiring diagram structure.

[0054] It should be noted that determining the wiring diagram nodes and constructing the wiring diagram structure based on the chip information and component location information helps to systematize and visualize the wiring process, provides clear node and connection relationships, and enables the wiring algorithm to search for paths efficiently, avoiding repeated calculations and unnecessary complexity.

[0055] Reference Manual Attached Figure 3 , showing a schematic diagram of a wiring diagram structure with connection edge weights provided in an embodiment of the present invention.

[0056] like Figure 3 The weights of adjacent connection edges that are too close to components or in the same mask as existing wire nets include the penalty cost of design constraint violation. The black pattern represents the wire nets routed in the first layer mask.

[0057] S3: According to the component position information and the wiring design constraint information, the wiring connection edge weights in the wiring diagram structure under different mask states are set.

[0058] Among them, the mask state is the state of the photolithography mask used in the wiring process. Different mask states will affect the implementation of wiring and the applicability of design constraints. The wiring connection edge weight refers to the weight value assigned to the edge connecting the nodes in the wiring diagram. The weight usually represents the cost or priority of the connection. The setting of the weight depends on the distance, design constraints and mask state.

[0059] In a possible implementation, the wiring connection edge weight specifically includes the actual spatial distance between each wiring diagram node, the layer switching connection cost between wiring diagram nodes of different chip layers, and the penalty cost of constraint violation under different mask states.

[0060] Among them, the actual spatial distance is the straight-line distance between two wiring diagram nodes in physical space, usually expressed in microns or other units. The layer change connection cost refers to the process of switching from one chip layer to another when wiring. This process will incur additional costs. The layer change connection cost takes into account the additional complexity and resource consumption in manufacturing and design. Constraint violation refers to the fact that in wiring design, there are usually a series of design rules and constraints (such as minimum spacing, maximum current, etc.). If these constraints are not met during the wiring process, a constraint violation will occur. The penalty cost refers to the fact that in the optimization algorithm, when a constraint violation occurs, in order to force the algorithm to find a solution that better meets the requirements, an additional penalty cost will be introduced. This cost is usually added when calculating the edge weight to reduce the priority of wiring schemes that do not meet the specifications.

[0061] It should be noted that setting the weight of the wiring connection edge according to the component position information and the wiring design constraint information helps to optimize the wiring path selection. Reasonable setting of weights under different mask states can ensure that the optimal wiring path is selected while meeting the design constraints. Through this dynamic weight setting, signal interference and physical space conflicts that occur during the wiring process can be effectively avoided, and the routing pass rate can be improved.

[0062] Reference Manual Attached Figure 4 , showing a schematic diagram of shading coding initialization provided by an embodiment of the present invention.

[0063] like Figure 4 , the black square represents the component as the starting point, the dark gray square represents the component as the end point, the black pattern represents the wire net routed in the first layer mask, the oblique line pattern represents the wire net routed in the second layer mask, the color coding attribute of the starting point is the default value, the color coding attribute of other nodes is initialized to 111 (the three-bit binary form of the integer 7), the color coding attribute of the occupied node is set to 000 (the three-bit binary form of the integer 0), the distance attribute of the starting point is 0, and the distance attribute of other nodes is positive infinity.

[0064] S4: Initialize the coloring code of the wiring diagram nodes.

[0065] Among them, color coding is a binary or other form of identification assigned to the wiring diagram nodes, which is usually used to indicate the state, hierarchy or connection information of the nodes.

[0066] In a possible implementation, S4 is specifically:

[0067] The wiring diagram node is set to a coloring code in the form of a 3-bit binary system with an initial value of 7 to initialize the coloring code of the wiring diagram node.

[0068] It should be noted that the color coding of the nodes in the initialization wiring diagram helps to perform effective state management and optimization during the wiring process. By clearly identifying the state of each node, it is possible to quickly determine which nodes have been visited or connected, thereby improving the efficiency of the wiring algorithm. Color coding can also simplify complex wiring constraint management, avoid potential design conflicts, and ensure the effectiveness and manufacturability of the final wiring solution.

[0069] Reference Manual Attached Figure 5 , shows a schematic diagram of color coding when the first target element is searched for provided by an embodiment of the present invention.

[0070] like Figure 5 , the node coloring coding attributes on the path from the starting point to the first target component are not exactly the same. The starting point (the small black square in the upper left corner) is the starting position of the path, and the target node (the dark gray square in the upper right corner) is the first target component to be searched. The color of each component changes depending on whether it is the starting point or the end point. The default component is a light gray rectangle. The path nodes in the figure are color-coded nodes, indicating that these nodes are part of the path. In the figure, the starting point S value is 111, the D value is 0, the end point S value is 011, and the D value is 6.

[0071] Reference Manual Attached Figure 6 , shows a schematic diagram of color coding after the wire net is updated when the first target element is searched for provided by an embodiment of the present invention.

[0072] like Figure 6 , is the color coding diagram of the wire network after updating when the first target element is searched, the color coding attributes of the nodes are reset, the distance attribute D of the starting point is 0, and the D value of each node on the path starting from the starting point increases from 1 to 6, indicating the distance from the starting point to the target node, and the color coding attribute S of the starting point changes from 111 to 011.

[0073] Reference Manual Attached Figure 7 , shows a schematic diagram of color coding after the wire net is updated when the second target element is searched for provided by an embodiment of the present invention.

[0074] like Figure 7 , which shows the path from the first target to the second target element and the state change of the nodes after the network is updated. The node attributes S on the path in the figure are all 001, and the D values ​​of all path nodes are set to 0, which means that the updated network sets the heuristic valuation and distance of the path.

[0075] S5: Setting the coloring code change rules during the wire mesh search process and the wire mesh update process.

[0076] The coloring code change rules refer to the rules that define how to update the coloring codes of the wiring diagram nodes during the wiring process. These rules usually change based on factors such as the connection status and distance between nodes.

[0077] In a possible implementation manner, the coloring code change rule in the wire mesh search process is specifically as follows.

[0078] If the i-th wiring diagram node is currently searched, the next node to be connected is the j-th wiring diagram node.

[0079] According to the distance from the i-th wiring diagram node to the starting node and the wiring connection edge E between the i-th wiring diagram node and the j-th wiring diagram node ij The weights under different masks are used to calculate the distance from the jth wiring diagram node to the starting node.

[0080] When the distance from the jth wiring diagram node to the starting node is less than the originally stored distance, the distance from the jth wiring diagram node to the starting node is updated, and the coloring code of the jth wiring diagram node is reset.

[0081] When the distance from the jth wiring diagram node to the starting node is equal to the original stored distance, the coloring code of the jth wiring diagram node is updated.

[0082] In a possible implementation manner, the coloring code change rule in the wire mesh update process is specifically as follows.

[0083] According to the coloring code of the i-th wiring diagram node, determine the wiring connection edge E between the i-th wiring diagram node and the j-th wiring diagram node ij , and trace back to the jth wiring diagram node, repeating the above process until returning to the starting node.

[0084] For the i-th wiring diagram node on the backtracking path, set the distance to 0 and mark it as the starting node;

[0085] When the j-th binary code of the coloring code of the current i-th wiring diagram node is different from the j-th binary code of the coloring code of the i-th wiring diagram node counted during the backtracking process, the coloring code of the i-th wiring diagram node is updated.

[0086] It should be noted that setting coloring code change rules can significantly improve the flexibility and efficiency of the routing process. Through clear rules, the algorithm can quickly determine and update the node status, thereby optimizing the search path and avoiding unnecessary repeated calculations. This mechanism can also ensure compliance with design constraints in complex multi-layer routing, thereby improving the quality and feasibility of routing solutions.

[0087] Reference Manual Attached Figure 8 , showing a schematic diagram of wiring results provided by an embodiment of the present invention.

[0088] like Figure 8 The black pattern represents the wire nets routed in the first layer of mask, the oblique pattern represents the wire nets routed in the second layer of mask, and the gray pattern represents the wire nets routed in the third layer of mask. After completing the search for multi-terminal wire nets, select a code from the node's coloring code as the final mask of the current node.

[0089] S6: Combine the coloring code change rules and the multi-terminal wire net connection relationship information to perform a wiring search on the multi-terminal wire net to obtain a final wiring plan.

[0090] In a possible implementation, S6 specifically includes:

[0091] S601: Combine the coloring code change rules and the multi-terminal net connection relationship information to perform a routing search on the multi-terminal net until all target components of the multi-terminal net are routed.

[0092] It should be noted that by combining the coloring coding change rules and the multi-terminal wire network connection relationship information, the wiring search process can be systematically optimized, the search efficiency can be improved, all target components can be ensured to be effectively connected, resource waste and potential design conflicts can be reduced, and the overall quality and reliability of the wiring solution can be ultimately improved.

[0093] S602: According to the routing search results and routing design constraint information, when the routing connection edge E ij When the kth mask is used and the distance between the wiring connection edge and the same layer routing is less than the minimum spacing constraint between each line, the weight of the wiring connection edge E ijk Add the preset penalty value P.

[0094] Specifically, by introducing a penalty mechanism to adjust the weights of routing connection edges and ensuring that the design complies with routing design constraints, the priority of non-compliant connection schemes is effectively reduced, routing optimization is promoted, and ultimately the feasibility of routing and circuit performance are improved, ensuring the integrity and stability of the design.

[0095] It should be noted that by combining the coloring coding change rules and the multi-terminal wire network connection relationship information, the wiring search can be performed efficiently and systematically, ensuring the connection of all target components, while optimizing the path selection, reducing wiring conflicts and design errors, and ultimately improving the efficiency and manufacturability of circuit design.

[0096] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0097] In the present invention, by directly processing a multi-terminal network, the traditional method of splitting a multi-terminal network into multiple two-terminal networks is avoided, thereby reducing the complexity of the wiring stage and improving the overall wiring efficiency. By using triple exposure technology, the wiring space can be more effectively utilized, the wiring length can be reduced, and the wiring delay and signal transmission loss can be reduced, thereby improving the performance of the chip. By comprehensively considering the connection relationship of the multi-terminal network, the connectivity of the signal path is ensured, thereby significantly improving the routing rate and reducing the risk of failure due to signal interference or path congestion. By setting the weights of the connection edges under different mask states, it is possible to flexibly respond to changes in design constraints, so that the wiring scheme maintains high adaptability and flexibility while following the design rules. Color coding is used to manage the state of the nodes, and the connection state and mask usage of each node are effectively recorded, so that the wiring algorithm can select the path more accurately during the search and optimization process, can handle circuit designs with higher complexity, and adapt to the needs of large-scale integrated circuits, thereby effectively reducing manufacturing costs and material waste, and achieving sustainability of the design.

[0098] Reference Manual Attached Fig. 9 , showing a structural schematic diagram of a triple exposure multi-terminal wire mesh wiring system based on color coding provided by the present invention.

[0099] The present invention further provides a triple exposure multi-terminal wire mesh wiring system 20 based on color coding, which is applied to the above-mentioned triple exposure multi-terminal wire mesh wiring method based on color coding, comprising:

[0100] Processor 201.

[0101] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201 , the coloring-coding-based triple-exposure multi-terminal wire mesh wiring method of the method embodiment is implemented.

[0102] The triple exposure multi-terminal wire mesh wiring system 20 based on color coding provided by the present invention can execute the above-mentioned triple exposure multi-terminal wire mesh wiring method based on color coding and achieve the same or similar technical effects. To avoid repetition, the present invention will not go into details.

[0103] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0104] In the present invention, by directly processing a multi-terminal network, the traditional method of splitting a multi-terminal network into multiple two-terminal networks is avoided, thereby reducing the complexity of the wiring stage and improving the overall wiring efficiency. By using triple exposure technology, the wiring space can be more effectively utilized, the wiring length can be reduced, and the wiring delay and signal transmission loss can be reduced, thereby improving the performance of the chip. By comprehensively considering the connection relationship of the multi-terminal network, the connectivity of the signal path is ensured, thereby significantly improving the routing rate and reducing the risk of failure due to signal interference or path congestion. By setting the weights of the connection edges under different mask states, it is possible to flexibly respond to changes in design constraints, so that the wiring scheme maintains high adaptability and flexibility while following the design rules. Color coding is used to manage the state of the nodes, and the connection state and mask usage of each node are effectively recorded, so that the wiring algorithm can select the path more accurately during the search and optimization process, can handle circuit designs with higher complexity, and adapt to the needs of large-scale integrated circuits, thereby effectively reducing manufacturing costs and material waste, and achieving sustainability of the design.

[0105] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0106] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0107] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When a computer instruction or computer program is loaded or executed on a computer, a process or function according to an embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0108] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0109] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0110] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0111] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0112] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0113] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0114] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0115] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0116] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0117] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, a triple-exposure multi-terminal network wiring method based on coloring coding as described in a method embodiment is implemented.

[0118] A computer-readable storage medium provided by the present invention can implement the steps and effects of the triple-exposure multi-terminal wire mesh wiring method based on color coding in the above method embodiment. To avoid repetition, the present invention will not go into details.

[0119] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0120] In the present invention, by directly processing a multi-terminal network, the traditional method of splitting a multi-terminal network into multiple two-terminal networks is avoided, thereby reducing the complexity of the wiring stage and improving the overall wiring efficiency. By using triple exposure technology, the wiring space can be more effectively utilized, the wiring length can be reduced, and the wiring delay and signal transmission loss can be reduced, thereby improving the performance of the chip. By comprehensively considering the connection relationship of the multi-terminal network, the connectivity of the signal path is ensured, thereby significantly improving the routing rate and reducing the risk of failure due to signal interference or path congestion. By setting the weights of the connection edges under different mask states, it is possible to flexibly respond to changes in design constraints, so that the wiring scheme maintains high adaptability and flexibility while following the design rules. Color coding is used to manage the state of the nodes, and the connection state and mask usage of each node are effectively recorded, so that the wiring algorithm can select the path more accurately during the search and optimization process, can handle circuit designs with higher complexity, and adapt to the needs of large-scale integrated circuits, thereby effectively reducing manufacturing costs and material waste, and achieving sustainability of the design.

[0121] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0122] There are a few points to note:

[0123] (1) The drawings of the embodiments of the present invention only involve structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0124] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0125] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0126] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A triple exposure multi-terminal wire mesh wiring method based on color coding, characterized in that: include: S1: Obtaining the chip's information to be wired, wherein the information to be wired includes chip information, component location information, wiring design constraint information, and multi-terminal wire net connection relationship information; S2: Determine the wiring diagram nodes according to the chip information and the component position information, and construct the wiring diagram structure of the area to be wired; S3: setting the wiring connection edge weights in the wiring diagram structure under different mask states according to the component position information and the wiring design constraint information; S4: Initialize the coloring code of the wiring diagram nodes; S5: Setting the coloring code change rules in the wire mesh search process and the wire mesh update process; S6: Combine the coloring code change rule and the multi-terminal wire net connection relationship information to perform a wiring search on the multi-terminal wire net to obtain a final wiring solution.

2. The triple exposure multi-terminal wire mesh wiring method based on color coding according to claim 1, characterized in that: The chip information includes chip size, chip layer number and chip track distribution; The component position information includes component size, component position and the layer where the component is located; The wiring design constraint information includes the routing width of different chip layers, the spacing between the lines of different chip layers, and the spacing between the lines and components of different chip layers; The multi-terminal line net connection relationship information includes multiple target component information in the area to be wired.

3. The triple exposure multi-terminal wire mesh wiring method based on color coding according to claim 1, characterized in that: The S2 specifically includes: S201: Determine, according to the chip information, a first wiring diagram node at an intersection of chip tracks of different chip layers; S202: Consider the location of the component as a second wiring diagram node; S203: determining, according to the component position information, an overlay relationship between the first wiring diagram node and the second wiring diagram node; S204: According to the covering relationship, adding a wiring connection edge between the second wiring diagram node and the corresponding first wiring diagram node to obtain the wiring diagram structure.

4. The triple exposure multi-terminal wire mesh wiring method based on color coding according to claim 1, characterized in that: The wiring connection edge weight specifically includes the actual spatial distance between each wiring diagram node, the layer switching connection cost between the wiring diagram nodes of different chip layers, and the penalty cost of constraint violation under different mask states.

5. The triple exposure multi-terminal wire mesh wiring method based on color coding according to claim 1, characterized in that: The S4 is specifically: The wiring diagram node is set to a coloring code in the form of a 3-bit binary system with an initial value of 7 to initialize the coloring code of the wiring diagram node.

6. The triple exposure multi-terminal wire mesh wiring method based on color coding according to claim 1, characterized in that: The coloring code change rules in the wire mesh search process are specifically as follows: If the i-th wiring diagram node is currently searched, the next node to be connected is the j-th wiring diagram node; According to the distance from the i-th wiring diagram node to the starting node and the wiring connection edge E between the i-th wiring diagram node and the j-th wiring diagram node ij The weights under different masks are used to calculate the distance from the jth wiring diagram node to the starting node; When the distance from the jth wiring diagram node to the starting node is less than the originally stored distance, updating the distance from the jth wiring diagram node to the starting node, and resetting the coloring code of the jth wiring diagram node; When the distance from the jth wiring diagram node to the starting node is equal to the original stored distance, the coloring code of the jth wiring diagram node is updated.

7. The triple exposure multi-terminal wire mesh wiring method based on color coding according to claim 6, characterized in that: The coloring code change rules in the line network update process are specifically as follows: According to the coloring code of the i-th wiring diagram node, determine the wiring connection edge E between the i-th wiring diagram node and the j-th wiring diagram node ij , and trace back to the jth wiring diagram node, repeating the above process until returning to the starting node; For the i-th wiring diagram node on the backtracking path, set the distance to 0 and mark it as the starting node; When the j-th binary code of the coloring code of the current i-th wiring diagram node is different from the j-th binary code of the coloring code of the i-th wiring diagram node counted during the backtracking process, the coloring code of the i-th wiring diagram node is updated.

8. The triple exposure multi-terminal wire mesh wiring method based on color coding according to claim 1, characterized in that: The S6 specifically includes: S601: performing a routing search on the multi-terminal net in combination with the coloring code change rule and the multi-terminal net connection relationship information until routing work is completed for all target elements of the multi-terminal net; S602: According to each routing search result and the routing design constraint information, when the routing connection edge E ij When the kth mask is used and the distance between the wiring connection edge and the same layer routing is less than the minimum spacing constraint between each line, the weight of the wiring connection edge E ijk Add the preset penalty value P.

9. A triple exposure multi-terminal wire mesh wiring system based on color coding, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the coloring-coding-based triple-exposure multi-terminal wire mesh wiring method according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the triple exposure multi-terminal wire mesh wiring method based on color coding as claimed in any one of claims 1 to 8 is implemented.

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