A method and system for triple-exposure multi-terminal line routing based on color-coded

Abstract

The application provides a kind of triple exposure multi-terminal line net wiring method and system based on color coding, it is related to circuit wiring technical field, method includes: obtaining the information to be wired of chip;According to the chip information and the element position information, determine wiring diagram node, construct the wiring diagram structure of the area to be wired;According to the element position information and the wiring design constraint information, set the wiring connection edge weight in the wiring diagram structure under different mask state;Initialize the color coding of the wiring diagram node;Set the color coding change rule in line net search process and line net update process;Combining the color coding change rule and the multi-terminal line net connection relationship information, carry out wiring search to multi-terminal line net, obtain final wiring scheme.The application can effectively improve the layout rate of triple exposure multi-terminal line net wiring and reduce the wiring running time, improve the wiring efficiency.

Description

Technical Field

[0001] This invention relates to the field of circuit routing technology, and in particular to a triple-exposure multi-terminal net routing method and system based on color coding. Background Technology

[0002] As integrated circuit feature sizes continue to shrink and layout density increases, multiple exposure lithography has become a key technology for further improving chip manufacturing success rates. Multiple exposure lithography decomposes the layout pattern onto multiple different photomasks, and through iterative processes of multiple exposures and etchings, ultimately forms a complete silicon wafer pattern. The minimum spacing between layout patterns on different photomasks can be smaller than the minimum spacing between layout patterns on the same photomask, thus placing higher and more complex requirements on integrated circuit design.

[0003] In the design of very large-scale integrated circuit chips, wiring is the most time-consuming and important step, which has an extremely important impact on the chip's performance and power consumption. In order to meet the requirements of multiple exposure lithography process, wiring needs to be distributed on different masks and the minimum spacing requirement of the layout patterns on different masks or the same mask must be met.

[0004] However, existing design methods mainly focus on double exposure technology or two-end net design. But as the scale and complexity of design increase, triple exposure technology is gradually becoming a new design trend. In the design of very large scale integrated circuit chips, multi-end nets are a common design format. Traditional methods often split them into multiple two-end nets, which leads to a solution with suboptimal output wiring length and easily reduces routing efficiency. Summary of the Invention

[0005] To address the limitations of existing design methods, which primarily focus on double-exposure techniques or two-end net designs, triple-exposure techniques are gradually becoming a new design trend as design scale and complexity increase. In VLSI chip design, multi-end nets are a common design format. Traditional methods often split them into multiple two-end nets, which may lead to suboptimal output wiring lengths and reduce routing efficiency. This invention provides a triple-exposure multi-end net routing method and system based on color coding.

[0006] The technical solutions provided by the embodiments of the present invention are as follows:

[0007] First aspect

[0008] This invention provides a triple-exposure multi-end net routing method based on color coding, comprising:

[0009] S1: Obtain the routing information of the chip, which includes chip information, component location information, routing design constraint information and multi-terminal net connection relationship information;

[0010] S2: Based on the chip information and component location information, determine the wiring diagram nodes and construct the wiring diagram structure for the area to be wired;

[0011] S3: Based on component location information and wiring design constraints, set the weights of wiring connection edges in the wiring diagram structure under different mask states;

[0012] S4: Initialize the color coding of the wiring diagram nodes;

[0013] S5: Define the color coding change rules during the net search process and net update process;

[0014] S6: Combining the color coding change rules and the multi-terminal net connection relationship information, perform a routing search on the multi-terminal net to obtain the final routing scheme.

[0015] Second aspect

[0016] This invention provides a triple-exposure multi-terminal net routing system based on color coding, comprising:

[0017] processor;

[0018] The memory stores computer-readable instructions, which, when executed by a processor, implement the color-coded triple-exposure multi-terminal net routing method of the first aspect.

[0019] Third aspect

[0020] The present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the color coding-based triple exposure multi-terminal net routing method as described in the first aspect.

[0021] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0022] In this invention, by directly processing multi-terminal nets, the traditional method of splitting multi-terminal nets into multiple two-terminal nets is avoided, thereby reducing the complexity of the routing stage and improving the overall routing efficiency. Utilizing triple exposure technology, routing space can be utilized more effectively, reducing routing length and helping to reduce routing delay and signal transmission loss, thus improving chip performance. By comprehensively considering the connection relationships of multi-terminal nets, the connectivity of signal paths is ensured, thereby significantly improving routing success rate and reducing the risk of failure due to signal interference or path congestion. By setting connection edge weights under different mask states, changes in design constraints can be flexibly addressed, allowing the routing scheme to maintain high adaptability and flexibility while adhering to design rules. Color coding is used for node state management, effectively recording the connection state and mask usage of each node, enabling the routing algorithm to select paths more accurately during the search and optimization process. This allows the algorithm to handle more complex circuit designs, adapt to the needs of large-scale integrated circuits, and effectively reduce manufacturing costs and material waste, achieving design sustainability. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a triple-exposure multi-terminal net routing method based on color coding, provided in an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the wiring structure provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a wiring diagram structure with connected edge weights provided in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of color coding initialization provided in an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of color coding when the first target element is found, provided in an embodiment of the present invention.

[0029] Figure 6 This is a schematic diagram of the color coding after the net is updated when the first target element is found, provided in an embodiment of the present invention.

[0030] Figure 7 This is a schematic diagram of the color coding after the net is updated when a second target element is found, provided in an embodiment of the present invention.

[0031] Figure 8 This is a schematic diagram of the wiring result provided in an embodiment of the present invention;

[0032] Figure 9 This is a schematic diagram of a triple-exposure multi-terminal net routing system based on color coding, provided in an embodiment of the present invention. Detailed Implementation

[0033] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0034] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0035] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0036] Reference manual attached Figure 1 The diagram shows a flowchart of a triple exposure multi-terminal net routing method based on color coding provided by an embodiment of the present invention.

[0037] This invention provides a triple-exposure multi-end net routing method based on color coding, comprising:

[0038] S1: Obtain the routing information of the chip, which includes chip information, component location information, routing design constraint information and multi-terminal net connection relationship information.

[0039] In one possible implementation, chip information includes chip size, number of chip layers, and chip track distribution; component location information includes component size, component location, and layer in which the component is located; routing design constraint information includes trace width of different chip layers, spacing between lines of different chip layers, and spacing between lines and components of different chip layers.

[0040] Among them, chip size refers to the physical size of an integrated circuit chip, usually expressed in micrometers (μm) or square micrometers (μm²). Chip layer number refers to the number of layers inside the chip, usually including multiple metal layers, insulating layers, and semiconductor layers. The number of layers affects the complexity of wiring and the signal transmission method. Chip track distribution refers to the arrangement of metal tracks (conductive paths used for wiring) on ​​the chip, including the position, width, and direction of the tracks in each layer. This distribution determines the effectiveness of the signal transmission path. Component size refers to the physical size of each component (such as resistors, capacitors, transistors, etc.) in the integrated circuit. Component position refers to the specific coordinates or position of the component on the chip, usually expressed in two-dimensional coordinates (x, y). Component layer refers to the specific level of the component in the multi-layer structure of the chip. Wiring design constraints refer to the rules and restrictions that need to be followed during the design process to ensure that the wiring meets the manufacturing process requirements. Trace width refers to the width of the metal tracks used for wiring. Different widths affect the signal transmission capability and wiring density.

[0041] It should be noted that obtaining the chip's routing information is the foundation of the entire routing process, ensuring that subsequent steps have sufficient data support. By fully understanding the chip information, component location information, design constraints, and connection relationships, the risk of design errors can be effectively reduced, and the accuracy and reliability of routing can be improved.

[0042] Reference manual attached Figure 2 The diagram shows a wiring diagram structure provided in an embodiment of the present invention.

[0043] like Figure 2 A is a schematic diagram of the wiring diagram structure. There are wiring connection edges between adjacent wiring diagram nodes in the vertical or horizontal direction. A component (represented by a light gray square) may cover multiple wiring diagram nodes.

[0044] S2: Based on the chip information and component location information, determine the wiring diagram nodes and construct the wiring diagram structure for the area to be wired.

[0045] In the routing diagram, nodes are key points and typically represent the connection points of components, intersections, or wiring. Each node acts as a decision point for path selection in the routing algorithm. The area to be routed refers to the area on the chip that has not yet been routed, which usually includes all the components that need to be connected and the connection relationships between them. The routing diagram structure is a graphical model used to describe the routing nodes and their connection relationships. The routing diagram structure consists of nodes and edges, with edges representing the connections between nodes or possible routing paths.

[0046] In one possible implementation, S2 specifically includes:

[0047] S201: Based on the chip information, determine the intersection of chip tracks of different chip layers as the first wiring diagram node.

[0048] It should be noted that determining the intersection of tracks in different chip layers as the first wiring diagram node based on chip information can effectively identify key connection locations.

[0049] S202: Treat the location of the component as a second wiring diagram node.

[0050] S203: Determine the coverage relationship between the first wiring diagram node and the second wiring diagram node based on the component location information.

[0051] The coverage relationship refers to the spatial relationship between the first wiring diagram node and the second wiring diagram node, indicating whether there is overlap or contact between the nodes, so that the signal can be transmitted from one node to another.

[0052] Specifically, determining the coverage relationship between the first and second wiring diagram nodes can effectively identify potential connection paths in the wiring. Through clear coverage relationships, wiring paths can be optimized, the risk of signal interference can be reduced, the circuit routing success rate can be improved, redundant connections in the wiring scheme can be reduced, and the efficiency and reliability of the overall design can be improved.

[0053] S204: Based on the coverage relationship, add wiring connection edges between the second wiring diagram node and the corresponding first wiring diagram node to obtain the wiring diagram structure.

[0054] It should be noted that determining the routing diagram nodes and constructing the routing diagram structure based on chip information and component location information helps to systematize and visualize the routing process, provides clear node and connection relationships, enables the routing algorithm to efficiently search for paths, and avoids redundant calculations and unnecessary complexity.

[0055] Reference manual attached Figure 3 This diagram illustrates a wiring diagram structure with connected edge weights provided in an embodiment of the present invention.

[0056] like Figure 3 The weight of adjacent connection edges that are too close to components or on the same mask as existing nets includes the penalty cost for violating design constraints. The black pattern represents nets that are routed in the first layer mask.

[0057] S3: Based on component location information and wiring design constraints, set the wiring connection edge weights in the wiring diagram structure under different mask states.

[0058] Among them, the mask state is the state of the photolithographic mask used in the routing process. Different mask states will affect the implementation of routing and the applicability of design constraints. Routing connection edge weight refers to the weight value assigned to the edge connecting the nodes in the routing diagram. The weight usually represents the cost or priority of the connection. The weight setting depends on the distance, design constraints and mask state.

[0059] In one possible implementation, the routing connection edge weight specifically includes the actual spatial distance between each routing graph node, the layer switching connection cost between routing graph nodes of different chip layers, and the penalty cost for constraint violation under different mask states.

[0060] Among them, actual spatial distance is the straight-line distance between two routing diagram nodes in physical space, usually expressed in micrometers or other units. Layer switching connection cost refers to the additional cost incurred when switching from one chip layer to another during routing. Layer switching connection cost takes into account the additional complexity and resource consumption in manufacturing and design. Constraint violation refers to the fact that there are usually a series of design rules and constraints (such as minimum spacing, maximum current, etc.) in routing design. If these constraints are not met during the routing process, a constraint violation will occur. Penalty cost refers to the additional penalty cost introduced in optimization algorithms when a constraint violation occurs, in order to force the algorithm to find a more compliant solution. This cost is usually added when calculating edge weights to reduce the priority of non-compliant routing schemes.

[0061] It should be noted that setting the weights of routing connection edges based on component location information and routing design constraints helps optimize routing path selection. Appropriately setting weights under different mask states ensures that the optimal routing path is selected while meeting design constraints. This dynamic weight setting effectively avoids signal interference and physical space conflicts during routing, improving routing success rate.

[0062] Reference manual attached Figure 4 The diagram illustrates the color coding initialization provided in an embodiment of the present invention.

[0063] like Figure 4 Black squares represent starting elements, dark gray squares represent ending elements, black patterns represent nets routed in the first mask, and diagonal patterns represent nets routed in the second mask. The color coding attribute of the starting point is the default value, the color coding attribute of other nodes is initialized to 111 (three-bit binary form of the integer 7), the color coding attribute of occupied nodes is set to 000 (three-bit binary form of the integer 0), the distance attribute of the starting point is 0, and the distance attribute of other nodes is positive infinity.

[0064] S4: Initialize the color coding of the wiring diagram nodes.

[0065] Color coding is a binary or other form of identifier assigned to nodes in a wiring diagram, typically used to represent the node's status, hierarchy, or connection information.

[0066] In one possible implementation, S4 specifically refers to:

[0067] The coloring code of the wiring diagram node is initialized by setting it to a 3-bit binary code with an initial value of 7.

[0068] It should be noted that color coding of initial routing diagram nodes helps to effectively manage and optimize the state during the routing process. By clearly identifying the state of each node, it is possible to quickly determine which nodes have been accessed or connected, thereby improving the efficiency of the routing algorithm. Color coding can also simplify the management of complex routing constraints, avoid potential design conflicts, and ensure the effectiveness and manufacturability of the final routing scheme.

[0069] Reference manual attached Figure 5 This diagram illustrates the color coding when the first target element is found, as provided in an embodiment of the present invention.

[0070] like Figure 5 The color coding attributes of the nodes on the path from the starting point to the first target element are not exactly the same. The starting point (the small black square in the upper left corner) is the starting position of the path, and the target node (the small dark gray square in the upper right corner) is the first target element to be searched. The color of each element changes depending on whether it is the starting point or the ending point. The element is a light gray rectangle by default. The path nodes in the figure are nodes with color coding, indicating that these nodes are part of the path. In the figure, the starting point S value is 111 and the D value is 0, and the ending point S value is 011 and the D value is 6.

[0071] Reference manual attached Figure 6 This diagram illustrates the color coding after the net is updated when the first target element is found, as provided in an embodiment of the present invention.

[0072] like Figure 6 This is a schematic diagram of the color coding after the net is updated when the first target element is found. The color coding attributes of the nodes are reset. The distance attribute D of the starting point is 0. The D value of each node on the path from the starting point increases from 1 to 6, indicating the distance from the starting point to the target node. The color coding attribute S of the starting point changes from 111 to 011.

[0073] Reference manual attached Figure 7 This diagram illustrates the color coding after the net is updated when a second target element is found, as provided in an embodiment of the present invention.

[0074] like Figure 7 This represents the path from the first target to the second target element and the state changes of the nodes after the network update. The node attribute S on the path is 001, and the D value of all path nodes is set to 0. This means that the updated network sets the heuristic estimate of the path and the distance.

[0075] S5: Define the rules for color coding changes during the net search and net update processes.

[0076] Among them, the color coding change rules refer to the rules for defining how to update the color coding of nodes in the routing diagram during the routing process. These rules are usually changed based on factors such as the connection status and distance between nodes.

[0077] In one possible implementation, the color coding change rule during the wire mesh search process is specifically as follows.

[0078] If the current search finds the i-th wiring diagram node, then the next node to connect to is the j-th wiring diagram node.

[0079] Based on the distance from the i-th routing graph node to the starting node and the routing connection edge E between the i-th routing graph node and the j-th routing graph node. ij Calculate the distance from the j-th wiring diagram node to the starting node based on the weights under different masks.

[0080] If the distance from the j-th wiring diagram node to the starting node is less than the original storage distance, update the distance from the j-th wiring diagram node to the starting node and reset the coloring code of the j-th wiring diagram node.

[0081] If the distance from the j-th wiring diagram node to the starting node is equal to the original storage distance, update the coloring code of the j-th wiring diagram node.

[0082] In one possible implementation, the color coding change rules during the net update process are specifically as follows.

[0083] Based on the coloring code of the i-th routing graph node, determine the routing connection edge E between the i-th routing graph node and the j-th routing graph node. ij Then backtrack to the j-th wiring diagram node and repeat the above process until returning to the starting node.

[0084] Set the distance to 0 for the i-th wiring graph node on the backtracking path and mark it as the starting node;

[0085] If the binary code of the j-th bit of the coloring code of the current i-th wiring diagram node is different from the binary code of the j-th bit of the coloring code of the i-th wiring diagram node counted during the backtracking process, update the coloring code of the i-th wiring diagram node.

[0086] It should be noted that setting color coding change rules can significantly improve the flexibility and efficiency of the routing process. With clear rules, the algorithm can quickly determine and update the node status, thereby optimizing the search path and avoiding unnecessary repeated calculations. This mechanism can also ensure that design constraints are adhered to in complex multi-layer routing, improving the quality and feasibility of the routing scheme.

[0087] Reference manual attached Figure 8 The diagram shows a wiring result provided by an embodiment of the present invention.

[0088] like Figure 8 Black patterns represent nets that are routed in the first layer mask, diagonal patterns represent nets that are routed in the second layer mask, and gray patterns represent nets that are routed in the third layer mask. After completing the search of multi-end nets, a code is selected from the node's color coding as the final mask for the current node.

[0089] S6: Combining the color coding change rules and the multi-terminal net connection relationship information, perform a routing search on the multi-terminal net to obtain the final routing scheme.

[0090] In one possible implementation, S6 specifically includes:

[0091] S601: Combining color coding change rules and multi-terminal net connection relationship information, perform routing search on multi-terminal nets until all target components of the multi-terminal nets have completed routing.

[0092] It should be noted that by combining color coding variation rules and multi-terminal net connection information, the routing search process can be systematically optimized, the search efficiency can be improved, all target components can be effectively connected, resource waste and potential design conflicts can be reduced, and the overall quality and reliability of the routing scheme can be improved.

[0093] S602: Based on the various cabling search results and cabling design constraint information, when the cabling connection edge E... ij When using the k-th mask and the spacing between the routing connection edge and the trace in the same layer is less than the minimum spacing constraint between all traces, the weight E of the routing connection edge is... ijk Add a preset penalty value P.

[0094] Specifically, by introducing a penalty mechanism to adjust the weight of wiring connection edges, the design is ensured to comply with wiring design constraints. This effectively reduces the priority of non-compliant connection schemes, promotes wiring optimization, and ultimately improves the feasibility of wiring and the performance of the circuit, ensuring the integrity and stability of the design.

[0095] It should be noted that by combining color coding variation rules and multi-terminal net connection information, routing search can be performed efficiently and systematically, ensuring the connection of all target components, while optimizing path selection, reducing routing conflicts and design errors, and ultimately improving the efficiency and manufacturability of circuit design.

[0096] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0097] In this invention, by directly processing multi-terminal nets, the traditional method of splitting multi-terminal nets into multiple two-terminal nets is avoided, thereby reducing the complexity of the routing stage and improving the overall routing efficiency. Utilizing triple exposure technology, routing space can be utilized more effectively, reducing routing length and helping to reduce routing delay and signal transmission loss, thus improving chip performance. By comprehensively considering the connection relationships of multi-terminal nets, the connectivity of signal paths is ensured, thereby significantly improving routing success rate and reducing the risk of failure due to signal interference or path congestion. By setting connection edge weights under different mask states, changes in design constraints can be flexibly addressed, allowing the routing scheme to maintain high adaptability and flexibility while adhering to design rules. Color coding is used for node state management, effectively recording the connection state and mask usage of each node, enabling the routing algorithm to select paths more accurately during the search and optimization process. This allows the algorithm to handle more complex circuit designs, adapt to the needs of large-scale integrated circuits, and effectively reduce manufacturing costs and material waste, achieving design sustainability.

[0098] Reference manual attached Figure 9 The diagram shows a structural schematic of a triple-exposure multi-terminal net routing system based on color coding provided by the present invention.

[0099] The present invention also provides a color-coded triple-exposure multi-end net routing system 20, applied to the above-mentioned color-coded triple-exposure multi-end net routing method, comprising:

[0100] Processor 201.

[0101] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201, they implement the color-coded triple-exposure multi-terminal net routing method as described in the method embodiment.

[0102] The color coding-based triple exposure multi-terminal net routing system 20 provided by the present invention can perform the above-described color coding-based triple exposure multi-terminal net routing method and achieve the same or similar technical effects. To avoid repetition, the present invention will not elaborate further.

[0103] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0104] In this invention, by directly processing multi-terminal nets, the traditional method of splitting multi-terminal nets into multiple two-terminal nets is avoided, thereby reducing the complexity of the routing stage and improving the overall routing efficiency. Utilizing triple exposure technology, routing space can be utilized more effectively, reducing routing length and helping to reduce routing delay and signal transmission loss, thus improving chip performance. By comprehensively considering the connection relationships of multi-terminal nets, the connectivity of signal paths is ensured, thereby significantly improving routing success rate and reducing the risk of failure due to signal interference or path congestion. By setting connection edge weights under different mask states, changes in design constraints can be flexibly addressed, allowing the routing scheme to maintain high adaptability and flexibility while adhering to design rules. Color coding is used for node state management, effectively recording the connection state and mask usage of each node, enabling the routing algorithm to select paths more accurately during the search and optimization process. This allows the algorithm to handle more complex circuit designs, adapt to the needs of large-scale integrated circuits, and effectively reduce manufacturing costs and material waste, achieving design sustainability.

[0105] It should be understood that the processor in the embodiments of the present invention can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0106] It should also be understood that the memory in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0107] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the flow or function according to the embodiments of the present invention is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. Semiconductor media can be solid-state drives.

[0108] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0109] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0110] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0111] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0112] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0113] In the embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0114] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0115] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0116] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0117] This invention provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the color-coded triple-exposure multi-terminal net routing method as described in the method embodiment.

[0118] The computer-readable storage medium provided by this invention can implement the steps and effects of the color coding-based triple exposure multi-terminal net routing method in the above-described method embodiments. To avoid repetition, this invention will not repeat the details.

[0119] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0120] In this invention, by directly processing multi-terminal nets, the traditional method of splitting multi-terminal nets into multiple two-terminal nets is avoided, thereby reducing the complexity of the routing stage and improving the overall routing efficiency. Utilizing triple exposure technology, routing space can be utilized more effectively, reducing routing length and helping to reduce routing delay and signal transmission loss, thus improving chip performance. By comprehensively considering the connection relationships of multi-terminal nets, the connectivity of signal paths is ensured, thereby significantly improving routing success rate and reducing the risk of failure due to signal interference or path congestion. By setting connection edge weights under different mask states, changes in design constraints can be flexibly addressed, allowing the routing scheme to maintain high adaptability and flexibility while adhering to design rules. Color coding is used for node state management, effectively recording the connection state and mask usage of each node, enabling the routing algorithm to select paths more accurately during the search and optimization process. This allows the algorithm to handle more complex circuit designs, adapt to the needs of large-scale integrated circuits, and effectively reduce manufacturing costs and material waste, achieving design sustainability.

[0121] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0122] The following points need to be explained:

[0123] (1) The accompanying drawings of the embodiments of the present invention only involve the structures involved in the embodiments of the present invention. Other structures can refer to the general design.

[0124] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the invention, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0125] (3) Where there is no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to obtain new embodiments.

[0126] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A triple-exposure multi-end net routing method based on color coding, characterized in that, include: S1: Obtain the routing information of the chip, wherein the routing information includes chip information, component location information, routing design constraint information and multi-terminal net connection relationship information; The chip information includes chip size, number of chip layers, and chip track distribution; The component location information includes component size, component location, and the layer in which the component is located; The routing design constraints include the trace width of different chip layers, the spacing between lines of different chip layers, and the spacing between lines and components of different chip layers; The multi-terminal wire network connection relationship information includes information on multiple target components in the area to be wired; S2: Based on the chip information and the component location information, determine the wiring diagram nodes and construct the wiring diagram structure for the area to be wired; S3: Based on the component location information and the wiring design constraint information, set the wiring connection edge weights in the wiring diagram structure under different mask states; S4: Initialize the coloring encoding of the wiring diagram nodes; S5: Define the color coding change rules during the net search process and net update process; S6: Combining the color coding change rules and the multi-terminal net connection relationship information, perform a routing search on the multi-terminal net to obtain the final routing scheme.

2. The triple-exposure multi-end net routing method based on color coding according to claim 1, characterized in that, S2 specifically includes: S201: Based on the chip information, determine the intersection of chip tracks of different chip layers as the first wiring diagram node; S202: Treat the location of the component as a second wiring diagram node; S203: Determine the coverage relationship between the first wiring diagram node and the second wiring diagram node based on the component location information; S204: Based on the coverage relationship, add a wiring connection edge between the second wiring diagram node and the corresponding first wiring diagram node to obtain the wiring diagram structure.

3. The triple-exposure multi-end net routing method based on color coding according to claim 1, characterized in that, Specifically, S4 is: The coloring code of the wiring diagram node is initialized by setting it to a 3-bit binary code with an initial value of 7.

4. The triple-exposure multi-terminal net routing method based on color coding according to claim 1, characterized in that, The specific rules for color coding changes during the wire mesh search process are as follows: If the current search finds the i-th wiring diagram node, then the next node to connect is the j-th wiring diagram node; Based on the distance from the i-th routing graph node to the starting node and the routing connection edge E between the i-th routing graph node and the j-th routing graph node. ij Calculate the distance from the j-th wiring diagram node to the starting node based on the weights under different masks; If the distance from the j-th wiring diagram node to the starting node is less than the original storage distance, update the distance from the j-th wiring diagram node to the starting node and reset the coloring code of the j-th wiring diagram node. If the distance from the j-th wiring diagram node to the starting node is equal to the original storage distance, update the coloring code of the j-th wiring diagram node.

5. The triple-exposure multi-end net routing method based on color coding according to claim 4, characterized in that, The specific rules for color encoding changes during the net update process are as follows: Based on the coloring code of the i-th routing graph node, determine the routing connection edge E between the i-th routing graph node and the j-th routing graph node. ij And backtrack to the j-th wiring diagram node, repeat the above process until returning to the starting node; Set the distance to 0 for the i-th wiring graph node on the backtracking path and mark it as the starting node; If the binary code of the j-th bit of the coloring code of the current i-th wiring diagram node is different from the binary code of the j-th bit of the coloring code of the i-th wiring diagram node counted during the backtracking process, update the coloring code of the i-th wiring diagram node.

6. The triple-exposure multi-end net routing method based on color coding according to claim 1, characterized in that, S6 specifically includes: S601: Combining the color coding change rules and the multi-terminal net connection relationship information, perform routing search on the multi-terminal net until all target elements of the multi-terminal net have completed the routing work; S602: Based on the various wiring search results and the wiring design constraint information, when the wiring connection edge E... ij When using the k-th mask and the spacing between the routing connection edge and the trace in the same layer is less than the minimum spacing constraint between all lines, the weight E of the routing connection edge is adjusted. ijk Add a preset penalty value P.

7. A triple-exposure multi-terminal net routing system based on color coding, characterized in that, include: processor; A memory storing computer-readable instructions, which, when executed by the processor, implement the triple-exposure multi-terminal net routing method based on color coding as described in any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the triple exposure multi-terminal net routing method based on color coding as described in any one of claims 1 to 6.

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