A method for reducing interference of chip on interposer routing

Abstract

The present invention discloses a method for reducing the interference of a chip on an intermediate layer routing, and relates to the technical field of integrated circuit design. The present invention effectively solves the signal interference problem mentioned in the background technology by accurately identifying and classifying the inductor area in the chip. In key areas such as PHY, bandwidth extension inductor, and phase-locked loop LC voltage-controlled oscillator, through the Virtuoso tool and image processing algorithm, the designer can identify the inductor area according to the actual layout, and use the PDK layer map to define the inductor area hierarchy, ensuring that the inductor area is correctly marked and processed in the design, which not only improves the accuracy of the inductor design, but also optimizes the frequency characteristics and quality factor of the inductor by modeling and simulating the inductor through the simulation tool, thereby reducing the interference of the magnetic field generated by the inductor during operation on the surrounding circuits, and improving the quality and reliability of signal transmission.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit design, and in particular to a method for reducing interference of a chip on an intermediate layer routing. Background Art

[0002] In integrated circuit design, the quality of signal transmission is crucial. With the development of 2.5D and 3D packaging technology, the distance between the interposer and the die has become very close, usually only 10 microns. However, the inductor inside the chip will generate a large magnetic field when working, which will interfere with the surrounding circuits, increase signal noise, and even change the signal. This interference is particularly evident in PHY, bandwidth extension inductors, and phase-locked loop LC voltage-controlled oscillators because these areas implement on-chip inductors. When signal lines pass over these inductors, they interfere with each other, affecting the integrity and reliability of the signal. Summary of the invention

[0003] The purpose of the present invention is to provide a method for reducing the interference of the chip on the intermediate layer routing, which effectively reduces the interference of the chip on the intermediate layer routing, improves the quality and reliability of signal transmission, and ensures the accuracy and performance of integrated circuit design.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present application provides a method for reducing the interference of a chip on an interposer routing, comprising the following steps:

[0006] Identify the inductor area in the chip, perform on-chip inductance in PHY, bandwidth extension inductor, and phase-locked loop LC voltage-controlled oscillator, and use Virtuoso to identify the inductor area in the chip based on the actual layout and determine the inductance;

[0007] Define the inductor area hierarchy. In Virtuoso, define a specific hierarchy to cover the inductor area. Then, according to the hierarchy in the PDK layer map provided by each manufacturer, select a specific inductor layer to cover the inductor area. The coverage rule adds 5um to the outermost side, the coverage pattern is a rectangle, and the attribute is defined as pin.

[0008] Extract the inductor area information. Use the Virtuoso tool to extract the layer, coordinates, and area of ​​the inductor area. Create a layout cell through Virtuoso, call the chip layout into it, and use PAD OPENING INFO to extract the coordinates, size, and name.

[0009] Return the PAD OPENING INFO extracted data to the TOP design, and then compare the interposer routing area and the chip inductor area;

[0010] When it is determined that there is a trace passing through the inductor area, the trace layout of the interposer or the chip inductor area data is modified according to the actual situation so that there is no trace in the inductor area. When it is determined that there is no trace in the inductor area, the process is completed.

[0011] Furthermore, Virtuoso is used to identify the inductor area in the chip based on the actual layout, including:

[0012] Obtain the layout data of the chip, analyze the layout through image processing algorithms, and identify the inductor area in the published image;

[0013] According to the pre-established inductor model library, the identified inductor area is matched to determine the type and parameters of the inductor;

[0014] For the PHY circuit, determine the type and quantity of on-chip inductors to be used, and mark the corresponding inductor area in the layout; for the bandwidth extension inductor, determine the required inductor parameters according to the circuit design requirements, and layout the corresponding inductor structure in the layout; for the phase-locked loop LC voltage-controlled oscillator, design a suitable LC resonant circuit according to the frequency and performance requirements of the oscillator, and layout the inductor and capacitor in the layout;

[0015] Use simulation tools to model and simulate on-chip inductors, analyze the frequency characteristics and quality factor of the inductors, and optimize the inductor design based on the simulation results;

[0016] After the layout design is completed, the DRC tool is used to check the design rules of the inductor area, and then the inductor parameters are extracted and verified.

[0017] Furthermore, the inductor region hierarchy is defined, including:

[0018] According to the PDK layer map, get the specific inductor layer used to define the inductor area, create a new layer in Virtuoso and name it "ind_area" to represent the inductor area, then get the geometry and coordinate information of the inductor area, and draw a rectangular shape covering the inductor area in the "ind_area" layer;

[0019] Expand the drawn rectangular shape, increase its outermost border by 5um, and define the attribute as a pin to identify and use the inductor area in design and layout;

[0020] In the "ind_area" level, a new geometric object is generated according to the coordinate information of the expanded rectangular figure, and it is added to the virtuoso database, and then the newly generated geometric object is checked and verified.

[0021] Furthermore, after extracting the hierarchy, coordinates and area of ​​the inductor area through the Virtuoso tool, it also includes: establishing a layout cell based on the extracted data and recording its attributes, integrating the chip layout information into the layout cell to build a complete circuit layout, and extracting the geometric information of the PAD OPENING area through image processing technology, performing feature extraction to identify attributes, and then integrating and storing the extracted features in the circuit layout database, and using design rule checking to verify and optimize the entire layout.

[0022] Furthermore, the hierarchy, coordinates and area information of the inductor area are obtained through the Virtuoso tool and stored in the database. The obtained inductor area information is used to create a corresponding layout cell in Virtuoso, and the attribute information of the layout cell is also stored in the database.

[0023] Read the chip layout information from the database and import it into the previously created layout cell to form a complete circuit layout. For the PAD OPENING area, extract the geometric information through image processing algorithms.

[0024] Perform feature extraction on the extracted geometric information of PAD OPENING to obtain attribute information, and associate the attribute information with the extracted information for storage;

[0025] The information of the inductor area, layout cell and PAD OPENING areas is integrated to build a complete circuit layout database. Based on the constructed circuit layout database and the design rule checking algorithm, the entire circuit layout is verified and optimized.

[0026] Furthermore, the PAD OPENING INFO extracted data is returned to the TOP design, including:

[0027] Acquire PAD opening information, including coordinates, two-dimensional graphics and name data of the PAD opening, extract the acquired PAD opening information data, and obtain feature data of the PAD opening coordinates, two-dimensional graphics and name;

[0028] According to the extracted PAD opening feature data, a PAD opening information model is constructed to represent the position, shape and identification information of the PAD opening;

[0029] Obtain the location and range data of the interposer routing area and the chip inductor area, spatially match the PAD opening information model with the interposer routing area and the chip inductor area data, and determine whether the PAD opening is located in the interposer routing area or the chip inductor area;

[0030] Furthermore, when the PAD opening is located in the interposer routing area or the chip inductor area, the PAD opening is marked as a critical PAD opening, and its spatial relationship data with the interposer routing or the chip inductor is recorded; the extracted PAD opening information data and the critical PAD opening marking results are returned to the TOP design to guide the layout and connection design of the PAD opening in the TOP design.

[0031] Furthermore, after modifying the routing layout of the intermediate layer or the chip inductance area data according to actual conditions, it also includes: using a convolutional neural network algorithm and quantitative analysis to identify and classify routing, selecting the optimal routing solution for high-frequency signals through an automatic wiring algorithm, and adjusting the inductance value and position of the low-frequency signal routing.

[0032] Furthermore, convolutional neural network algorithms and quantitative analysis are used to identify and classify routing, including:

[0033] Identify the inductor area range according to the pre-established circuit layout image database, obtain the internal image of the inductor area range, and use the convolutional neural network algorithm to extract the routing features, and perform quantitative analysis to determine the quantitative analysis indicators;

[0034] When the quantitative analysis index exceeds the preset threshold range, it is determined that the routing exists, and the routing category information is identified through the preset routing rules;

[0035] When the routing category information belongs to high-frequency signal routing, the automatic routing algorithm is called to calculate other paths without high-frequency signal routing interference and determine a set of alternative routing solutions.

[0036] Furthermore, after using the convolutional neural network algorithm and quantitative analysis to identify and classify the routing, it also includes: intelligently predicting the potential conflict between the inductor area and the routing through a deep learning algorithm;

[0037] The method of intelligently predicting potential conflicts between inductor regions and routing lines by using a deep learning algorithm includes: collecting and preprocessing layout design data, including the position, shape, size of the inductor region and routing layout information; extracting the edge of the inductor region, the routing path, and key features of the spatial relationship from the layout image using CNN, and evaluating the features of the routing; using annotated data sets to identify routing layouts that cause electromagnetic interference, and applying the trained data to the layout design to predict potential conflicts between the inductor region and the routing; and automatically adjusting the routing path using a deep learning model or a reinforcement learning algorithm based on the conflict prediction results.

[0038] Furthermore, by obtaining the routing length and delay data corresponding to each scheme in the set of alternative routing schemes, a weighted calculation is performed on the routing length and delay to obtain the loss parameter, and the optimal scheme is selected from them;

[0039] When the routing category information belongs to low-frequency signal routing, the optimal solution for adjusting the inductance value corresponding to the chip inductance area is calculated according to the current value and voltage value corresponding to the low-frequency signal, and the position information of the changed inductance area is determined;

[0040] According to the optimal position information of the inductor area and the preset three-dimensional model library, the corresponding layout model after adjustment is retrieved to obtain the updated circuit layout, and the electromagnetic field simulation is performed using the finite element analysis method to verify whether the simulation results are consistent with the pre-established model.

[0041] The beneficial effects of the present invention are:

[0042] The present invention effectively solves the signal interference problem mentioned in the background technology by accurately identifying and classifying the inductor areas in the chip. In key areas such as PHY, bandwidth extension inductor, and phase-locked loop LC voltage-controlled oscillator, the designer can identify the inductor area according to the actual layout through the Virtuoso tool and image processing algorithm, and define the inductor area hierarchy using the PDK layer map to ensure that the inductor area is correctly marked and processed in the design. This not only improves the accuracy of the inductor design, but also optimizes the frequency characteristics and quality factor of the inductor by modeling and simulating the inductor through the simulation tool, thereby reducing the interference of the magnetic field generated by the inductor during operation on the surrounding circuits and improving the quality and reliability of signal transmission.

[0043] The present invention realizes fine management of circuit layout by defining the inductance region hierarchy and extracting PAD OPENING INFO data. By returning PAD OPENING INFO data to TOP design and spatially matching with the intermediate layer routing region and the chip inductance region, the designer can identify and mark key PAD openings to avoid conflicts or interferences between the PAD openings and the intermediate layer routing or the chip inductance region. By using a convolutional neural network algorithm and quantitative analysis, the present invention can identify and classify routing, select the optimal routing scheme for high-frequency signals, and adjust the inductance value and position of low-frequency signal routing, which not only improves the automation and intelligence level of circuit design, but also ensures that the design meets the established performance requirements through electromagnetic field simulation by finite element analysis, further enhancing the overall performance and reliability of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0045] Figure 1 A flow chart of a method for reducing interference of a chip on an interposer routing provided in the present application;

[0046] Figure 2 A schematic diagram of a process for identifying an inductance region in a chip in a method for reducing interference of a chip on an interposer routing provided in the present application;

[0047] Figure 3 A schematic diagram of a flow chart of defining the inductor region hierarchy for a method of reducing chip interference to interposer routing provided in the present application. DETAILED DESCRIPTION

[0048] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0049] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0050] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0051] See also Figure 1-Figure 3 This embodiment provides a method for reducing the interference of the chip on the routing of the interposer, comprising the following steps:

[0052] S1. Identify the inductor area in the chip, implement on-chip inductors in PHY, bandwidth extension inductors, and phase-locked loop LC voltage-controlled oscillators, and use virtuoso to identify the inductor area in the chip based on the actual layout to determine which ones are inductors;

[0053] Furthermore, Virtuoso is used to identify the inductor area in the chip based on the actual layout, including:

[0054] S11, obtaining the layout data of the chip, analyzing the layout through an image processing algorithm, and identifying the inductance area in the published image;

[0055] S12, matching the identified inductor region according to a pre-established inductor model library, and determining the type and parameters of the inductor;

[0056] For the PHY circuit, determine the type and quantity of on-chip inductors to be used, and mark the corresponding inductor area in the layout; for the bandwidth extension inductor, determine the required inductor parameters according to the circuit design requirements, and layout the corresponding inductor structure in the layout; for the phase-locked loop LC voltage-controlled oscillator, design a suitable LC resonant circuit according to the frequency and performance requirements of the oscillator, and layout the inductor and capacitor in the layout;

[0057] S13, modeling and simulating the on-chip inductor through simulation tools, analyzing the frequency characteristics and quality factor of the inductor, and optimizing the inductor design according to the simulation results;

[0058] S14. After the layout design is completed, use the Design Rule Check (DRC) tool to check the design rules of the inductor area to ensure that the inductor layout meets the process requirements, and extract and verify the inductor parameters to ensure that the inductor performance meets the design indicators.

[0059] Among them, PHY is the physical layer interface, and Virtuoso is an EDA (electronic design automation) software used in the design and verification process of integrated circuits.

[0060] Specifically, the Virtuoso tool and image processing algorithm are used to accurately identify and classify the inductor areas in the chip, design appropriate on-chip inductors for the PHY circuit, bandwidth extension inductor and phase-locked loop LC voltage-controlled oscillator, optimize the inductor performance through simulation tools, and finally use the Design Rule Check (DRC) tool to ensure that the inductor layout meets the process requirements. These steps together ensure the accuracy of the inductor design and the reliability of the circuit performance, thereby improving the overall performance and signal integrity of the integrated circuit.

[0061] S2. Define the inductor area hierarchy. In Virtuoso, define a specific hierarchy that covers the inductor area. According to the hierarchy in the PDK layer map provided by each manufacturer, select a specific inductor layer to cover the inductor area. The coverage rule adds 5um to the outermost side, the coverage pattern is a rectangle, and the attribute is defined as pin.

[0062] Furthermore, the inductor region hierarchy is defined, including:

[0063] S21. According to the PDK layer map, obtain the specific inductor layer used to define the inductor area, create a new layer in Virtuoso and name it "ind_area" to represent the inductor area, then obtain the geometric shape and coordinate information of the inductor area, and draw a rectangular shape covering the inductor area in the "ind_area" layer based on this information;

[0064] S22, the drawn rectangular figure is expanded, and its outermost border is increased by 5um to ensure that the inductor area is completely covered, and the attribute of the expanded rectangular figure is defined as pin, so that the inductor area can be identified and used in subsequent design and layout;

[0065] S23. In the "ind_area" layer, a new geometric object is generated according to the coordinate information of the expanded rectangular figure, and it is added to the database of virtuoso. The newly generated geometric object is then checked and verified to ensure that it can correctly represent the inductor area and does not conflict or overlap with other layers and components.

[0066] Among them, PDK layer map is an important file for integrated circuit design. It defines the correspondence between different design layers and specific process nodes. This file allows the design software to identify and use the correct layers to build circuits, ensuring that the design meets the requirements of specific manufacturing processes. In the PDK layer map, the properties of various layers are listed in detail, including their materials, thickness, uses and other information. Inductor layer refers to the layer dedicated to inductors in the PDK layer map. Inductors are components used to store magnetic energy in integrated circuits. In integrated circuit design, the inductor layer is used to implement on-chip inductors. These inductors can be spiral or other shapes. They are designed on specific metal layers to provide the required inductance characteristics. ind_area is the name of a specific layer used to represent the inductor area in EDA tools such as Virtuoso. It is used to cover the inductor area for identification and management during the design process. The creation of the ind_area layer is based on the specific inductor layer in the PDK layer map.

[0067] Specifically, the inductor area hierarchy is defined through the Virtuoso tool. First, the specific inductor layer is obtained according to the PDK layer map, and a new hierarchy "ind_area" is created in Virtuoso to represent the inductor area. This step involves obtaining the layout data of the chip, analyzing the layout with an image processing algorithm, identifying the inductor area, and drawing a rectangular graphic covering these areas in the "ind_area" hierarchy. In order to ensure complete coverage, the rectangular graphic is extended by 5um, and the extended graphic attributes are set to pin to facilitate identification and use in design and layout. Next, based on the coordinate information of the extended rectangular graphic, a new geometric object is generated in the "ind_area" hierarchy and added to the Virtuoso database. Finally, the newly generated geometric object is checked and verified in detail to ensure that it correctly represents the inductor area and does not conflict or overlap with other hierarchies and components, thereby solving the electromagnetic interference problem mentioned in the background technology and improving the accuracy and reliability of integrated circuit design.

[0068] S3. Extract the inductor area information. Use the Virtuoso tool to extract the layer, coordinates, and area of ​​the inductor area. Create a layout cell through Virtuoso, call the chip layout into it, and use PAD OPENING INFO to extract the coordinates, size, and name.

[0069] Among them, layout cell refers to the layout unit, which is the basic building block in integrated circuit design. It can be a standard logic gate, storage unit or more complex subcircuit. The layout unit is the smallest unit used by design automation tools (such as Virtuoso) to layout and route on the chip; chip layout refers to the layout of the entire chip, including the placement and interconnection of all layout units. Chip layout covers the physical design of the entire chip, including the layout of functional units, interconnection lines (routing), pad (PAD) layout, and possible power and ground distribution. Use PAD OPENINGINFO to extract coordinates, size and name. This information is the key parameter in layout design and is used to determine the physical location and connection method of each part on the chip.

[0070] Furthermore, after extracting the hierarchy, coordinates and area of ​​the inductor area through the Virtuoso tool, it also includes: establishing a layout cell based on the extracted data and recording its attributes, integrating the chip layout information into the layout cell to build a complete circuit layout, and extracting the geometric information of the PAD OPENING area through image processing technology, performing feature extraction to identify attributes, and then integrating and storing the extracted features in the circuit layout database, using design rule checking to verify and optimize the entire layout to ensure that the design meets the established requirements, thereby completing a comprehensive integrated circuit design and verification process.

[0071] Furthermore, the hierarchy, coordinates and area information of the inductor area are obtained through the Virtuoso tool and stored in the database. The obtained inductor area information is used to create a corresponding layout cell in Virtuoso, and the attribute information of the layout cell is also stored in the database.

[0072] Read the chip layout information from the database and load it into the previously created layout cell to form a complete circuit layout. For the PAD OPENING area, extract its coordinates, size and other geometric information through image processing algorithms such as edge detection and area segmentation.

[0073] Perform feature extraction on the extracted geometric information of PAD OPENING to obtain its name and other attribute information, and associate the attribute information with the extracted information for storage;

[0074] The information of different areas such as the inductor area, layout cell, and PAD OPENING are integrated to build a complete circuit layout database. Based on the constructed circuit layout database, combined with algorithms such as design rule checking, the entire circuit layout is verified and optimized to ensure that it meets the design requirements.

[0075] Specifically, the Virtuoso tool is used to extract the level, coordinates, and area information of the inductor area, and a layout cell is established to record its attributes. This process not only provides accurate inductor area data for integrated circuit design, but also builds a complete circuit layout by integrating chip layout information. Image processing technology is then used to extract the geometric information of the PAD OPENING area and perform feature extraction to ensure that the attributes of the PAD opening are accurately identified and recorded. These extracted features are integrated and stored in the circuit layout database, providing a basis for design rule checking, allowing the design team to systematically verify and optimize the entire layout. This process ensures that the integrated circuit design meets the established performance requirements while also meeting the standards of the manufacturing process, thereby improving the reliability and production efficiency of the design and effectively avoiding potential design conflicts and electromagnetic interference problems.

[0076] S4. Return the PAD OPENING INFO extracted data to the TOP design, including coordinates, two-dimensional graphics and names; compare the interposer routing area and the chip inductor area;

[0077] Among them, TOP design usually refers to the top-level layout of the entire integrated circuit design. The data here includes coordinates, two-dimensional graphics and names.

[0078] Furthermore, the PAD OPENING INFO extracted data is returned to the TOP design, including:

[0079] Acquire PAD opening information, including data such as coordinates, two-dimensional graphics, and names of the PAD opening, extract the acquired PAD opening information data, and obtain feature data of the PAD opening coordinates, two-dimensional graphics, and names;

[0080] According to the extracted PAD opening feature data, a PAD opening information model is constructed to represent information such as the position, shape, and identification of the PAD opening;

[0081] Obtain the location and range data of the interposer routing area and the chip inductor area, spatially match the PAD opening information model with the interposer routing area and the chip inductor area data, and determine whether the PAD opening is located in the interposer routing area or the chip inductor area;

[0082] Further, when the PAD opening is located in the interposer wiring area or the chip inductor area, the PAD opening is marked as a key PAD opening, and the spatial relationship data between the PAD opening and the interposer wiring or the chip inductor is recorded;

[0083] The extracted PAD opening information data and key PAD opening marking results are returned to the TOP design to guide the layout and connection design of the PAD opening in the TOP design, so as to avoid conflicts or interferences between the PAD opening and the interposer routing area and the chip inductor area.

[0084] Among them, PAD OPENING INFO refers to more detailed PAD opening data, including the PAD's geometry, layer information, and other design parameters related to the PAD. PAD opening information refers to the opening details of the package pad (PAD) in integrated circuit design, including key data such as the pad's coordinates, size, and name, which are used to ensure the correct connection between the chip package and the circuit board.

[0085] Specifically, the PAD OPENING INFO data is extracted through the Virtuoso tool and returned to the TOP design. This process ensures the accuracy and availability of key information such as the coordinates, two-dimensional graphics and names of the PAD opening. By building a PAD opening information model, the location, shape and identification of the PAD opening can be accurately represented. This information is spatially matched with the data of the interposer routing area and the chip inductor area, which helps to identify and determine whether the PAD opening overlaps or is close to these areas. When the PAD opening is detected in a critical area, it is marked as a critical PAD opening and its spatial relationship data is recorded. The return and application of this data guides the PAD opening layout and connection design in the TOP design, thereby effectively avoiding conflicts or interference between the PAD opening and the interposer routing or chip inductor area, ensuring the reliability and signal integrity of the integrated circuit design.

[0086] S5. When it is determined that there is a trace passing through the inductor area, modify the trace layout of the interposer or the chip inductor area data according to the actual situation so that there is no trace in the inductor area. When it is determined that there is no trace in the inductor area, the process is completed.

[0087] Furthermore, after modifying the routing layout of the intermediate layer or the chip inductance area data according to actual conditions, it also includes: using a convolutional neural network algorithm and quantitative analysis to identify and classify routing, selecting the optimal routing solution for high-frequency signals through an automatic wiring algorithm, and adjusting the inductance value and position of the low-frequency signal routing.

[0088] Furthermore, convolutional neural network algorithms and quantitative analysis are used to identify and classify routing, including:

[0089] Identify the inductor area range according to the pre-established circuit layout image database, obtain the internal image of the inductor area range, and use the convolutional neural network algorithm to extract the routing features, and perform quantitative analysis to determine the quantitative analysis indicators;

[0090] When the quantitative analysis index exceeds the preset threshold range, it is determined that the routing exists, and the routing category information is identified through the preset routing rules;

[0091] When the routing category information belongs to high-frequency signal routing, the automatic routing algorithm is called to calculate other paths without high-frequency signal routing interference and determine a set of alternative routing solutions;

[0092] Furthermore, by obtaining the routing length and delay data corresponding to each scheme in the set of alternative routing schemes, a weighted calculation is performed on the routing length and delay to obtain the loss parameter, and the optimal scheme is selected from them;

[0093] When the routing category information belongs to low-frequency signal routing, the optimal solution for adjusting the inductance value corresponding to the chip inductance area is calculated according to the current value and voltage value corresponding to the low-frequency signal, and the position information of the changed inductance area is determined;

[0094] According to the optimal position information of the inductor area and the preset three-dimensional model library, the corresponding layout model after adjustment is retrieved to obtain the updated circuit layout, and the electromagnetic field simulation is performed using the finite element analysis method to verify whether the simulation results are consistent with the pre-established model.

[0095] After using convolutional neural network algorithms and quantitative analysis to identify and classify routing, it also includes: intelligently predicting potential conflicts between inductive areas and routing through deep learning algorithms.

[0096] Specifically, it includes: collecting and preprocessing a large amount of layout design data, including the location, shape, size of the inductor area and the layout information of the routing, to provide a basis for the training of the deep learning model; then using CNN to extract the edges of the inductor area, the routing path, and the key features of the spatial relationship from the layout image, and evaluate the routing characteristics, such as length, width and current carrying capacity. Then use the annotated data set to identify the routing layout that causes electromagnetic interference, and apply the trained data to the layout design to predict the potential conflict between the inductor area and the routing; according to the conflict prediction results, use the deep learning model or reinforcement learning algorithm to automatically adjust the routing path.

[0097] Among them, the optimization algorithm will consider multiple factors such as routing length, electromagnetic interference, thermal impact, etc. in this process to propose the optimal routing solution, and then perform electromagnetic simulation on the adjusted routing layout to verify whether the optimized layout meets the design requirements, and further fine-tune the routing path based on the simulation results to ensure that the interference between the inductor area and the routing is minimized; in addition, the simulation and actual test results are fed back to the deep learning model to continuously improve the model's prediction accuracy, and through continuous iterative optimization, improve the performance and effectiveness of the solution.

[0098] In integrated circuit design, when it is found that there are traces passing through the inductor area, the design process includes modifying the trace layout of the interposer or the chip inductor area data to ensure that there is no trace interference in the inductor area. Using convolutional neural network algorithms and quantitative analysis, the inductor area range is identified based on the circuit layout image database, trace features are extracted, and quantitative analysis is performed to determine indicators. For high-frequency signal traces, the automatic routing algorithm is used to calculate interference-free paths, determine alternative trace solutions, and select the optimal solution. For low-frequency signal traces, the inductor value and position are adjusted according to the current and voltage values. The finite element analysis method is used for electromagnetic field simulation to verify the consistency of the updated circuit layout with the pre-established model to ensure that the design meets the requirements. This process significantly improves the quality and reliability of circuit design through precise trace identification, classification and optimization, effectively avoids electromagnetic interference, and ensures signal integrity and circuit performance.

[0099] This method uses Virtuoso tools and image processing technology to accurately identify and classify inductor areas in integrated circuits, designs appropriate on-chip inductors for key parts such as PHY circuits, bandwidth extension, and phase-locked loop LC voltage-controlled oscillators, and ensures the process compatibility of inductor performance and layout through simulation and design rule checking. It then defines the inductor area hierarchy, integrates chip layout information, extracts PAD OPENING data, and builds a circuit layout database to achieve comprehensive verification and optimization of circuit layout. In addition, it uses convolutional neural network algorithms and quantitative analysis to identify and classify routing, and the automatic routing algorithm selects the optimal routing solution for high-frequency signals. At the same time, it adjusts the inductance value and position of low-frequency signal routing to ensure that there is no routing interference in the inductor area. Specifically, it effectively reduces the interference of the chip on the intermediate layer routing, improves the quality and reliability of signal transmission, and ensures the accuracy and performance of integrated circuit design.

[0100] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for reducing chip interference to interposer routing, characterized in that: The steps include: Identify the inductor area in the chip, perform on-chip inductance in PHY, bandwidth extension inductor, and phase-locked loop LC voltage-controlled oscillator, and use Virtuoso to identify the inductor area in the chip based on the actual layout and determine the inductance; Define the inductor area hierarchy. In Virtuoso, define an initial hierarchy to cover the inductor area. Then, according to the hierarchy in the PDK layer map provided by each manufacturer, select the initial inductor layer to cover the inductor area. The outermost side of the coverage rule is increased by 5um, the coverage pattern is a rectangle, and the attribute is defined as pin. Extract the inductor area information. Use the Virtuoso tool to extract the layer, coordinates, and area of ​​the inductor area. Create a layout cell through Virtuoso, call the chip layout into it, and use PAD OPENING INFO to extract the coordinates, size, and name. Return the PAD OPENING INFO extracted data to the TOP design, and then compare the interposer routing area and the chip inductor area; When it is determined that there is a trace passing through the inductor area, modify the trace layout of the interposer or the chip inductor area data according to the actual situation so that there is no trace in the inductor area. When it is determined that there is no trace in the inductor area, the process is completed; After modifying the routing layout of the interposer or the chip inductance area data according to the actual situation, it also includes: using a convolutional neural network algorithm and quantitative analysis to identify and classify routing, selecting the optimal routing solution for high-frequency signals through an automatic routing algorithm, and adjusting the inductance value and position of low-frequency signal routing; The use of convolutional neural network algorithms and quantitative analysis to identify and classify routing includes: Identify the inductor area range according to the pre-established circuit layout image database, obtain the internal image of the inductor area range, and use the convolutional neural network algorithm to extract the routing features, and perform quantitative analysis to determine the quantitative analysis indicators; When the quantitative analysis index exceeds the preset threshold range, it is determined that the routing exists, and the routing category information is identified through the preset routing rules; When the routing category information belongs to high-frequency signal routing, the automatic routing algorithm is called to calculate other paths without high-frequency signal routing interference and determine a set of alternative routing solutions.

2. The method for reducing chip interference to interposer routing according to claim 1, characterized in that: Through Virtuoso, the inductor area in the chip is identified according to the actual layout, including: Obtain the layout data of the chip, analyze the layout through image processing algorithms, and identify the inductor area in the published image; According to the pre-established inductor model library, the identified inductor area is matched to determine the type and parameters of the inductor; For the PHY circuit, determine the type and quantity of on-chip inductors to be used, and mark the corresponding inductor area in the layout; for the bandwidth extension inductor, determine the required inductor parameters according to the circuit design requirements, and layout the corresponding inductor structure in the layout; for the phase-locked loop LC voltage-controlled oscillator, design a suitable LC resonant circuit according to the frequency and performance requirements of the oscillator, and layout the inductor and capacitor in the layout; Use simulation tools to model and simulate on-chip inductors, analyze the frequency characteristics and quality factor of the inductors, and optimize the inductor design based on the simulation results; After the layout design is completed, the DRC tool is used to check the design rules of the inductor area, and then the inductor parameters are extracted and verified.

3. The method for reducing chip interference to interposer routing according to claim 1, characterized in that: Define the inductor region hierarchy, including: According to the PDK layer map, get the initial inductor layer used to define the inductor area, create a new layer in Virtuoso and name it "ind_area" to represent the inductor area, then get the geometric shape and coordinate information of the inductor area, and draw a rectangular shape covering the inductor area in the "ind_area" layer; Expand the drawn rectangular shape, increase its outermost border by 5um, and define the attribute as a pin to identify and use the inductor area in design and layout; In the "ind_area" level, a new geometric object is generated according to the coordinate information of the expanded rectangular figure, and it is added to the virtuoso database, and then the newly generated geometric object is checked and verified.

4. The method for reducing chip interference to interposer routing according to claim 1, characterized in that: After extracting the hierarchy, coordinates, and area of ​​the inductor region through the Virtuoso tool, the process also includes: establishing a layout cell based on the extracted data and recording its attributes, integrating the chip layout information into the layout cell to build a complete circuit layout, and extracting the geometric information of the PAD OPENING area through image processing technology, performing feature extraction to identify attributes, and then integrating and storing the extracted features in the circuit layout database, and using design rule checking to verify and optimize the entire layout.

5. The method for reducing chip interference to interposer routing according to claim 4, characterized in that: The hierarchy, coordinates, and region information of the inductor region are obtained through the Virtuoso tool and stored in the database. The corresponding layout cell is created in Virtuoso using the obtained inductor region information, and the attribute information of the layout cell is also stored in the database. Read the chip layout information from the database and import it into the previously created layout cell to form a complete circuit layout. For the PAD OPENING area, extract the geometric information through image processing algorithms. Perform feature extraction on the extracted geometric information of PAD OPENING to obtain attribute information, and associate the attribute information with the extracted information for storage; The information of the inductor area, layout cell and PAD OPENING areas is integrated to build a complete circuit layout database. Based on the constructed circuit layout database and the design rule checking algorithm, the entire circuit layout is verified and optimized.

6. The method for reducing chip interference to interposer routing according to claim 1, characterized in that: Return the PADOPENING INFO extracted data to the TOP design, including: Acquire PAD opening information, including coordinates, two-dimensional graphics and name data of the PAD opening, extract the acquired PAD opening information data, and obtain feature data of the PAD opening coordinates, two-dimensional graphics and name; According to the extracted PAD opening feature data, a PAD opening information model is constructed to represent the position, shape and identification information of the PAD opening; The position and range data of the interposer routing area and the chip inductor area are obtained, and the PAD opening information model is spatially matched with the interposer routing area and the chip inductor area data to determine whether the PAD opening is located in the interposer routing area or the chip inductor area.

7. The method for reducing chip interference to interposer routing according to claim 6, characterized in that: When the PAD opening is located in the interposer routing area or the chip inductor area, the PAD opening is marked as a key PAD opening, and the spatial relationship data between the PAD opening and the interposer routing or the chip inductor is recorded; The extracted PAD opening information data and key PAD opening marking results are returned to the TOP design to guide the layout and connection design of the PAD openings in the TOP design.

8. The method for reducing chip interference to interposer routing according to claim 1, characterized in that: After using convolutional neural network algorithms and quantitative analysis to identify and classify routing, it also includes: intelligently predicting potential conflicts between inductive areas and routing through deep learning algorithms.

9. The method for reducing chip interference to interposer routing according to claim 8, characterized in that: The method of intelligently predicting potential conflicts between inductor regions and routing lines by using a deep learning algorithm includes: collecting and preprocessing layout design data, including the position, shape, size of the inductor region and routing layout information; extracting the edge of the inductor region, the routing path, and key features of the spatial relationship from the layout image using CNN, and evaluating the features of the routing; using annotated data sets to identify routing layouts that cause electromagnetic interference, and applying the trained data to the layout design to predict potential conflicts between the inductor region and the routing; and automatically adjusting the routing path using a deep learning model or a reinforcement learning algorithm based on the conflict prediction results.

10. The method for reducing chip interference to interposer routing according to claim 1, characterized in that: By obtaining the routing length and delay data corresponding to each plan in the set of alternative routing plans, weighted calculation is performed on the routing length and delay to obtain the loss parameter, and the best plan is selected from them; When the routing category information belongs to low-frequency signal routing, the optimal solution for adjusting the inductance value corresponding to the chip inductance area is calculated according to the current value and voltage value corresponding to the low-frequency signal, and the position information of the changed inductance area is determined; According to the optimal position information of the inductor area and the preset three-dimensional model library, the corresponding layout model after adjustment is retrieved to obtain the updated circuit layout, and the electromagnetic field simulation is performed using the finite element analysis method to verify whether the simulation results are consistent with the pre-established model.

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