Display panel and display device

Abstract

Embodiments of the present invention disclose a display panel and a display device. The display panel includes a plurality of first pixel circuits and a second pixel circuit. The plurality of first pixel circuits are located in a display area and arranged in an array. Each first pixel circuit is connected to a light-emitting element, and the first pixel circuit is used to drive the light-emitting element to emit light. At least n rows of first pixel circuits simultaneously perform threshold voltage compensation. A plurality of second pixel circuits are located in a non-display area and arranged in an array. The second pixel circuits are used to pad the number of pixel circuits simultaneously performing threshold voltage compensation to n rows when threshold voltage compensation is performed on the first row of first pixel circuits and / or the last row of first pixel circuits, thereby compensating for the compensation current of the first row of first pixel circuits and / or the last row of first pixel circuits. The number of transistors in the second pixel circuit is smaller than the number of transistors in the first pixel circuit. This solution can solve the problem of abnormal display of pixels in the first and last rows.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, display panels are moving towards high refresh rates.

[0003] At high refresh rates, there is a problem of abnormal display of pixels in the first and last rows. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device to solve the problem of abnormal display of pixels in the first and last rows.

[0005] According to one aspect of the present invention, a display panel is provided, the display panel having a display area and a non-display area arranged around the display area, the display panel comprising:

[0006] a plurality of first pixel circuits, the plurality of first pixel circuits being located in the display area and arranged in an array of m rows, each of the first pixel circuits being connected to a light-emitting element, the first pixel circuit being configured to drive the light-emitting element to emit light; wherein at least n rows of the first pixel circuits simultaneously perform threshold voltage compensation, where m and n are both positive integers greater than 1, and m is greater than n;

[0007] a plurality of second pixel circuits, the plurality of second pixel circuits being located in the non-display area and arranged in an array of t rows, the second pixel circuits being configured to configure the second pixel circuits in row x to perform threshold voltage compensation when the first pixel circuits in the preceding row a perform threshold voltage compensation, and / or being configured to configure the second pixel circuits in row y to perform threshold voltage compensation when the first pixel circuits in the following row b perform threshold voltage compensation, wherein t, a, x, b, and y are all positive integers greater than 1, x and y are both not greater than t, and a+x and b+y are both not greater than n;

[0008] The number of transistors in the second pixel circuit is smaller than the number of transistors in the first pixel circuit.

[0009] Optionally, x is equal to na, and / or, y is equal to nb;

[0010] Preferably, t is equal to 2n-2, wherein n-1 rows of the second pixel circuits are provided in the non-display area close to the first row of the first pixel circuits, and n-1 rows of the second pixel circuits are provided in the non-display area close to the last row of the first pixel circuits.

[0011] Optionally, the number of the second pixel circuits in a row is less than or equal to the number of the first pixel circuits in a row.

[0012] Optionally, the second pixel circuit includes a first driving module, a first initialization module, a first compensation module and a first storage module;

[0013] A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the first end of the first driving module;

[0014] A first end of the first driving module is connected to a first power line, a second end of the first driving module is connected to a first end of the first compensation module, a second end of the first compensation module is connected to a control end of the first driving module, the control end of the first compensation module is connected to a second scan line, and the first compensation module is used to compensate for the threshold voltage of the first driving module in a threshold voltage compensation stage;

[0015] Optionally, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, and the first storage module includes a first storage capacitor; a first electrode of the first transistor is connected to the first power line, a second electrode of the first transistor is connected to the first electrode of the second transistor, a second electrode of the second transistor is connected to the gate of the first transistor, and the gate of the second transistor is connected to the second scan line, a first electrode of the third transistor is connected to the first initialization signal line, a second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; a first electrode of the first storage capacitor is connected to the gate of the first transistor, and a second electrode of the first storage capacitor is connected to the first electrode of the first transistor;

[0016] Optionally, the first transistor, the second transistor and the third transistor are all P-type transistors.

[0017] Optionally, the second pixel circuit includes a first driving module, a first initialization module, a first compensation module and a first storage module;

[0018] A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, and the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase; and the first storage module is connected between the control end and the second end of the first driving module.

[0019] A first end of the first driving module is connected to a first end of the first compensation module, a second end of the first driving module is connected to a second power line, a second end of the first compensation module is connected to a control end of the first driving module, and the control end of the first compensation module is connected to a second scan line. The first compensation module is used to compensate for the threshold voltage of the first driving module in a threshold voltage compensation stage;

[0020] Optionally, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, and the first storage module includes a first storage capacitor; a first electrode of the first transistor is connected to a first electrode of the second transistor, a second electrode of the first transistor is connected to the second power line, a second electrode of the second transistor is connected to a gate of the first transistor, and the gate of the second transistor is connected to the second scan line; a first electrode of the third transistor is connected to the first initialization signal line, a second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; a first electrode of the first storage capacitor is connected to the gate of the first transistor, and a second electrode of the first storage capacitor is connected to the second electrode of the first transistor;

[0021] Optionally, the first transistor, the second transistor and the third transistor are all N-type transistors.

[0022] Optionally, the second pixel circuit includes a first driving module, a first initialization module, a first compensation module, an auxiliary module and a first storage module;

[0023] A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the first end of the first driving module;

[0024] A first end of the first driving module is connected to a first power line via the auxiliary module, a second end of the first driving module is connected to a first end of the first compensation module, a second end of the first compensation module is connected to a second power line, a control end of the first compensation module is connected to a second scan line, the first compensation module is used to compensate for the threshold voltage of the first driving module in a threshold voltage compensation phase, and the control end of the auxiliary module is connected to a third scan line;

[0025] Optionally, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, the auxiliary module includes a fourth transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the second electrode of the fourth transistor, the first electrode of the fourth transistor is connected to the first power line, the gate of the fourth transistor is connected to the third scan line, the second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to the second power line, the gate of the second transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the first electrode of the first transistor;

[0026] Optionally, the first transistor, the second transistor, the third transistor and the fourth transistor are all P-type transistors.

[0027] Optionally, the second pixel circuit includes a first driving module, a first initialization module, a first compensation module, an auxiliary module and a first storage module;

[0028] A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the second end of the first driving module;

[0029] A first end of the first driving module is connected to a first power line via the first compensation module, a second end of the first driving module is connected to a first end of the auxiliary module, a second end of the auxiliary module is connected to a second power line, a control end of the first compensation module is connected to a third scan line, the first compensation module is used to compensate for the threshold voltage of the first driving module in a threshold voltage compensation phase, and the control end of the auxiliary module is connected to the second scan line;

[0030] Optionally, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, the auxiliary module includes a fourth transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the gate of the second transistor is connected to the third scan line, the second electrode of the first transistor is connected to the first electrode of the fourth transistor, the second electrode of the fourth transistor is connected to the second power line, the gate of the fourth transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the second electrode of the first transistor;

[0031] Optionally, the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors.

[0032] Optionally, the on-time of the first compensation module is equal to the row time of n rows of the first pixel circuits.

[0033] Optionally, in the second pixel circuits in the same row, the second pixel circuits share the same first initialization module and the first storage module;

[0034] Optionally, the first initialization module and the first storage module in the second pixel circuits of each row are arranged at the second pixel circuit positions in the first column or the last column;

[0035] Optionally, in the same row of the second pixel circuits, the second pixel circuits share the same first compensation module.

[0036] Optionally, the first pixel circuit includes a second driving module, a data writing module, a second compensation module, a second storage module, a third storage module, a second initialization module, a third initialization module and a light emitting module;

[0037] Optionally, the second driving module and the light-emitting module are connected between a third power line and a fourth power line, the data writing module is connected between the data line and the first end of the second storage module, the control end of the data writing module is connected to the fourth scan line, the second end of the second storage module is connected to the control end of the second driving module, and the third storage module is connected between the first end of the second driving module and the first end of the second storage module;

[0038] The second compensation module is connected between the second terminal and the control terminal of the second driving module, the control terminal of the second compensation module is connected to the fifth scan line, and the second compensation module is used to compensate for the threshold voltage of the second driving module in the threshold voltage compensation stage;

[0039] The second initialization module is connected between the second initialization signal line and the first end of the second storage module, and the control end of the second initialization module is connected to the fifth scan line;

[0040] The third initialization module is connected between the third initialization signal line and the first end of the second driving module, and the control end of the third initialization module is connected to the sixth scan line;

[0041] Optionally, the conduction time of the second compensation module is equal to the row time of n rows of the first pixel circuits;

[0042] Optionally, the first pixel circuit further includes a first light-emitting control module and a second light-emitting control module, wherein a first end of the first light-emitting control module is connected to the third power line, a second end of the first light-emitting control module is connected to the second end of the second driving module, a first end of the second light-emitting control module is connected to the first end of the second driving module, a second end of the second light-emitting control module is connected to the first end of the light-emitting module, and a second end of the light-emitting module is connected to the fourth power line; a control end of the first light-emitting control module is connected to a first light-emitting control signal line, and a control end of the second light-emitting control module is connected to a second light-emitting control signal line;

[0043] Optionally, the first pixel circuit further includes a fourth initialization module, the fourth initialization module is connected between a fourth initialization signal line and the first end of the light emitting module, and a control end of the fourth initialization module is connected to the sixth scan line.

[0044] According to another aspect of the present invention, a display device is provided. The display device includes the display panel provided by any embodiment of the present invention.

[0045] The technical solution provided by the embodiment of the present invention is that a first pixel circuit provided in the display area is used to drive a light-emitting element to emit light, and at least n rows of first pixel circuits perform threshold voltage compensation simultaneously; by providing multiple rows of second pixel circuits in the non-display area, so that there is a corresponding pixel circuit row in front of the first row of first pixel circuits and / or behind the last row of first pixel circuits, so that when the threshold voltage compensation is performed on the first row of first pixel circuits and / or the last row of first pixel circuits, the pixel circuit rows that are compensated simultaneously with the first row of first pixel circuits and / or the last row of first pixel circuits are padded to n rows or close to n rows, thereby compensating the compensation current of the first row of first pixel circuits and / or the last row of first pixel circuits, thereby making the compensation current corresponding to the first row of first pixel circuits and / or the last row of first pixel circuits consistent with the compensation current corresponding to the first pixel circuits in other intermediate rows, thereby making the threshold voltage compensation effect of each row of first pixel circuits in the display area consistent, avoiding the problem of display abnormality of the first row of pixels in the display area. In addition, since the number of transistors in the second pixel circuit is less than the number of transistors in the first pixel circuit, it is beneficial to reduce the space occupied by the second pixel circuit, thereby reducing the width of the non-display area and reducing the impact on the frame of the display panel.

[0046] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A schematic diagram of a compensation process for pixel circuits in each row of a display panel in the related art;

[0049] Figure 2 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of a compensation process for pixel circuits in each row of a display panel provided by an embodiment of the present invention;

[0051] Figure 4 A schematic structural diagram of a second pixel circuit provided by an embodiment of the present invention;

[0052] Figure 5A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention

[0053] Figure 6 A driving timing diagram of a second pixel circuit provided by an embodiment of the present invention;

[0054] Figure 7 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0055] Figure 8 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0056] Figure 9 A driving timing diagram of another second pixel circuit provided by an embodiment of the present invention;

[0057] Figure 10 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0058] Figure 11 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0059] Figure 12 A driving timing diagram of another second pixel circuit provided by an embodiment of the present invention;

[0060] Figure 13 A schematic structural diagram of another second pixel circuit provided in an embodiment of the present invention;

[0061] Figure 14 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0062] Figure 15 A driving timing diagram of another second pixel circuit provided by an embodiment of the present invention;

[0063] Figure 16 A structural diagram of an arrangement of a second pixel circuit provided by an embodiment of the present invention;

[0064] Figure 17 A structural diagram of another arrangement of a second pixel circuit provided by an embodiment of the present invention;

[0065] Figure 18 A schematic structural diagram of a first pixel circuit provided by an embodiment of the present invention;

[0066] Figure 19 A schematic structural diagram of another first pixel circuit provided by an embodiment of the present invention;

[0067] Figure 20A driving timing diagram of a first pixel circuit provided by an embodiment of the present invention;

[0068] Figure 21 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0069] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0070] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] As described in the background art, existing display panels have the problem of abnormal display of pixels in the first and last rows at high refresh rates. The inventors have found that the reason for the above problem is that at high refresh rates, the row time of the pixel circuit is greatly compressed, resulting in the inability of the internal compensation circuit to complete the compensation process within a row time. In order to solve the above problem, the relevant technology uses cross-row compensation to compensate for the threshold voltage. The so-called cross-row compensation refers to the fact that the threshold voltage compensation time of the pixel circuit exceeds the row time, so that the compensation time spans multiple rows, that is, there is a phenomenon of simultaneous compensation of multiple rows of pixel circuits to improve the compensation effect. However, in the current display panels, the compensation method of the pixel circuit is a charge-discharge structure. Multiple rows of pixel circuits charge and discharge the first storage capacitor at the same time, and there is a phenomenon of instantaneous voltage drop in the DC voltage involved in the compensation. Moreover, since the number of rows compensated simultaneously by the first and last row pixel circuits is insufficient, the DC voltage involved in the compensation of the first and last row pixel circuits will be different from the DC voltage at other positions, which in turn causes the problem of abnormal display of the first and last row pixels.

[0072] For example, Figure 1A schematic diagram of a compensation process of pixel circuits in each row of a display panel in the related art, referring to Figure 1 , the X direction represents time, and the Y direction represents pixel rows. Taking the simultaneous compensation of 5 rows of pixel circuits as an example, during the compensation process, the pixel circuits in the middle row overlap the compensation time of 2 rows of pixel circuits above and below. For example, during the threshold voltage compensation process of the 8th row of pixel circuits Row8, the two rows above it (the 6th row of pixel circuits Row6 and the 7th row of pixel circuits Row7) and the two rows below it (the 9th row of pixel circuits Row9 and the 10th row of pixel circuits Row10) simultaneously perform threshold voltage compensation, and the DC voltage drop used for compensation of each row of pixel circuits is 1V. However, there is no pixel circuit row overlapping with it above the 1st row of pixel circuits Row1. Therefore, the DC voltage drop used for compensation of the 1st row of pixel circuits Row1 is less than 1V, resulting in different compensation currents for the 1st row of pixel circuits Row1 and the middle row of pixel circuits, which in turn leads to the inconsistent compensation effect of the threshold voltage of the 1st row of pixel circuits Row1 and the middle row of pixel circuits, resulting in abnormal driving of the 1st row of pixel circuits Row1 and abnormal display of the 1st row of pixels Row1. The compensation effect of the pixel circuit in the last row (taking Row 15 as an example) is the same as the compensation effect of the pixel circuit in Row 1.

[0073] like Figure 1 At the middle dotted line, during the simultaneous compensation process, the first 5 rows and the last 5 rows of pixel circuits will both lack corresponding pixel circuit rows.

[0074] To address the above problem, an embodiment of the present invention provides a display panel that adds redundant pixel circuits to make up for the missing pixel circuit rows of the first and last rows during the compensation process. Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, referring to Figure 2 The display panel provided in this embodiment has a display area AA and a non-display area NA arranged around the display area, and the display panel includes:

[0075] A plurality of first pixel circuits 11 are located in the display area AA and arranged in an array of m rows. Each first pixel circuit AA is connected to a light-emitting element, and the first pixel circuit 11 is used to drive the light-emitting element to emit light. At least n rows of first pixel circuits 11 simultaneously perform threshold voltage compensation, where m and n are both positive integers greater than 1, and m is greater than n.

[0076] a plurality of second pixel circuits 21, the plurality of second pixel circuits 21 being located in the non-display area NA and arranged in an array of t rows, the second pixel circuits 21 being configured to configure the second pixel circuits in row x to perform threshold voltage compensation when the first pixel circuits 11 in the preceding row a perform threshold voltage compensation, and / or to configure the second pixel circuits 21 in row y to perform threshold voltage compensation when the first pixel circuits 11 in the following row b perform threshold voltage compensation, wherein t, a, x, b, and y are all positive integers greater than 1, x and y are both not greater than t, and a+x and b+y are both not greater than n;

[0077] The number of transistors in the second pixel circuit 21 is smaller than the number of transistors in the first pixel circuit 11 .

[0078] Specifically, the first pixel circuits 11 are arranged in the display area AA, with a total of m rows, and are connected to light-emitting elements (not shown in the figure), and can be used to drive the light-emitting elements to emit light, thereby realizing screen display. The second pixel circuits 21 are arranged in the non-display area NA, with a total of t rows, and are not connected to the light-emitting elements. That is, the second pixel circuits 21 are redundant pixel circuits and can be used to make up for the number of rows missing from the first and last rows of first pixel circuits 11. For example, there are n rows of first pixel circuits 11 that perform threshold voltage compensation simultaneously, but for the first pixel circuits 11 in the first a rows, since the number of rows of first pixel circuits 11 in front of each row in the first a rows is less than n-1 rows, the number of rows of the difference between the first pixel circuits 11 in the first row and the first pixel circuits 11 in the a-th row decreases successively. In this case, the threshold voltage compensation can be performed by controlling the second pixel circuits 21 in the x rows so that when the first pixel circuits 11 in the first a rows perform threshold voltage compensation, the number of rows of pixel circuits that perform threshold voltage compensation simultaneously is close to n rows, or equal to n rows, so as to reduce the difference in threshold voltage compensation when the first pixel circuits 11 in the first a rows in the display area AA perform threshold voltage compensation. Similarly, for the first pixel circuits 11 in the last b rows, since the number of rows of first pixel circuits 11 following the last b rows is less than n-1 rows, the number of rows behind the first pixel circuits 11 in the nb-th row to the last row of first pixel circuits 11 increases successively. At this time, by controlling the second pixel circuits 21 in the y row to perform threshold voltage compensation, when the first pixel circuits 11 in the last b rows perform threshold voltage compensation, the number of pixel circuit rows simultaneously performing threshold voltage compensation is close to or equal to n rows, thereby reducing the difference in threshold voltage compensation performed by the first pixel circuits 11 in the last b rows within the display area AA.

[0079] Figure 3 A schematic diagram of a compensation process of pixel circuits in each row of a display panel provided by an embodiment of the present invention, with reference to Figure 3Taking the simultaneous threshold voltage compensation of five rows of first pixel circuits 11 as an example (i.e., n=5), corresponding rows of second pixel circuits 21 are added in front of the first pixel circuit 11 in Row 1 and behind the first pixel circuit 11 in the last row (only Row 15 is used as the last row in the display area AA for illustration, i.e., m=15). This allows the first / last row of first pixel circuits 11 to be supplemented when multiple rows of threshold voltage compensation are performed simultaneously by the first pixel circuits 11 in the first / last row. For example, in this embodiment, four rows of second pixel circuits 21, namely Du1, Du2, ..., Du8, are added to the first pixel circuits 11 in the first and last rows, respectively, i.e., t=8. In this way, near the start time of the threshold voltage compensation of the first pixel circuit 11 in the first row Row1 (the position of the first dotted line), the second pixel circuit Du1 in the first row, the second pixel circuit Du2 in the second row, the second pixel circuit Du3 in the third row, the second pixel circuit Du4 in the fourth row and the first pixel circuit Row1 in the first row are compensated at the same time. As time goes by, near the end time of the threshold voltage compensation of the first pixel circuit Row1 in the first row (the position of the second dotted line), the first pixel circuit Row1 in the first row, the first pixel circuit Row2 in the second row, the first pixel circuit Row3 in the third row, the first pixel circuit Row4 in the fourth row and the first pixel circuit Row5 in the fifth row are compensated at the same time. Compensation is performed simultaneously. Therefore, during the compensation process of the first pixel circuit Row1 in the first row, there are always 4 rows of pixel circuits that perform compensation together with it, so that the compensation current corresponding to the first pixel circuit Row1 in the first row is consistent with the compensation currents corresponding to the first pixel circuits in other rows; similarly, during the compensation process of the first pixel circuit 11 in the last row, there are always 4 rows of pixel circuits that perform compensation together with it, so that the compensation current corresponding to the first pixel circuit 11 in the last row is consistent with the compensation currents corresponding to the first pixel circuits 11 in other middle rows, so that the compensation effect of the threshold voltage of the first pixel circuits 11 in each row in the display area AA is consistent, avoiding the problem of display abnormality of the first and last rows of pixels in the display area AA.

[0080] In actual operation, two rows of pixel circuits before and after the current row participate in compensation simultaneously.

[0081] It should be noted that if there is a process of simultaneously performing threshold voltage compensation for n rows of first pixel circuits 11, the number of rows compensated simultaneously by the first four rows of first pixel circuits 11 and the last four rows of first pixel circuits 11 is insufficient, and the number of missing rows decreases or increases successively (the number of rows missing by the first four rows of first pixel circuits 11 decreases successively, and the number of rows missing by the last four rows of first pixel circuits 11 increases successively, that is, the number of rows missing by the first pixel circuit 11 in Row 1 and the first pixel circuit 11 in the last row is the largest). In this embodiment, since the first pixel circuits 11 in the first and last rows of the display area AA both have n-1 rows of pixel circuits (including the first pixel circuit 11 in row a and the second pixel circuit 21 in row x, or including the first pixel circuit 11 in row b and the second pixel circuit 21 in row y) performing compensation simultaneously therewith, the first pixel circuits 11 in the second row and the second-to-last row in the display area AA also have n-1 rows of pixel circuits performing compensation simultaneously therewith. That is to say, while ensuring that the first pixel circuits 11 in the first and last rows in the display area AA have n-1 rows of pixel circuits to compensate simultaneously with them, each row of first pixel circuits 11 in the display area AA has other n-1 rows of pixel circuits to compensate simultaneously with the pixel circuit in that row.

[0082] In this embodiment, since the second pixel circuit 21 is not connected to the light-emitting element and the second pixel circuit 21 has a compensation function, the second pixel circuit 21 only needs to have a compensation circuit, so that the number of transistors in the second pixel circuit 21 is smaller than the number of transistors in the first pixel circuit 11, thereby reducing the occupied area of ​​the second pixel circuit 21, which is conducive to reducing the border width.

[0083] According to a technical solution provided by an embodiment of the present invention, a first pixel circuit 11 provided in a display area is used to drive a light-emitting element to emit light, and at least n rows of first pixel circuits 11 perform threshold voltage compensation simultaneously. By providing multiple rows of second pixel circuits 21 in a non-display area, a corresponding pixel circuit row exists in front of the first row Row1 first pixel circuit 11 and / or behind the last row of first pixel circuits 11. When threshold voltage compensation is performed on the first row Row1 first pixel circuit 11 and / or the last row of first pixel circuits 11, the pixel circuit rows that are compensated simultaneously with the first row Row1 first pixel circuit 11 and / or the last row of first pixel circuits 11 are padded to n rows or close to n rows, thereby compensating for the compensation current of the first row Row1 first pixel circuit 11 and / or the last row of first pixel circuits 11, thereby making the compensation current corresponding to the first row Row1 first pixel circuit 11 and / or the last row of first pixel circuits 11 consistent with the compensation current corresponding to the first pixel circuits 11 in other intermediate rows, thereby making the threshold voltage compensation effect of the first pixel circuits 11 in each row in the display area AA consistent, thereby avoiding the problem of display abnormality of the first row of pixels in the display area AA. In addition, since the number of transistors in the second pixel circuit 21 is smaller than the number of transistors in the first pixel circuit 11, it is beneficial to reduce the space occupied by the second pixel circuit 21, thereby helping to reduce the width of the non-display area and reduce the impact on the frame of the display panel.

[0084] Optionally, x is equal to na, and / or y is equal to nb, so that the pixel circuit rows that are compensated simultaneously for the first row Row1 first pixel circuit 11 and / or the last row first pixel circuit 11 are padded to n rows to eliminate the differences in the compensation currents corresponding to the first pixel circuits 11 in each row.

[0085] Continue to refer Figure 2 and Figure 3 Optionally, in this embodiment, at least n-1 rows of second pixel circuits 21 are arranged in the non-display area NA close to the side of the first row Row1 first pixel circuit 11, and at least n-1 rows of second pixel circuits 21 are arranged in the non-display area NA close to the side of the last row of first pixel circuits 11.

[0086] Optionally, t is equal to 2n-2. n-1 rows of second pixel circuits 21 are provided in the non-display area NA near the side of the first row of first pixel circuits 11, and n-1 rows of second pixel circuits 21 are provided in the non-display area NA near the side of the last row of first pixel circuits 11, so as to ensure that the first and last rows of first pixel circuits 11 are simultaneously compensated for threshold voltages by n-1 rows of pixel circuits.

[0087] Each row of second pixel circuits 21 is disposed in the non-display area NA. To meet the compensation requirements of the first and last rows of first pixel circuits 11, the minimum number of rows of second pixel circuits 21 required can be flexibly set based on the number of rows of first pixel circuits 11 in the display area AA that simultaneously undergo threshold voltage compensation. For example, if five rows of first pixel circuits 11 undergo simultaneous threshold voltage compensation, at least four rows of second pixel circuits 21 must be added to the first and last rows of first pixel circuits 11 to ensure that five rows of pixel circuits undergo simultaneous threshold voltage compensation during the compensation process, including the first row of Row 1 and the last row of first pixel circuits 11.

[0088] Of course, in other embodiments, according to the requirements of image processing quality, stability, reliability, etc., more than 4 rows of second pixel circuits 21 can be added to realize redundant pixels, and the timing can be controlled so that only 5 rows of pixel circuits perform the threshold voltage compensation process at the same time.

[0089] The structure of the second pixel circuit 21 in FIG4 is introduced below. By optimizing the structure of the second pixel circuit 21 , the non-display area NA is minimally increased, thereby reducing the impact of the second pixel circuit 21 on the frame of the display panel.

[0090] In an optional implementation provided in this embodiment, Figure 4 A schematic diagram of the structure of a second pixel circuit provided by an embodiment of the present invention, referring to Figure 4 On the basis of the above embodiments, optionally, the second pixel circuit 21 includes a first driving module 101, a first initialization module 102, a first compensation module 103 and a first storage module 104; a first end of the first initialization module 104 is connected to the first initialization signal line RE1, a second end of the first initialization module 102 is connected to the control end of the first driving module 101, and the control end of the first initialization module 102 is connected to the first scan line, the first scan line is used to transmit the first scan signal S1, and the first initialization module 102 is used to increase the first initialization voltage vref on the first initialization signal line RE1 during the initialization phase. 1 is transmitted to the control end of the first driving module 101, and the first storage module 104 is connected between the control end and the first end of the first driving module 101; the first end of the first driving module 101 is connected to the first power line L1, the second end of the first driving module 101 is connected to the first end of the first compensation module 103, the second end of the first compensation module 103 is connected to the control end of the first driving module 101, the control end of the first compensation module 103 is connected to the second scan line, the second scan line is used to transmit the second scan signal S2, and the first compensation module 103 is used to compensate for the threshold voltage of the first driving module 101 in the threshold voltage compensation stage.

[0091] The first driving module 101 is not connected to the light emitting element. Therefore, the second pixel circuit 21 does not need to be written with data and is only used to achieve threshold voltage compensation. Therefore, the number of modules in the second pixel circuit 21 can be reduced.

[0092] Figure 5 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention, specifically Figure 4 The second pixel circuit shown is refined into a device structure, referring to Figure 4 and Figure 5 The first driving module 101 includes a first transistor M1, the first compensation module 103 includes a second transistor M2, the first initialization module 102 includes a third transistor M3, and the first storage module 104 includes a first storage capacitor C1; a first electrode of the first transistor M1 is connected to the first power line L1, a second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, a second electrode of the second transistor M2 is connected to the gate of the first transistor M1, and the gate of the second transistor M2 is connected to the second scan line, a first electrode of the third transistor M3 is connected to the first initialization signal line RE1, a second electrode of the third transistor M3 is connected to the gate of the first transistor M1, and the gate of the third transistor M3 is connected to the first scan line; a first electrode of the first storage capacitor C1 is connected to the gate of the first transistor M1, and a second electrode of the first storage capacitor C1 is connected to the first electrode of the first transistor M1.

[0093] Figure 6 A driving timing diagram of a second pixel circuit provided in an embodiment of the present invention can be applied to Figure 5 The second pixel circuit 21 shown, wherein Figure 5 The first transistor M1, the second transistor M2 and the third transistor M3 in the second pixel circuit 21 are all P-type transistors. The first electrode of the first transistor M1 is the source electrode, and the second electrode is the drain electrode. The first transistor (driving transistor) M1 is a diode connection mode. Based on the above embodiments, combined with Figure 5 and Figure 6 Taking a row of second pixel circuits 21 arranged close to the last row of first pixel circuits 11 as an example, the working process of the second pixel circuits 21 includes an initialization phase T1 and a threshold voltage compensation phase T2.

[0094] During the initialization phase T1, the first scan signal S1 is at a low level, the second scan signal S2 is at a high level, the third transistor M3 is turned on, and the second transistor M2 is turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 via the third transistor M3, initializing the gate of the first transistor M1 and turning on the first transistor M1.

[0095] During the threshold voltage compensation phase T2, the first scan signal S1 is at a high level, the second scan signal S2 is at a low level, the third transistor M3 is turned off, and the second transistor M2 is turned on. The first power supply voltage VDD transmitted on the first power line L1 charges the gate of the first transistor M1 via the first transistor M1 and the second transistor M2. When the gate voltage of the first transistor M1 reaches VDD + Vth1, the first transistor M1 is turned off, and the first storage capacitor C1 stores the gate voltage of the first transistor M1. Vth1 is the threshold voltage of the first transistor M1.

[0096] The on-time of the first compensation module 103 is equal to the row time of the n rows of first pixel circuits 11. That is, the duration of the threshold voltage compensation phase T2 is equal to the row time of the n rows of first pixel circuits 11, thereby improving the threshold voltage compensation rate.

[0097] In another optional implementation provided in this embodiment, Figure 7 This is a schematic diagram of the structure of another second pixel circuit provided by an embodiment of the present invention, referring to Figure 7 Based on the above embodiments, optionally, the second pixel circuit 21 includes a first driving module 101, a first initialization module 102, a first compensation module 103 and a first storage module 104; a first end of the first initialization module 102 is connected to the first initialization signal line RE1, a second end of the first initialization module 102 is connected to the control end of the first driving module 101, the control end of the first initialization module 102 is connected to the first scan line, and the first initialization module 102 is used to transmit the first initialization voltage Vref1 on the first initialization signal line RE1 to the control end of the first driving module 101 during the initialization phase; the first storage module 104 is connected between the control end and the second end of the first driving module 101; a first end of the first driving module 101 is connected to the first end of the first compensation module 101, a second end of the first driving module 101 is connected to the second power line L2, a second end of the first compensation module 103 is connected to the control end of the first driving module 101, the control end of the first compensation module 103 is connected to the second scan line, and the first compensation module 103 is used to compensate for the threshold voltage of the first driving module 101 during the threshold voltage compensation phase.

[0098] Figure 8 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention, specifically Figure 7 The second pixel circuit 21 is shown as a detailed device structure, referring to Figure 7 and Figure 8The first driving module 101 includes a first transistor M1, the first compensation module 103 includes a second transistor M2, the first initialization module 102 includes a third transistor M3, and the first storage module 104 includes a first storage capacitor C1; the first electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, the second electrode of the first transistor M1 is connected to the second power line L2, the second electrode of the second transistor M2 is connected to the gate of the first transistor M1, the gate of the second transistor M3 is connected to the second scan line, the first electrode of the third transistor M3 is connected to the first initialization signal line RE1, the second electrode of the third transistor M3 is connected to the gate of the first transistor M1, the gate of the third transistor M3 is connected to the first scan line, the first electrode of the first storage capacitor C1 is connected to the gate of the first transistor M1, and the second electrode of the first storage capacitor C1 is connected to the second electrode of the first transistor M1. Figure 8 The first transistor M1 of the second pixel circuit 21 is also connected in a diode manner. Figure 6 The difference between the structures shown is that the first transistor M1 , the second transistor M2 and the third transistor M3 are all N-type transistors, the first electrode of the first transistor M1 is a drain, and the second electrode is a source.

[0099] Figure 9 Another driving timing diagram of the second pixel circuit provided in an embodiment of the present invention can be applied to Figure 8 The second pixel circuit 21 shown in FIG. Figure 8 and Figure 9 The working process of the second pixel circuit 21 provided in this embodiment includes: an initialization stage T1 and a threshold voltage compensation stage T2.

[0100] During the initialization phase T1, the first scan signal S1 is at a high level, the second scan signal S2 is at a low level, the third transistor M3 is turned on, and the second transistor M2 is turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 via the third transistor M3, initializing the gate of the first transistor M1 and turning on the first transistor M1.

[0101] During the threshold voltage compensation phase T2, the first scan signal S1 is at a low level, the second scan signal S2 is at a high level, the third transistor M3 is turned off, and the second transistor M2 is turned on. The gate voltage of the first transistor M1 is discharged through the second transistor M2, the first transistor M1, and the second power line L2. When the gate voltage of the first transistor M1 reaches V2+Vth1, the first transistor M1 is turned off, and the first storage capacitor C1 stores the gate voltage of the first transistor M1. Vth1 is the threshold voltage of the first transistor M1, and V2 is the second power supply voltage transmitted on the second power line. V2 can be less than the first initialization voltage Vref1.

[0102] The on-time of the first compensation module 103 is equal to the row time of the n rows of first pixel circuits 11. That is, the duration of the threshold voltage compensation phase T2 is equal to the row time of the n rows of first pixel circuits 11, thereby improving the threshold voltage compensation rate.

[0103] In another optional implementation provided in this embodiment, Figure 10 This is a schematic diagram of the structure of another second pixel circuit provided by an embodiment of the present invention, referring to Figure 10 Optionally, the second pixel circuit 21 includes a first driving module 101, a first initialization module 102, a first compensation module 103, an auxiliary module 105 and a first storage module 104; a first end of the first initialization module 102 is connected to the first initialization signal line RE1, a second end of the first initialization module 102 is connected to the control end of the first driving module 101, the control end of the first initialization module 102 is connected to the first scan line, the first initialization module 102 is used to respond to the first scan signal S1 on the first scan line during the initialization phase, and transmit the first initialization voltage Vref1 on the first initialization signal line RE1 to the control end of the first driving module 101, and the first storage module 104 is used to transmit the first initialization voltage Vref1 on the first initialization signal line RE1 to the control end of the first driving module 101. The module 104 is connected between the control end and the first end of the first driving module 101; the first end of the first driving module 101 is connected to the first power line L1 via the auxiliary module 105, the second end of the first driving module 101 is connected to the first end of the first compensation module 103, the second end of the first compensation module 103 is connected to the second power line L2, the control end of the first compensation module 103 is connected to the second scan line, and the first compensation module 103 is configured to be turned on in response to the second scan signal S2 on the second scan line during the threshold voltage compensation stage to compensate for the threshold voltage of the first driving module 101. The control end of the auxiliary module 105 is connected to the third scan line to respond to the third scan signal on the second scan line.

[0104] Figure 11 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention, specifically Figure 10 The second pixel circuit shown is a schematic diagram of a specific device structure, refer to Figure 11The first driving module 101 includes a first transistor M1, the first compensation module 103 includes a second transistor M2, the first initialization module 102 includes a third transistor M3, the auxiliary module 105 includes a fourth transistor M4, and the first storage module 104 includes a first storage capacitor C1; the first electrode of the first transistor M1 is connected to the second electrode of the fourth transistor M4, the first electrode of the fourth transistor M4 is connected to the first power line L1, the gate of the fourth transistor M4 is connected to the third scan line, the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, the second electrode of the second transistor M2 is connected to the second power line L2, the gate of the second transistor M2 is connected to the second scan line, the first electrode of the third transistor M3 is connected to the first initialization signal line RE1, the second electrode of the third transistor M3 is connected to the gate of the first transistor M1, and the gate of the third transistor M3 is connected to the first scan line; the first electrode of the first storage capacitor C1 is connected to the gate of the first transistor M1, and the second electrode of the first storage capacitor C1 is connected to the first electrode of the first transistor M1. Here, the first transistor M1, the second transistor M2, and the third transistor M3 are all P-type transistors, the first electrode of the first transistor M1 is the source, and the second electrode is the drain.

[0105] Figure 12 Another driving timing diagram of the second pixel circuit provided in an embodiment of the present invention can be applied to Figure 11 The second pixel circuit 21 shown in FIG. Figure 11 and Figure 12 The working process of the second pixel circuit 21 includes an initialization phase T1 and a threshold voltage compensation phase T2.

[0106] During the initialization phase T1, the first scan signal S1 is at a low level, the second scan signal S2 is at a high level, and the third scan signal S3 is at a low level. The fourth transistor M4 and the third transistor M3 are turned on, and the second transistor M2 is turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 via the third transistor M3, initializing the gate of the first transistor M1 and turning on the first transistor M1. Simultaneously, the first power supply voltage VDD on the first power line L1 is transmitted to the first electrode of the first transistor M1 via the fourth transistor M4, initializing the first electrode of the first transistor M1.

[0107] During the threshold voltage compensation phase T2, the first scan signal S1 is at a low level, the second scan signal S2 is at a low level, and the third scan signal S3 is at a high level. The second transistor M2 and the third transistor M3 are turned on, and the fourth transistor M4 is turned off. The first initialization voltage Vref1 continuously supplies power to the gate of the first transistor M1. The voltage at the first electrode of the first transistor M1 is discharged through the first transistor M1 and the second transistor M2. When the voltage at the first electrode of the first transistor M1 reaches Vref1 + Vth1, the first transistor M1 is turned off, achieving threshold voltage compensation. The first storage capacitor C1 stores the gate voltage of the first transistor M1. Wherein, Vth1 is the threshold voltage of the first transistor M1.

[0108] The on-time of the first compensation module 103 is equal to the row time of the n rows of first pixel circuits 11. That is, the duration of the threshold voltage compensation phase T2 is equal to the row time of the n rows of first pixel circuits 11, thereby improving the threshold voltage compensation rate.

[0109] In another optional implementation provided in this embodiment, Figure 13 This is a schematic structural diagram of another second pixel circuit provided in an embodiment of the present invention, referring to Figure 13 Optionally, the second pixel circuit 21 includes a first driving module 101, a first initialization module 102, a first compensation module 103, an auxiliary module 105 and a first storage module 104; a first end of the first initialization module 102 is connected to the first initialization signal line RE1, a second end of the first initialization module 102 is connected to the control end of the first driving module 101, and the control end of the first initialization module 102 is connected to the first scan line. The first initialization module 101 is configured to respond to the first scan signal S1 on the first scan line during the initialization phase and turn on, transmitting the first initialization voltage Vref1 on the first initialization signal line RE1 to the first driving module The first storage module 104 is connected between the control end and the second end of the first driving module 101; the first end of the first driving module 101 is connected to the first power line L1 via the first compensation module 103, the second end of the first driving module 101 is connected to the first end of the auxiliary module 105, the second end of the auxiliary module 105 is connected to the second power line L2, the control end of the first compensation module 103 is connected to the third scan line, the first compensation module 103 is used to compensate for the threshold voltage of the first driving module 101 in response to the third scan signal S3 on the third scan line during the threshold voltage compensation stage, and the control end of the auxiliary module 105 is connected to the second scan line.

[0110] Figure 14 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention, specifically Figure 13 The second pixel circuit shown is a schematic diagram of a device structure, referring to Figure 14The first driving module 101 includes a first transistor M1, the first compensation module 103 includes a second transistor M2, the first initialization module 102 includes a third transistor M3, the auxiliary module 105 includes a fourth transistor M4, and the first storage module 104 includes a first storage capacitor C1; a first electrode of the first transistor M1 is connected to the second electrode of the second transistor M2, a first electrode of the second transistor M2 is connected to the first power line L1, a gate of the second transistor M2 is connected to the third scan line, a second electrode of the first transistor M1 is connected to the first electrode of the fourth transistor M4, a second electrode of the fourth transistor M4 is connected to the second power line L2, a gate of the fourth transistor M4 is connected to the second scan line, a first electrode of the third transistor M3 is connected to the first initialization signal line RE1, a second electrode of the third transistor M3 is connected to the gate of the first transistor M1, and the gate of the third transistor M3 is connected to the first scan line; a first electrode of the first storage capacitor C1 is connected to the gate of the first transistor M1, and a second electrode of the first storage capacitor C1 is connected to the second electrode of the first transistor M1.

[0111] in, Figure 14 The second pixel circuit 21 and Figure 11 The first transistor M1 in the second pixel circuit 21 is connected in a source-follower manner, and only the channel type and connection relationship of the transistor are different. The number of transistors included in the two is the same. In this embodiment, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all N-type transistors.

[0112] Figure 15 Another driving timing diagram of the second pixel circuit provided in an embodiment of the present invention can be applied to Figure 14 The second pixel circuit 21 shown, referring to Figure 14 and Figure 15 The working process of the second pixel circuit 21 provided in this embodiment includes: an initialization stage T1 and a threshold voltage compensation stage T2.

[0113] During the initialization phase T1, the first scan signal S1 is at a high level, the second scan signal S2 is at a high level, and the third scan signal S3 is at a low level. The third transistor M3 and the fourth transistor M4 are turned on, and the second transistor M2 is turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 via the third transistor M3, initializing the gate of the first transistor M1 and turning on the first transistor M1. At the same time, the second power supply voltage V2 is transmitted to the second electrode of the first transistor M1 via the fourth transistor M4, initializing the second electrode of the first transistor M1.

[0114] During the threshold voltage compensation phase T2, the first scan signal S1 is at a high level, the second scan signal S2 is at a low level, and the third scan signal S3 is at a high level. The second transistor M2 and the third transistor M3 are turned on, and the fourth transistor M4 is turned off. The first initialization voltage Vref1 continuously supplies power to the gate of the first transistor M1. The voltage at the second electrode of the first transistor M1 leaks through the fourth transistor M4. When the voltage at the second electrode of the first transistor M1 reaches Vref1 + Vth1, the first transistor M1 is turned off, achieving threshold voltage compensation. The first storage capacitor C1 stores the gate voltage of the first transistor M1. Wherein, Vth1 is the threshold voltage of the first transistor M1.

[0115] The on-time of the first compensation module 103 is equal to the row time of the n rows of first pixel circuits 11. That is, the duration of the threshold voltage compensation phase T2 is equal to the row time of the n rows of first pixel circuits 11, thereby improving the threshold voltage compensation rate.

[0116] In the above-mentioned four structures and driving timings of the second pixel circuit 21, Sn-last Row is the control signal for controlling the compensation transistor in the first pixel circuit 11 in the last row. The second scanning signal S2 or the third scanning signal S3 (the scanning signal connected to the second transistor M2) corresponding to the row can be obtained by shifting Sn-last Row.

[0117] In this embodiment, the second pixel circuit 21 includes at most four transistors and one first storage capacitor, which can greatly reduce the space added to the non-display area NA and help reduce the impact on the frame.

[0118] In the actual design process, any one of the four structures of the second pixel circuit 21 can be selected according to specific needs. The following description will take the connection structure of the N-type transistor source follower as an example. Figure 16 A schematic diagram of a second pixel circuit arrangement according to an embodiment of the present invention is provided. Figure 16 The display area AA includes a plurality of pixel units arranged in an array. Each pixel unit includes a plurality of sub-pixels, for example, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Each sub-pixel corresponds to a first pixel circuit 11. That is, three first pixel circuits 11 are provided under each pixel unit. In the non-display area, only one second pixel circuit 21, three second pixel circuits 21, or two second pixel circuits 21 may be provided under each pixel unit.

[0119] Specifically, since the second pixel circuits 21 are used to compensate for the compensation current of the first and last rows of the first pixel circuits 11, as long as the second pixel circuits 21 in each row can generate the required compensation current value, the uniformity of the compensation current of each row of pixel circuits (including the first pixel circuits 11 and the second pixel circuits 21) can be guaranteed. Therefore, the number of second pixel circuits 21 in a row can be less than the number of first pixel circuits 11 in a row (e.g. Figure 16 As shown), the space occupied by the second pixel circuit 21 is reduced. Even if the threshold voltage compensation time is too long, the width of the non-display area NA can be effectively reduced by reducing the number of second pixel circuits 21 and the number of transistors inside the second pixel circuit 21, thereby reducing the impact on the border of the display panel.

[0120] Of course, in other embodiments, the number of second pixel circuits 21 in a row may also be equal to the number of first pixel circuits 11 in a row.

[0121] Optionally, in this embodiment, in the second pixel circuits 21 in the same row, the second pixel circuits 21 share the same first initialization module 102 and first storage module 104 . Figure 17 A structural diagram of another arrangement of the second pixel circuit provided by an embodiment of the present invention, referring to Figure 14 and Figure 17 Taking the second pixel circuit 21 as an example of the fourth structure, the third transistor M3 included in the first initialization module 102 and the first storage capacitor C1 included in the first storage module 104 are pulled out and installed at the location of the second pixel circuit 21 in the first or last column. The second pixel circuits 21 in other columns share the same third transistor M3 and first storage capacitor C1 with the first or last column of second pixel circuits 21. In this way, the number of transistors and storage capacitors in some second pixel circuits 21 can be further reduced, thereby further reducing the space occupied by the second pixel circuit 21, and further reducing the increase in frame size caused by the addition of the second pixel circuit 21.

[0122] In extreme cases, the first initialization module 102, the first compensation module 103, the auxiliary module 105 and the first storage module 104 in the second pixel circuit 21 can all be pulled out, so that except for the first or last column of second pixel circuits 21, the second pixel circuits 21 in other columns only include the first driving module 101, and the other modules are shared with the first or last column of second pixel circuits 21, so as to minimize the increase in the space outside the display area AA, that is, to minimize the increase in the border size.

[0123] Optionally, in Figure 17In the structure shown, since multiple second pixel circuits 21 in the same row share the same third transistor M3 (first initialization module 102), in order to ensure that the first transistors M1 of the entire row are smoothly turned on, the third transistor M3 and / or the first storage capacitor C1 can be optimized to increase the driving capability of the third transistor M3 and the storage capacity of the first storage capacitor C1, thereby meeting the timing matching requirements.

[0124] Optionally, this embodiment further provides a structure of a first pixel circuit 11, Figure 18 A schematic structural diagram of a first pixel circuit provided by an embodiment of the present invention, referring to Figure 18 Based on the above embodiments, optionally, the first pixel circuit 11 includes a second driving module 111, a data writing module 112, a second compensation module 113, a second storage module 115, a third storage module 116, a second initialization module 114, a third initialization module 117, and a light-emitting module 121. The second driving module 11 and the light-emitting module 121 are connected between the third power line L3 and the fourth power line L4. The data writing module 112 is connected between the data line and the first end of the second storage module 115. The control end of the data writing module 112 is connected to the fourth scan line. The second end of the second storage module 115 is connected to the control end of the second driving module 111. The third storage module 116 is connected between the first end of the second driving module 11 and the first end of the second storage module 115.

[0125] The second compensation module 113 is connected between the second end and the control end of the second driving module 111. The control end of the second compensation module 113 is connected to the fifth scan line. The second compensation module 113 is used to compensate for the threshold voltage of the second driving module 111 during the threshold voltage compensation stage; wherein, the conduction time of the second compensation module 113 is equal to the row time of the n rows of first pixel circuits 11.

[0126] The second initialization module 114 is connected between the second initialization signal line and the first end of the second storage module 115, and the control end of the second initialization module 114 is connected to the fifth scan line; the third initialization module 117 is connected between the third initialization signal line and the first end of the second driving module 111, and the control end of the third initialization module 117 is connected to the sixth scan line.

[0127] Optionally, the first pixel circuit 11 also includes a first light-emitting control module 118 and a second light-emitting control module 119, the first end of the first light-emitting control module 118 is connected to the third power line L3, the second end of the first light-emitting control module 118 is connected to the second end of the second driving module 111, the first end of the second light-emitting control module 119 is connected to the first end of the second driving module 111, the second end of the second light-emitting control module 119 is connected to the first end of the light-emitting module 121, and the second end of the light-emitting module 121 is connected to the fourth power line L4; the control end of the first light-emitting control module 118 is connected to the first light-emitting control signal line, and the control end of the second light-emitting control module 119 is connected to the second light-emitting control signal line.

[0128] The first pixel circuit 11 further includes a fourth initialization module 120 . The fourth initialization module 120 is connected between the fourth initialization signal line and the first end of the light emitting module 120 . A control end of the fourth initialization module 120 is connected to the sixth scan line.

[0129] Figure 19 A schematic structural diagram of another first pixel circuit provided by an embodiment of the present invention, specifically Figure 18 The first pixel circuit shown is a schematic diagram of a specific device structure, refer to Figure 18 and Figure 19 The first driving module 111 includes a driving transistor Q1, the second compensation module 113 includes a compensation transistor Q2, the data writing module 112 includes a data writing transistor Q3, the second initialization module 114 includes a second initialization transistor Q4, the first light-emitting control module 118 includes a first light-emitting control transistor Q5, the second light-emitting control module 119 includes a second light-emitting control transistor Q6, the third initialization module 117 includes a third initialization transistor Q7, the fourth initialization module 120 includes a fourth initialization transistor Q8, the light-emitting module 121 includes a light-emitting diode D1, the second storage module 115 includes a second storage capacitor C2, and the third storage module 116 includes a third storage capacitor C3.

[0130] The first light-emitting control transistor Q5, the driving transistor Q1, the second light-emitting control transistor Q6 and the light-emitting diode D1 are connected in series between the third power line L3 and the fourth power line L4. The gate of the first light-emitting control transistor Q5 is connected to the first light-emitting control signal line, and the gate of the second light-emitting control transistor Q6 is connected to the second light-emitting control signal line.

[0131] The compensation transistor Q2 is connected between the first electrode and the gate of the driving transistor Q1, and the gate of the compensation transistor Q2 is connected to the fifth scan line; the data writing transistor Q3 is connected between the data line and the first electrode of the second storage capacitor C2, and the gate of the data writing transistor Q3 is connected to the fourth scan line; the second electrode of the second storage capacitor C2 is connected to the gate of the driving transistor Q1; the third storage capacitor C3 is connected between the second electrode of the driving transistor Q1 and the first electrode of the second storage capacitor C2.

[0132] The second initialization transistor Q4 is connected between the second initialization signal line and the first electrode of the second storage capacitor C2, and the gate of the second initialization transistor Q4 is connected to the fifth scan line; the third initialization transistor Q7 is connected between the third initialization signal line and the second electrode of the driving transistor Q1, and the fourth initialization transistor Q8 is connected between the fourth initialization signal line and the first electrode of the light-emitting diode D1, and the gate of the third initialization transistor Q7 and the gate of the fourth initialization transistor Q8 are both connected to the sixth scan line.

[0133] Figure 20 A driving timing diagram of a first pixel circuit provided by an embodiment of the present invention, referring to Figure 19 and Figure 20 The operation process of the first pixel circuit 11 includes: an initialization phase t1, a threshold voltage compensation phase t2, a data writing phase t3, and a light emitting phase t4. The threshold voltage compensation phase t2 of at least the first and last rows of first pixel circuits 11 overlaps with the threshold voltage compensation phase T2 of the second pixel circuits 21 in time, and the threshold voltage compensation phase t2 of each row of first pixel circuits 11 is greater than a row time, for example, the sum of n row times, where n is an integer greater than 1.

[0134] Taking the case where all transistors are N-type transistors as an example, the specific working process of the first pixel circuit 11 is as follows:

[0135] During initialization phase t1, the fourth scan signal on the fourth scan line is low, the fifth scan signal on the fifth scan line is high, and the sixth scan signal on the sixth scan line is low. The first light control signal EM1 on the first light control signal line is high, and the second light control signal EM2 on the second light control signal line is low. Consequently, the compensation transistor Q2, the second initialization transistor Q4, and the first light control transistor Q5 are turned on. The second initialization voltage Vini1 on the second initialization signal line is transmitted to the first electrode of the second storage capacitor C2 via the second initialization transistor Q4. The third power supply voltage ELVDD on the third power line L3 is transmitted to the second electrode of the second storage capacitor C2 (i.e., the gate of the drive transistor Q1) via the first light control transistor Q5 and the compensation transistor Q2, thereby initializing the second storage capacitor C2. At this point, the potential at the second electrode of the drive transistor Q1 changes with the displayed grayscale of the previous frame. Since the gate of the drive transistor Q1 is reset to the high potential of the third power supply voltage ELVDD, the drive transistor Q1 is turned on.

[0136] During threshold voltage compensation phase t2, the fourth scan signal on the fourth scan line is low, the fifth scan signal on the fifth scan line is high, and the sixth scan signal on the sixth scan line is high. The first light-emission control signal EM1 on the first light-emission control signal line is low, and the second light-emission control signal EM2 on the second light-emission control signal line is low. Consequently, the compensation transistor Q2, the second initialization transistor Q4, the third initialization transistor Q7, and the fourth initialization transistor Q8 are turned on. The second electrode of the drive transistor Q1 is reset to the third initialization voltage VEH on the third initialization signal line, and the first electrode of the light-emitting diode D1 is reset to the fourth initialization voltage Vini2 on the fourth initialization signal line. The compensation transistor Q2 remains on, and the drive transistor Q1 maintains a diode connection. The gate of the drive transistor Q1 discharges through the compensation transistor Q2 and the third initialization transistor Q7 until the gate of the drive transistor Q1 reaches VEH + VTH1. At this point, the drive transistor Q1 turns off, and compensation ends. VTH1 is the threshold voltage of the drive transistor Q1.

[0137] The duration of the threshold voltage compensation phase t2 is greater than the row time, and there is a situation where multiple rows of first pixel circuits 11 are compensated simultaneously. In this embodiment, by providing multiple rows of second pixel circuits 21 in the non-display area, corresponding pixel circuit rows exist before the first pixel circuit 11 in the first row and / or after the first pixel circuit 11 in the last row. When the first pixel circuit 11 in the first row and / or the last pixel circuit 11 in the last row are compensated, the pixel circuit rows that are compensated simultaneously with the first pixel circuit 11 in the first row and / or the last pixel circuit 11 are padded to n rows, thereby compensating the compensation current of the first pixel circuit 11 in the first row and / or the last pixel circuit 11. This ensures that the compensation current corresponding to the first pixel circuit 11 in the first row and / or the last pixel circuit 11 is consistent with the compensation current corresponding to the first pixel circuit 11 in the other intermediate rows, thereby achieving consistent threshold voltage compensation effects for the first pixel circuits 11 in each row of the display area AA, thereby avoiding display abnormalities in the first row of pixels in the display area AA.

[0138] Optionally, the fourth initialization signal line may be multiplexed as the third initialization signal line to reduce the number of signal lines.

[0139] In the data writing phase t3, the fourth scan signal on the fourth scan line is high, the fifth scan signal on the fifth scan line is low, the sixth scan signal on the sixth scan line is high, the first light control signal EM1 on the first light control signal line is low, and the second light control signal EM2 on the second light control signal line is low. Therefore, the data writing transistor Q3, the third initialization transistor Q7, and the fourth initialization transistor Q8 are turned on, and the first electrode of the second storage capacitor C2 jumps from the second initialization voltage Vini1 to the data voltage Vdata. Under the coupling effect of the second storage capacitor C2, the gate voltage of the driving transistor Q1 changes by k*(Vdata-Vini1), where k=c2 / (c2+c0), c2 is the capacitance of the second storage capacitor C2, and C0 is other capacitance (e.g., coupling capacitance) on the gate of the driving transistor Q1. At this time, the gate voltage of the driving transistor Q1 becomes VEH+VTH1+k*(Vdata-Vini1), and the voltage at the second electrode of the driving transistor Q1 remains at the third initialization voltage VEH.

[0140] During light-emitting phase t4, the fourth scan signal on the fourth scan line is low, the fifth scan signal on the fifth scan line is low, and the sixth scan signal on the sixth scan line is low. The first light-emission control signal EM1 on the first light-emission control signal line is high, and the second light-emission control signal EM2 on the second light-emission control signal line is high. Consequently, the first light-emission control transistor Q5 and the second light-emission control transistor Q6 are turned on, forming a current loop between the third power line L3 and the fourth power line L4. The driver transistor Q1 generates a drive current I, which drives the light-emitting diode D1 to emit light. At this time, the voltage at the first electrode of the light-emitting diode D1 changes from Vini2 to ELVSS+VD1. When the fourth initialization voltage Vini2 is reused as the third initialization voltage VEH, that is, VEH=Vini2, the voltage at the second electrode of the driving transistor Q1 also changes from Vini2 to ELVSS+VD1. According to the principle that the voltage difference across the capacitor remains unchanged, the gate voltage of the driving transistor Q1 becomes VEH+VTH1+k*(Vdata-Vini1)+k*(ELVSS+VD1-Vini2)=Vini2+VTH1+k*(Vdata-Vini1)+k*(ELVSS+VD1-Vini2). Ignoring other capacitances at the gate of the driving transistor Q1, when k is equal to 1 or approximately equal to 1, the above formula becomes VTH1+Vdata-Vini1+ELVSS+VD1, that is, the gate voltage of the driving transistor Q1 is VTH1+Vdata-Vini1+ELVSS+VD1.

[0141] Among them, the driving current I can be expressed as:

[0142]

[0143] Wherein, μ is the electron mobility of the driving transistor Q1, Cox is the channel capacitance per unit area of ​​the driving transistor Q1, W / L is the width-to-length ratio of the driving transistor Q1, VTH1 is the threshold voltage of the driving transistor Q1, and VD1 is the voltage drop of the light-emitting diode D1.

[0144] The third power line L3 connected to the first pixel circuit 11 provided in this embodiment can be reused as the first power line L1 connected to the second pixel circuit 21, and the fourth power line L4 can also be reused as the second power line L2. Of course, there can also be four independent power lines.

[0145] Optionally, an embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. Figure 21This is a structural schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device 200 can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals and other products. The embodiment of the present invention does not specifically limit this.

[0146] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0147] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: The display panel has a display area and a non-display area arranged around the display area, and the display panel includes: a plurality of first pixel circuits, the plurality of first pixel circuits being located in the display area and arranged in an array of m rows, each of the first pixel circuits being connected to a light-emitting element, the first pixel circuit being configured to drive the light-emitting element to emit light; wherein at least n rows of the first pixel circuits simultaneously perform threshold voltage compensation, where m and n are both positive integers greater than 1, and m is greater than n; a plurality of second pixel circuits, the plurality of second pixel circuits being located in the non-display area and arranged in an array of t rows, the second pixel circuits being configured to configure the second pixel circuits in row x to perform threshold voltage compensation when the first pixel circuits in the preceding row a perform threshold voltage compensation, and / or being configured to configure the second pixel circuits in row y to perform threshold voltage compensation when the first pixel circuits in the following row b perform threshold voltage compensation, wherein t, a, x, b, and y are all positive integers greater than 1, x and y are both not greater than t, and a+x and b+y are both not greater than n; wherein the number of transistors in the second pixel circuit is less than the number of transistors in the first pixel circuit; x is equal to na, and / or, y is equal to nb; t is equal to 2n-2, wherein n-1 rows of the second pixel circuits are provided in the non-display area close to the first row of the first pixel circuits, and n-1 rows of the second pixel circuits are provided in the non-display area close to the last row of the first pixel circuits; The number of the second pixel circuits in one row is less than or equal to the number of the first pixel circuits in one row.

2. The display panel according to claim 1, wherein: The second pixel circuit includes a first driving module, a first initialization module, a first compensation module and a first storage module; A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the first end of the first driving module; A first end of the first driving module is connected to a first power line, a second end of the first driving module is connected to a first end of the first compensation module, a second end of the first compensation module is connected to a control end of the first driving module, the control end of the first compensation module is connected to a second scan line, and the first compensation module is used to compensate for the threshold voltage of the first driving module in a threshold voltage compensation stage.

3. The display panel according to claim 2, wherein: The first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the first power line, the second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to the gate of the first transistor, and the gate of the second transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the first electrode of the first transistor.

4. The display panel according to claim 3, wherein: The first transistor, the second transistor, and the third transistor are all P-type transistors.

5. The display panel according to claim 1, wherein: The second pixel circuit includes a first driving module, a first initialization module, a first compensation module and a first storage module; A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, and the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase; and the first storage module is connected between the control end and the second end of the first driving module. A first end of the first driving module is connected to a first end of the first compensation module, a second end of the first driving module is connected to a second power line, a second end of the first compensation module is connected to a control end of the first driving module, and the control end of the first compensation module is connected to a second scan line. The first compensation module is used to compensate for the threshold voltage of the first driving module in a threshold voltage compensation stage.

6. The display panel according to claim 5, wherein: The first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the first transistor is connected to the second power line, the second electrode of the second transistor is connected to the gate of the first transistor, the gate of the second transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, the gate of the third transistor is connected to the first scan line, the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the second electrode of the first transistor.

7. The display panel according to claim 6, wherein: The first transistor, the second transistor and the third transistor are all N-type transistors.

8. The display panel according to claim 1, wherein: The second pixel circuit includes a first driving module, a first initialization module, a first compensation module, an auxiliary module and a first storage module; A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the first end of the first driving module; A first end of the first driving module is connected to a first power line via the auxiliary module, a second end of the first driving module is connected to a first end of the first compensation module, a second end of the first compensation module is connected to a second power line, a control end of the first compensation module is connected to a second scan line, the first compensation module is used to compensate for the threshold voltage of the first driving module in a threshold voltage compensation stage, and the control end of the auxiliary module is connected to a third scan line.

9. The display panel according to claim 8, wherein: The first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, the auxiliary module includes a fourth transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the second electrode of the fourth transistor, the first electrode of the fourth transistor is connected to the first power line, the gate of the fourth transistor is connected to the third scan line, the second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to the second power line, the gate of the second transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the first electrode of the first transistor.

10. The display panel according to claim 9, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are all P-type transistors.

11. The display panel according to claim 1, wherein The second pixel circuit includes a first driving module, a first initialization module, a first compensation module, an auxiliary module and a first storage module; A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the second end of the first driving module; A first end of the first driving module is connected to a first power line via the first compensation module, a second end of the first driving module is connected to a first end of the auxiliary module, a second end of the auxiliary module is connected to a second power line, a control end of the first compensation module is connected to a third scan line, the first compensation module is used to compensate for the threshold voltage of the first driving module in a threshold voltage compensation stage, and the control end of the auxiliary module is connected to the second scan line.

12. The display panel according to claim 11, wherein: The first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, the auxiliary module includes a fourth transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the gate of the second transistor is connected to the third scan line, the second electrode of the first transistor is connected to the first electrode of the fourth transistor, the second electrode of the fourth transistor is connected to the second power line, the gate of the fourth transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the second electrode of the first transistor.

13. The display panel according to claim 12, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are all N-type transistors.

14. The display panel according to any one of claims 2 to 13, wherein: The conduction time of the first compensation module is equal to the row time of n rows of the first pixel circuits.

15. The display panel according to any one of claims 2 to 13, characterized in that: In the same row of the second pixel circuits, the second pixel circuits share the same first initialization module and the first storage module.

16. The display panel according to claim 15, wherein: The first initialization module and the first storage module in the second pixel circuits of each row are arranged at the position of the second pixel circuits in the first column or the last column.

17. The display panel according to claim 16, wherein: In the same row of the second pixel circuits, the second pixel circuits share the same first compensation module.

18. The display panel according to claim 1, wherein The first pixel circuit includes a second driving module, a data writing module, a second compensation module, a second storage module, a third storage module, a second initialization module, a third initialization module and a light emitting module; The second driving module and the light emitting module are connected between a third power line and a fourth power line, the data writing module is connected between the data line and the first end of the second storage module, the control end of the data writing module is connected to the fourth scan line, the second end of the second storage module is connected to the control end of the second driving module, and the third storage module is connected between the first end of the second driving module and the first end of the second storage module; The second compensation module is connected between the second terminal and the control terminal of the second driving module, the control terminal of the second compensation module is connected to the fifth scan line, and the second compensation module is used to compensate for the threshold voltage of the second driving module in the threshold voltage compensation stage; The second initialization module is connected between the second initialization signal line and the first end of the second storage module, and the control end of the second initialization module is connected to the fifth scan line; The third initialization module is connected between the third initialization signal line and the first end of the second driving module, and the control end of the third initialization module is connected to the sixth scan line.

19. The display panel according to claim 18, wherein: The conduction time of the second compensation module is equal to the row time of n rows of the first pixel circuits.

20. The display panel according to claim 19, wherein The first pixel circuit also includes a first light-emitting control module and a second light-emitting control module, wherein the first end of the first light-emitting control module is connected to the third power line, the second end of the first light-emitting control module is connected to the second end of the second driving module, the first end of the second light-emitting control module is connected to the first end of the second driving module, the second end of the second light-emitting control module is connected to the first end of the light-emitting module, and the second end of the light-emitting module is connected to the fourth power line; the control end of the first light-emitting control module is connected to the first light-emitting control signal line, and the control end of the second light-emitting control module is connected to the second light-emitting control signal line.

21. The display panel according to claim 20, wherein: The first pixel circuit further includes a fourth initialization module connected between a fourth initialization signal line and the first end of the light emitting module, and a control end of the fourth initialization module is connected to the sixth scan line.

22. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 21.

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