Pixel circuit driving method, device and equipment

Abstract

The invention discloses a driving method, device and equipment of a pixel circuit, relates to the technical field of display, and can solve the problems that in the picture display process, the brightness difference amplitude of a non-light-emitting stage and a light-emitting stage is too large, the non-light-emitting time is too long, and the flicker feeling is too strong due to non-light-emitting or weak light-emitting in a part of periods. According to the invention, the duration of each level stage in each control period can be flexibly and non-uniformly configured in duty ratio, for example, the duration of one or more level stages for light emission after anode resetting is flexibly configured according to whether each control period is used for anode resetting or not; or differential driving of a level stage which is not used for light emitting is carried out in a refresh frame period and a holding frame period based on different reset frequencies and / or different display refresh rates, so that on the premise of ensuring that pixels can normally emit light in each control period, light emitting of multiple control periods is uniform, or a light emitting duty ratio is improved to optimize screen flash, and the display quality of the display device is improved. And better display and eye protection effects are realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving method, device and equipment for a pixel circuit. Background Art

[0002] At present, when displaying images, the display screens of electronic devices often use dimming strategies such as pulse width modulation (PWM) and direct current (DC) modulation to achieve better display effects and improve user visual experience. For example, conventional technologies usually control the error of the luminous duration in each luminous cycle in the picture frame to be within a certain range to achieve consistency of the luminous cycle, thereby improving the user visual experience.

[0003] However, since the display screen usually also includes other devices such as field-induced luminescence (electroluminance, EL) devices and pixel circuit anodes, or data writing, anode reset, gate reset and other operations are required in some cycles, data writing, gate reset or EL device anode reset will compress the luminescence duration in one or more cycles, or cause part or all of the luminescence current in a certain cycle to be used for device (such as capacitor) charging instead of pixel luminescence, which will cause the brightness difference amplitude between the non-luminescent and luminescent stages in the picture display process to be too large, the non-luminescent time to be too long, and the flickering feeling to be too strong due to no luminescence or weak luminescence in some cycles. Summary of the invention

[0004] The present application provides a driving method, device and equipment for a pixel circuit, which can solve the problems of excessively large brightness difference amplitude between the non-luminous and luminous stages during the picture display process, too long non-luminous time, and excessive flickering caused by non-luminous or weak luminous in some cycles, thereby improving the visual experience of users during use.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, a driving method for a pixel circuit is provided, wherein a display cycle of the pixel circuit includes a plurality of consecutive control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a first control cycle, the first control cycle is used for anode reset, the pixel circuit includes a light emitting control circuit and an anode reset circuit, the anode reset circuit receives an anode reset control signal, and controls the anode reset according to the first control cycle, the method comprising: detecting a screen brightness value; when the screen brightness value is less than a first brightness threshold, configuring a duration of the second level stage in a plurality of control cycles according to the first control cycle; the light emitting control circuit receives a light emitting control signal, and controls the light emitting according to the duration of the first level stage and the duration of the second level stage in the plurality of control cycles.

[0007] Exemplarily, the above method can be applied to a display panel, a display screen, or an electronic device including a display screen, such as a mobile phone, a tablet computer, etc., without limitation.

[0008] Exemplarily, the first level stage of the control cycle is a high level stage, and the second level stage is a low level stage, or the first level stage is a low level stage, and the second level stage is a high level stage, without limitation.

[0009] The solution provided in the first aspect above can flexibly and non-uniformly configure the duty cycle of the level stage (such as the second level stage) used for luminescence in each control cycle according to actual conditions such as whether each control cycle is used for anode reset in scenarios where the brightness is less than the first brightness threshold, such as medium and low brightness scenarios. For example, the duration of one or more second level stages after the anode reset can be flexibly configured, so that the light emission of multiple control cycles is uniform while ensuring that the pixels can emit light normally in each control cycle, so as to optimize screen flicker and achieve better display and eye protection effects.

[0010] As a possible implementation, the above-mentioned multiple control cycles also include a second control cycle, wherein the second control cycle is not used for anode reset, and the above-mentioned configuration of the duration of the second level stage in multiple control cycles according to the first control cycle includes: configuring the duration of the second level stage in the above-mentioned first control cycle as the first duration, and configuring the duration of the second level stage in the second control cycle as the second duration, wherein the first duration is greater than the second duration. Based on this, the duration of the second level stage in the control cycle used for anode reset can be made greater than the duration of the second level stage in the control cycle not used for anode reset, while ensuring uniform light emission in multiple low-level stages of the same picture frame, and improving the applicability, compatibility and flexibility of the solution in different scenarios.

[0011] As a possible implementation, the first control cycle includes at least one second level stage, and the first duration includes the total duration of at least one second level stage in the first control cycle. Based on this, the duration of the second level stage in the control cycle for anode reset can be made longer than the duration of the second level stage in the control cycle not for anode reset in a variety of ways, such as lengthening the duration of the second level stage in the display drive cycle for anode reset compared to other cycles or increasing the number of second level stages in multiple display drive cycles for anode reset, while ensuring uniform light emission in multiple low-level stages of the same picture frame, the applicability, compatibility and flexibility of the solution in different scenarios are improved.

[0012] Exemplarily, the first control cycle includes a second level stage, and the duration of the second level stage in the first control cycle is greater than the duration of the second level stage in the second control cycle.

[0013] Or, exemplarily, the first control cycle includes multiple second level stages, and the sum of the durations of the multiple second level stages in the first control cycle (ie, the total duration) is greater than the duration of the second level stage in the second control cycle.

[0014] As a possible implementation, the above-mentioned multiple control cycles also include a third control cycle, wherein the third control cycle is a control cycle after the first control cycle, and the third control cycle is not used for anode reset. The above-mentioned configuration of the duration of the second level stage in the multiple control cycles according to the first control cycle includes: configuring the duration of the second level stage in the above-mentioned third control cycle to be a third duration, wherein the third duration is greater than the second duration. Based on this, the duration of the second level stage in the control cycle that is not used for anode reset of the picture frame can be flexibly adjusted according to actual conditions to perform luminous compensation, ensuring that the pixels can maintain normal luminescence in each control cycle, and making the luminescence amount of the pixels in each control cycle the same or close, thereby ensuring uniform luminescence in multiple low-level stages of the same picture frame.

[0015] As a possible implementation, the third control cycle includes at least one second level stage, and the third duration includes the total duration of at least one second level stage in the third control cycle. Based on this, a variety of methods can be used to ensure uniform light emission in multiple low-level stages of the same picture frame while improving the applicability, compatibility and flexibility of the solution in different scenarios.

[0016] As an example, the third duration is less than or equal to the first duration.

[0017] As a possible implementation, the first control cycle includes at least one control cycle; and / or, the second control cycle includes at least one control cycle; and / or, the third control cycle includes at least one control cycle. That is, there may be one or more first control cycles, one or more second control cycles, and one or more third control cycles. Based on this, when there are multiple first control cycles, second control cycles, or third control cycles, a similar operation of configuring the duration of the second level stage can be performed for each control cycle, so that the duration of the second level stage in multiple control cycles for anode reset is greater than the duration of the second level stage in the control cycle not used for anode reset, and / or, the duration of the second level stage in the first control cycle after multiple anode resets is greater than the duration of the second level stage in other control cycles not used for anode reset, while ensuring uniform light emission in multiple low-level stages of the same picture frame, the applicability, compatibility and flexibility of the solution in different scenarios are improved.

[0018] In a second aspect, a driving method for a pixel circuit is provided, wherein a display cycle of the pixel circuit includes a plurality of consecutive control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a refresh frame period, the refresh frame period is used for display refresh and gate reset, the pixel circuit includes a light-emitting control circuit and a reset circuit, the reset circuit receives a reset control signal, and controls gate reset and display refresh according to the refresh frame period, the method comprising: detecting a screen brightness value; when the screen brightness value is greater than a second brightness threshold, configuring a duration of the first level stage in the plurality of control cycles according to a display refresh rate corresponding to the light-emitting control signal and / or a reset frequency corresponding to the reset control signal; the light-emitting control circuit receives the light-emitting control signal, and controls light emission according to a duration of the first level stage and a duration of the second level stage in the plurality of control cycles.

[0019] Exemplarily, the above method can be applied to a display panel, a display screen, or an electronic device including a display screen, such as a mobile phone, a tablet computer, etc., without limitation.

[0020] Exemplarily, the display refresh rate is such as 120 Hz, 60 Hz, 1 Hz, etc., without limitation; the reset frequency is such as the source reset frequency or the drain reset frequency, such as 120 Hz, 240 Hz, 360 Hz, etc., without limitation.

[0021] Exemplarily, the first level stage of the control cycle is a high level stage, and the second level stage is a low level stage, or the first level stage is a low level stage, and the second level stage is a high level stage, without limitation.

[0022] The solution provided in the second aspect above, in scenarios where the brightness is greater than the second brightness threshold, such as high-brightness scenarios, flexibly and non-uniformly configures the duty cycle of the level stage (such as the first level stage) not used for luminescence in each control cycle according to actual conditions, such as differentiated driving of the first level stage in the refresh frame cycle and the holding frame cycle based on different reset frequencies and / or different display refresh rates. On the premise of ensuring the normal operation of the pixels in each control cycle, the luminous duty cycle is improved to optimize the screen flicker, and the duty cycle is kept equivalent under different display refresh rates and / or different reset frequencies, thereby avoiding flickering when the display refresh rate or reset frequency is switched, thereby achieving better display and eye protection effects.

[0023] As a possible implementation, the above-mentioned multiple control cycles also include a holding frame cycle, the holding frame cycle is used to maintain the display, the display refresh rate corresponding to the light-emitting control signal is the first refresh rate, and the reset frequency corresponding to the reset control signal is the first frequency. The above-mentioned configuration of the duration of the first level stage in multiple control cycles according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring the duration of the first level stage in the refresh frame cycle to the fourth duration, and configuring the duration of the first level stage in the holding frame cycle to the fifth duration, wherein the fifth duration is less than the fourth duration. Based on this, it can ensure that the pixels work normally in each control cycle, improve the light-emitting duty cycle to optimize the screen flicker, and achieve better display and eye protection effects.

[0024] Exemplarily, the display period of the above-mentioned picture frame includes N control periods, N=F1 / F2, F1 is the source reset frequency or the drain reset frequency, F2 is the display refresh rate, and the above-mentioned configuration of the duration of the first level stage in multiple control periods according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring the duration of the first level stage in N-1 maintaining frame periods to be less than the duration of the first level stage in the refresh frame period.

[0025] As a possible implementation, multiple control cycles also include a holding frame cycle, the holding frame cycle is used to maintain the display, the display refresh rate corresponding to the light-emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, and the reset frequency corresponding to the reset control signal is a first frequency. The above configuration of the duration of the first level stage in multiple control cycles according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring the duration of the first level stage in the refresh frame cycle to be a fourth duration, configuring the duration of the first level stage in the holding frame cycle to be a sixth duration, the sixth duration is less than the fourth duration, and the sixth duration is greater than the fifth duration. Based on this, it can not only ensure that the pixels work normally in each control cycle, improve the light-emitting duty cycle to optimize screen flicker, but also make the duty cycle at different display refresh rates and / or different reset frequencies remain equivalent, avoid flickering when the display refresh rate or reset frequency is switched, and achieve better display and eye protection effects.

[0026] As a possible implementation, the refresh frame period includes one control period; and / or the hold frame period includes at least one control period. That is, there may be one refresh frame period, and there may be one or more hold frame periods. Based on this, when there is one refresh frame period and one or more hold frame periods, a similar operation of configuring the duration of the first level stage can be performed for each control period, so as to realize differentiated driving of the first level stage in the refresh frame period and the hold frame period.

[0027] Of course, in some examples, the frame period may not be maintained. In this case, the operation of configuring the duration of the first level phase may be performed only for the refresh frame period.

[0028] In a third aspect, a display screen is provided, which includes an integrated circuit, a gate driving unit and a pixel circuit, wherein a display cycle of the pixel circuit includes a plurality of consecutive control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a first control cycle, the first control cycle is used for anode reset, and the pixel circuit includes a light-emitting control circuit and an anode reset circuit; the anode reset circuit is used for: receiving an anode reset control signal, and controlling the anode reset according to the first control cycle; the integrated circuit is used for: detecting a screen brightness value; and configuring a duration of the second level stage in a plurality of control cycles according to the first control cycle when the screen brightness value is less than a first brightness threshold; the light-emitting control circuit is used for: receiving a light-emitting control signal, and controlling light emission according to the duration of the first level stage and the duration of the second level stage in a plurality of control cycles.

[0029] Illustratively, in an integrated circuit such as a driver integrated circuit (IC), the gate driving unit may include but is not limited to a gate driven on array (GOA).

[0030] The solution provided in the third aspect above can flexibly and non-uniformly configure the duty cycle of the level stage (such as the second level stage) used for luminescence in each control cycle in scenarios where the brightness is less than the first brightness threshold, such as medium and low brightness scenarios, according to actual conditions such as whether each control cycle is used for anode reset, and flexibly configure the duration of one or more second level stages after the anode reset. On the premise of ensuring that the display screen can emit light normally in each control cycle, the light emission of multiple control cycles is uniform, so as to optimize screen flicker and achieve better display and eye protection effects.

[0031] As a possible implementation, the above-mentioned multiple control cycles also include a second control cycle, wherein the second control cycle is not used for anode reset, and the above-mentioned integrated circuit is used to: configure the duration of the second level stage in the above-mentioned first control cycle to be the first duration, and configure the duration of the second level stage in the second control cycle to be the second duration, wherein the first duration is greater than the second duration. Based on this, the duration of the second level stage in the control cycle used for anode reset can be made greater than the duration of the second level stage in the control cycle not used for anode reset, while ensuring uniform light emission in multiple low-level stages of the same picture frame, the applicability, compatibility and flexibility of the solution in different scenarios are improved.

[0032] As a possible implementation, the first control cycle includes at least one second level stage, and the first duration includes the total duration of at least one second level stage in the first control cycle. Based on this, a variety of methods can be used to make the duration of the second level stage in the control cycle for anode reset longer than the duration of the second level stage in the control cycle not used for anode reset, such as lengthening the duration of the second level stage in the display drive cycle for anode reset compared to other cycles or increasing the number of second level stages in the display drive cycle for anode reset, while ensuring uniform light emission in multiple low-level stages of the same picture frame, and improving the applicability, compatibility and flexibility of the solution in different scenarios.

[0033] Exemplarily, the first control cycle includes a second level stage, and the duration of the second level stage in the first control cycle is greater than the duration of the second level stage in the second control cycle.

[0034] Or, exemplarily, the first control cycle includes multiple second level stages, and the sum of the durations of the multiple second level stages in the first control cycle (ie, the total duration) is greater than the duration of the second level stage in the second control cycle.

[0035] As a possible implementation, the above-mentioned multiple control cycles also include a third control cycle, wherein the third control cycle is a control cycle after the first control cycle, and the third control cycle is not used for anode reset, and the above-mentioned integrated circuit is specifically used to: configure the duration of the second level stage in the above-mentioned third control cycle to be a third duration, wherein the third duration is greater than the second duration. Based on this, the duration of the second level stage in the control cycle of the picture frame that is not used for anode reset can be flexibly adjusted according to actual conditions to perform luminous compensation, ensuring that the display screen can maintain normal luminescence in each control cycle, and making the luminescence of each pixel of the display screen in each control cycle the same or close, thereby ensuring uniform luminescence in multiple low-level stages of the same picture frame.

[0036] As a possible implementation, the third control cycle includes at least one second level stage, and the third duration includes the total duration of at least one second level stage in the third control cycle. Based on this, a variety of methods can be used to ensure uniform light emission in multiple low-level stages of the same picture frame while improving the applicability, compatibility and flexibility of the solution in different scenarios.

[0037] As an example, the third duration is less than or equal to the first duration.

[0038] As a possible implementation, the first control cycle includes at least one control cycle; and / or, the second control cycle includes at least one control cycle; and / or, the third control cycle includes at least one control cycle. That is, there may be one or more first control cycles, one or more second control cycles, and one or more third control cycles. Based on this, when there are multiple first control cycles, second control cycles, or third control cycles, a similar operation of configuring the duration of the second level stage can be performed for each control cycle, so that the duration of the second level stage in multiple control cycles for anode reset is greater than the duration of the second level stage in the control cycle not used for anode reset, and / or, the duration of the second level stage in the first control cycle after multiple anode resets is greater than the duration of the second level stage in other control cycles not used for anode reset, while ensuring uniform light emission in multiple low-level stages of the same picture frame, the applicability, compatibility and flexibility of the solution in different scenarios are improved.

[0039] In a fourth aspect, a display screen is provided, which includes: an integrated circuit, a gate driving unit and a pixel circuit, wherein a display cycle of the pixel circuit includes a plurality of consecutive control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a refresh frame period, the refresh frame period is used for display refresh and gate reset, the pixel circuit includes a light-emitting control circuit and a reset circuit; the reset circuit is used for: receiving a reset control signal, controlling gate reset and display refresh according to the refresh frame period, the integrated circuit is used for: detecting a screen brightness value; and when the screen brightness value is greater than a second brightness threshold, configuring a duration of the first level stage in the plurality of control cycles according to a display refresh rate corresponding to the light-emitting control signal and / or a reset frequency corresponding to the reset control signal; the light-emitting control circuit is used for: receiving a light-emitting control signal, and controlling light emission according to a duration of the first level stage and a duration of the second level stage in the plurality of control cycles.

[0040] The solution provided in the fourth aspect above, in scenarios where the brightness is greater than the second brightness threshold, such as high-brightness scenarios, flexibly and non-uniformly configures the duty cycle according to actual conditions by adjusting the duration of the level stage (such as the first level stage) not used for luminescence in each control cycle, such as differentiated driving of the first level stage in the refresh frame cycle and the holding frame cycle based on different reset frequencies and / or different display refresh rates. On the premise of ensuring that the display screen works normally in each control cycle, the luminous duty cycle is improved to optimize screen flicker, and the duty cycle is kept equivalent under different display refresh rates and / or different reset frequencies, thereby avoiding flickering when the display refresh rate or reset frequency is switched, thereby achieving better display and eye protection effects.

[0041] As a possible implementation, the above-mentioned multiple control cycles also include a holding frame cycle, the holding frame cycle is used to maintain the display, the display refresh rate corresponding to the light-emitting control signal is the first refresh rate, the reset frequency corresponding to the reset control signal is the first frequency, and the above-mentioned integrated circuit is specifically used to: configure the duration of the first level stage in the refresh frame cycle to the fourth duration, and configure the duration of the first level stage in the holding frame cycle to the fifth duration, wherein the fifth duration is less than the fourth duration. Based on this, it can ensure that the display screen works normally in each control cycle, improve the light-emitting duty cycle to optimize the screen flicker, and achieve better display and eye protection effects.

[0042] As a possible implementation method, multiple control cycles also include a holding frame cycle, the holding frame cycle is used to maintain the display, the display refresh rate corresponding to the light-emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, the reset frequency corresponding to the reset control signal is the first frequency, and the above integrated circuit is specifically used to: configure the duration of the first level stage in the refresh frame cycle to the fourth duration, and configure the duration of the first level stage in the holding frame cycle to the sixth duration, the sixth duration is less than the fourth duration, and the sixth duration is greater than the fifth duration. Based on this, it can not only ensure that the pixels work normally in each control cycle, improve the light-emitting duty cycle to optimize screen flicker, but also make the duty cycle at different display refresh rates and / or different reset frequencies remain equivalent, avoid flickering when the display refresh rate or reset frequency is switched, and achieve better display and eye protection effects.

[0043] As a possible implementation, the refresh frame period includes one control period; and / or the hold frame period includes at least one control period. That is, there may be one refresh frame period, and there may be one or more hold frame periods. Based on this, when there is one refresh frame period and one or more hold frame periods, a similar operation of configuring the duration of the first level stage can be performed for each control period, so as to realize differentiated driving of the first level stage in the refresh frame period and the hold frame period.

[0044] Of course, in some examples, the frame period may not be maintained. In this case, the operation of configuring the duration of the first level phase may be performed only for the refresh frame period.

[0045] In a fifth aspect, an electronic device is provided, comprising: a display screen for interface display; a memory for storing computer program instructions; and a processor for executing the computer program instructions to support the electronic device to implement a method in any possible implementation of the first aspect or the second aspect.

[0046] In a sixth aspect, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method in any possible implementation of the first aspect or the second aspect is implemented.

[0047] In a seventh aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to implement a method in any possible implementation of the first aspect or the second aspect.

[0048] In an eighth aspect, a chip system is provided, the chip system comprising a processing circuit and a storage medium, wherein the storage medium stores computer program instructions; when the computer program instructions are executed by the processor, the method in any possible implementation of the first aspect or the second aspect is implemented. The chip system may be composed of a chip, or may include a chip and other discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of the principle of emitting control using a conventional emitting (EM) control signal;

[0050] Figure 2 A schematic diagram of the light-emitting effect of a conventional EM control signal driving a pixel;

[0051] Figure 3 Schematic diagram of the principle of luminescence control using two other conventional EM control signals;

[0052] Figure 4 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0053] Figure 5 Schematic diagram of the luminous effect of the EM control signal driving the pixel provided in the embodiment of the present application Figure 1 ;

[0054] Figure 6 Schematic diagram of the luminous effect of the EM control signal driving the pixel provided in the embodiment of the present application Figure 2 ;

[0055] Figure 7 Schematic diagram of the luminous effect of the EM control signal driving the pixel provided in the embodiment of the present application Figure 3 ;

[0056] Figure 8 Schematic diagram of the luminous effect of the EM control signal driving the pixel provided in the embodiment of the present application Figure 4 ;

[0057] Fig. 9 Schematic diagram of the luminous effect of the EM control signal driving the pixel provided in the embodiment of the present application Figure 5 ;

[0058] Fig.10 Schematic diagram of the principle of EM control signal for light emission control provided in the embodiment of the present application Figure 1 ;

[0059] Fig.11 Schematic diagram of the principle of EM control signal for light emission control provided in the embodiment of the present application Figure 2 ;

[0060] Fig.12 Schematic diagram of the principle of EM control signal for light emission control provided in the embodiment of the present application Figure 3 ;

[0061] Fig.13 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0062] Fig.14 A schematic diagram of a driving timing corresponding to a refresh frame period provided in an embodiment of the present application;

[0063] Fig.15 The driving timing diagram corresponding to the frame period provided in the embodiment of the present application is as follows Figure 1 ;

[0064] Fig.16 The driving timing diagram corresponding to the frame period provided in the embodiment of the present application is as follows Figure 2 ;

[0065] Fig.17 The driving timing diagram corresponding to the frame period provided in the embodiment of the present application is as follows Figure 3 ;

[0066] Fig.18 A structural block diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0068] In the following, the terms "first", "second", etc. are only used to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. For example, if the described object is a "field", the ordinal number before the "field" in the "first field" and the "second field" does not limit the position or order between the "fields", and the "first" and "second" do not limit whether the "fields" they modify are in the same message, nor do they limit the order of the "first field" and the "second field". For another example, if the described object is a "level", the ordinal number before the "level" in the "first level" and the "second level" does not limit the priority between the "levels". For another example, the number of described objects is not limited by the ordinal number, and can be one or more. Taking the "first device" as an example, the number of "devices" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the described object is a "device", the "first device" and the "second device" can be devices of the same type or devices of different types. For another example, if the described object is "information", the "first information" and the "second information" can be information of the same content or information of different contents. In summary, the use of prefixes such as ordinal numbers to distinguish the described objects in the embodiments of the present application does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes.

[0069] Furthermore, in the embodiments of the present application, "connection" may be a direct connection or an indirect connection; in addition, it may refer to an electrical connection or a communication connection; for example, the connection between two electrical components A and B may refer to a direct connection between A and B, or may refer to an indirect connection between A and B through other electrical components or connecting media, or may refer to an indirect connection between A and B through other communication devices or communication media, as long as communication between A and B can be achieved.

[0070] As described in the background technology, the display screens of existing electronic devices, such as active matrix organic light emitting diode (AMOLED) panels, often use dimming strategies such as PWM and DC modulation for dimming, such as using PWM dimming strategies in medium and low brightness scenes and using DC modulation dimming strategies in high brightness scenes, so as to achieve better display effects and improve user visual experience by adjusting the duty cycle and / or brightness value of the display screen. However, the above dimming methods are all strategies under relatively ideal conditions, and do not take into account the actual situation of the display screen when it is working.

[0071] For example, in low- to medium-brightness scenarios, existing dimming methods do not take into account the effects of anode resetting and charging of components such as EL capacitors and pixel circuit anodes on the display screen on the light-emitting time of the display screen.

[0072] like Figure 1 As shown, taking the 2nit screen brightness value as an example, the emitting (EM) control signal is used to control the emitting light, the EM control signal uses 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 120Hz, and the display period of one frame includes 12 control periods. In general, the PWM dimming strategy can be used to control the brightness value by adjusting the duty cycle to achieve a uniform dimming effect. Among them, the display refresh rate can be simply understood as the number of times the screen is lit per unit time; the duty cycle can be simply understood as the proportion of the time that drives the pixel to emit light to the total time. For example, taking a pulse sequence with a pulse width of 1μs and a control period of 4μs as an example, the duty cycle of the pulse sequence is 1μs / 4μs=0.25. Among them, Figure 1 In the EM control signal, when the EM control signal is low, the display screen lights up; when the EM control signal is high, the display screen goes out. Figure 1 The display screen lighting up when the EM control signal is at a low level is only taken as an example, and is not specifically limited in practical applications. For example, in some embodiments, a high level corresponds to a pixel lighting up, and a low level corresponds to a pixel off, depending on the specific situation.

[0073] However, using Figure 1 The dimming method shown has the following problems: AMOLED and other display screens usually include EL capacitors, pixel circuit anodes and other devices, such as Figure 2 As shown, in the first control cycle of a picture frame, taking the display screen performing anode reset at a frequency of 120 Hz as an example, when the EM control signal is switched to a low level, the EL capacitor, the pixel circuit anode and other devices need to be charged, so the actual luminous duration of the display screen in the first control cycle will be shortened, such as Figure 2 In severe cases, the light may not be emitted at all. This may result in no light or weak light emission in some control cycles during the image display process, causing flickering of low-frequency components that can be perceived by the human eye, i.e., the stroboscopic effect visibility measure (SVM) increases, resulting in a strong flickering sensation on the image.

[0074] For another example, in high-brightness scenes, such as when the screen brightness value is greater than 90 nit, the existing dimming method does not take into account the impact of refreshing the frame period and maintaining the same length of the high-level phase in the frame period on the display screen's luminous time.

[0075] like Figure 3As shown, taking the example of controlling the luminescence through the EM control signal at a screen brightness value of 500nit, and the display screen luminescence when the EM control signal is at a low level, in general, controlling the refresh frame period and the duration of the control signal being at a low level in the frame period to be consistent (or the error is within a certain acceptable range) can make the refresh frame period and the duration of the display screen luminescence in the frame period consistent, thereby achieving a uniform dimming effect. In addition, for different display refresh rates, such as Figure 3 The display refresh rates shown are 120 Hz and 60 Hz, and the refresh frame period and the time during which the EM control signal is kept at a low level within the frame period are also consistent or the error is within an acceptable range), so as to achieve consistent duty cycle under different display refresh rates, thereby avoiding brightness differences caused by switching of the display refresh rate.

[0076] However, using Figure 3 The dimming method shown has the following problems: In practical applications, since the refresh frame period requires gate reset and data writing (such as for display refresh), the duration of the high level stage is long, that is, the display screen does not emit light for a long time, so the duration of the EM low level will inevitably be shortened. If the refresh frame period is to be kept consistent with the duration of the EM control signal being at a low level within the frame period, the screen light duration within the frame period will be shortened, which will cause the display screen to require a higher brightness amplitude when the EM is at a low level to achieve the set brightness target value, and the average luminous time in a frame is low. Both of these effects will lead to an increase in SVM, that is, the problem of excessive flickering of the screen.

[0077] Need to explain, Figure 1-Figure 3 In the example shown, when the EM control signal is at a low level, the display screen is illuminated; when the EM control signal is at a high level, the display screen is off. Of course, in actual applications, a high level may correspond to a light-emitting display screen, and a low level may correspond to a non-light-emitting display screen, depending on the specific situation.

[0078] In order to solve the problem of excessive flickering caused by the large SVM value caused by non-luminous and luminous stages during the display screen display process, the embodiment of the present application provides a driving method for a pixel circuit, which can solve the screen flicker problem in brightness scenes such as medium and low brightness scenes and high brightness scenes.

[0079] For example, based on the solution provided in the embodiments of the present application, in medium and low brightness scenes, a non-uniform duty cycle configuration can be adopted in each control cycle of the display cycle (such as the EM cycle, and the EM cycle is taken as an example for relevant introduction below), so that the low-level stage after taking into account factors such as anode reset and device charging can be able to emit light normally, and the light emission in multiple low-level stages is made uniform, thereby optimizing screen flicker and achieving better display and eye protection effects.

[0080] For example, based on the solution provided in the embodiment of the present application, in a high-brightness scene, the parameters of at least one control cycle corresponding to the picture frame can be adjusted according to the screen brightness value, display refresh rate, reset frequency (such as source reset frequency, drain reset frequency, etc.), such as the duration of the first level stage, and finally the interface display is performed according to the parameters of the adjusted control cycle. For example, based on different reset frequencies (such as 120Hz, 240Hz, 360Hz) and / or different display refresh rates (such as 1Hz, 60Hz, 120Hz), differentiated driving can be performed in the refresh frame period and the holding frame period, such as making the refresh frame period and the holding frame period The first level stage (such as a high level stage, the following takes the first level stage as an example for related introduction) duration (i.e., the duration of the display screen not emitting light) differs by more than 1H, and at the same time, the duty ratio under different display refresh rates and / or different reset frequencies is high and basically maintained (such as a difference of less than 0.2%), so as to optimize the screen flicker and achieve better display and eye protection effects. Among them, 1H is the scanning time unit of each line of the display screen, usually between 1 and 3us.

[0081] The display screen described in the embodiment of the present application is a display screen of an electronic device, and the electronic device may include but is not limited to a smart phone, a netbook, a tablet computer, a smart drawing board, a handwriting board, a smart watch, a smart bracelet, a phone watch, smart glasses, a smart camera, a PDA, a car computer, a personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), an augmented reality (AR) / virtual reality (VR) device, a smart TV, a projection device, or a somatosensory game console in a human-computer interaction scene, etc. Alternatively, the electronic device may also be an electronic device with a display screen of other types or structures, which is not limited in the present application.

[0082] As an example, see Figure 4 , Figure 4 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application is shown.

[0083] like Figure 4 As shown, the electronic device may include a processor 410, a memory 420, a charging management module 430, a power management module 440, a battery 450, a display screen 460, and the like.

[0084] The processor 410 may include one or more processing units. For example, the processor 410 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a flight controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0085] The processor 410 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 410 is a cache memory. The memory may store instructions or data that the processor 410 has just used or cyclically used. If the processor 410 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 410, and thus improves the efficiency of the system.

[0086] The charging management module 430 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 430 may receive charging input from a wired charger through a USB interface. In some wireless charging embodiments, the charging management module 430 may receive wireless charging input through a wireless charging coil. While the charging management module 430 is charging the battery 450, it may also power the electronic device through the power management module 440.

[0087] The power management module 440 is used to connect the battery 450, the charging management module 430 and the processor 410. The power management module 440 receives input from the battery 450 and / or the charging management module 430, and supplies power to the processor 410, the internal memory 420, the display screen 460, the camera 393 and the wireless communication module 360. The power management module 440 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 440 can also be set in the processor 410. In other embodiments, the power management module 440 and the charging management module 430 can also be set in the same device.

[0088] In the embodiment of the present application, the power management module 440 receives input from the battery 450 and / or the charging management module 430 to provide power to the display screen 460 to support normal operation of the display screen, such as lighting or turning off.

[0089] The electronic device implements the display function through a GPU, a display screen 460, and an AP. The GPU is a microprocessor for image processing, which connects the display screen 460 and the AP. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 410 may include one or more GPUs, which execute program instructions to generate or change display information.

[0090] The display screen 460 is used to display images, videos, etc. The display screen 460 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light emitting diode (AMOLED), a flexible light-emitting diode (FLED), MiniLED, MicroLED, Micro-OLED, quantum dot light emitting diodes (QLED), etc.

[0091] In the embodiment of the present application, the display screen 460 can display images based on the normal operation of the display panel.

[0092] In some embodiments, the display screen can adopt a non-uniform duty cycle configuration in each EM cycle of the display cycle in medium and low brightness scenarios to ensure that the display screen can emit light normally in the first second level stage (such as a low level stage, and the following introduction takes the second level stage as the low level stage as an example) after completing anode resetting, device charging, etc., and make the light emitted by multiple low level stages in the same display cycle uniform.

[0093] In some embodiments, the display screen can be driven differentially in the refresh frame period and the hold frame period based on different reset frequencies (such as 120Hz, 240Hz, 360Hz) and / or different display refresh rates (such as 1Hz, 60Hz, 120Hz) in high-brightness scenarios, so that the duty cycle at different display refresh rates and / or different reset frequencies is high and basically remains the same (such as the difference is less than 0.2%), so as to achieve a smaller SVM value, optimize screen flicker, and achieve better display and eye protection effects.

[0094] In some embodiments, Figure 4As shown, the display screen may include an integrated circuit (such as a driver integrated circuit (IC)), a gate driving unit and a pixel circuit.

[0095] The pixel circuit includes a light emitting control circuit and a reset circuit.

[0096] The driver IC is used to: obtain the screen brightness value; and, when the screen brightness value is less than the first brightness threshold, configure the duration of the second level stage in multiple control cycles according to the cycle for positive reset (such as the first control cycle); or when the screen brightness value is greater than the second brightness threshold, configure the duration of the first level stage in multiple control cycles according to the display refresh rate corresponding to the light control signal and / or the reset frequency corresponding to the reset control signal. Exemplarily, the gate driving unit may include but is not limited to GOA.

[0097] The light emitting control circuit is used to control the light emitting by controlling the duration of the first level stage not used for light emitting and the duration of the second level stage used for light emitting in multiple control cycles of the pixel circuit according to the light emitting control signal.

[0098] The reset circuit is used to: control whether multiple control cycles are used for reset according to the reset control signal, such as controlling the reset in the first control cycle, such as, the anode reset circuit is used to control whether multiple control cycles are used for anode reset according to the anode reset control signal, the source reset circuit is used to control whether multiple control cycles are used for source reset according to the source reset control signal, and the drain reset circuit is used to control whether multiple control cycles are used for drain reset according to the drain reset control signal.

[0099] The external memory interface 320 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor 410 through the external memory interface 320 to implement a data storage function.

[0100] The internal part can be used to store computer executable program codes. Exemplarily, the computer program may include an operating system program and an application program. Among them, the executable program code includes instructions. The processor 410 executes various functional applications and data processing of the electronic device by running the instructions stored in the memory 420. The memory 420 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application program required for at least one function, etc. The data storage area may store data created during the use of the electronic device, etc. In addition, the memory 420 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 410 executes various functional applications and data processing of the electronic device by running the instructions stored in the memory 420, and / or the instructions stored in the memory provided in the processor.

[0101] It is understandable that this application Figure 4 The illustrated structure does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0102] For example, in some examples, the electronic device may also include a universal serial bus (USB) interface, an antenna, a mobile communication module, a wireless communication module, an audio module, a speaker, a receiver, a microphone, a headphone interface, a sensor module, buttons, a motor, an indicator, a camera, and one or more other devices or modules, which are not described here.

[0103] The following will specifically introduce the driving method of the pixel circuit provided in the embodiment of the present application in combination with specific scenarios.

[0104] Embodiment 1:

[0105] In Embodiment 1, when the electronic device performs picture frame display based on the pixel circuit, the display cycle of one picture frame generally includes a plurality of continuous control cycles. The pixel circuit includes a light emitting control circuit and an anode reset circuit, the light emitting control circuit is configured to receive a light emitting control signal, such as an EM control signal; the anode reset circuit is configured to receive an anode reset control signal; that is, the pixel circuit can receive the EM control signal, and control the light emission according to the duration of the level stage not used for light emission and the duration of the level stage used for light emission in a plurality of control cycles; the anode reset circuit can control whether a plurality of control cycles are used for anode reset according to the anode reset control signal.

[0106] In Example 1 of the present application, the pixel circuit adopts a non-uniform duty cycle configuration in each control cycle to ensure that the pixel can emit light normally in each low-level stage, and the light emission in each low-level stage is the same or close, thereby ensuring uniform light emission in multiple low-level stages of the same display cycle.

[0107] In some embodiments, the solution provided in Example 1 can be applied to a scene where the screen brightness value is less than a first brightness threshold. For example, the first brightness threshold is 90 nit, etc., that is, the solution provided in Example 1 can be applied to medium and low brightness scenes, and the specific value of the first brightness threshold is not specifically limited.

[0108] In some embodiments, the duration of multiple control cycles included in the display cycle of the pixel circuit is the same, and the multiple control cycles all include a first level stage and a second level stage, that is, each control cycle includes a first level stage and a second level stage, wherein the first level stage is a level stage for anode reset, and the second level stage is a level stage for light emission. In Embodiment 1 of the present application, the duration of the second level stage in multiple control cycles can be configured according to the control cycle (such as the first control cycle) for anode reset in multiple control cycles, and then the light emission is controlled according to the duration of the first level stage and the duration of the second level stage used in multiple control cycles.

[0109] In some embodiments, the first level stage is a high level stage, and the second level stage is a low level stage; or, the first level stage is a low level stage, and the second level stage is a high level stage, which is not limited in the embodiments of the present application. The following embodiments take the first level stage as a high level stage, and the second level stage as a low level stage as an example.

[0110] As a possible implementation, the first control cycle may include at least one control cycle, and the second control cycle may include at least one control cycle. That is, there may be one or more first control cycles, and there may be one or more second control cycles, wherein the first control cycle is used for anode reset, and the second control cycle is not used for anode reset. Based on this, a similar operation of configuring the duration of the second level stage can be performed for each first control cycle and each second control cycle, such as configuring the duration of the second level stage in each first control cycle and each second control cycle according to each first control cycle, and then controlling the light emission according to the duration of the first level stage and the duration of the second level stage in multiple control cycles (including each first control cycle and each second control cycle). For example, the duration of the second level stage in the first control cycle can be configured as the first duration, and the duration of the second level stage in the second control cycle can be configured as the second duration, so that the first duration is greater than the second duration. Based on this, the duration of the first second level stage after the anode reset can be made longer than the duration of the second level stage in the control cycle without anode reset, so as to ensure that the duration of each second level stage is sufficient to charge the EL capacitor, pixel circuit anode and other devices and maintain sufficient luminescence, and make the luminescence of each second level stage the same or close.

[0111] For example, taking the case where the EM control signal is used to control the light emission at a screen brightness value of 2nit, the EM control signal uses 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 120Hz, the display cycle of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage as an example, the schematic diagram of the EM control signal and the light emission effect of the pixel may be as follows: Figure 5 As shown, Figure 5 The 12 EM cycles shown (such as Figure 5 The EM cycle 1, EM cycle 2, ..., EM cycle 12) shown in the figure each include a high level phase and a low level phase. For example, according to the timing sequence, the EM control signal includes Figure 5 As shown, high level stage 1, low level stage 1, high level stage 2, low level stage 2, high level stage 3, low level stage 3, ..., high level stage 12, low level stage 12. Figure 5As shown, compared with the duration of the low level phase of other EM cycles (such as the second control cycle above) (i.e. the second duration above), the duration of the low level phase in EM cycle 1 (i.e. the first control cycle above) for anode reset (i.e. the first duration above) is longer. Therefore, after completing the anode reset, the electronic device can switch to the low level phase in advance to start charging the EL capacitor, the pixel circuit anode and other devices, thereby ensuring that the luminescence of the pixel in the first low level phase is equal to or close to the luminescence of the pixel in other low level phases.

[0112] As an example, the first duration has the following relationship with the duration of the low-level phase in the control period with the shortest duration of the low-level phase in the display period (such as recorded as "duration Min"): (first duration - duration Min) / duration Min> (or ≥) first preset threshold, illustratively, the first preset threshold is a value within 10%-100%, such as 60%. Of course, the embodiment of the present application does not limit the specific first preset threshold, which depends on the specific situation in actual application.

[0113] In some embodiments, the first control cycle includes a second level phase. In this case, the first duration is the duration of the second level phase of the first control cycle.

[0114] In some embodiments, the first control cycle includes a plurality of second level phases. In this case, the first duration includes the total duration (ie, the sum of the durations) of the plurality of second level phases in the first control cycle.

[0115] For example, taking the case where the EM control signal is used to control the light emission at a screen brightness value of 2nit, the EM control signal uses 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 120Hz, the display cycle of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage as an example, the schematic diagram of the light emission effect of the EM control signal driving the pixel may be as follows Figure 6 As shown, 12 EM cycles (such as Figure 6 EM cycle 1, EM cycle 2, ..., EM cycle 12) shown in the figure each include a high level phase and a low level phase (for ease of reading the figure, Figure 6 The various high and low level stages are not shown in the figure. For more information, please refer to Figure 5 ).like Figure 6As shown, compared with the duration of the low-level stage of other EM cycles (such as the second control cycle above) (i.e., the second duration above), the EM cycle 1 (i.e., the first control cycle above) for anode reset has two low-level stages, and the total duration of these two low-level stages (i.e., the first duration above) is longer. Therefore, in EM cycle 1 (i.e., the first control cycle above), after completing the anode reset, the electronic device can switch to the low-level stage in advance to start charging the EL capacitor, the pixel circuit anode and other devices, and start emitting light when entering the next low-level stage in the same EM cycle, thereby ensuring that the light emission of the pixel in the first light-emitting stage is equal to or close to the light emission of the pixel in other low-level stages.

[0116] In addition, it should be noted that this application Figure 5 and Figure 6 The example shown only takes one anode reset in one display cycle as an example. In actual applications, the solution provided in the embodiment of the present application is also applicable to the case where the anode reset is performed multiple times (such as 2 times, 3 times, etc., without limiting the number) in one display cycle. That is, one display cycle may include multiple first control cycles, and the duration of the second level stage in multiple first control cycles for anode reset can be configured based on the solution provided in the present application.

[0117] For example, taking the case where the EM control signal is used to control the light emission at a screen brightness value of 2nit, the EM control signal uses 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 360Hz, the display cycle of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage as an example, the schematic diagram of the light emission effect of the EM control signal driving the pixel may be as follows Figure 7 As shown, 12 EM cycles (such as Figure 7 EM cycle 1, EM cycle 2, ..., EM cycle 3) shown in the figure each include a high level phase and a low level phase (for ease of reading the figure, Figure 7 The various high and low level stages are not shown in the figure. For more information, please refer to Figure 5 ).like Figure 7 As shown, compared with the duration of the low level phase of other EM cycles (such as the second control cycle mentioned above) (i.e. the second duration mentioned above), the duration of the low level phase in EM cycle 1, EM cycle 5 and EM cycle 9 (i.e. the multiple first control cycles mentioned above) for anode reset (i.e. the first duration mentioned above) is longer. Therefore, after each anode reset is completed, the electronic device can switch to the low level phase in advance to start charging of devices such as the EL capacitor and the pixel circuit anode, thereby ensuring that the luminescence of the pixel in the first low level phase after each anode reset is equal to or close to the luminescence of the pixel in other low level phases.

[0118] For another example, taking the case where the EM control signal is used to control the light emission at a screen brightness value of 2nit, the EM control signal adopts 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 360Hz, the display cycle of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage as an example, the schematic diagram of the light emission effect of the EM control signal driving the pixel may be as follows: Figure 8 As shown, 12 EM cycles (such as Figure 8 EM cycle 1, EM cycle 2, ..., EM cycle 12) shown in the figure each include a high level phase and a low level phase (for ease of reading the figure, Figure 8 The various high and low level stages are not shown in the figure. For more information, please refer to Figure 5 ) paragraph. Figure 8 As shown, compared with the duration of the low-level stage of other EM cycles (such as the second control cycle mentioned above) (i.e., the second duration mentioned above), there are two low-level stages in EM cycle 1, EM cycle 5 and EM cycle 9 (i.e., the first control cycle mentioned above) for anode reset, and the total duration of the two low-level stages in each cycle (i.e., the first duration mentioned above) is longer. Therefore, after each anode reset is completed, the electronic device can switch to the low-level stage in advance to start charging the EL capacitor, the pixel circuit anode and other devices, and start emitting light when entering the next low-level stage, thereby ensuring that the light emission of the pixel in the first light-emitting stage after each anode reset is equal to or close to the light emission of the pixel in other low-level stages.

[0119] And, it should be noted that this application Figure 5 and Figure 6 The example shown is only used to ensure the duration of the first light-emitting stage (i.e., the second level stage) after the anode is reset. In actual applications, for one or more other light-emitting stages after the anode is reset, the method provided in the embodiment of the present application can also be used to ensure the light emission.

[0120] As a possible implementation, the duration of the second level stage in the third control cycle can be configured as a third duration, so that the third duration is greater than the second duration, wherein the third control cycle is not used for anode reset. As an example, the third control cycle can be a control cycle after the first control cycle, such as the first control cycle after the first control cycle. Based on this, it can be ensured that the second second level stage after the anode reset has sufficient luminescence, and the luminescence of each second level stage is the same or close.

[0121] As an example, the third control cycle may include at least one control cycle, that is, the third control cycle may have one or more. Based on this, a similar operation of configuring the duration of the second level stage can be performed for each third control cycle, such as configuring the duration of the second level stage in each third control cycle according to the first control cycle, and then controlling the light emission according to the duration of the first level stage and the duration of the second level stage in multiple control cycles (including each third control cycle).

[0122] As an example, the third duration is less than or equal to the first duration.

[0123] For example, taking the case where the EM control signal is used to control the light emission at a screen brightness value of 2nit, the EM control signal uses 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 120Hz, the display cycle of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage as an example, the schematic diagram of the light emission effect of the EM control signal driving the pixel may be as follows Fig. 9 As shown, 12 EM cycles (such as Fig. 9 As shown, the EM cycle 1, EM cycle 2, ..., EM cycle 12) each include a high level phase and a low level phase (for ease of reading the diagram, Fig. 9 The various high and low level stages are not shown in the figure. For more information, please refer to Figure 5 ).like Fig. 9 As shown, compared with the duration of the low level phase of other EM cycles (such as the second control cycle mentioned above) (i.e. the second duration mentioned above), the duration of the low level phase (i.e. the third duration mentioned above) in EM cycle 1 (i.e. the first control cycle mentioned above) for anode resetting and EM cycle 1 after EM cycle 1 (i.e. the third control cycle mentioned above) is longer. Therefore, after completing the anode resetting, the electronic device can switch to the low level phase in advance to start charging the EL capacitor, the pixel circuit anode and other devices, thereby making the luminescence of the pixel in the first low level phase after the anode resetting equal to or close to the luminescence of the pixel in other low level phases; and, Fig. 9 As shown, the electronic device can enter the second low-level stage after the anode reset in advance to perform light compensation, thereby ensuring that the light emission in this stage is equal to or close to the light emission of the pixel in other low-level stages.

[0124] In some embodiments, Fig. 9 In the example shown, the duration of the low level phase in EM cycle 1 (ie, low level phase 1) and the duration of the low level phase in EM cycle 2 (ie, low level phase 2) may be the same or different, and so on.

[0125] Need to explain, this application Figure 5 , Figure 6 and Fig. 9 The example shown only uses the EM control signal using 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 120Hz, and the display cycle of one frame includes 12 EM cycles to illustrate the schematic diagram of the luminous effect of three possible EM control signals driving pixels. Figure 7 and Figure 8 The example shown only illustrates two possible schematic diagrams of the luminous effect of pixels driven by EM control signals, in which the EM control signal adopts 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 360Hz, and the display period of one frame includes 12 EM periods. In actual applications, there is no specific limitation on the type of specific luminous control signal, the dimming frequency of the luminous control signal, the display refresh rate and the anode reset frequency, which depend on the actual type, structure or material of the actual display screen.

[0126] It can be understood that based on the solution provided in Example 1 of the present application, the electronic device flexibly adopts non-uniform duty cycle configuration in each control period of the display cycle, such as making the duration of the low-level stage of some control periods with insufficient brightness longer than other low-level stages, to ensure that each pixel of the display screen can maintain normal light emission in each low-level stage, and make the light emission in each low-level stage the same or close, thereby ensuring uniform light emission in multiple low-level stages of the same display cycle.

[0127] For example, compared to Figure 2 The EM control signal shown, Figure 5 and Figure 7 The duration of the first low-level stage after the anode reset in the EM control signal shown is longer than that of other low-level stages. Therefore, after the EL capacitor, the anode of the pixel circuit and other devices are charged, there is still enough low-level duration to ensure the luminescence of the pixel in this stage, so that the luminescence is equal to or close to the luminescence of the pixel in other low-level stages. Based on this, compared with Figure 2 The display effect is shown as Figure 5 and Figure 7 As shown, in the first low-level stage after the anode reset, each pixel of the display screen emits light normally and the light-emitting effect is basically consistent with that of other low-level stages in the same display cycle.

[0128] For example, compared to Figure 2 The EM control signal shown, Figure 6 and Figure 8The first low-level stage after the anode is reset in the EM control signal shown is used to charge the EL capacitor, the pixel circuit anode and other devices, while the first low-level stage after the original anode is reset is used for luminescence. Therefore, after the EL capacitor, the pixel circuit anode and other devices are charged, there is still enough low-level duration to ensure the luminescence of the pixel in this stage, so that the luminescence is equal to or close to the luminescence of the pixel in other low-level stages. Based on this, compared with Figure 2 The display effect is shown. Figure 6 In the first EM cycle, each pixel of the display screen emits light normally and the light-emitting effect is basically consistent with that in other low-level stages of the same display cycle. Figure 8 In the first EM cycle, the fifth EM cycle and the ninth EM cycle, each pixel of the display screen emits light normally and the light-emitting effect is basically consistent with that in other low-level stages of the same display cycle.

[0129] For example, compared to Figure 2 The EM control signal shown, Fig. 9 The duration of the first low-level stage and the second low-level stage after the anode reset in the EM control signal shown is longer than that of other low-level stages. Therefore, after the charging of the EL capacitor, the anode of the pixel circuit and other devices is completed, there is still enough low-level duration to ensure the luminescence of the pixel in the first low-level stage, so that the luminescence is equal to or close to the luminescence of the pixel in other low-level stages; and by entering the second low-level stage after the anode reset in advance, it can be ensured that the luminescence in the second low-level stage is equal to or close to the luminescence of the pixel in other low-level stages. Based on this, compared to Figure 2 The display effect is shown as Fig. 9 As shown, in the first low level stage and the second low level stage after the anode reset, each pixel of the display screen emits light normally and the light-emitting effect is basically consistent with that of other low level stages of the same picture frame.

[0130] Embodiment 2:

[0131] In Embodiment 2, when the electronic device performs picture frame display based on the pixel circuit, the display cycle of one picture frame generally includes a plurality of continuous control cycles. Wherein, the pixel circuit includes a light-emitting control circuit and a reset circuit (such as a source reset circuit or a drain reset circuit of a driving thin film transistor (DTFT)), the light-emitting control circuit is configured to receive a light-emitting control signal, such as an EM control signal; the reset circuit is configured to receive a reset control signal, such as a source reset circuit configured to receive a source reset control signal, and a drain reset circuit configured to receive a drain reset control signal; that is, the pixel circuit can receive the EM control signal, and control the light emission according to the duration of the level stage not used for light emission and the duration of the level stage used for light emission in the plurality of control cycles; the reset circuit can control whether the plurality of control cycles are used for reset according to the reset control signal, such as controlling whether the plurality of control cycles are used for source reset according to the source reset control signal, or controlling whether the plurality of control cycles are used for drain reset according to the drain reset control signal.

[0132] In some embodiments, the display cycle of the pixel circuit includes multiple control cycles with the same duration, and the multiple control cycles all include a first level stage and a second level stage, that is, each control cycle includes a first level stage and a second level stage, wherein the first level stage is a level stage for resetting (such as a source reset circuit or a drain reset circuit), and the second level stage is a level stage for emitting light.

[0133] In some embodiments, the first level stage is a high level stage, and the second level stage is a low level stage; or, the first level stage is a low level stage, and the second level stage is a high level stage, which is not limited in the embodiments of the present application. The following embodiments take the first level stage as a high level stage, and the second level stage as a low level stage as an example.

[0134] In embodiment 1 of the present application, the electronic device configures the duration of the first level stage in multiple control cycles of the display cycle based on the reset frequency corresponding to the reset control signal and / or the display refresh rate corresponding to the light-emitting control signal, and then controls the light-emitting according to the duration of the first level stage and the duration of the second level stage in the multiple control cycles.

[0135] As an example, the multiple control cycles include a refresh frame cycle and a hold frame cycle, such as there may be one refresh frame cycle, and there may be one or more hold frame cycles. Among them, the refresh frame cycle is used for display refresh and gate reset, and the hold frame cycle is used to hold the display. The electronic device can perform differentiated driving in the refresh frame cycle and each hold frame cycle (for the case where there are multiple hold frame cycles) in the display cycle of the picture frame based on the reset frequency corresponding to the reset control signal and / or the display refresh rate corresponding to the light emitting control signal, such as adjusting the duration of the first level stage in each hold frame cycle based on different reset frequencies and / or different refresh rates.

[0136] Furthermore, after adjusting the duration of the first level stage in each holding frame cycle, the electronic device can perform display refresh and reset when entering the first level stage of the refresh frame cycle, and control light emission according to the duration of the first level stage and the duration of the second level stage in multiple control cycles (including refresh frame cycles and holding frame cycles), such as not emitting light when entering the first level stage of the refresh frame cycle, emitting light when entering the second level stage of the refresh frame cycle, and then not emitting light when entering the first level stage of the holding frame cycle, and emitting light when entering the second level stage of the holding frame cycle.

[0137] In some examples, the plurality of control periods include a refresh frame period but do not include a hold frame period. In this case, the electronic device may only set the duration of the first level phase in the refresh frame period.

[0138] For example, in Example 2, the duration of the first level stage (such as the high level stage) of the frame period in the display cycle can be reduced based on different reset frequencies and / or different display refresh rates, so that the duty cycle at different display refresh rates and / or different reset frequencies is maintained at a high level to optimize screen flicker, and the duty cycle at different display refresh rates and / or different reset frequencies is kept basically the same (such as the difference is less than a preset threshold) to achieve better display and eye protection effects.

[0139] In some embodiments, the solution provided in Example 2 can be applied to a scene where the screen brightness value is greater than a second brightness threshold, where the second brightness threshold is greater than the first brightness threshold. For example, the second brightness threshold is 90 nit, etc., that is, the solution provided in Example 2 can be applied to a high brightness scene, and the specific value of the second brightness threshold is not specifically limited.

[0140] It can be understood that, taking the light emitting control signal as an EM control signal as an example, the display period of a picture frame usually includes multiple EM periods. For example, the number of EM periods included in a display period is N=F1 / F2, where 1 EM period is a refresh frame period, N-1 EM periods are hold frame periods, F1 is the source reset frequency or the drain reset frequency, and F2 is the display refresh rate. Among them, display refresh, gate reset, source reset / drain reset, threshold compensation, etc. are usually performed in the refresh frame period of the display period, and display refresh, gate reset, source reset / drain reset, threshold compensation, etc. are usually not performed in the hold frame period of the display period.

[0141] Taking the case where the source reset frequency or the drain reset frequency is 360 Hz and the display refresh rate is 120 Hz as an example, N=360 Hz / 120 Hz=3, that is, the display period of one picture frame includes 3 EM periods, wherein the first EM period is the refresh frame period, and the other two EM periods are the hold frame periods; taking the case where the source reset frequency or the drain reset frequency is 360 Hz and the display refresh rate is 60 Hz as an example, N=360 Hz / 60 Hz=6, that is, the display period of one picture frame includes 6 EM periods, wherein the first EM period is the refresh frame period, and the other five EM periods are the hold frame periods; by analogy, taking the case where the source reset frequency or the drain reset frequency is 360 Hz and the display refresh rate is 1 Hz as an example, N=360 Hz / 1 Hz=360, that is, the display period of one picture frame includes 360 EM periods, wherein the first EM period is the refresh frame period, and the other 359 EM periods are the hold frame periods.

[0142] Taking the case where the source reset frequency or the drain reset frequency is 240 Hz and the display refresh rate is 120 Hz as an example, N=240 Hz / 120 Hz=2, that is, the display period of one picture frame includes 2 EM periods, wherein the first EM period is the refresh frame period, and the second EM period is the hold frame period; taking the case where the source reset frequency or the drain reset frequency is 240 Hz and the display refresh rate is 60 Hz as an example, N=240 Hz / 60 Hz=4, that is, the display period of one picture frame includes 4 EM periods, wherein the first EM period is the refresh frame period, and the other three EM periods are hold frame periods; by analogy, taking the case where the source reset frequency or the drain reset frequency is 240 Hz and the display refresh rate is 1 Hz as an example, N=240 Hz / 1 Hz=240, that is, the display period of one picture frame includes 240 EM periods, wherein the first EM period is the refresh frame period, and the other 239 EM periods are hold frame periods.

[0143] It should be noted that the embodiments of the present application do not limit whether the display period includes a frame retention period. In some cases, the display period of a picture frame may not include a frame retention period.

[0144] For example, taking the source reset frequency or the drain reset frequency being 120 Hz and the display refresh rate being 120 Hz as an example, N=120 Hz / 120 Hz=1, that is, the display period of one picture frame includes 1 EM period, and the 1 EM period is the refresh frame period; taking the source reset frequency or the drain reset frequency being 120 Hz and the display refresh rate being 60 Hz as an example, N=120 Hz / 60 Hz=2, that is, the display period of one picture frame includes 2 EM periods, wherein the first EM period is the refresh frame period, and the second EM period is the hold frame period; and so on, taking the source reset frequency or the drain reset frequency being 120 Hz and the display refresh rate being 1 Hz as an example, N=120 Hz / 1 Hz=120, that is, the display period of one picture frame includes 120 EM periods, wherein the first EM period is the refresh frame period, and the other 119 EM periods are hold frame periods.

[0145] In conventional methods, the duration of the first level stage (such as the high level stage) in the refresh frame period and the holding frame period is usually the same, and the duration of the second level stage (such as the low level stage) is usually the same, so as to ensure that the duration of the display screen lighting in the refresh frame period and the holding frame period is consistent, thereby achieving a uniform dimming effect. However, the conventional method takes a long time to perform display refresh, gate reset, source reset / drain reset, threshold compensation, etc. in the refresh frame period, resulting in a shortened total screen-on duration in the display period, which will lead to an increase in SVM, that is, the problem of excessive flickering of the screen.

[0146] In order to solve the above problems, in some embodiments, the electronic device can configure the duration of the first level stage (such as the high level stage) in the refresh frame period and the holding frame period to be less than the duration of the first level stage in the refresh frame period, and at the same time make the total duration of the second level stage in the display period equal or close under different display refresh rates / reset frequencies. It can be understood that after reducing the duration of the first level stage of the holding frame period, the duration of the second level stage of the holding frame period is increased accordingly, which can increase the total duration of the bright screen in the display period, thereby reducing SVM, optimizing screen flicker, and achieving better display and eye protection effects.

[0147] As an example, the electronic device can configure the duration of the first level phase of the refresh frame period in the display period to be the fourth duration, and configure the duration of the first level phase in the maintenance frame period to be the fifth duration, wherein the fifth duration is less than the fourth duration. Taking the fourth duration as 80H as an example, the fifth duration is a value between 36H-75H. In some embodiments, the difference between the fourth duration and the fifth duration is greater than or equal to 1H.

[0148] Taking the first level stage as a high level stage and the second level stage as a low level stage as an example, in some embodiments, the reduction in the duration of the high level stage in the frame period compared to the duration of the high level stage in the refresh frame period may be related to one or more of the following factors: specific attributes of the display screen, display refresh rate, source reset frequency or drain reset frequency, etc. Exemplarily, the specific attributes of the display screen include the type, structure or material of the display panel, etc.; the display refresh rate is not limited to 120Hz, 60Hz, 1Hz, etc.; the source reset frequency or drain reset frequency is not limited to 120Hz, 240Hz, 360Hz, etc.

[0149] In some embodiments, when other factors such as screen brightness value, specific properties of the display screen, and reset frequency remain unchanged, the adjustment range when adjusting the duration of the first level stage in the frame period varies with the display refresh rate.

[0150] As an example, when other factors such as screen brightness value, specific properties of the display screen and reset frequency remain unchanged, the duration of the high level phase in the refresh frame period of the display refresh rate of the first refresh rate is the fourth duration, and the duration of the high level phase in the frame period is the fifth duration, and the duration of the high level phase in the refresh frame period of the display refresh rate of the second refresh rate is the fourth duration, and the duration of the high level phase in the frame period is the sixth duration. Among them, the first refresh rate is greater than the second refresh rate, the sixth duration is greater than the fifth duration, and the fifth duration and the sixth duration are a value between 36H-75H.

[0151] When other factors such as the screen brightness value, specific properties of the display screen and display refresh rate remain unchanged, the adjustment range when adjusting the duration of the first level stage in the frame period varies with the reset frequency.

[0152] As an example, when other factors such as screen brightness value, specific attributes of the display screen and display refresh rate remain unchanged, the duration of the high level phase in the refresh frame period when the reset frequency is the first frequency is the fourth duration, and the duration of the high level phase in the holding frame period is the seventh duration, and the duration of the high level phase in the refresh frame period when the reset frequency is the second frequency is the fourth duration, and the duration of the high level phase in the holding frame period is the eighth duration. Among them, the first frequency is greater than the second frequency, the eighth duration is less than the fourth duration, the ninth duration is less than the fourth duration, the eighth duration is different from the ninth duration, and the eighth duration and the ninth duration are a value between 36H-75H. As an example, the eighth duration is less than or equal to the ninth duration.

[0153] For example, under a screen brightness value of 500nit, the EM control signal adopts 1440Hz PWM dimming, the reset frequency is 360Hz, the first level stage is a high level stage, the second level stage is a low level stage, and the duration of the high level stage in the refresh frame period is 80H. The duration of the high level stage in the refresh frame period and the hold frame period under different display refresh rates may be as shown in Table 1 below:

[0154] Table 1

[0155]

[0156] And, illustratively, taking the case where the screen brightness value is 500nit, the EM control signal adopts 1440Hz PWM dimming, the reset frequency is 240Hz, the first level stage is a high level stage, the second level stage is a low level stage, and the duration of the high level stage in the refresh frame period is 80H as an example, the duration of the high level stage in the refresh frame period and the hold frame period under different display refresh rates may be as shown in the following Table 2:

[0157] Table 2

[0158]

[0159] And, illustratively, taking the case where the screen brightness value is 500nit, the EM control signal adopts 1440Hz PWM dimming, the reset frequency is 120Hz, the first level stage is a high level stage, the second level stage is a low level stage, and the duration of the high level stage in the refresh frame period is 80H as an example, the duration of the high level stage in the refresh frame period and the hold frame period under different display refresh rates may be as shown in the following Table 3:

[0160] Table 3

[0161]

[0162] It should be noted that Tables 1, 2 and 3 are only example values ​​for dynamically adjusting the frame period under different reset frequencies and display refresh rates. In actual applications, the adjustment range of the frame period may be different from that of the refresh frame period. The embodiments of the present application do not make specific limitations and depend on the specific circumstances.

[0163] In addition, Tables 1, 2 and 3 respectively show example values ​​of dynamic adjustment for maintaining the frame period when the reset frequency is 360 Hz, 240 Hz and 120 Hz, and the display refresh rate is 120 Hz, 60 Hz and 1 Hz, respectively. In actual applications, the reset frequency may also be other frequencies such as 480 Hz, 600 Hz, 720 Hz, and the display refresh rate may also be other values ​​such as 180 Hz, 240 Hz, etc. The embodiments of the present application do not make specific limitations and depend on the specific circumstances.

[0164] It can be understood that after optimizing (such as shortening) the duration of the high-level phase in the frame period based on the solution provided in Example 2 of the present application, the duration of the high-level phase in the refresh frame period that requires display refresh, gate reset, source reset / drain reset, threshold compensation and other operations is longer than the maintenance frame period that does not require display refresh, gate reset, source reset / drain reset, threshold compensation and other operations. Based on this, not only can normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. be guaranteed in the refresh frame period, but also a high and comparable duty cycle can be maintained at different display refresh rates and / or different reset frequencies to optimize SVM and achieve better high-brightness display effects. For example, compared to similar Figure 3 The solution in which the duration of the high-level phase in each EM cycle of the display cycle is equal can achieve a higher duty cycle based on the solution provided in Example 2 of the present application. In addition, the solution provided in Example 2 of the present application maintains the difference in the duty cycle of the display cycle under different reset frequencies and / or different display refresh rates within a range of less than 0.2% by differentially configuring the duration of the high-level phase in the refresh frame cycle and the hold frame cycle.

[0165] For example, see Fig.10 , Fig.10 Taking the scheme shown in Table 1 as an example, a schematic diagram of the driving principle of an EM driving signal provided by an embodiment of the present application is shown. Taking the source reset frequency or the drain reset frequency as 360 Hz as an example, Fig.10 As shown, when the display refresh rate is 120 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 3 (i.e., N=360 Hz / 120 Hz=3) EM periods, of which 1 is a refresh frame period, and the other 2 (i.e., N-1=2) are hold frame periods; when the display refresh rate is 60 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 6 (i.e., N=360 Hz / 60 Hz=6) EM periods, of which 1 is a refresh frame period, and the other 5 (i.e., N-1=5) are hold frame periods; when the display refresh rate is 1 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 360 (i.e., N=360 Hz / 1 Hz=360) EM periods, of which 1 is a refresh frame period, and the other 359 (i.e., N-1=359) are hold frame periods. Since gate reset, source reset / drain reset, threshold compensation, etc. are not performed during the hold frame period, it is not necessary to maintain the same high level phase duration as that during the refresh frame period, such as Fig.10As shown, after optimizing (such as reducing) the duration of the high-level phase of the holding frame period based on the solution provided in Example 2 of the present application, the duration of the high-level phase in the refresh frame period that requires display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer than the holding frame period that does not require display refresh, gate reset, source reset / drain reset, etc. Based on this, not only can normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. in the refresh frame period be guaranteed, but also the difference in the duty cycle of the display period under different display refresh rates when the source reset frequency or the drain reset frequency is 360Hz can be maintained within a very small range by differentially configuring the duration of the high-level phase in the refresh frame period and the holding frame period.

[0166] As an example, the duty cycle r of the display period can be calculated based on the following formula: r = [120 / F2*number of light array rows-first duration-second duration*(F1 / F2-1)] / (120 / F2*number of light array rows), where F1 is the source reset frequency or the drain reset frequency, F2 is the display refresh rate, the number of light array rows is such as the number of screen light array rows, or for the case where the display screen includes front and rear corridor light arrays, the number of light array rows = the number of screen light array rows + the number of front and rear corridor light array rows.

[0167] As shown in Table 1, taking the number of rows of the light-emitting array as 3120 as an example, when the source reset frequency or the drain reset frequency is 360 Hz, after optimizing (such as reducing) the duration of the high-level stage in the frame period based on the solution provided in Example 2 of the present application, when the display refresh rate is 120 Hz, the duty cycle of the display screen is 95.13%, when the display refresh rate is 60 Hz, the duty cycle of the display screen is 95.11%, and when the display refresh rate is 1 Hz, the duty cycle of the display screen is 95.18%. The duty cycle can be maintained between 95.1% and 95.2%, which is comparable to similar Figure 3 The duty cycle (e.g., 94%) of the scheme shown is greatly improved. Since high-brightness scenes have high requirements for brightness values, the scheme shown in Table 1 can maintain a high duty cycle to optimize SVM and achieve better high-brightness display effects. In addition, as shown in Table 1, the difference in the duty cycle of the display cycle under different display refresh rates is maintained within a range of less than 0.2%, so it can be ensured that when the display refresh rate changes, the overall picture display effect is not much different for the user.

[0168] For example, please refer to Fig.11 , Fig.11 Taking the scheme shown in Table 2 as an example, a schematic diagram of the light emitting control principle of an EM control signal provided in an embodiment of the present application is shown. Taking the source reset frequency or the drain reset frequency as 240 Hz as an example, Fig.11As shown, when the display refresh rate is 120 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 2 (i.e., N=240 Hz / 120 Hz=2) EM periods, of which 1 is a refresh frame period, and the other 1 (i.e., N-1=1) is a hold frame period; when the display refresh rate is 60 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 4 (i.e., N=240 Hz / 60 Hz=4) EM periods, of which 1 is a refresh frame period, and the other 3 (i.e., N-1=3) are hold frame periods; when the display refresh rate is 1 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 240 (i.e., N=240 Hz / 1 Hz=240) EM periods, of which 1 is a refresh frame period, and the other 239 (i.e., N-1=239) are hold frame periods. Since gate reset, source reset / drain reset, threshold compensation, etc. are not performed during the hold frame period, it is not necessary to maintain the same high level phase duration as that during the refresh frame period, such as Fig.11 As shown, after optimizing (such as reducing) the duration of the high-level phase of the holding frame period based on the solution provided in Example 2 of the present application, the duration of the high-level phase in the refresh frame period that needs to perform tasks such as display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer than the holding frame period that does not need to perform tasks such as display refresh, gate reset, source reset / drain reset, threshold compensation, etc. Based on this, not only can the normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. in the refresh frame period be guaranteed, but also the difference in the duty cycle of the display period under different display refresh rates when the source reset frequency or the drain reset frequency is 240Hz can be maintained within a range of less than 0.2% by differentially configuring the duration of the high-level phase in the refresh frame period and the holding frame period.

[0169] As shown in Table 2, taking the number of rows of the light-emitting array as 3120 as an example, when the source reset frequency or the drain reset frequency is 240 Hz, after optimizing (such as shortening) the duration of the high-level stage in the frame period based on the solution provided in Example 2 of the present application, when the display refresh rate is 120 Hz, the duty cycle of the display screen is 96.28%, when the display refresh rate is 60 Hz, the duty cycle of the display screen is 96.27%, and when the display refresh rate is 1 Hz, the duty cycle of the display screen is 96.28%. The duty cycle can be maintained between 96.2% and 96.3%, which is comparable to similar Figure 3The duty cycle (e.g., 94.9%) of the scheme shown is greatly improved. Since high-brightness scenes have high requirements for brightness values, the scheme shown in Table 2 can maintain a high duty cycle to optimize SVM and achieve better high-brightness display effects. In addition, as shown in Table 2, the difference in the duty cycle of the display cycle under different display refresh rates is maintained within a range of less than 0.2%, so it can be ensured that when the display refresh rate changes, the overall picture display effect is not much different for the user.

[0170] For example, please refer to Fig.12 , Fig.12 Taking the scheme shown in Table 3 as an example, a schematic diagram of the driving principle of a light emitting control signal provided by an embodiment of the present application is shown. Taking the source reset frequency or the drain reset frequency as 120 Hz as an example, Fig.12 As shown, when the display refresh rate is 120 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 1 (i.e., N=120 Hz / 120 Hz=1) EM period, which is the refresh frame period; when the display refresh rate is 60 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 2 (i.e., N=120 Hz / 60 Hz=2) EM periods, one of which is the refresh frame period, and the other one (i.e., N-1=1) is the hold frame period; when the display refresh rate is 1 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 120 (i.e., N=120 Hz / 1 Hz=120) EM periods, one of which is the refresh frame period, and the other 119 (i.e., N-1=119) are the hold frame periods. Since gate reset, source reset / drain reset, threshold compensation, etc. are not performed during the hold frame period, it is not necessary to maintain the same high level phase duration as that during the refresh frame period, such as Fig.12 As shown, after optimizing (such as reducing) the duration of the high-level phase of the holding frame period based on the solution provided in Example 2 of the present application, the duration of the high-level phase in the refresh frame period that needs to perform tasks such as display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer than the holding frame period that does not need to perform tasks such as display refresh, gate reset, source reset / drain reset, threshold compensation, etc. Based on this, not only can the normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. in the refresh frame period be guaranteed, but also the difference in the duty cycle of the display period under different display refresh rates when the source reset frequency or the drain reset frequency is 120Hz can be maintained within a range of less than 0.2% by differentially configuring the duration of the high-level phase in the refresh frame period and the holding frame period.

[0171] As shown in Table 3, taking the number of rows of the light-emitting array as 3120 as an example, when the source reset frequency or the drain reset frequency is 120 Hz, after optimizing (such as reducing) the duration of the high-level stage in the frame period based on the solution provided in Example 2 of the present application, when the display refresh rate is 120 Hz, the duty cycle of the display screen is 97.44%, when the display refresh rate is 60 Hz, the duty cycle of the display screen is 97.60%, and when the display refresh rate is 1 Hz, the duty cycle of the display screen is 97.59%. The duty cycle can be maintained between 97.4% and 97.6%, which is comparable to similar Figure 3 The duty cycle of the scheme shown is greatly improved. Since high-brightness scenes have high requirements for brightness values, the scheme shown in Table 3 can maintain a high duty cycle to optimize SVM and achieve better high-brightness display effects. In addition, as shown in Table 3, the difference in the duty cycle of the display cycle under different display refresh rates is maintained within a range of less than 0.2%, so it can be ensured that when the display refresh rate changes, the overall picture display effect is not much different for the user.

[0172] Need to explain, Fig.10 , Fig.11 , Fig.12 Taking the case where the screen brightness value is 500nit, the EM control signal adopts 1440HzPWM dimming, and the duration of the high level phase of the refresh frame cycle is 80H as an example, a schematic diagram of the driving principle of the light-emitting control signal under different source reset frequencies or drain reset frequencies and different display refresh rates is shown. In actual applications, the screen brightness value can also be other values ​​such as 21nit, 249nit, 1200nit, the dimming frequency of the EM control signal can also be other values, and the duration of the high level phase of the refresh frame cycle can also be other values. The embodiments of the present application are not limited to these values ​​and depend on the specific circumstances.

[0173] As a possible implementation method, the process of driving the pixel circuit by the EM control signal can be divided into the following four stages:

[0174] Phase 1: Gate reset (also called "gate initialization") phase.

[0175] This stage 1 is usually performed in the first level stage of the refresh frame cycle. Taking the first level stage of the refresh frame cycle as a high level stage and the second level stage of the refresh frame cycle as a low level stage as an example, the gate reset stage is usually performed in the high level stage of the refresh frame cycle.

[0176] In some embodiments, the first level stage may also be used for data writing, such as interface data of a picture to be displayed, to perform display refresh, without limitation.

[0177] The pixel circuit is as follows Fig.13As shown, the driving timing of the pixel circuit corresponding to the refresh frame period is as follows Fig.14 As shown in the figure, the first level stage is a high level stage, and the second level stage is a low level stage. Please refer to Fig.14 , Fig.14 FIG. 1 shows a driving timing diagram of a pixel circuit provided by an embodiment of the present application. Fig.14 T1-T8 are thin film transistors (TFTs), and by way of example, Fig.14 As shown, T1 can be a DTFT, N1-N3 are nodes in the circuit, C1 is a capacitor, Em is the light-emitting control signal received by the circuit, S1n-S4n are the control signals received by the circuit for resetting and data writing, ELVDD and ELVSS are the operating voltages, Vinit1-Vinit3 are the reset voltages, and Vdata is used to control the current flowing through the TFT to drive the pixel circuit to emit light of different brightness. Fig.14 As shown, in the refresh frame period, Fig.13 As shown in the figure, EM first sets the high level to close the light path, and then S2n and S4n are switched from low level to high level in turn to achieve Fig.13 Shown is the initialization of the N1 node.

[0178] For example, during the refresh frame period, Fig.13 The switching frequency of the EM shown can be 360 ​​Hz, so the light emitting control circuit in the pixel circuit (such as Fig.13 The light emitting control signal received by the circuit (EM signal) and the circuit of the transistors T5 and T6 may be as follows: Fig.10 As shown; as shown, Fig.13 The switching frequency of the EM shown in the figure may be 240 Hz, so the light control signal received by the light control circuit may be as follows: Fig.11 As shown; as shown, Fig.13 The switching frequency of the EM shown in the figure may be 120 Hz, so the light control signal received by the light control circuit may be as follows: Fig.12 shown.

[0179] In some embodiments, Fig.13 The switching frequency of the EM shown may be the same as the drain reset frequency or the source reset frequency, but the embodiments of the present application are not limited thereto. For example, in some embodiments, the switching frequency of the EM may also be different from the drain reset frequency and the source reset frequency, depending on the specific circumstances.

[0180] Phase 2: Threshold compensation and data writing phase.

[0181] The stage 2 is mainly used for threshold compensation and data writing of T1. For example, T1 may be a DTFT, and the data may be brightness data.

[0182] The pixel circuit is as follows Fig.13 As shown, the driving timing of the pixel circuit corresponding to the refresh frame period is as follows Fig.14 As shown in FIG. 1 , the first level stage is a high level stage and the second level stage is a low level stage. Fig.14 As shown, in the refresh frame period, when S2n is set to high level and S1n is set to low level, Fig.13 The threshold of T1 is compensated and the brightness data is written. At this time, Vdata enters the N3 node through T2, then flows to T2 through T1 and is written to the N1 node through T3. In the process of Vdata passing through T1, the threshold of T1 is compensated, and the voltage corresponding to the brightness indicated by the brightness data is written to the gate N1 node of T1 to control the current flowing through T1 after the subsequent EM is turned on to achieve accurate light emission.

[0183] Phase 3: Drain and anode reset phase.

[0184] The pixel circuit is as follows Fig.13 As shown, the driving timing of the pixel circuit corresponding to the refresh frame period is as follows Fig.14 As shown in FIG. 1 , the first level stage is a high level stage and the second level stage is a low level stage. Fig.14 As shown, in the refresh frame period, when S3n is set to low level, Fig.13 The N2 node is shown to be reset.

[0185] For example, Fig.13 As shown, the switching frequency of S3n can be maintained at 360 Hz, that is, the reset frequency of the N2 node is 360 Hz, then the light control signal received by the light control circuit may be as follows: Fig.10 As shown; as shown, Fig.13 As shown, the switching frequency of S3n can be maintained at 240 Hz, that is, the reset frequency of the N2 node is 240 Hz, then the light control signal received by the light control circuit may be as follows: Fig.11 As shown; as shown, Fig.13 As shown, the switching frequency of S3n can be maintained at 120 Hz, that is, the reset frequency of the N2 node is 120 Hz, then the light control signal received by the light control circuit may be as follows: Fig.12 In the embodiment of the present application, when S3n is set to a low level, Fig.13 The circuit shown performs anode reset, and the anode reset frequency is consistent with the reset frequency of the N2 node, such as 360Hz. For example, different frequencies can be set according to different brightness. Fig.13 The voltage values ​​of Vinit2 and Vinit3 are shown to achieve the reset of the N2 node and the anode reset.

[0186] Phase 4: Lighting phase.

[0187] This stage 4 is usually carried out in the second level stage of the refresh frame cycle. Taking the first level stage of the refresh frame cycle as a high level stage, the second level stage of the refresh frame cycle as a low level stage, and the pixel emitting light in the low level stage as an example, the light-emitting stage is usually carried out in the low level stage.

[0188] The pixel circuit is as follows Fig.13 As shown, the driving timing of the pixel circuit corresponding to the refresh frame period is as follows Fig.14 As shown in FIG. 1 , the first level stage is a high level stage and the second level stage is a low level stage. Fig.14 As shown, during the refresh frame period, EM is set to low level and Fig.13 As shown, T5 and T6 are turned on, at which time the pixel emits light.

[0189] For example, during the refresh frame period, Fig.13 The switching frequency of the EM shown is the same as the drain reset frequency. For example, if it is 360 Hz, the light control signal received by the light control circuit may be as follows: Fig.10 As shown; as Fig.13 The switching frequency of the EM shown is the same as the drain reset frequency. For example, if it is 240 Hz, the light control signal received by the light control circuit may be as follows: Fig.11 As shown; as Fig.13 The switching frequency of the EM shown is the same as the drain reset frequency. For example, if it is 120Hz, the light control signal received by the light control circuit may be as follows: Fig.12 shown.

[0190] Need to explain, Fig.13 This is only an example of a pixel circuit. In practical applications, other types of pixel circuits may also be used; and, Fig.14 Only Fig.13 The pixel circuit shown is used as an example to introduce a possible driving timing example of a refresh frame. In practical applications, the pixel circuit can also use other driving timings to drive the pixel circuit. The embodiments of the present application do not limit the pixel circuit and driving timing, etc., which depends on the specific circumstances.

[0191] It is understandable that Fig.14 As shown, in the refresh frame period, due to the need to perform reset, threshold compensation, etc., the first level stage (such as the high level stage) needs to last for a long time. Fig.14As shown in 80H. In the holding frame period, since only light emission is required, and reset and threshold compensation are not required as in the refresh frame, the duration of the first level stage (such as the high level stage) of the holding frame period can be adaptively and dynamically adjusted compared to the refresh frame period. While ensuring the normal light emission of the pixel, the light emission duty cycle is increased to optimize the screen flicker, and the duty cycles under different display refresh rates and / or different reset frequencies are kept comparable (such as the difference is less than the preset threshold), avoiding flickering when the display refresh rate or reset frequency is switched, and achieving better display and eye protection effects.

[0192] For example, a pixel circuit such as Fig.13 As shown, the first level stage is a high level stage, the second level stage is a low level stage, the drain reset frequency (for some other pixel circuits, it may also be a source reset frequency) is 360 Hz, and the driving timing of the pixel circuit corresponding to the frame period may be as follows Fig.15 As shown. Fig.15 As shown, in the holding frame period, first Fig.13 The pixel circuit shown can set EM to a high level and keep S1n at a high level, S2n and S4n at a low level, and then Fig.13 The pixel circuit shown can be used when S3n is set to low level. Fig.13 As shown, T7 and T8 are turned on and last for 32 hours. After that, when EM is set to low level and S3n is kept high level, Fig.13 As shown, T5 and T6 are turned on and the pixel emits light. Based on this, compared to Fig.14 The driving timing of the refresh frame period shown in the figure can not only ensure the reset function of the pixel circuit in the frame period by reducing the duration of the first level stage (i.e., the high level stage) of the frame period from 80H to the range of 36H to 50H, but also improve the duty cycle to achieve a smaller SVM value (such as reduced to 0.23, etc., without limitation), thereby optimizing the screen flicker, and the difference in the total EM duty cycle at different display refresh rates is less than the preset threshold, such as the duty cycle is maintained between 95.1% and 95.2% as shown in Table 1, so as to achieve better display and eye protection effects.

[0193] As an example, taking the screen brightness value of 500nit, the EM control signal adopts 360Hz, the source reset frequency or the drain reset frequency is 360Hz, and the duration of the high level phase of the refresh frame cycle is 80H, as shown in Table 1, if the display refresh rate is 120Hz, the duration of maintaining the first level phase (such as the high level phase) of the frame cycle can be 36H; if the display refresh rate is 60Hz, the duration of maintaining the first level phase (such as the high level phase) of the frame cycle can be 45H; if the display refresh rate is 1Hz, the duration of maintaining the first level phase (such as the high level phase) of the frame cycle can be 50H.

[0194] Or, illustratively, with a pixel circuit such as Fig.13 As shown, the first level stage is a high level stage, the second level stage is a low level stage, and the drain reset frequency (for some other pixel circuits, it may also be a source reset frequency) is 240 Hz. For example, the driving timing of the pixel circuit corresponding to the frame period may be as follows Fig.16 As shown. Fig.16 As shown, in the holding frame period, first Fig.13 The pixel circuit shown can set EM to a high level and keep S1n at a high level, S2n and S4n at a low level, and then Fig.13 The pixel circuit shown can be used when S3n is set to low level. Fig.13 As shown, T7 and T8 are turned on and last for 32 hours. After that, when EM is set to low level and S3n is kept high level, Fig.13 As shown, T5 and T6 are turned on and the pixel emits light. Based on this, compared to Fig.14 The driving timing of the refresh frame period shown in the figure can not only ensure the reset function of the pixel circuit in the frame period by reducing the duration of the first level stage (i.e., the high level stage) of the frame period from 80H to the range of 36H to 58H, but also improve the duty cycle to achieve a smaller SVM value (such as reduced to 0.18, etc., without limitation), thereby optimizing the screen flicker, and the difference in the total EM duty cycle at different display refresh rates is less than the preset threshold, such as the duty cycle is maintained between 96.2% and 96.3% as shown in Table 2, so as to achieve better display and eye protection effects.

[0195] As an example, taking the screen brightness value of 500nit, the EM control signal adopts 240Hz, the source reset frequency or the drain reset frequency is 240Hz, and the duration of the high level stage in the refresh frame period is 80H, as shown in Table 2, if the display refresh rate is 120Hz, the duration of maintaining the first level stage (such as the high level stage) of the frame period can be 36H; if the display refresh rate is 60Hz, the duration of maintaining the first level stage (such as the high level stage) in the frame period can be 51H; if the display refresh rate is 1Hz, the duration of maintaining the first level stage (such as the high level stage) in the frame period can be 58H.

[0196] Or, for example, a pixel circuit of a display screen such as Fig.13 As shown, the first level stage is a high level stage, the second level stage is a low level stage, the drain reset frequency (for some other pixel circuits, it may also be a source reset frequency) is 120Hz, and the driving timing of the pixel circuit corresponding to the frame period may be as follows Fig.17 As shown. Fig.17 As shown, in the holding frame period, first Fig.13 The pixel circuit shown can set EM to a high level and keep S1n at a high level, S2n and S4n at a low level, and then Fig.13 The pixel circuit shown can be used when S3n is set to low level. Fig.13 As shown, T7 and T8 are turned on and last for 32 hours. After that, when EM is set to low level and S3n is kept high level, Fig.13 As shown, T5 and T6 are turned on and the pixel emits light. Based on this, compared to Fig.14 The driving timing of the refresh frame period shown in the figure can not only ensure the reset function of the pixel circuit in the frame period, but also improve the duty cycle to optimize the screen flicker, and the difference in the total EM duty cycle at different display refresh rates is less than the preset threshold, such as the duty ratio is maintained between 97.4% and 97.6% as shown in Table 3, so as to achieve better display and eye protection effects.

[0197] As an example, taking the screen brightness value of 500nit, the EM control signal adopts 120Hz, the source reset frequency or the drain reset frequency is 120Hz, and the duration of the high level stage in the refresh frame period is 80H, as shown in Table 3, if the display refresh rate is 60Hz, the duration of maintaining the first level stage (such as the high level stage) in the frame period can be 70H; if the display refresh rate is 1Hz, the duration of maintaining the first level stage (such as the high level stage) in the frame period can be 75H.

[0198] Need to explain, Fig.15 , Fig.16 , Fig.17 Only Fig.13 The pixel circuit shown is used as an example to introduce three different driving timing examples for maintaining frame periods. In practical applications, other types of pixel circuits can also be used, and other driving timings can also be used for specific pixel circuits to drive the pixel circuit. The embodiments of the present application do not limit the pixel circuit and driving timing, etc., which depends on the specific circumstances.

[0199] It should be understood that the various schemes of the embodiments of the present application can be used in reasonable combination, and the explanations or descriptions of the various terms appearing in the embodiments can be mutually referenced or explained in the various embodiments, without limitation.

[0200] It should also be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0201] It is understandable that, in order to implement the functions of any of the above-mentioned embodiments, the electronic device, etc., includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0202] In the embodiments of the present application, electronic devices and the like can be divided into functional modules. For example, each functional module can be divided into functional modules corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. For example, Fig.18 As shown, the display panel of the electronic device may include an integrated circuit 1810 (such as a driver IC), a gate driving unit 1820 and a pixel circuit 1830, wherein the pixel circuit 1830 includes a light-emitting control circuit and a reset circuit; the light-emitting control circuit is used to: receive a light-emitting control signal, and control light emission according to the duration of the first level stage and the duration of the second level stage in multiple control cycles; the reset circuit is used to: receive a reset control signal to control anode reset, gate reset, source reset or drain reset. The integrated circuit 1810 is used to: obtain a screen brightness value; and, when the screen brightness value is less than a first brightness threshold, configure the duration of the second level stage in multiple control cycles according to the first control cycle for anode reset; or when the screen brightness value is greater than the second brightness threshold, configure the duration of the first level stage in multiple control cycles according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal.

[0203] It should be noted that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. It should also be understood that each module in an electronic device, etc. can be implemented in software and / or hardware form, and there is no specific limitation on this. In other words, electronic devices, etc. are presented in the form of functional modules. The "module" here may refer to an application-specific integrated circuit ASIC, a circuit, a processor and memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions.

[0204] In an optional manner, when data transmission is implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is implemented in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disk (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0205] The steps of the method or algorithm described in conjunction with the embodiments of the present application can be implemented in a hardware manner or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM) memory, register, hard disk, mobile hard disk, compact disc read-only memory (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an application specific integrated circuit (ASIC). In addition, the ASIC can be located in an electronic device. Of course, the processor and the storage medium can also exist as discrete components.

[0206] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

Claims

1. A method for driving a pixel circuit, characterized in that: The display cycle of the pixel circuit includes a plurality of continuous control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a first control cycle, the first control cycle is used for anode reset, the pixel circuit includes a light emitting control circuit and an anode reset circuit, the anode reset circuit receives an anode reset control signal, and controls anode reset according to the first control cycle, and the method includes: Detect screen brightness value; When the screen brightness value is less than a first brightness threshold, configuring the duration of the second level stage in the plurality of control cycles according to the first control cycle; The light emitting control circuit receives a light emitting control signal and controls light emitting according to a duration of a first level stage and a duration of a second level stage in the plurality of control cycles.

2. The method according to claim 1, characterized in that The multiple control cycles also include a second control cycle, the second control cycle is not used for anode reset, and the configuring the duration of the second level stage in the multiple control cycles according to the first control cycle includes: The duration of the second level stage in the first control cycle is configured as a first duration, and the duration of the second level stage in the second control cycle is configured as a second duration, and the first duration is greater than the second duration.

3. The method according to claim 2, characterized in that The first control cycle includes at least one second level phase, and the first duration includes a total duration of the at least one second level phase in the first control cycle.

4. The method according to claim 2 or 3, characterized in that: The multiple control cycles also include a third control cycle, the third control cycle is a control cycle after the first control cycle, the third control cycle is not used for anode reset, and the duration of the second level stage in the multiple control cycles configured according to the first control cycle includes: The duration of the second level phase in the third control cycle is configured as a third duration, and the third duration is greater than the second duration.

5. The method according to claim 4, characterized in that The third control cycle includes at least one second level phase, and the third duration includes the total duration of at least one second level phase in the third control cycle.

6. The method according to claim 4 or 5, characterized in that: The third duration is less than or equal to the first duration.

7. The method according to any one of claims 1 to 6, characterized in that The first level stage is a high level stage, and the second level stage is a low level stage; or, The first level stage is a low level stage, and the second level stage is a high level stage.

8. The method according to any one of claims 1 to 7, characterized in that The first control cycle includes at least one control cycle; and / or, The second control cycle includes at least one control cycle; and / or, The third control period includes at least one control period.

9. A method for driving a pixel circuit, characterized in that: The display cycle of the pixel circuit includes a plurality of continuous control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a refresh frame period, the refresh frame period is used for display refresh and gate reset, the pixel circuit includes a light emitting control circuit and a reset circuit, the reset circuit receives a reset control signal, and controls gate reset and display refresh according to the refresh frame period, and the method includes: Detect screen brightness value; When the screen brightness value is greater than a second brightness threshold, configuring the duration of the first level stage in the multiple control cycles according to the display refresh rate corresponding to the light control signal and / or the reset frequency corresponding to the reset control signal; The light emitting control circuit receives a light emitting control signal and controls light emitting according to a duration of a first level stage and a duration of a second level stage in the plurality of control cycles.

10. The method according to claim 9, characterized in that The multiple control cycles also include a holding frame cycle, the holding frame cycle is used for display holding, the display refresh rate corresponding to the light emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the duration of the first level stage in the multiple control cycles is configured according to the display refresh rate corresponding to the light emitting control signal and / or the reset frequency corresponding to the reset control signal, including: The duration of the first level phase in the refresh frame period is configured as a fourth duration, and the duration of the first level phase in the hold frame period is configured as a fifth duration, and the fifth duration is shorter than the fourth duration.

11. The method according to claim 9, characterized in that The multiple control cycles also include a holding frame cycle, the holding frame cycle is used for display holding, the display refresh rate corresponding to the light emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the duration of the first level stage in the multiple control cycles is configured according to the display refresh rate corresponding to the light emitting control signal and / or the reset frequency corresponding to the reset control signal, including: The duration of the first level phase in the refresh frame period is configured as a fourth duration, and the duration of the first level phase in the hold frame period is configured as a sixth duration, wherein the sixth duration is less than the fourth duration and greater than the fifth duration.

12. The method according to any one of claims 9 to 11, characterized in that: The first level stage is a high level stage, and the second level stage is a low level stage; or, The first level stage is a low level stage, and the second level stage is a high level stage.

13. The method according to any one of claims 10 to 12, characterized in that: The refresh frame period includes a control period; and / or, The holding frame period includes at least one control period.

14. A display screen, characterized in that: The display screen includes an integrated circuit, a gate driving unit and a pixel circuit, the display cycle of the pixel circuit includes a plurality of continuous control cycles, the plurality of control cycles each include a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a first control cycle, the first control cycle is used for anode reset, and the pixel circuit includes a light emitting control circuit and an anode reset circuit; The anode reset circuit is used to: receive an anode reset control signal and control the anode reset according to the first control period; The integrated circuit is used to: obtain a screen brightness value; when the screen brightness value is less than a first brightness threshold, configure the duration of the second level stage in the plurality of control cycles according to the first control cycle; The light emitting control circuit is used to receive a light emitting control signal and control light emitting according to the duration of the first level stage and the duration of the second level stage in the multiple control cycles.

15. The display screen according to claim 14, characterized in that: The multiple control cycles further include a second control cycle, the second control cycle is not used for anode reset, and the integrated circuit is specifically used for: The duration of the second level stage in the first control cycle is configured as a first duration, and the duration of the second level stage in the second control cycle is configured as a second duration, and the first duration is greater than the second duration.

16. The display screen according to claim 15, characterized in that: The first control cycle includes at least one second level phase, and the first duration includes a total duration of the at least one second level phase in the first control cycle.

17. The display screen according to any one of claims 14 to 16, characterized in that: The multiple control cycles include a third control cycle, the third control cycle is a control cycle after the first control cycle, the third control cycle is used for anode reset, and the integrated circuit is further used for: The duration of the second level phase in the third control cycle is configured as a third duration, and the third duration is greater than the second duration.

18. The display screen according to claim 17, characterized in that: The third control cycle includes at least one second level phase, and the third duration includes the total duration of at least one second level phase in the third control cycle.

19. The display screen according to claim 17 or 18, characterized in that: The third duration is less than or equal to the first duration.

20. The display screen according to any one of claims 14 to 19, characterized in that: The first level stage is a high level stage, and the second level stage is a low level stage; or, The first level stage is a low level stage, and the second level stage is a high level stage.

21. The display screen according to any one of claims 14 to 20, characterized in that: The first control cycle includes at least one control cycle; and / or, The second control cycle includes at least one control cycle; and / or, The third control period includes at least one control period.

22. A display screen, characterized in that: The display screen includes an integrated circuit, a gate driving unit and a pixel circuit, the display cycle of the pixel circuit includes a plurality of continuous control cycles, the plurality of control cycles each include a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a refresh frame period, the refresh frame period is used for display refresh and gate reset, and the pixel circuit includes a light emitting control circuit and a reset circuit; The reset circuit is used to: receive a reset control signal, and control gate reset and display refresh according to the refresh frame period; The integrated circuit is used to: obtain a screen brightness value; and when the screen brightness value is greater than a second brightness threshold, configure the duration of the first level stage in the multiple control cycles according to the display refresh rate corresponding to the light control signal and / or the reset frequency corresponding to the reset control signal; The light emitting control circuit is used to receive a light emitting control signal and control light emitting according to the duration of the first level stage and the duration of the second level stage in the multiple control cycles.

23. The display screen according to claim 22, characterized in that: The multiple control periods further include a holding frame period, the holding frame period is used for display holding, the display refresh rate corresponding to the light emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically used for: The duration of the first level phase in the refresh frame period is configured as a fourth duration, and the duration of the first level phase in the hold frame period is configured as a fifth duration, and the fifth duration is shorter than the fourth duration.

24. The display screen according to claim 23, characterized in that: The multiple control periods further include a holding frame period, the holding frame period is used for display holding, the display refresh rate corresponding to the light emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically used for: The duration of the first level phase in the refresh frame period is configured as a fourth duration, and the duration of the first level phase in the hold frame period is configured as a sixth duration, wherein the sixth duration is less than the fourth duration, and the sixth duration is greater than the fifth duration.

25. The display screen according to any one of claims 22 to 24, characterized in that: The first level stage is a high level stage, and the second level stage is a low level stage; or, The first level stage is a low level stage, and the second level stage is a high level stage.

26. The display screen according to any one of claims 23 to 25, characterized in that: The refresh frame period includes a control period; and / or, The holding frame period includes at least one control period.

27. An electronic device, characterized in that: The electronic device comprises: Display screen, used for interface display; a memory for storing computer program instructions; A processor, configured to execute the computer program instructions to support the electronic device to implement the method as described in any one of claims 1-8 or 9-13.

28. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, which, when executed by a processing circuit, implement the method according to any one of claims 1-8 or 9-13.

29. A computer program product comprising instructions, characterized in that When the computer program product is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 8 or 9 to 13.

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