Shift register and driving method, gate driving circuit and display device

Abstract

Embodiments of the present disclosure provide a shift register and a driving method, a gate driving circuit and a display device. Relate to the technical field of display, for improving the display effect of display panel, the shift register comprises a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a first storage sub-circuit and a first control sub-circuit. The first input sub-circuit is coupled with a signal input end, a first node and a first clock signal end; the second input sub-circuit is coupled with the first node, a second node and the first clock signal end; the first output sub-circuit is coupled with a second clock signal end, the second node and a cascade signal output end; the first control sub-circuit is coupled with the second clock signal end, the cascade signal output end and the first node; the first control sub-circuit is configured to, in an output stage, in response to a working level at the cascade signal output end, transmit the working level received at the second clock signal end to the first node. The above-mentioned shift register is used for driving a pixel circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register and driving method, a gate driving circuit and a display device. BACKGROUND

[0002] With the development of display technology, display devices (such as mobile phones, notebook computers or tablet computers, etc.) are more and more applied to people's life. Among them, the organic light-emitting diode (English: Organic Light-Emitting Diode, for short: OLED) display device has the advantages of active light-emitting, wide viewing angle, high contrast, fast response speed, low power consumption, ultra-thin, etc., so it has attracted widespread attention. SUMMARY

[0003] Embodiments of the present disclosure aim to provide a shift register and driving method, a gate driving circuit and a display device, to improve the display effect of the display panel.

[0004] To achieve the above-mentioned purpose, embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a shift register is provided. The shift register includes a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a first storage sub-circuit, and a first control sub-circuit. The first input sub-circuit is coupled to a signal input terminal, a first node, and a first clock signal terminal; the first input sub-circuit is configured to, in an input phase, transmit a working level received at the signal input terminal to the first node in response to a first clock signal received at the first clock signal terminal; and in an output phase, cut off the signal input terminal and the first node in response to the first clock signal received at the first clock signal terminal; in the output phase, a non-working level is received at the signal input terminal; the first input sub-circuit includes a first transistor, and the first transistor is a low-temperature polysilicon transistor; the second input sub-circuit is coupled to the first node, a second node, and the first clock signal terminal; the second input sub-circuit is configured to, in the input phase, transmit a voltage at the first node to the second node in response to the first clock signal received at the first clock signal terminal, and in the output phase, cut off the first node and the second node in response to the first clock signal received at the first clock signal terminal; the second input sub-circuit includes a second transistor, and the second transistor is a low-temperature polysilicon transistor; the first output sub-circuit is coupled to a second clock signal terminal, the second node, and a cascade signal output terminal; the first output sub-circuit is configured to, in the input phase, transmit a non-working level received at the second clock signal terminal to the cascade signal output terminal under control of a voltage at the second node; and in the output phase, transmit a working level received at the second clock signal terminal to the cascade signal output terminal under control of the voltage at the second node; the first control sub-circuit is coupled to the second clock signal terminal, the cascade signal output terminal, and the first node; the first control sub-circuit is configured to, in the output phase, transmit a working level received at the second clock signal terminal to the first node in response to a working level at the cascade signal output terminal.

[0006] In the output phase, the first control sub-circuit transmits a signal received at the second clock signal terminal to the first node under control of a signal at the cascade signal output terminal, so that a source-drain voltage difference of a transistor included in the second input sub-circuit is small, a drain current of the transistor included in the second input sub-circuit is small or non-existent, thereby reducing the risk of leakage of the first node to the second node, improving the voltage stability at the second node, improving the stability of the on degree of a transistor included in the first output sub-circuit, improving the stability of a working level received at the cascade signal output terminal, and thereby improving the display effect of the display panel.

[0007] In some embodiments, the first control sub-circuit comprises a third transistor. A first pole of the third transistor is connected with the second clock signal end, a second pole is connected with the first node, and a control pole is connected with the cascade signal output end.

[0008] In some embodiments, the shift register further comprises a third input sub-circuit, a second control sub-circuit and a second output sub-circuit. The third input sub-circuit is coupled with a first voltage signal end, a third node and a fourth node; the third input sub-circuit is configured to, in the input stage, transmit a first voltage signal received at the first voltage signal end to the third node under the control of the voltage at the fourth node; the first voltage signal is a non-working level; the second control sub-circuit is coupled with the second node, the third node, the first voltage signal end, a second voltage signal end and a third clock signal end; the second control sub-circuit is configured to, in the holding stage, transmit a second voltage signal received at the second voltage signal end to the third node and transmit the first voltage signal received at the first voltage signal end to the second node in response to a third clock signal received at the third clock signal end; the second voltage signal is a working level; the second output sub-circuit is coupled with a third voltage signal end, the third node and the cascade signal output end; the second output sub-circuit is configured to, in the holding stage, transmit a third voltage signal received at the third voltage signal end to the cascade signal output end under the control of the voltage at the third node; the third voltage signal is a non-working level.

[0009] In some embodiments, the second control sub-circuit comprises a primary control sub-circuit and a secondary control sub-circuit. The primary control sub-circuit is coupled with the third node, the second voltage signal end and the third clock signal end; the primary control sub-circuit is configured to, in the holding stage, transmit the second voltage signal received at the second voltage signal end to the third node in response to a third clock signal received at the third clock signal end; the second voltage signal is a working level; the secondary control sub-circuit is coupled with the second node, the third node and the first voltage signal end; the secondary control sub-circuit is configured to, in the holding stage, transmit the first voltage signal received at the first voltage signal end to the second node under the control of the second voltage signal at the third node.

[0010] In some embodiments, the secondary control sub-circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit is coupled with the third node, the first voltage signal terminal and a fifth node; the first sub-circuit is configured to, in the output stage, cut off the first voltage signal terminal and the fifth node under the control of the voltage at the third node; the first sub-circuit includes a fourth transistor, and the fourth transistor is a low-temperature polysilicon transistor; the second sub-circuit is coupled with the second node, the third node and the fifth node; the second sub-circuit is configured to, in the output stage, cut off the fifth node and the second node under the control of the voltage at the third node; the second sub-circuit includes a fifth transistor, and the fifth transistor is a low-temperature polysilicon transistor. The secondary control sub-circuit further includes a tertiary control sub-circuit, which is coupled with the fifth node, the second node and the second voltage signal terminal; the tertiary control sub-circuit is configured to, in the output stage, transmit a second voltage signal received at the second voltage signal terminal to the fifth node under the control of the voltage at the second node.

[0011] In some embodiments, the primary control sub-circuit includes a sixth transistor. The first pole of the sixth transistor is connected with the second voltage signal terminal, the second pole is connected with the third node, and the control pole is connected with the third clock signal terminal.

[0012] In some embodiments, the fourth node is connected with the signal input terminal, or the fourth node is connected with the first node, or the fourth node is connected with the fifth node.

[0013] In some embodiments, the first output sub-circuit includes a seventh transistor, the first pole of the seventh transistor is connected with the second clock signal terminal, the second pole is connected with the cascade signal output terminal, and the control pole is connected with the second node; the third input sub-circuit includes an eighth transistor, the first pole of the eighth transistor is connected with the first voltage signal terminal, the second pole is connected with the cascade signal output terminal, and the control pole is connected with the fourth node; the second output sub-circuit includes a ninth transistor, the first pole of the ninth transistor is connected with the third voltage signal terminal, the second pole is connected with the cascade signal output terminal, and the control pole is connected with the third node; the tertiary control sub-circuit includes a tenth transistor, the first pole of the tenth transistor is connected with the second voltage signal terminal, the second pole is connected with the fifth node, and the control pole is connected with the second node; the first storage sub-circuit further includes a first storage capacitor, the first plate of the first storage capacitor is coupled with the second node, and the second plate is coupled with the cascade signal output terminal.

[0014] In another aspect, a gate drive circuit is provided. The gate drive circuit includes a plurality of cascaded shift registers as described in any of the above embodiments.

[0015] In some embodiments, the shift register is connected with a first clock signal terminal, a second clock signal terminal and a third clock signal terminal; the gate drive circuit further includes a plurality of clock signal lines, the plurality of clock signal lines are divided into a plurality of groups, in the same group, the clock signal line connected with the second clock signal terminal in the upper shift register of the adjacent two shift registers is the same as the clock signal line connected with the first clock signal terminal in the lower shift register, the clock signal line connected with the third clock signal terminal in the upper shift register is the same as the clock signal line connected with the second clock signal terminal in the lower shift register, the clock signal line connected with the first clock signal terminal in the upper shift register is different from the clock signal line connected with the third clock signal terminal in the lower shift register, and the clock signal line connected with the same clock signal terminal in any two shift registers is different.

[0016] In some embodiments, the gate drive circuit further includes a first voltage signal line and a second voltage signal line. The first voltage signal line is connected with the first voltage signal terminal and the shift register; the second voltage signal line is connected with the third voltage signal terminal and the shift register; the width of the first voltage signal line is smaller than the width of the second voltage signal line.

[0017] In some embodiments, the width of the first voltage signal line is 3-10 μm; and / or, the width of the second voltage signal line is 10-20 μm.

[0018] In some embodiments, the plurality of shift registers are arranged in intervals along a second direction; the shift register includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the first voltage signal line extends along the second direction, and along the first direction, the first voltage signal line is located between the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor and the tenth transistor, and the seventh transistor and the ninth transistor; the second voltage signal line extends along the second direction, and along the first direction, the second voltage signal line is located on the side of the seventh transistor and the ninth transistor away from the first voltage signal line; the second direction intersects the first direction.

[0019] In some embodiments, the shift register further comprises a first storage capacitor; the first storage capacitor is located at a side of the seventh transistor and the ninth transistor, away from the first voltage signal line, a normal projection of the second voltage signal line on a reference plane overlaps with a normal projection of the first storage capacitor on the reference plane; along the first direction, two ends of the first storage capacitor are beyond two ends of the second voltage signal line.

[0020] In some embodiments, the clock signal line extends along a second direction, and the clock signal line is located at a side of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor and the tenth transistor, away from the first voltage signal line;

[0021] The gate drive circuit further comprises a third voltage signal line connected with the second voltage signal end and the shift register, the third voltage signal line extends along the second direction and is located between the clock signal line and the shift register.

[0022] In some embodiments, the fourth transistor and the fifth transistor are located between the first transistor, the second transistor, the third transistor, the sixth transistor, the eighth transistor and the tenth transistor and the first voltage signal line, along the second direction, the fourth transistor is located at a side of the fifth transistor; and / or, the third transistor and the sixth transistor are located between the first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor and the tenth transistor and the third voltage signal line, along the second direction, the third transistor is located at a side of the sixth transistor.

[0023] In some embodiments, the eighth transistor is located between the fourth transistor and the fifth transistor and the third transistor and the sixth transistor, and is located at a side of the first transistor, the second transistor and the tenth transistor, away from the next level of the shift register; the fourth transistor is located at a side of the fifth transistor, away from the next level of the shift register, and the ninth transistor is located at a side of the seventh transistor, away from the next level of the shift register; the gate drive circuit further comprises a first connection line connected with a gate of the third transistor, a second electrode of the seventh transistor and a first electrode of the next level of the first transistor; the first connection line is located at a side of the first transistor, the second transistor, the fourth transistor, the fifth transistor and the tenth transistor, close to the next level of the shift register.

[0024] In some embodiments, along the first direction, the channel portion of the first transistor is located on the side of the channel portion of the second transistor close to the upper stage of the shift register, and along the second direction, the channel portion of the first transistor is located on the side of the channel portion of the second transistor away from the first voltage signal line; the channel portion of the third transistor is located on the side of the channel portions of the first transistor and the second transistor away from the first voltage signal line.

[0025] In another aspect, a display device is provided. The display device includes the shift register according to any one of the above embodiments, or the gate driving circuit according to any one of the above embodiments.

[0026] In another aspect, a driving method of a shift register is provided, for driving the shift register according to any one of the above embodiments. One display frame period includes an input stage and an output stage; in the input stage, a first input sub-circuit transmits the working level received at a signal input end to the first node in response to a first clock signal received at a first clock signal end; a second input sub-circuit transmits the working level at the first node to a second node in response to the first clock signal received at the first clock signal end; a first storage sub-circuit stores the working level at the second node; a first output sub-circuit transmits a non-working level received at a second clock signal end to the cascade signal output end under the control of the working level at the second node; in the output stage, the first input sub-circuit cuts off the signal input end and the first node in response to the first clock signal received at the first clock signal end, and the signal received at the signal input end is the non-working level; the second input sub-circuit cuts off the first node and the second node in response to the first clock signal received at the first clock signal end; the first output sub-circuit transmits the working level received at the second clock signal end to the cascade signal output end under the control of the working level at the second node; the first storage sub-circuit writes the difference between the working level and the non-working level received at the second clock signal end into the second node; and a first control sub-circuit transmits the working level received at the cascade signal output end to the first node under the control of the working level at the cascade signal output end.

[0027] In some embodiments, one display frame period further comprises a holding stage located after the output stage; in the input stage, under the control of the voltage at the fourth node, the third input sub-circuit transmits the first voltage signal received at the first voltage signal terminal to the third node, under the control of the first voltage signal at the third node, the second output sub-circuit cuts off the third voltage signal terminal and the cascade signal output terminal; the second control sub-circuit controls the third voltage signal terminal and the third node to be cut off in response to the third clock signal received at the third clock signal terminal, and under the control of the first voltage signal at the third node, the second control sub-circuit cuts off the first voltage signal terminal and the second node; in the output stage, the second control sub-circuit controls the second voltage signal terminal and the third node to be cut off in response to the third clock signal received at the third clock signal terminal, under the control of the first voltage signal at the third node, the second output sub-circuit cuts off the third voltage signal terminal and the cascade signal output terminal, and the second control sub-circuit cuts off the first voltage signal terminal and the second node; in the holding stage, the second control sub-circuit transmits the second voltage signal received at the second voltage signal terminal to the third node and transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the third clock signal received at the third clock signal terminal; under the control of the first voltage signal at the second node, the first output sub-circuit cuts off the second clock signal terminal and the cascade signal output terminal; under the control of the second voltage signal at the third node, the second output sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the cascade signal output terminal.

[0028] In some embodiments, in the output stage, under the control of the second voltage signal at the third node, the first sub-circuit controls the second voltage signal terminal and the fifth node to be cut off, and the second sub-circuit controls the fifth node and the second node to be cut off; under the control of the voltage at the second node, the third control sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the fifth node. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0030] Figure 1A structural diagram of a display device according to some embodiments;

[0031] Figure 2 Another structural diagram of a display device according to some embodiments;

[0032] Figure 3 A structural diagram of a display device including a display panel according to some embodiments;

[0033] Figure 4 A structural diagram of a display panel according to some embodiments;

[0034] Figure 5 A structural diagram of a gate driver circuit according to some embodiments;

[0035] Figure 6 A structural diagram of an input circuit according to some embodiments;

[0036] Figure 7 A structural diagram of an input circuit including a transistor and a capacitor according to some embodiments;

[0037] Figure 8 A timing diagram of an input circuit according to some embodiments;

[0038] Figure 9 Another structural diagram of an input circuit according to some embodiments;

[0039] Figure 10 Yet another structural diagram of an input circuit according to some embodiments;

[0040] Figure 11 A structural diagram of Figure 4 A partial enlarged view of C in FIG. 9;

[0041] Figure 12 A structural diagram of a transistor included in an input circuit according to some embodiments in which the transistor is turned on;

[0042] Figure 13 Another structural diagram of a transistor included in an input circuit according to some embodiments in which the transistor is turned on;

[0043] Figure 14 Yet another structural diagram of a transistor included in an input circuit according to some embodiments in which the transistor is turned on;

[0044] Figure 15 Yet another structural diagram of a transistor included in an input circuit according to some embodiments in which the transistor is turned on;

[0045] Figure 16 Yet another structural diagram of a transistor included in an input circuit according to some embodiments in which the transistor is turned on. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0047] Unless otherwise required by context, the term "comprise" and its other forms such as "comprises" and "comprising" are to be construed as open, inclusive, meaning that "comprising" does not exclude additional, unrecited elements. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0048] Hereinafter, the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0049] In describing some embodiments, "coupled" and "connected" and their derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0050] “A, B, and C at least one of” has the same meaning as “at least one of A, B, or C,” and includes the following combinations: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, the term “if’ is optionally interpreted as meaning “when” or “while” or “in response to a determination” or “in response to a detection of,” depending on the context. Similarly, the phrase “if determined” or “if detected [a stated condition or event]” is optionally interpreted as meaning “upon a determination” or “in response to a determination” or “upon a detection of [a stated condition or event]” or “in response to a detection of [a stated condition or event],” depending on the context.

[0053] Use of “adapted to” or “configured to” herein means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0054] Additionally, use of “based on” means open and inclusive, as a process, step, calculation, or other action that is “based on” one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0055] As used herein, “about,” “approximately,” or “circa” includes the recited value and average values within a range of acceptable deviation from the stated value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, “parallel,” “perpendicular,” and “equal” include the recited condition and conditions that approximate the recited condition, within a range of acceptable deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallel and near parallel, where near parallel can have an acceptable deviation range of, for example, within 5°; “perpendicular” includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable deviation range of, for example, within 5°. “Equal” includes absolute equality and near equality, where near equality can have an acceptable deviation range of, for example, a difference between the two that is less than or equal to 5% of either.

[0057] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0058] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region that would be formed by a given manufacturing technique. The purpose of such illustrations is to more effectively illustrate the embodiments described herein.

[0059] In embodiments of the present disclosure, the capacitor can be a capacitor device fabricated separately by a process, for example, by fabricating a special capacitor electrode, each capacitor electrode of the capacitor can be implemented by a metal layer, a semiconductor layer (for example, doped polysilicon), or the like. The capacitor can also be a parasitic capacitor between transistors, or implemented by a transistor itself and other devices, lines, or implemented by using a parasitic capacitor between lines of a circuit itself.

[0060] In the circuit provided by embodiments of the present disclosure, the first node, the second node, the third node, the fourth node and the fifth node do not represent actual existing components, but represent the convergence points of relevant electrical connections in the circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram.

[0061] The "working level" of the shift register provided in embodiments of the present disclosure refers to a level capable of turning on the operated transistor included therein, and accordingly, the "non-working level" refers to a level incapable of turning on the operated transistor included therein (i.e., the transistor is turned off).

[0062] The control electrode of each transistor provided in embodiments of the present disclosure is the gate of the transistor, the first electrode is one of the source and the drain of the transistor, and the second electrode is the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain of the transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in embodiments of the present disclosure can be indistinguishable in structure. For example, in the case of a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0063] As Figure 1 shown, some embodiments of the present disclosure provide a display device 1000, which can be any device displaying anything whether moving (e.g., video) or fixed (e.g., still image) and whether text or image.

[0064] Exemplarily, the display device 1000 can be any product or component having display function such as television, notebook computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, vehicle display, flight display, projection device, etc.

[0065] In some examples, as Figure 1 shown, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as Figure 1 shown.

[0066] In yet some examples, as Figure 2 shown, the display device 1000 can be a wearable device. For example, the display device can be a watch as Figure 2 shown.

[0067] In some embodiments, as Figure 3 shown, the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300 and a cover plate 400.

[0068] The display panel 100 has opposite light emitting side 100A and non-light emitting side 100B. The light emitting side 100A refers to a side (the upper side of the display panel 100 in Figure 3 ) on which the display panel 100 can emit light. The non-light emitting side 100B refers to the other side (the lower side of the display panel 100 in Figure 3 ) opposite to the light emitting side 100A.

[0069] The driving circuit board 200 is disposed on the non-light emitting side of the display panel 100 and connected with the display panel 100 to provide light emitting signal to the display panel 100.

[0070] The housing 300 can be a box-shaped structure having an opening. The display panel 100 and the driving circuit board 200 can be disposed in the housing 300. The cover plate 400 is disposed on the light emitting side of the display panel 100 and located at the opening of the housing 300.

[0071] As Figure 3As shown, the longitudinal section of the shell 300 can be in a U shape, the display panel 100 and the driving circuit board 200 are arranged in the shell 300, and the cover plate 400 is arranged at the opening of the shell 300.

[0072] The type of the display panel 100 described above includes various types, which can be selected and arranged according to actual needs.

[0073] Exemplarily, the display panel 100 described above can be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel, or a mini / micro light-emitting display (MLED) display panel, etc., which is not specifically limited in the embodiments of the present disclosure.

[0074] For example, the Micro LED refers to an LED with a size (e.g., length) less than 50 μm, and the Mini LED refers to an LED with a size (e.g., length) of 50 μm to 200 μm.

[0075] As shown, Figure 4 The display panel 100 has a display area AA and a peripheral area BB arranged at least on one side of the display area AA. Figure 3 For example, the peripheral area BB surrounds the display area AA.

[0076] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel.

[0077] In some embodiments, as shown, Figure 4 The display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.

[0078] The material used in the substrate 10 can include a polymer resin or glass. For example, the substrate 10 can be flexible, and the material used in the substrate 10 can include one of a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formic acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenyl sulfide granula (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). For example, the substrate 10 can be rigid, and the material used in the substrate 10 can include a glass material including SiO2 as a main component.

[0079] As shown in Figure 4 The plurality of sub-pixels 20 are arranged on the substrate 10 and located in the display area AA.

[0080] The plurality of sub-pixels 20 can include a first sub-pixel with a first color, a second sub-pixel with a second color, and a third sub-pixel with a third color. The first color, the second color, and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green, which are not limited in the embodiments of the present disclosure.

[0081] In some examples, the plurality of sub-pixels 20 can be arranged in multiple rows and multiple columns, each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0082] In some embodiments, as shown in Figure 4 The display panel 100 can further include a plurality of gate lines GL and a plurality of data lines DL.

[0083] The plurality of gate lines GL extend along the first direction X and are arranged at intervals along the second direction Y, and one gate line GL is connected to at least one row of sub-pixels 20. For example, one gate line GL is connected to one row of sub-pixels 20.

[0084] Multiple data lines DL extend along the second direction Y and are spaced apart along the first direction X. Each data line DL is connected to at least one column of sub-pixels 20. For example, one data line DL is connected to one column of sub-pixels 20.

[0085] In some embodiments, such as Figure 4 As shown, the display panel 100 also includes a gate driving circuit 30. The gate driving circuit 30 is located on the side of the substrate 10 near the sub-pixel 20 and is located in the peripheral region BB. The gate driving circuit 30 is connected to the gate line GL. In this way, the gate driving circuit 30 can transmit signals to the sub-pixel 20 to drive the sub-pixel 20 to display normally.

[0086] In some examples, such as Figure 4 As shown, the display panel 100 has a gate driving circuit 30 on one side of the peripheral area BB, which drives each gate line GL sequentially from one side, that is, the gate driving circuit is driven on one side.

[0087] In other examples, the display panel 100 may have gate drive circuits 30 on two sides in the peripheral area BB along the extension direction of the gate line GL, and the two gate drive circuits 30 simultaneously drive each gate line GL row by row from both sides, that is, the gate drive circuits 30 are dual-sided drive.

[0088] In some other examples, the display panel 100 may have two gate drive circuits 30 on each side of the peripheral area BB along the extension direction of the gate line GL. The two gate drive circuits 30 alternately drive each gate line GL from both sides row by row, that is, the gate drive circuits 30 are cross-driven.

[0089] In some embodiments, such as Figure 4 As shown, the gate drive circuit 30 includes N cascaded shift registers RS. In this case, the display panel 100 includes N cascaded shift registers RS, each connected to one of the N gate lines GL, where N is a positive integer.

[0090] For the shift register RS ​​described above, in some embodiments, such as Figure 4 As shown, the shift register RS ​​of the gate drive circuit 30 includes a scan signal output terminal OUTPUT1, which is connected to the gate line GL. Thus, the scan signal output terminal OUTPUT1 outputs the gate scan signal to the sub-pixel 20 through the gate line GL connected to it.

[0091] In some embodiments, the scan signal output terminal OUTPUT1 can also be connected to a lower stage shift register RS to pass a cascade signal to the lower stage shift register RS as an input signal of the lower stage shift register RS on the basis that the shift register RS comprises the scan signal output terminal OUTPUT1. That is, the scan signal output terminal OUTPUT1 also serves as a cascade signal output terminal OUTPUT2, and the scan signal output terminal OUTPUT1 and the cascade signal output terminal OUTPUT2 are the same signal output terminal.

[0092] In some embodiments, the scan signal output terminal OUTPUT1 can also be connected to a lower stage shift register RS to pass a cascade signal to the lower stage shift register RS as an input signal of the lower stage shift register RS on the basis that the shift register RS comprises the scan signal output terminal OUTPUT1. That is, the scan signal output terminal OUTPUT1 also serves as a cascade signal output terminal OUTPUT2, and the scan signal output terminal OUTPUT1 and the cascade signal output terminal OUTPUT2 are the same signal output terminal.

[0093] In some embodiments, as shown in FIG. 2, the shift register RS of the gate drive circuit 30 further comprises a signal input terminal INPUT. In each of two adjacent shift registers RS, the cascade signal output terminal OUTPUT2 of an upper stage shift register RS is connected to the signal input terminal INPUT of a lower stage shift register RS, and the signal input terminal INPUT of the first stage shift register RS is connected to the initialization signal terminal STV. Figure 4

[0094] Based on the above structure, the cascade structure of each stage shift register RS in the gate drive circuit 30 can be as follows:

[0095] In each of two adjacent shift registers RS, the signal input terminal INPUT of a lower stage shift register RS is connected to the cascade signal output terminal OUTPUT2 of an upper stage shift register RS, and the signal input terminal INPUT of the first stage shift register RS is connected to the signal input terminal STV. The scan signal output terminal OUTPUT1 of each stage shift register RS is connected to at least one gate line GL.

[0096] In some examples, the N stage cascade shift registers RS are arranged at intervals along the second direction Y.

[0097] In some embodiments, as shown in FIG. 2, the shift register RS comprises an input circuit RS1, a noise removal control circuit RS2, a noise removal circuit RS3, and an output circuit RS4. Figure 5

[0098] In some embodiments, as shown in FIG. 2, the shift register RS comprises an input circuit RS1, a noise removal control circuit RS2, a noise removal circuit RS3, and an output circuit RS4. Figure 6 Figure 7 ​​​​​​​​​​As shown, the input circuit RS1 includes a first input sub-circuit 1, a second input sub-circuit 2, a first output sub-circuit 3 and a first storage sub-circuit 4.

[0099] In some examples, as shown in Figure 6 and Figure 7 the first input sub-circuit 1 is coupled with a signal input terminal INPUT, a first node N1 and a first clock signal terminal CK1. The first input sub-circuit 1 is configured to, in an input phase P1, transfer a working level received at the signal input terminal INPUT to the first node N1 in response to a first clock signal received at the first clock signal terminal CK1, and in an output phase P2, cut off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, a non-working level being received at the signal input terminal INPUT in the output phase P2.

[0100] Exemplarily, as shown in Figure 6 and Figure 7 the first input sub-circuit 1 includes a first transistor T1, a first electrode of the first transistor T1 being connected with the signal input terminal INPUT, a second electrode being connected with the first node N1, and a control electrode being connected with the first clock signal terminal CK1.

[0101] In some examples, as shown in Figure 6 and Figure 7 the second input sub-circuit 2 is coupled with the first node N1, a second node N2 and the first clock signal terminal CK1. The second input sub-circuit 2 is configured to, in the input phase P1, transfer a working level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal terminal CK1, and in the output phase P2, cut off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1.

[0102] Exemplarily, as shown in Figure 6 and Figure 7 the second input sub-circuit 2 includes a second transistor T2, a first electrode of the second transistor T2 being connected with the first node N1, a second electrode being connected with the second node N2, and a control electrode being connected with the first clock signal terminal CK1.

[0103] In this way, the first transistor T1 and the second transistor T2 form a double-gate transistor, which can reduce the leakage current.

[0104] In some examples, as shown in Figure 6 and Figure 7As shown in the figure, the first output sub-circuit 3 is coupled with the second clock signal terminal CK2, the second node N2 and the cascade signal output terminal OUTPUT2. The first output sub-circuit 3 is configured to, in the input phase P1, transfer the non-working level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2 under the control of the voltage at the second node N2, and in the output phase P2, transfer the working level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2 under the control of the voltage at the second node N2.

[0105] As shown in the figure, Figure 7 As shown in the figure, the first output sub-circuit 3 includes a seventh transistor T7, the first electrode of which is connected with the second clock signal terminal CK2, the second electrode is connected with the cascade signal output terminal OUTPUT2, and the control electrode is connected with the second node N2.

[0106] As shown in the figure, Figure 6 and Figure 7 As shown in the figure, the first storage sub-circuit 4 is coupled with the second node N2 and the cascade signal output terminal OUTPUT2. The first storage sub-circuit 4 is configured to, in the input phase P1, store the voltage at the second node N2, and in the output phase P2, write the difference between the working level and the non-working level received at the second clock signal terminal CK2 into the second node N2.

[0107] As shown in the figure, Figure 7 As shown in the figure, the first storage sub-circuit 4 includes a first storage capacitor C1, the first plate of which is connected with the second node N2, and the second plate is connected with the cascade signal output terminal OUTPUT2.

[0108] Based on the above structure, as shown in the figure, Figure 8 In the input phase P1, the first input sub-circuit 1 transfers the working level received at the signal input terminal INPUT to the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, the second input sub-circuit 2 transfers the working level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal terminal CK1, the first storage sub-circuit 4 stores the working level at the second node N2, and the first output sub-circuit 3 transfers the non-working level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2 under the control of the working level at the second node N2.

[0109] In the output stage P2, the first input sub-circuit 1 cuts off the signal input end INPUT and the first node N1 in response to the first clock signal received at the first clock signal end CK1, the signal received at the signal input end INPUT is at the non-working level. The second input sub-circuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal end CK1, the first output sub-circuit 3 transmits the working level received at the second clock signal end CK2 to the cascade signal output end OUTPUT2 under the control of the working level at the second node N2, and the first storage sub-circuit 4 writes the difference between the working level and the non-working level received at the second clock signal end CK2 into the second node N2.

[0110] In some examples, the working level received at the signal input end INPUT is a low level, for example, the working level received at the signal input end INPUT is Vss, and the non-working level received at the signal input end INPUT is a high level, for example, the non-working level received at the signal input end INPUT is Vdd. The working level received at the second clock signal end CK2 is a low level, for example, the working level received at the second clock signal end CK2 is Vss, and the non-working level received at the second clock signal end CK2 is a high level, for example, the non-working level received at the second clock signal end CK2 is Vdd.

[0111] At this time, in the input stage P1, the Vss signal received at the signal input end INPUT is transmitted to the first node N1 through the first input sub-circuit 1, the Vss signal received at the first node N1 is transmitted to the second node N2, and is stored in the first storage sub-circuit 4, and the Vdd signal received at the second clock signal end CK2 is transmitted to the cascade signal output end OUTPUT2 through the first output sub-circuit 3 under the control of the Vss signal received at the second node N2.

[0112] In the output stage P2, the Vdd signal received at the signal input end INPUT cannot be transmitted to the first node N1 and the second node N2 through the first input sub-circuit 1, and the Vss signal is still at the second node N2, and the Vss signal received at the second clock signal end CK2 is transmitted to the cascade signal output end OUTPUT2 through the first output sub-circuit 3 under the control of the Vss signal at the second node N2. The signal received at the cascade signal output end OUTPUT2 changes from Vdd to Vss, that is, the voltage at the cascade signal output end OUTPUT2 decreases by Vdd-Vss, and the first storage sub-circuit 4 also makes the voltage at the second node N2 decrease by Vdd-Vss, that is, the voltage at the second node N2 is 2Vss-Vdd.

[0113] In the related art, the display effect of the display panel is poor. The inventors have found that the material of the transistor of the first input sub-circuit includes low-temperature polysilicon, i.e., the transistor of the first input sub-circuit is a low-temperature polysilicon transistor. The material of the transistor of the second input sub-circuit includes low-temperature polysilicon, i.e., the transistor of the second input sub-circuit is a low-temperature polysilicon transistor. The low-temperature polysilicon transistor has a leakage tailing characteristic, i.e., when the low-temperature polysilicon transistor is in an off state, the higher the source-drain voltage difference of the low-temperature polysilicon transistor, the greater the leakage current of the low-temperature polysilicon transistor.

[0114] According to the above, in the output stage, the voltage difference between the signal input end and the second node is Vdd-(2Vss-Vdd)=2Vdd-2Vss, i.e., the voltage difference between the signal input end and the second node is large, which causes the leakage current of the transistor of the first input sub-circuit and the transistor of the second input sub-circuit to be large, the signal input end leaks to the second node, the voltage at the second node changes, i.e., the voltage at the second node is unstable, thereby causing the conduction degree of the transistor included in the first output sub-circuit to change, the working level received at the cascade signal output end is unstable, thereby causing the display effect of the display panel to be poor.

[0115] To solve the above technical problem, as shown in Figure 6 and Figure 7 Some embodiments of the present disclosure provide a shift register RS, which further includes a first control sub-circuit 5.

[0116] In some examples, the first control sub-circuit 5 is coupled with the second clock signal end CK2, the cascade signal output end OUTPUT2 (of the present stage) and the first node N1. The first control sub-circuit 5 is configured to, in the output stage P2, in response to the working level at the cascade signal output end OUTPUT2, transfer the working level received at the second clock signal end CK2 to the first node N1.

[0117] Exemplarily, the first control sub-circuit 5 includes a third transistor T3, the first pole of the third transistor T3 is connected with the second clock signal end CK2, the second pole is connected with the first node N1, and the control pole is connected with the cascade signal output end OUTPUT2.

[0118] In some examples, the working level received at the second clock signal end CK2 is a low level, for example, the working level received at the second clock signal end CK2 is Vss, and the non-working level received at the second clock signal end CK2 is a high level, for example, the non-working level received at the second clock signal end CK2 is Vdd.

[0119] At this time, in the input stage P1, the first control sub-circuit 5 controls the second clock signal end CK2 and the first node N1 to be cut off under the control of the Vdd signal received at the cascaded signal output end OUTPUT2. In the output stage P2, the first control sub-circuit 5 transmits the Vss signal received at the second clock signal end CK2 to the first node N1 under the control of the VSS signal at the cascaded signal output end OUTPUT2. At this time, the voltage difference between the first node N1 and the second node N2 is Vss-(2Vss-Vdd)=Vdd-Vss.

[0120] In this way, the first control sub-circuit 5 can make the voltage difference between the first node N1 and the second node N2 be Vdd-Vss, that is, the source-drain voltage difference of the transistor included in the second input sub-circuit 2 is Vdd-Vss. In this way, the source-drain voltage difference of the transistor included in the second input sub-circuit 2 is small, and the drain current of the transistor included in the second input sub-circuit 2 is small or even zero, thereby reducing the risk of drain current of the first node N1 to the second node N2, and improving the voltage stability at the second node N2, improving the stability of the conduction degree of the transistor included in the first output sub-circuit 3, and improving the stability of the working level received at the cascaded signal output end OUTPUT2, thereby improving the display effect of the display panel 100.

[0121] In some embodiments, as shown in Figure 6 and Figure 7 , the shift register RS further includes a third input sub-circuit 6, a second control sub-circuit 7 and a second output sub-circuit 8.

[0122] In some examples, as shown in Figure 6 and Figure 7 , the third input sub-circuit 6 is coupled with the first voltage signal end VDD1, the third node N3 and the fourth node N4. The third input sub-circuit 6 is configured to, in the input stage P1, transmit the first voltage signal received at the first voltage signal end VDD1 to the third node N3 under the control of the voltage of the fourth node N4. The first voltage signal is a non-working level.

[0123] Exemplarily, as shown in Figure 7 , the third input sub-circuit 6 includes an eighth transistor T8, the first electrode of the eighth transistor T8 is connected with the second voltage signal end, the second electrode is connected with the third node N3, and the control electrode is connected with the fourth node N4.

[0124] In some examples, as shown in Figure 6 and Figure 7As shown, the second control sub-circuit 7 is coupled with the second node N2, the third node N3, the first voltage signal terminal VDD1, the second voltage signal terminal VSS and the third clock signal terminal CK3. The second control sub-circuit 7 is configured to, in the holding stage P3, transmit the second voltage signal received at the second voltage signal terminal VSS to the third node N3 and transmit the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2 in response to the third clock signal received at the third clock signal terminal CK3. The second voltage signal is a working level.

[0125] In some examples, as shown in Figure 6 and Figure 7 As shown, the second output sub-circuit 8 is coupled with the third voltage signal terminal VDD3, the third node N3 and the cascade signal output terminal OUTPUT2. The second output sub-circuit 8 is configured to, in the holding stage, transmit the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2 under the control of the voltage at the third node N3, the third voltage signal being a non-working level.

[0126] Exemplarily, as shown in Figure 7 The second output sub-circuit 8 includes a ninth transistor T9, a first electrode of the ninth transistor T9 being connected with the third voltage signal terminal VDD3, a second electrode being connected with the cascade signal output terminal OUTPUT2, and a control electrode being connected with the third node N3.

[0127] Based on the above structure, in the input stage P1, the third input sub-circuit 6 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the third node N3 under the control of the voltage at the fourth node N4, the second output sub-circuit 8 is turned off between the third voltage signal terminal VDD3 and the cascade signal output terminal OUTPUT2 under the control of the first voltage signal at the third node N3. The second control sub-circuit 7 is turned off between the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3, and the second control sub-circuit 7 is turned off between the first voltage signal terminal VDD1 and the second node N2 under the control of the first voltage signal at the third node N3.

[0128] In the output stage P2, the second output sub-circuit 8 is turned off between the third voltage signal terminal VDD3 and the cascade signal output terminal OUTPUT2 under the control of the first voltage signal at the third node N3. The second control sub-circuit 7 is turned off between the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3, and the second control sub-circuit 7 is turned off between the first voltage signal terminal VDD1 and the second node N2 under the control of the first voltage signal at the third node N3.

[0129] In the holding phase P3, the second control sub-circuit 7 transmits the second voltage signal received at the second voltage signal terminal VSS to the third node N3 under the control of the second voltage signal at the third node N3, and transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. The second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2 under the control of the second voltage signal at the third node N3. The first input sub-circuit 1 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2 under the control of the third voltage signal at the second node N2.

[0130] In some examples, as shown in FIG. 1, the holding phase P3 includes a first holding phase P31, a second holding phase P32, and a third holding phase P33. Figure 8

[0131] In the first holding phase P31, the first input sub-circuit 1 cuts off the signal input terminal INPUT and the first node N1 under the control of the first clock signal received at the first clock signal terminal CK1, and the signal received at the signal input terminal INPUT is at a non-working level. The second input sub-circuit 2 cuts off the first node N1 and the second node N2 under the control of the first clock signal received at the first clock signal terminal CK1. The third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3 under the control of the voltage at the fourth node N4. The second control sub-circuit 7 transmits the second voltage signal received at the second voltage signal terminal VSS to the third node N3 under the control of the third clock signal received at the third clock signal terminal CK3, and the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2 under the control of the second voltage signal at the third node N3. The second control sub-circuit 7 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2, and the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2 under the control of the first voltage signal at the second node N2. The second clock signal received at the second clock signal terminal CK2 is at a non-working level, and the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1 under the control of the third voltage signal at the cascade signal output terminal OUTPUT2.

[0132] ​In the second holding phase P32, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, transmits the non-working level received at the signal input terminal INPUT to the first node N1. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, transmits the non-working level at the first node N1 to the second node N2. Under the control of the voltage at the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The second control sub-circuit 7, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2, and transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the first voltage signal and / or the non-working level at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, the level received at the second clock signal terminal CK2 being the non-working level. Under the control of the first voltage signal at the cascade signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the cascade signal output terminal OUTPUT2 and the first node N1.

[0133] In the third holding phase P33, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, the signal received at the signal input terminal INPUT being the non-working level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the voltage at the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The second control sub-circuit 7, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2, and transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the first voltage signal at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, the level received at the second clock signal terminal CK2 being the working level. Under the control of the first voltage signal at the cascade signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the cascade signal output terminal OUTPUT2 and the first node N1.

[0134] In some examples, the working level received at the signal input terminal INPUT is low, for example, the working level received at the signal input terminal INPUT is Vss, the non-working level received at the signal input terminal INPUT is high, for example, the non-working level received at the signal input terminal INPUT is Vdd. The working level received at the second clock signal terminal CK2 is low, for example, the working level received at the second clock signal terminal CK2 is Vss, the non-working level received at the second clock signal terminal CK2 is high, for example, the non-working level received at the second clock signal terminal CK2 is Vdd. The first voltage signal received at the first voltage signal terminal VDD1 is high, for example, the first voltage signal received at the first voltage signal terminal VDD1 is Vdd. The second voltage signal received at the second voltage signal terminal VSS is low, for example, the second voltage signal received at the second voltage signal terminal VSS is Vss. The third voltage signal received at the third voltage signal terminal VDD3 is high, for example, the third voltage signal received at the third voltage signal terminal VDD3 is Vdd.

[0135] At this time, in the input stage P1, the Vss signal received at the signal input terminal INPUT is transmitted to the second node N2 through the first input sub-circuit 1 and the second input sub-circuit 2, and under the control of the Vss signal at the second node N2, the first output sub-circuit 3 transmits the Vdd signal received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2.

[0136] Under the control of the voltage at the fourth node N4, the third input sub-circuit 6 transmits the Vdd signal received at the first voltage signal terminal VDD1 to the third node N3, and the second control sub-circuit 7 controls the second voltage signal terminal VSS and the third node N3 to be cut off in response to the third clock signal received at the third clock signal terminal CK3, and the Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3 through the second control sub-circuit 7, so that the received signal at the third node N3 is the Vdd signal.

[0137] Under the control of the Vdd signal at the third node N3, the second control sub-circuit 7 cuts off the first voltage signal terminal VDD1 and the second node N2, and the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the second node N2 through the second control sub-circuit 7, so that the received signal at the second node N2 is the Vss signal. Under the control of the Vdd signal at the third node N3, the second output sub-circuit 8 cuts off the third voltage signal terminal VDD3 and the cascade signal output terminal OUTPUT2. The Vdd signal received at the third voltage signal terminal VDD3 cannot be transmitted to the cascade signal output terminal OUTPUT2 through the second output sub-circuit 8.

[0138] In the output stage P2, the first input sub-circuit 1 turns off the signal input end INPUT and the first node N1 in response to the first clock signal received at the first clock signal end CK1, and the second input sub-circuit 2 turns off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal end CK1. The Vdd signal received at the signal input end INPUT cannot be transmitted to the second node N2.

[0139] The second control sub-circuit 7 turns off the second voltage signal end VSS and the third node N3 in response to the third clock signal received at the third clock signal end CK3, and the Vss signal received at the second voltage signal end VSS cannot be transmitted to the third node N3 through the second control sub-circuit 7, so that the received signal at the third node N3 is the Vdd signal.

[0140] The second control sub-circuit 7 turns off the first voltage signal end VDD1 and the second node N2 under the control of the Vdd signal at the third node N3, and the Vdd signal received at the first voltage signal end VDD1 cannot be transmitted to the second node N2. The first output sub-circuit 3 transmits the Vss signal received at the second clock signal end CK2 to the cascade signal output end OUTPUT2 under the control of the Vss signal at the second node N2. The second output sub-circuit 8 turns off the first voltage signal end VDD1 and the cascade signal output end OUTPUT2 under the control of the Vdd signal at the third node N3, so that the signal at the cascade signal output end OUTPUT2 is the Vss signal. The first storage sub-circuit 4 writes the difference between the Vdd signal and the Vss signal received at the second clock signal end into the second node, and the received signal at the second node N2 is 2Vss-Vdd.

[0141] In the first holding stage P31, the first input sub-circuit 1 turns off the signal input end INPUT and the first node N1 in response to the first clock signal received at the first clock signal end CK1. The second input sub-circuit 2 turns off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal end CK1. The Vdd signal received at the signal input end INPUT cannot be transmitted to the second node N2.

[0142] The third input sub-circuit 6 turns off the first voltage signal end VDD1 and the third node N3 under the control of the voltage at the fourth node N4, and the Vdd signal received at the first voltage signal end VDD1 cannot be transmitted to the third node N3.

[0143] The second control sub-circuit 7 transmits the Vss signal received at the second voltage signal end VSS to the third node N3 in response to the third clock signal received at the third clock signal end CK3.

[0144] The second control sub-circuit 7 transmits the Vdd signal received at the first voltage signal end VDD1 to the third node N3 under the control of the Vss signal at the third node N3, and the first output sub-circuit 3 cuts off the second clock signal end CK2 and the cascade signal output end OUTPUT2 under the control of the Vdd signal at the second node N2, and the Vdd signal received at the second clock signal end CK2 cannot be transmitted to the cascade signal output end OUTPUT2. The second output sub-circuit 8 transmits the Vdd signal received at the third voltage signal end VDD3 to the cascade signal output end OUTPUT2 under the control of the Vss signal at the third node N3.

[0145] The first control sub-circuit 5 cuts off the second clock signal end CK2 and the first node N1 under the control of the Vdd signal at the cascade signal output end OUTPUT2, and the Vdd signal received at the second clock signal end CK2 cannot be transmitted to the first node N1.

[0146] In the second holding phase P32, the first input sub-circuit 1 transmits the Vdd signal received at the signal input end INPUT to the first node N1 in response to the first clock signal received at the first clock signal end CK1, and the second input sub-circuit 2 transmits the Vdd signal received at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal end CK1.

[0147] The third input sub-circuit 6 cuts off the first voltage signal end VDD1 and the third node N3 under the control of the voltage at the fourth node N4, and the Vdd signal received at the first voltage signal end VDD1 cannot be transmitted to the third node N3.

[0148] The second control sub-circuit 7 cuts off the second voltage signal end VSS and the third node N3 in response to the third clock signal received at the third clock signal end CK3. The Vss signal received at the second voltage signal end VSS cannot be transmitted to the third node N3, and the signal received at the third node N3 is the Vss signal received at the third node N3 in the first holding phase P31, that is, in the second holding phase P32, the signal received at the third node N3 is still the Vss signal.

[0149] The second control sub-circuit 7 transmits the Vdd signal received at the first voltage signal terminal VDD1 to the third node N3 under the control of the Vss signal at the third node N3, and the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2 under the control of the Vdd signal at the second node N2, and the Vdd signal received at the second clock signal terminal CK2 cannot be transmitted to the cascade signal output terminal OUTPUT2. The second output sub-circuit 8 transmits the Vdd signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2 under the control of the Vss signal at the third node N3.

[0150] The first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1 under the control of the Vdd signal at the cascade signal output terminal OUTPUT2. The Vdd signal received at the cascade signal output terminal OUTPUT2 cannot be transmitted to the first node N1.

[0151] In the third holding phase P33, the first input sub-circuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1. The second input sub-circuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. The Vdd signal received at the signal input terminal INPUT cannot be transmitted to the second node N2.

[0152] The third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3 under the control of the voltage at the fourth node N4, and the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the third node N3.

[0153] The second control sub-circuit 7 cuts off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3, and the Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3, and the signal received at the third node N3 is the Vss signal received at the third node N3 in the second holding phase P32, that is, in the third holding phase P33, the signal received at the third node N3 is still the VSS signal.

[0154] The second control sub-circuit 7 transmits the Vdd signal received at the second voltage signal terminal VSS to the second node N2 under the control of the Vss signal at the third node N3, and the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2 under the control of the received Vdd signal at the second node N2, and the Vss signal received at the second clock signal terminal CK2 cannot be transmitted to the cascade signal output terminal OUTPUT2. The second output sub-circuit 8 transmits the Vdd signal received at the first voltage signal terminal VDD1 to the cascade signal output terminal OUTPUT2 under the control of the Vss signal at the third node N3.

[0155] The first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1 under the control of the Vdd signal received at the cascade signal output terminal OUTPUT2, and the Vdd signal received at the cascade signal output terminal OUTPUT2 cannot be transmitted to the first node N1.

[0156] In some embodiments, as shown in Figure 6 and Figure 7 , the second control sub-circuit 7 includes a primary control sub-circuit 71 and a secondary control sub-circuit 72.

[0157] In some examples, as shown in Figure 6 and Figure 7 , the primary control sub-circuit 71 is coupled with the third node N3, the second voltage signal terminal VSS and the third clock signal terminal CK3. The primary control sub-circuit 71 is configured to transmit the second voltage signal received at the second voltage signal terminal VSS to the third node N3 in response to the third clock signal received at the third clock signal terminal CK3 in the holding phase P3. The second voltage signal is a working voltage level.

[0158] Exemplarily, as shown in Figure 7 , the primary control sub-circuit 71 includes a sixth transistor T6, the first electrode of which is coupled with the second voltage signal terminal VSS, the second electrode is coupled with the third node N3, and the control electrode is coupled with the third clock signal terminal CK3.

[0159] In some examples, as shown in Figure 6 and Figure 7 , the secondary control sub-circuit 72 is coupled with the second node N2, the third node N3 and the first voltage signal terminal VDD1. The secondary control sub-circuit 72 is configured to transmit the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2 under the control of the voltage at the third node N3 in the holding phase P3.

[0160] In some embodiments, as shown in Figure 6 and Figure 7As shown, the secondary control sub-circuit 72 includes a first sub-circuit 721 and a second sub-circuit 722.

[0161] In some examples, such as Figure 6 and Figure 7 As shown, the first sub-circuit 721 is coupled to the third node N3, the first voltage signal terminal VDD1, and the fifth node N5. The first sub-circuit 721 is configured to, during the output phase P2, cut off the first voltage signal terminal VDD1 and the fifth node N5 under the control of the second voltage signal at the third node N3.

[0162] For example, such as Figure 7 As shown, the first sub-circuit 721 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the first voltage signal terminal VDD1, the second terminal is connected to the fifth node N5, and the control is connected to the third node N3. For example, the fourth transistor T4 is a low-temperature polysilicon transistor.

[0163] like Figure 6 and Figure 7 As shown, the second sub-circuit 722 is coupled to the second node N2, the third node N3, and the fifth node N5. The second sub-circuit 722 is configured to, during the output phase P2, cut off the fifth node N5 and the second node N2 under the control of the voltage at the third node N3.

[0164] For example, such as Figure 7 As shown, the second sub-circuit 722 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the fifth node N5, the second terminal is connected to the second node N2, and the control terminal is connected to the third node N3. For example, the fifth transistor T5 is a low-temperature polysilicon transistor.

[0165] Based on this, such as Figure 6 and Figure 7 As shown, the second control sub-circuit 7 also includes a third-level control sub-circuit 73.

[0166] In some examples, the three-level control subcircuit 73 is coupled to the fifth node N5, the second node N2, and the second voltage signal terminal VSS. The three-level control subcircuit 73 is configured to, during the output phase P2, transmit the second voltage signal received at the second voltage signal terminal VSS to the fifth node N5 under the control of the voltage at the second node N2.

[0167] For example, such as Figure 7 As shown, the three-level control sub-circuit 73 includes a tenth transistor T10. The first terminal of the tenth transistor T10 is connected to the second voltage signal terminal VSS, the second terminal is connected to the fifth node N5, and the control terminal is connected to the second node N2.

[0168] Based on the above structure, in the output stage P2, under the control of the voltage at the third node N3, the first sub-circuit 721 controls the first voltage signal end VDD1 and the fifth node N5 to be off, and the second sub-circuit 722 controls the fifth node N5 and the second node N2 to be off. Under the control of the voltage at the second node N2, the third control sub-circuit 73 transmits the second voltage signal received at the second voltage signal end VSS to the fifth node N5.

[0169] In some examples, the second voltage signal received at the second voltage signal end VSS is a low level, for example, the second voltage signal received at the second voltage signal end VSS is Vss.

[0170] At this time, in the input stage P1, under the control of the Vss signal at the second node N2, the third control sub-circuit 73 transmits the Vss signal received at the third voltage signal end VDD3 to the fifth node N5. In the output stage P2, under the control of the Vss signal or the 2Vss-Vdd signal at the second node N2, the third control sub-circuit 73 transmits the Vss signal received at the second voltage signal end VSS to the fifth node N5, at this time, the voltage difference between the fifth node N5 and the second node N2 is Vss-(2Vss-Vdd)=Vdd-Vss.

[0171] In this way, the third control sub-circuit 73 can make the voltage difference between the fifth node N5 and the second node N2 be Vdd-Vss, that is, the source-drain voltage difference of the transistor included in the second sub-circuit 722 is Vdd-Vss, so that the source-drain voltage difference of the transistor included in the second sub-circuit 722 is small, and the drain current of the transistor included in the second sub-circuit 722 is small or none, thereby reducing the risk of drain current of the fifth node N5 to the second node N2, and further improving the voltage stability at the second node N2, the stability of the on degree of the transistor of the first output sub-circuit 3, and the stability of the working level received at the cascade signal output end OUTPUT2, thereby improving the display effect of the display panel 100.

[0172] In some embodiments, as shown in Figure 6 and Figure 7 The fourth node N4 is connected with the signal input end INPUT.

[0173] In some other embodiments, as shown in Figure 9 The fourth node N4 is connected with the first node N1.

[0174] In yet some embodiments, as shown in Figure 10 The fourth node N4 is connected with the fifth node N5.

[0175] In some embodiments, as shown in Figure 6 and Figure 7As shown, the shift register RS further includes a second storage sub-circuit 9.

[0176] In some examples, the second storage sub-circuit 9 is coupled with a third voltage signal terminal VDD3 and a third node N3. The second storage sub-circuit 9 is configured to store a voltage at the third node N3.

[0177] Exemplarily, as Figure 7 shown, the second storage sub-circuit 9 includes a second storage capacitor C2, a first plate of the second storage capacitor C2 is connected with the third node N3, and a second plate is connected with the third voltage signal terminal VDD3.

[0178] In some embodiments, as Figure 11 shown, the gate driving circuit 30 further includes a plurality of clock signal lines CL, which are divided into groups. In the same group, the clock signal line CL connected with the second clock signal terminal CK2 of the upper stage shift register RS is the same as the clock signal line CL connected with the first clock signal terminal CK1 of the lower stage shift register RS, the clock signal line CL connected with the third clock signal terminal CK3 of the upper stage shift register RS is the same as the clock signal line CL connected with the second clock signal terminal CK2 of the lower stage shift register RS, the clock signal line CL connected with the first clock signal terminal CK1 of the upper stage shift register RS is different from the clock signal line CL connected with the third clock signal terminal CK3 of the lower stage shift register RS, and the clock signal lines CL connected with the same clock signal terminal of any two stage shift registers RS are different.

[0179] In this way, the number of clock signal lines CL is greater than three, so that the clock frequency on the clock signal line CL can be reduced, which is beneficial to reduce the power consumption of the display panel 100.

[0180] In some examples, the gate driving circuit 30 includes four clock signal lines CL. For the convenience of description, in the direction away from the display area AA, the first clock signal line CL is marked as the first clock signal line CL(1), the second clock signal line CL is marked as the second clock signal line CL(2), the third clock signal line CL is marked as the third clock signal line CL(3), and the fourth clock signal line CL is marked as the fourth clock signal line CL(4).

[0181] The plurality of shift registers RS are divided into groups, and one group includes four shift registers RS. For the convenience of description, in the cascading order, the four shift registers RS included in one group of shift registers RS are sequentially marked as the first stage shift register RS(1), the second stage shift register RS(2), the third stage shift register RS(3), and the fourth stage first shift register RS(4).

[0182] In some examples, asFigure 11 As shown in the figure, the first clock signal end CK1 of the first stage shift register RS(1) is connected with the first clock signal line CL(1), the second clock signal end CK2 is connected with the second clock signal line CL(2), and the third clock signal line CL is connected with the third clock signal line CL(3). The first clock signal end CK1 of the second stage shift register RS(2) is connected with the second clock signal line CL(2), the second clock signal end CK2 is connected with the third clock signal line CL(3), and the third clock signal end CK3 is connected with the fourth clock signal line CL(4). The first clock signal end CK1 of the third stage shift register RS(3) is connected with the third clock signal line CL(3), the second clock signal end CK2 is connected with the fourth clock signal line CL(4), and the third clock signal end CK3 is connected with the first clock signal line CL(1). The first clock signal end CK1 of the fourth stage shift register RS(4) is connected with the fourth clock signal line CL(4), the second clock signal end CK2 is connected with the first clock signal line CL(1), and the third clock signal end CK3 is connected with the second clock signal line CL(2).

[0183] In some embodiments, as Figure 11 shown, the gate drive circuit 30 further includes a first voltage signal line VL1 and a second voltage signal line VL2. The first voltage signal line VL1 is connected with the first voltage signal end VDD1 and the shift register RS. The second voltage signal line VL2 is connected with the third voltage signal end VDD3 and the shift register RS.

[0184] In this way, the first voltage signal end VDD1 and the third voltage signal end VDD3 are independent of each other, which can reduce the influence between the second control sub-circuit 7 and the second output sub-circuit 8, and is conducive to improving the display effect of the display panel 100.

[0185] On this basis, the width of the first voltage signal line VL1 is smaller than the width of the second voltage signal line VL2.

[0186] In this way, the width of the second voltage signal line VL2 is larger, the resistance of the second voltage signal line VL2 is smaller, and the voltage drop on the second voltage signal line VL2 is smaller, which can improve the signal quality at the cascade signal output end OUTPUT2, and is conducive to improving the display effect of the display panel 100.

[0187] In some examples, the line width of the first voltage signal line VL1 is 3 μm to 10 μm.

[0188] For example, the line width of the first voltage signal line VL1 is 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0189] In some examples, the line width of the second voltage signal line VL2 is 10 μm to 20 μm.

[0190] For example, the line width of the second voltage signal line VL2 is 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, or 20 μm.

[0191] In some embodiments, the plurality of shift registers RS are arranged at intervals along the second direction Y. The first voltage signal line VL1 extends along the second direction Y, and along the first direction X, the first voltage signal line VL1 is located between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10, and between the seventh transistor T7 and the ninth transistor T9. The second voltage signal line VL2 extends along the second direction Y, and along the first direction X, the second voltage signal line VL2 is located on the side away from the first voltage signal line VL1 of the seventh transistor T7 and the ninth transistor T9.

[0192] In this way, the line width of the first voltage signal line VL1 is narrow, the length of the connection line across the first voltage signal line VL1 can be shortened, the voltage drop of the connection line is reduced, the signal quality on the connection line is improved, and the display effect of the display panel 100 is improved.

[0193] In some embodiments, as shown in FIG. 1A, the first storage capacitor C1 is located on the side away from the first voltage signal line VL1 of the seventh transistor T7 and the ninth transistor T9, and the second voltage signal line VL2 is located on the side away from the first voltage signal line VL1 of the seventh transistor T7 and the ninth transistor T9. Figure 11 In this way, the line width of the first voltage signal line VL1 is narrow, the length of the connection line across the first voltage signal line VL1 can be shortened, the voltage drop of the connection line is reduced, the signal quality on the connection line is improved, and the display effect of the display panel 100 is improved.

[0194] In this way, the line width of the first voltage signal line VL1 is narrow, the length of the connection line across the first voltage signal line VL1 can be shortened, the voltage drop of the connection line is reduced, the signal quality on the connection line is improved, and the display effect of the display panel 100 is improved.

[0195] In some embodiments, as shown in FIG. 1A, the first storage capacitor C1 is located on the side away from the first voltage signal line VL1 of the seventh transistor T7 and the ninth transistor T9, and the second voltage signal line VL2 is located on the side away from the first voltage signal line VL1 of the seventh transistor T7 and the ninth transistor T9. Figure 11As shown, the second storage capacitor C2 is located on the side of the first storage capacitor C1 away from the next stage of the shift register RS, and on the side of the seventh transistor T7 and the ninth transistor T9 away from the first voltage signal line VL1. The orthogonal projection of the second storage capacitor C2 on the reference plane overlaps the orthogonal projection of the second voltage signal line VL2 on the reference plane, and along the first direction, the two ends of the second storage capacitor C2 exceed the two ends of the second voltage signal line VL2.

[0196] In some embodiments, as shown in FIG. 1, the clock signal line CL extends along the second direction Y, and the clock signal line CL is located on the side of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 away from the first voltage signal line VL1. Figure 11

[0197] The gate drive circuit 30 further comprises a third voltage signal line VL3 connected with the second voltage signal end VSS and the shift register RS, the third voltage signal line VL3 extends along the second direction and is located between the clock signal line CL and the shift register RS.

[0198] In some embodiments, as shown in FIG. 1, the fourth transistor T4 and the fifth transistor T5 are located between the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 and the first voltage signal line VL1, and along the second direction, the fourth transistor T4 is located on the side of the fifth transistor T5. Figure 11 In this way, the distance between the fourth transistor T4 and the first voltage signal line VL1 can be shortened, the length of the connection line connecting the fourth transistor T4 and the first voltage signal line VL1 can be shortened, the voltage drop on the connection line connecting the fourth transistor T4 and the first voltage signal line VL1 can be reduced, and the quality of the signal transmitted from the first voltage signal line VL1 to the fourth transistor T4 can be improved, which is beneficial to improve the display effect of the display panel 100.

[0199] In some embodiments, as shown in FIG. 1, the third transistor T3 and the sixth transistor T6 are located between the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8 and the tenth transistor T10 and the third voltage signal line VL3, and along the second direction, the third transistor T3 is located on the side of the fifth transistor T5.

[0200] Figure 11

[0201] ​​​This configuration allows for a shorter distance between the third transistor T3 and the clock signal line CL, reducing the length of the connection line between them, lowering the voltage drop on the connection line, and improving the quality of the signal transmitted from the clock signal line CL to the third transistor T3. This, in turn, enhances the display effect of the display panel 100.

[0202] On the other hand, the distance between the sixth transistor T6 and the third voltage signal line VL3 can be shortened, thereby reducing the length of the connection line between the sixth transistor T6 and the third voltage signal line VL3, reducing the voltage drop on the connection line between the sixth transistor T6 and the third voltage signal line VL3, improving the quality of the signal transmitted from the third voltage signal line VL3 to the sixth transistor T6, and thus improving the display effect of the display panel 100.

[0203] In some embodiments, such as Figure 11 As shown, the eighth transistor T8 is located between the fourth transistor T4 and the fifth transistor T5, and between the third transistor T3 and the sixth transistor T6, and is located on the side of the first transistor T1, the second transistor T2 and the tenth transistor T10 away from the next-stage shift register RS; the fourth transistor T4 is located on the side of the fifth transistor T5 away from the next-stage shift register RS, and the ninth transistor T9 is located on the side of the seventh transistor T7 away from the next-stage shift register RS;

[0204] The gate drive circuit 30 also includes a first connection line 31, which is connected to the first terminal of the third transistor T3, the second terminal of the seventh transistor T7, and the gate of the next-stage eighth transistor T8. The first connection line 31 is located on the side of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the tenth transistor T10 near the next-stage shift register RS.

[0205] This configuration allows for a shorter distance between the eighth transistor T8 and the first connection line 31, reducing the length of the connection line between the eighth transistor T8 and the first connection line 31, lowering the voltage drop on the connection line between the eighth transistor T8 and the first connection line 31, improving the quality of the signal transmitted from the first connection line 31 to the eighth transistor T8, and thus enhancing the display effect of the display panel 100.

[0206] In some embodiments, such as Figure 11As shown, along the second direction Y, the channel portion of the first transistor T1 is located on the side of the channel portion of the second transistor T2 close to the upper stage of the shift register RS, along the first direction X, the channel portion of the first transistor T1 is located on the side of the channel portion of the second transistor T2 away from the first voltage signal line VL1, and the channel portion of the third transistor T3 is located on the side of the channel portion of the first transistor T1 and the channel portion of the second transistor T2 away from the first voltage signal line VL1.

[0207] In this way, the distance between the first transistor T1 and the third transistor T3 is short, and the distance between the second transistor T2 and the third transistor T3 is short, which is beneficial to reduce the area occupied by the first transistor T1, the second transistor T2 and the third transistor T3, thereby facilitating the realization of the narrow frame of the display panel 100.

[0208] The working process of the above shift register RS in one display frame period P will be described in detail below in combination with a timing diagram. The following embodiments take the above various transistors as P-type as an example.

[0209] In some embodiments, as shown in Figure 7 and Figure 8 The fourth node N4 is connected with the signal input end INPUT. One display frame period P includes an input stage P1, an output stage P2, and a first holding stage P31, a second holding stage P32 and a third holding stage P33.

[0210] As shown in Figure 8 and Figure 12As shown, in the input stage P1, the first input sub-circuit 1 transmits the operating level received at the signal input end INPUT to the first node N1 in response to the first clock signal received at the first clock signal end CK1, and the second input sub-circuit 2 transmits the operating level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal end CK1. The first storage sub-circuit 4 stores the operating level at the second node N2. The first output sub-circuit 3 transmits the non-operating level received at the second clock signal end CK2 to the cascade signal output end OUTPUT2 under the control of the operating level at the second node N2. The first control sub-circuit 5 cuts off the second clock signal end CK2 and the first node N1 in response to the non-operating level at the cascade signal output end OUTPUT2. The third input sub-circuit 6 transmits the first voltage signal received at the first voltage signal end VDD1 to the third node N3 in response to the operating level received at the second clock signal end CK2. The first control sub-circuit 71 cuts off the second voltage signal end VSS and the third node N3 in response to the third clock signal received at the third clock signal end CK3. The second output sub-circuit 8 cuts off the third voltage signal end VDD3 and the cascade signal output end OUTPUT2 under the control of the first voltage signal at the third node N3, and the first sub-circuit 721 cuts off the first voltage signal end VDD1 and the fifth node N5 under the control of the first voltage signal at the third node N3, and the second sub-circuit 722 cuts off the fifth node N5 and the second node N2 under the control of the voltage at the second node N2. The third control sub-circuit 73 transmits the second voltage signal at the second voltage signal end VSS to the fifth node N5 under the control of the voltage at the second node N2.

[0211] As an example, each sub-circuit in the shift register RS includes a transistor or a storage capacitor. As shown in FIG. 1, the shift register RS includes a first input sub-circuit 1, a second input sub-circuit 2, a first storage sub-circuit 4, a first output sub-circuit 3, a first control sub-circuit 5, a third input sub-circuit 6, a first control sub-circuit 71, a second output sub-circuit 8, a first sub-circuit 721, a second sub-circuit 722, and a third control sub-circuit 73. Figure 8 As shown, in the input stage P1, the first input signal is 0, the first clock signal is 0, the second voltage signal is 0, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0212] In this case, as shown in FIG. 2, the signal input end INPUT, the first clock signal end CK1, and the second voltage signal end VSS input low levels, and the second clock signal end CK2, the third clock signal end CK3, the first voltage signal end VDD1, and the third voltage signal end VDD3 input high levels. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned on. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are cut off. Figure 8 Figure 12 As shown, in the input stage P1, the first input signal is 0, the first clock signal is 0, the second voltage signal is 0, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0213] ​At this time, the working level received at the signal input terminal INPUT is transmitted to the first node N1 through the first transistor T1, and to the second node N2 through the first transistor T1 and the second transistor T2. The non-working level received at the second clock signal terminal CK2 is transmitted to the cascaded signal output terminal OUTPUT2 through the seventh transistor T7. The first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the third node N3 through the eighth transistor T8. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the fifth node N5 through the tenth transistor T10.

[0214] like Figure 8 and Figure 13 As shown, in the output stage P2, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, and the signal received at the signal input terminal INPUT is at a non-working level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the working level at the second node N2, the first output sub-circuit 3 transmits the working level received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2, and the first storage sub-circuit 4 writes the difference between the working level and the non-working level received at the second clock signal terminal CK2 into the second node N2. The first control sub-circuit 5, in response to the working level at the cascaded signal output terminal OUTPUT2, transmits the working level received at the second clock signal terminal CK2 to the first node N1. The third input sub-circuit 6, in response to the non-working level received at the second clock signal terminal CK2, cuts off the first voltage signal terminal VDD1 and the third node N3. The first-level control sub-circuit 71, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the first voltage signal at the third node N3, the second output sub-circuit 8 cuts off the third voltage signal terminal VDD3 and the cascaded signal output terminal OUTPUT2. Also under the control of the first voltage signal at the third node N3, the first sub-circuit 721 cuts off the first voltage signal terminal VDD1 and the fifth node N5, and the second sub-circuit 722 cuts off the fifth node N5 and the second node N2. Under the control of the voltage at the second node N2, the third-level control sub-circuit 73 transmits the second voltage signal at the second voltage signal terminal VSS to the fifth node N5.

[0215] For example, the sub-circuits in the shift register RS ​​include transistors or storage capacitors. For instance... Figure 8 As shown, in the input stage P1, the second clock signal is 0, the second voltage signal is 0, the first input signal is 1, the first clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0216] like Figure 8 and Figure 13 As shown, in this case, the second clock signal terminal CK2 and the second voltage signal terminal VSS are input at low levels, while the signal input terminals INPUT, the first clock signal terminal CK1, the third clock signal terminal CK3, the first voltage signal terminal VDD1, and the third voltage signal terminal VDD3 are input at high levels. The third transistor T3, the seventh transistor T7, and the tenth transistor T10 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0217] At this time, the operating level received at the second clock signal terminal CK2 is transmitted to the cascaded signal output terminal OUTPUT2 through the seventh transistor T7, and the operating level at the cascaded signal output terminal OUTPUT2 is transmitted to the first node N1 through the third transistor T3. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the fifth node N5 through the tenth transistor T10.

[0218] like Figure 8 and Figure 14As shown, in the first holding phase P31, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, and the signal received at the signal input terminal INPUT is at a non-working level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the non-working level at the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The first-level control sub-circuit 71, in response to the third clock signal received at the third clock signal terminal CK3, transmits the second voltage signal received at the second voltage signal terminal VSS to the third node N3. Under the control of the second voltage signal at the third node N3, the first sub-circuit 721 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5, and the second sub-circuit 722 transmits the first voltage signal at the fifth node N5 to the second node N2. Under the control of the second voltage signal at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is a non-operating level. Under the control of the second voltage signal at the second node N2, the third-level control sub-circuit 73 cuts off the second voltage signal terminal VSS and the fifth node N5. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2. Under the control of the third voltage signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1.

[0219] For example, the sub-circuits in the shift register RS ​​include transistors or storage capacitors. For instance... Figure 14 As shown, in the input stage P1, the third clock signal is 0, the second voltage signal is 0, the first input signal is 1, the first clock signal is 1, the second clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0220] like Figure 8 and Figure 14 As shown, in this case, the third clock signal terminal CK3 and the second voltage signal terminal VSS are input at low levels, while the signal input terminals INPUT, the first clock signal terminal CK1, the second clock signal terminal CK2, the first voltage signal terminal VDD1, and the third voltage signal terminal VDD3 are input at high levels. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0221] At this time, the first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal terminal VDD3 is transmitted to the cascaded signal output terminal OUTPUT2 through the ninth transistor T9.

[0222] like Figure 8 and Figure 15 As shown, during the second hold phase P32, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, transmits the non-working level received at the signal input terminal INPUT to the first node N1. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, transmits the non-working level at the first node N1 to the second node N2. Under the control of the non-working level at the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The first-level control sub-circuit 71, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the second voltage signal at the third node N3, the first sub-circuit 721 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5, and the second sub-circuit 722 transmits the first voltage signal at the fifth node N5 to the second node N2. Under the control of the second voltage signal at the second node N2, and / or under the control of the non-working level at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is a non-working level. Under the control of the second voltage signal at the second node N2, the third-level control sub-circuit 73 cuts off the second voltage signal terminal VSS and the fifth node N5. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2. Under the control of the third voltage signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1.

[0223] For example, the sub-circuits in the shift register RS ​​include transistors or storage capacitors. For instance... Figure 8 As shown, in the input stage P1, the first clock signal is 0, the second voltage signal is 0, the first input signal is 1, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0224] likeFigure 8 and Figure 15 In this case, the first clock signal terminal CK1 and the second voltage signal terminal VSS input low level, the signal input terminal INPUT, the second clock signal terminal CK2, the third clock signal terminal CK3, the first voltage signal terminal VDD1 and the third voltage signal terminal VDD3 input high level. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the ninth transistor T9 are turned on. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are turned off.

[0225] At this time, the operating level received at the signal input terminal INPUT is transmitted to the first node N1 through the first transistor T1, and is transmitted to the second node N2 through the first transistor T1 and the second transistor T2. The first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and is transmitted to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal terminal VDD3 is transmitted to the cascade signal output terminal OUTPUT2 through the ninth transistor T9.

[0226] As Figure 8 and Figure 16As shown, in the third holding stage P33, the first input sub-circuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, the signal received at the signal input terminal INPUT being at the working level. The second input sub-circuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. The third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3 under the control of the non-working level at the fourth node N4. The first control sub-circuit 71 cuts off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. The first sub-circuit 721 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5 and the second sub-circuit 722 transmits the first voltage signal at the fifth node N5 to the second node N2 under the control of the second voltage signal at the third node N3. The first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2 under the control of the second voltage signal at the second node N2, the level received at the second clock signal terminal CK2 being at the non-working level. The third control sub-circuit 73 cuts off the second voltage signal terminal VSS and the fifth node N5 under the control of the second voltage signal at the second node N2. The second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2 under the control of the third voltage signal at the cascade signal output terminal OUTPUT2, and the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1.

[0227] As an example, each sub-circuit in the shift register RS includes a transistor or a storage capacitor. As shown in Fig. 1, the shift register RS includes a first input sub-circuit 1, a second input sub-circuit 2, a first output sub-circuit 3, a second output sub-circuit 8, a first control sub-circuit 5, a second control sub-circuit 71, a third control sub-circuit 73, a first input terminal INPUT, a first clock signal terminal CK1, a second clock signal terminal CK2, a third clock signal terminal CK3, a first voltage signal terminal VDD1, a second voltage signal terminal VSS, a third voltage signal terminal VDD3, a first node N1, a second node N2, a third node N3, a fourth node N4, a fifth node N5, and a cascade signal output terminal OUTPUT2. Figure 8 As shown, in the input stage PI, the first clock signal is 0, the second voltage signal is 0, the first input signal is 1, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0228] As shown, in the input stage PI, the first clock signal is 0, the second voltage signal is 0, the first input signal is 1, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1. Figure 8 As shown, in the input stage PI, the first clock signal is 0, the second voltage signal is 0, the first input signal is 1, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1. Figure 16 As shown, in this case, the second clock signal terminal CK2 and the second voltage signal terminal VSS input low levels, and the first clock signal terminal CK1, the signal input terminal INPUT, the third clock signal terminal CK3, the first voltage signal terminal VDD1, and the third voltage signal terminal VDD3 input high levels. The fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are cut off.

[0229] At this time, the working level received at the signal input end INPUT is transmitted to the first node N1 through the first transistor T1, and to the second node N2 through the first transistor T1 and the second transistor T2, the first voltage signal received at the first voltage signal end VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal end VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal end VDD3 is transmitted to the cascade signal output end OUTPUT2 through the ninth transistor T9.

[0230] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0231] The above description is merely specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A shift register, characterized by, The application relates to a signal input circuit, comprising: a first input sub-circuit coupled with a signal input end, a first node and a first clock signal end; the first input sub-circuit is configured to, in an input stage, transmit a working level received at the signal input end to the first node in response to a first clock signal received at the first clock signal end; and in an output stage, cut off the signal input end and the first node in response to the first clock signal received at the first clock signal end; in the output stage, a non-working level is received at the signal input end; the first input sub-circuit comprises a first transistor, and the first transistor is a low-temperature polysilicon transistor; a second input sub-circuit coupled with the first node, a second node and the first clock signal end; the second input sub-circuit is configured to, in the input stage, transmit a voltage at the first node to the second node in response to the first clock signal received at the first clock signal end, and in the output stage, cut off the first node and the second node in response to the first clock signal received at the first clock signal end; the second input sub-circuit comprises a second transistor, and the second transistor is a low-temperature polysilicon transistor; a first output sub-circuit coupled with a second clock signal end, the second node and a cascade signal output end; the first output sub-circuit is configured to, in the input stage, transmit a non-working level received at the second clock signal end to the cascade signal output end under the control of a voltage at the second node; and in the output stage, transmit a working level received at the second clock signal end to the cascade signal output end under the control of the voltage at the second node; a first storage sub-circuit coupled with the second node and the cascade signal output end; the first storage sub-circuit is configured to, in the input stage, store the voltage at the second node, and in the output stage, write a difference between the working level and the non-working level received at the second clock signal end into the second node; a first control sub-circuit coupled with the second clock signal end, the cascade signal output end and the first node; the first control sub-circuit is configured to, in the output stage, transmit the working level received at the second clock signal end to the first node in response to a working level at the cascade signal output end; the first control sub-circuit comprises a third transistor, a first electrode of the third transistor is connected with the second clock signal end, a second electrode is connected with the first node, and a control electrode is connected with the cascade signal output end; a third input sub-circuit coupled with a first voltage signal end, a third node and a fourth node; the third input sub-circuit is configured to, in the input stage, transmit a first voltage signal received at the first voltage signal end to the third node under the control of a voltage at the fourth node; the first voltage signal is a non-working level; ​ ​ ​ The second control sub-circuit is coupled with the second node, the third node, the first voltage signal terminal, a second voltage signal terminal and a third clock signal terminal; the second control sub-circuit is configured to, in the holding stage, in response to a third clock signal received at the third clock signal terminal, transmit a second voltage signal received at the second voltage signal terminal to the third node, and transmit a first voltage signal received at the first voltage signal terminal to the second node; The second voltage signal is a working voltage level; The second output sub-circuit is coupled with a third voltage signal terminal, the third node and the cascade signal output terminal; the second output sub-circuit is configured to, in the holding stage, under the control of the voltage at the third node, transmit a third voltage signal received at the third voltage signal terminal to the cascade signal output terminal; The third voltage signal is a non-working voltage level; The second control sub-circuit comprises: A first-level control sub-circuit is coupled with the third node, the second voltage signal terminal and the third clock signal terminal; the first-level control sub-circuit is configured to, in the holding stage, in response to a third clock signal received at the third clock signal terminal, transmit a second voltage signal received at the second voltage signal terminal to the third node; the second voltage signal is a working voltage level; A second-level control sub-circuit is coupled with the second node, the third node and the first voltage signal terminal; the second-level control sub-circuit is configured to, in the holding stage, under the control of the second voltage signal at the third node, transmit a first voltage signal received at the first voltage signal terminal to the second node; the second-level control sub-circuit comprises: A first sub-circuit is coupled with the third node, the first voltage signal terminal and a fifth node; the first sub-circuit is configured to, in the output stage, under the control of the voltage at the third node, cut off the first voltage signal terminal and the fifth node; the first sub-circuit comprises a fourth transistor, and the fourth transistor is a low-temperature polysilicon transistor; A second sub-circuit is coupled with the second node, the third node and the fifth node; the second sub-circuit is configured to, in the output stage, under the control of the voltage at the third node, cut off the fifth node and the second node; the second sub-circuit comprises a fifth transistor, and the fifth transistor is a low-temperature polysilicon transistor; A third-level control sub-circuit is coupled with the fifth node, the second node and the second voltage signal terminal; the third-level control sub-circuit is configured to, in the output stage, under the control of the voltage at the second node, transmit a second voltage signal received at the second voltage signal terminal to the fifth node.

2. The shift register of claim 1, wherein, The first-level control sub-circuit comprises: A sixth transistor, a first electrode of the sixth transistor is connected with the second voltage signal terminal, a second electrode of the sixth transistor is connected with the third node, and a control electrode of the sixth transistor is connected with the third clock signal terminal.

3. The shift register according to claim 1 or 2, characterized in that, The fourth node is connected with the signal input terminal, or the fourth node is connected with the first node, or the fourth node is connected with the fifth node.

4. The shift register of claim 2, wherein, The first output sub-circuit comprises a seventh transistor, a first electrode of the seventh transistor is connected with the second clock signal terminal, a second electrode is connected with the cascade signal output terminal, and a control electrode is connected with the second node; The third input sub-circuit comprises an eighth transistor, a first electrode of the eighth transistor is connected with the first voltage signal terminal, a second electrode is connected with the cascade signal output terminal, and a control electrode is connected with the fourth node; The second output sub-circuit comprises a ninth transistor, a first electrode of the ninth transistor is connected with the third voltage signal terminal, a second electrode is connected with the cascade signal output terminal, and a control electrode is connected with the third node; The third control sub-circuit comprises a tenth transistor, a first electrode of the tenth transistor is connected with the second voltage signal terminal, a second electrode is connected with the fifth node, and a control electrode is connected with the second node; The first storage sub-circuit further comprises a first storage capacitor, a first plate of the first storage capacitor is coupled with the second node, and a second plate is coupled with the cascade signal output terminal.

5. A gate drive circuit characterized by comprising: Comprise: A plurality of cascaded shift registers according to any one of claims 1-4.

6. The gate drive circuit according to claim 5, characterized by The shift register is connected with a first clock signal terminal, a second clock signal terminal and a third clock signal terminal; The gate drive circuit further comprises: A plurality of clock signal lines are divided into a plurality of groups, in the same group, in adjacent two-stage shift registers, a clock signal line connected with the second clock signal terminal in the upper-stage shift register is the same as a clock signal line connected with the first clock signal terminal in the lower-stage shift register, a clock signal line connected with the third clock signal terminal in the upper-stage shift register is the same as a clock signal line connected with the second clock signal terminal in the lower-stage shift register, a clock signal line connected with the first clock signal terminal in the upper-stage shift register is different from a clock signal line connected with the third clock signal terminal in the lower-stage shift register, and clock signal lines connected with the same clock signal terminal in any two-stage shift registers are different.

7. The gate drive circuit according to claim 5 or 6, characterized in that, Further comprise: A first voltage signal line is connected with the first voltage signal terminal and the shift register; A second voltage signal line is connected with the third voltage signal terminal and the shift register; the width of the first voltage signal line is smaller than the width of the second voltage signal line.

8. The gate drive circuit according to claim 7, characterized by The width of the first voltage signal line is 3-10 μm; and / or, the width of the second voltage signal line is 10-20 μm.

9. The gate drive circuit according to claim 7, characterized by Along the second direction, a plurality of the shift registers are arranged at intervals; the shift register comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The first voltage signal line extends along a second direction, and along a first direction, the first voltage signal line is located between the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor and the tenth transistor, and the seventh transistor and the ninth transistor; The second voltage signal line extends along the second direction, and along a first direction, the second voltage signal line is located on a side away from the first voltage signal line of the seventh transistor and the ninth transistor; the second direction intersects the first direction.

10. The gate drive circuit according to claim 9, characterized by The shift register further comprises a first storage capacitor; the first storage capacitor is located on a side away from the first voltage signal line of the seventh transistor and the ninth transistor, and a normal projection of the second voltage signal line on a reference surface overlaps a normal projection of the first storage capacitor on the reference surface; along the first direction, two ends of the first storage capacitor are beyond two ends of the second voltage signal line.

11. The gate drive circuit according to claim 9, characterized by The clock signal line extends along a second direction, and the clock signal line is located on a side away from the first voltage signal line of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor and the tenth transistor; The gate drive circuit further comprises: A third voltage signal line is connected with the second voltage signal end and the shift register, the third voltage signal line extends along the second direction, and is located between the clock signal line and the shift register.

12. The gate drive circuit according to claim 11, characterized by The fourth transistor and the fifth transistor are located between the first transistor, the second transistor, the third transistor, the sixth transistor, the eighth transistor and the tenth transistor, and the first voltage signal line, along the second direction, the fourth transistor is located on a side of the fifth transistor; and / or, The third transistor and the sixth transistor are located between the first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor and the tenth transistor, and the third voltage signal line, along the second direction, the third transistor is located on a side of the sixth transistor.

13. The gate drive circuit according to claim 12, characterized by The eighth transistor is located between the fourth transistor and the fifth transistor, and the third transistor and the sixth transistor, and is located on a side away from the shift register of the first transistor, the second transistor and the tenth transistor; the fourth transistor is located on a side away from the shift register of the fifth transistor, and the ninth transistor is located on a side away from the shift register of the seventh transistor; The gate drive circuit further comprises: A first connection line is connected with the gate of the third transistor, the second electrode of the seventh transistor and the first electrode of the first transistor of the next stage; the first connection line is located at the side of the first transistor, the second transistor, the fourth transistor, the fifth transistor and the tenth transistor close to the next stage of the shift register.

14. The gate drive circuit according to claim 13, characterized by In the first direction, the channel part of the first transistor is located at the side of the channel part of the second transistor close to the previous stage of the shift register, and in the second direction, the channel part of the first transistor is located at the side of the channel part of the second transistor away from the first voltage signal line; the channel part of the third transistor is located at the side of the channel part of the first transistor and the channel part of the second transistor away from the first voltage signal line.

15. A display device comprising: The shift register according to any one of claims 1-4 or the gate drive circuit according to any one of claims 5-14.

16. A driving method of a shift register, characterized by, The shift register according to any one of claims 1-4 is driven by a display frame period including an input stage and an output stage. In the input stage, a first input sub-circuit transmits the working level received at the signal input end to the first node in response to the first clock signal received at the first clock signal end; A second input sub-circuit transmits the working level at the first node to the second node in response to the first clock signal received at the first clock signal end; A first storage sub-circuit stores the working level at the second node; A first output sub-circuit transmits the non-working level received at the second clock signal end to the cascade signal output end under the control of the working level at the second node; In the output stage, the first input sub-circuit cuts off the signal input end and the first node in response to the first clock signal received at the first clock signal end, and the signal received at the signal input end is a non-working level; the second input sub-circuit cuts off the first node and the second node in response to the first clock signal received at the first clock signal end; The first output sub-circuit transmits the working level received at the second clock signal end to the cascade signal output end under the control of the working level at the second node; The first storage sub-circuit writes the difference between the working level and the non-working level received at the second clock signal end into the second node; A first control sub-circuit transmits the working level received at the cascade signal output end to the first node under the control of the working level at the cascade signal output end.

17. The register driving method according to claim 16, wherein A display frame period further includes a holding stage, which is located after the output stage; In the input stage, a third input sub-circuit transmits the first voltage signal received at the first voltage signal end to the third node under the control of the voltage at the fourth node, and a second output sub-circuit cuts off the third voltage signal end and the cascade signal output end under the control of the first voltage signal at the third node; The second control sub-circuit controls the third voltage signal end and the third node to be cut off in response to the third clock signal received at the third clock signal end, and under the control of the first voltage signal at the third node, the second control sub-circuit controls the first voltage signal end and the second node to be cut off; In the output stage, the second control sub-circuit controls the second voltage signal end and the third node to be cut off in response to the third clock signal received at the third clock signal end, under the control of the first voltage signal at the third node, the second output sub-circuit controls the third voltage signal end and the cascade signal output end to be cut off, and the second control sub-circuit controls the first voltage signal end and the second node to be cut off; In the holding stage, the second control sub-circuit transmits the second voltage signal received at the second voltage signal end to the third node and transmits the first voltage signal received at the first voltage signal end to the second node in response to the third clock signal received at the third clock signal end; Under the control of the first voltage signal at the second node, the first output sub-circuit controls the second clock signal end and the cascade signal output end to be cut off; under the control of the second voltage signal at the third node, the second output sub-circuit transmits the third voltage signal received at the third voltage signal end to the cascade signal output end.

18. The register driving method of claim 17, wherein, In the output stage, under the control of the second voltage signal at the third node, the first sub-circuit controls the second voltage signal end and the fifth node to be cut off, and the second sub-circuit controls the fifth node and the second node to be cut off; under the control of the voltage at the second node, the third control sub-circuit transmits the third voltage signal received at the third voltage signal end to the fifth node.

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