Package structure and manufacturing method thereof

Abstract

A new packaging structure is developed by matching with a specific chip substrate material and characteristics, and comprises a lead frame, a crystal grain, a bonding wire, a first solder and a molding material. The die includes a substrate, a bonding pad disposed on a first surface of the substrate, and a back metal layer disposed on a second surface of the substrate. The lead frame comprises a groove, and the crystal grains are arranged in the groove. The bonding wire electrically connects the bonding pad of the die to the leadframe, the first solder is disposed between the back metal layer of the die and the recess, and the first solder solders the die to the leadframe. The molding material coats the crystal grains and the bonding wires and covers the lead frame.

Description

[Technical field]

[0001] The present disclosure relates to a chip packaging technology, and more particularly to a packaging structure including a lead frame and a manufacturing method thereof. [Background technology]

[0002] With the development of 5G communication and electric vehicle industries and various electronic products, the demand for high-frequency and high-power semiconductor components is also growing. These high-frequency and high-power semiconductor components can be, for example, high-frequency transistors, high-power field-effect transistors or high electron mobility transistors (HEMT). High-frequency and high-power semiconductor components generally use semiconductor compounds, such as III-V semiconductor compounds such as gallium nitride and silicon carbide, which have the characteristics of high frequency, high voltage resistance, low on-resistance, etc., and are usually used under high voltage and high temperature operating conditions. Generally speaking, high-frequency and high-power semiconductor components can be bonded to a printed circuit board using traditional packaging, such as die bonding, wire bonding and molding, so that the semiconductor components can be fixed to the printed circuit board.

[0003] However, conventional chip packaging is generally more suitable for semiconductor devices operating at low voltage and room temperature. For semiconductor devices operating at high voltage and high temperature, conventional chip packaging does not fully reflect the advantages of new materials in all aspects to achieve packaging optimization. [Summary of the invention]

[0004] In view of this, the present disclosure proposes a packaging structure and a manufacturing method thereof, which are suitable for semiconductor components operating at high voltage and high temperature, wherein the die has a back metal layer, the lead frame has a groove, the die is placed in the groove of the lead frame, and the back metal layer of the die is soldered to the lead frame by solder. The main advantage of some embodiments of the present disclosure is that the die utilizes the excellent heat dissipation capability of the composite substrate (QST substrate), and the height of the overall packaging structure is reduced, which can greatly improve the heat dissipation effect of the packaging structure. At the same time, in order to take into account the mass production of the packaging production, the use of the lead frame is still retained, so that batch production can be achieved and it is suitable for current mass production machines to save production costs.

[0005] According to one embodiment of the present disclosure, a packaging structure is provided, including a lead frame, a die, a bonding wire, a first solder, and a molding material. The lead frame includes a groove, and the die is disposed in the groove. The die includes a substrate, a bonding pad, and a back metal layer, wherein the bonding pad is disposed on a first surface of the substrate, and the back metal layer is disposed on a second surface of the substrate. The bonding wire electrically connects the bonding pad of the die to the lead frame, the first solder is disposed between the back metal layer and the groove, and the die is welded to the lead frame through the first solder. The molding material covers the die and the bonding wire, and covers the lead frame.

[0006] According to one embodiment of the present disclosure, a method for manufacturing a packaging structure is provided, comprising the following steps: providing a lead frame and forming a groove in the lead frame; providing a die, including: providing a substrate having a first surface and a second surface; forming a bonding pad on the first surface; and forming a back metal layer on the second surface; placing the die in the groove; using a first solder to solder the back metal layer of the die to the lead frame; forming a bonding wire to electrically connect the bonding pad of the die to the lead frame; and using a molding material to encapsulate the die and the bonding wire and cover the lead frame.

[0007] In order to make the features of the present disclosure more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description as follows.

Brief Description of the Drawings

[0008] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading this disclosure. The specific embodiments of the present disclosure are explained in detail through the specific embodiments in this article and with reference to the corresponding drawings, and the working principles of the specific embodiments of the present disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced. Figure 1 FIG. 4 is a cross-sectional schematic diagram of a packaging structure according to an embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view of a substrate of a die according to some embodiments of the present disclosure. Figure 3 FIG. 4 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present disclosure. Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 Schematic cross-sectional views of some stages of a method for manufacturing a packaging structure according to an embodiment of the present disclosure. [Specific implementation method]

[0009] The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the sake of simplicity, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and / or text annotations. The use of these repeated reference symbols and annotations is to make the description more concise and clear, rather than to indicate the relationship between different embodiments and / or configurations.

[0010] In addition, for the spatially related descriptive words mentioned in the present disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one component or feature and another (or multiple) components or features in the drawings. In addition to the orientation shown in the drawings, these spatially related words are also used to describe the possible orientations of the package structure during use and operation. As the orientation of the package structure is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0011] Although the present disclosure uses the terms first, second, third, etc. to describe various components, parts, regions, layers, and / or sections, it should be understood that these components, parts, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish a certain component, part, region, layer, and / or block from another component, part, region, layer, and / or block, and they themselves do not imply or represent any previous ordinal number of the component, nor do they represent the order of arrangement of a certain component and another component, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first component, part, region, layer, or block discussed below can also be referred to as the second component, part, region, layer, or block.

[0012] The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0013] The terms "coupled", "coupled", and "electrically connected" mentioned in the present disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0014] In the present disclosure, "compound semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element, which may also be referred to as a group III-V compound semiconductor. The group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Further, the "compound semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), the like or a combination of the above compounds, but not limited thereto.

[0015] Although the invention disclosed herein is described below by way of specific embodiments, the inventive principles disclosed herein may also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the art.

[0016] The present disclosure relates to a packaging structure of a crystal grain and a manufacturing method thereof. A back metal layer is formed on the back of the crystal grain, a groove is formed on a lead frame, the crystal grain is placed in the groove of the lead frame, and the back metal layer of the crystal grain is soldered to the lead frame by solder, thereby reducing the height of the packaging structure and greatly improving the heat dissipation effect of the packaging structure. The invention is particularly suitable for semiconductor components operating at high voltage and high temperature, such as high-frequency and high-power semiconductor components using III-V compound semiconductors.

[0017] In addition, in some embodiments disclosed herein, the base of the die may be a composite substrate (QST (Qromis Substrate Technology) substrate). The thermal conductivity of the QST substrate is more than 100 times that of the silicon substrate. The use of the QST substrate can provide excellent heat dissipation capabilities. Combined with the packaging method of the embodiments disclosed herein, the heat dissipation effect of the die packaging structure can be greatly improved.

[0018] Figure 1 1 is a cross-sectional view of a package structure 100 according to an embodiment of the present disclosure. The package structure 100 includes a lead frame 101, such as a lead frame made of copper or other metal with better heat dissipation. The lead frame 101 includes a first portion 101-1 and a second portion 101-2 separated from each other, and a groove 103 is formed in the first portion 101-1 of the lead frame 101. In some embodiments, in the Z-axis direction, the depth d of the groove 103 may be one quarter to one half of the thickness T of the lead frame 101, so that the lead frame 101 with the groove 103 can still provide sufficient support for the die. For example, the thickness T of the lead frame 101 may be about 400 micrometers (μm), and the depth d of the groove 103 may be about 100 μm to 200 μm, but is not limited thereto. A first conductive pad 105-1 and a second conductive pad 105-2 may be respectively disposed on the first portion 101-1 and the second portion 101-2 of the lead frame 101 for subsequent wire bonding between the lead frame 101 and the die. In this embodiment, the lead frame 101 may further include a through hole 104 formed under the bottom surface of the groove 103, and the through hole 104 penetrates the thinner portion of the lead frame 101 located under the groove 103, so that the through hole 104 is connected to the groove 103.

[0019] In addition, the package structure 100 includes a die 110 disposed in a groove 103 of a lead frame 101. The die 110 includes a substrate 111 having a first surface 111A and a second surface 111B opposite to each other. In one embodiment, a semiconductor layer 112 may be formed on the first surface 111A of the substrate 111, and a plurality of bonding pads (bonding pads) separated from each other laterally, such as a first bonding pad 113-1 and a second bonding pad 113-2, may be formed on the semiconductor layer 112. In some embodiments, the composition of the semiconductor layer 112 may include silicon, polysilicon, or a III-V compound semiconductor, and the semiconductor layer 112 may be a single semiconductor layer or a semiconductor stack, wherein the single semiconductor layer may be a silicon layer, a polysilicon layer, or a III-V compound semiconductor layer. The semiconductor stack may include stacked semiconductor sublayers, such as a plurality of III-V compound semiconductor sublayers, each of which may be composed of, for example, gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), aluminum nitride (AlN), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), aluminum gallium nitride (InAlGaN) or indium gallium nitride (InGaN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs) or indium gallium arsenide (InGaAs), but not limited thereto. In some embodiments, the semiconductor layer 112 may be used to fabricate a high electron mobility transistor (HEMT) or other high power transistors, and a plurality of bonding pads on the semiconductor layer 112, such as the first bonding pad 113-1 and the second bonding pad 113-2, are electrically connected to electrodes of the transistor. The first bonding pad 113-1 and the second bonding pad 113-2 can be a single-layer structure or a composite structure. For example, the composition of the single-layer structure may include Au, Ag or Cu, and the multi-layer structure can be selected from the group consisting of Ti / Ni / Au, Ti / Cu, Ti / Au, Cu / Ni / Au, Ni / Pd / Au, Ni / Au, Au / As, Al / Ni / Ag and combinations of the foregoing.

[0020] In some embodiments, the substrate 111 of the die 110 may be a semiconductor substrate, such as a silicon substrate or other semiconductor substrates. In other embodiments, the substrate 111 of the die 110 may be a composite substrate (or QST substrate) composed of a core layer and a composite material layer. Figure 21 is a cross-sectional schematic diagram of a substrate 111 of a crystal grain 110 of some embodiments disclosed herein. In one embodiment, the substrate 111 may be a QST substrate 111Q1, which includes a core layer 111C and a composite material layer 111D wrapping the core layer 111C. The composite material layer 111D may include a plurality of insulating layers and a plurality of semiconductor bonding layers arranged in sequence, such as a first insulating layer 111D-1, a semiconductor bonding layer 111D-2, and a second insulating layer 111D-3 wrapping the core layer 111C in sequence from the inside to the outside, but not limited thereto. In some embodiments, the composition of the core layer 111C may be aluminum nitride (AlN), silicon carbide (SiC), aluminum oxide (Al2O3) (or referred to as a sapphire substrate), or a ceramic substrate of a combination of the foregoing. The first insulating layer 111D-1 and the second insulating layer 111D-3 may be insulating layers of the same or different compositions, such as oxides, nitrides, oxynitrides, or other suitable insulating materials, and the semiconductor bonding layer 111D-2 may be a semiconductor material, such as silicon, but not limited thereto. Compared to a single crystal silicon substrate, a QST substrate is used as the base 111 of the die 110. In addition to having a higher mechanical strength than a single crystal silicon substrate and being less prone to cracking or bending, the QST substrate can also provide a better heat dissipation effect. For example, the thermal conductivity k value of a silicon substrate is about 1.1 watts / meter·absolute temperature (W / m·k), and the thermal conductivity k value of a QST substrate is about 220W / m·k, wherein a higher thermal conductivity k value represents better thermal conductivity. According to some embodiments of the present disclosure, the use of a QST substrate can provide excellent heat dissipation capabilities. For example, the heat dissipation capability of a QST substrate is significantly superior to that of a silicon substrate, and thus the heat dissipation effect of the die packaging structure can be greatly improved.

[0021] See also Figure 1 According to some embodiments of the present disclosure, a backside metal layer (BM) 114 is formed on the second surface 111B of the substrate 111 of the die 110. The backside metal layer 114 can be a single-layer structure or a multi-layer structure, wherein the composition of the single-layer structure is, for example, Au, Ag, Cu or pre-solder, and the multi-layer structure can be selected from the group consisting of Ti / Ni / Ag, Ti / NiV / Ag, Ti / Ni / Au, Ti / Cu, Ti / Au, Cu / Ni / Au, Ni / Pd / Au, Ni / Au, Au / As, Al / Ni / Ag and combinations thereof. In one embodiment, the substrate 111 can be a silicon substrate, and the backside metal layer 114 can be formed on the back side of the silicon substrate. See also Figure 1 and Figure 2In one embodiment, the substrate 111 is a QST substrate 111Q1, and the back metal layer 114 may be formed on the back side of the QST substrate 111Q1, for example, on the bottom surface of the second insulating layer 111D-3. In another embodiment, the substrate 111 is a QST substrate 111Q2, and the QST substrate 111Q1 may be subjected to a back thinning and cutting separation process, so that the composite material layer 111D located on the bottom surface B and the side surface S of the core layer 111C is removed, and the composite material layer 111D located on the top surface of the core layer 111C is retained to form the QST substrate 111Q2. In this embodiment, the back metal layer 114 formed on the back side of the QST substrate 111Q2 contacts the bottom surface B of the core layer 111C. In some embodiments, the back metal layer 114 may cover at least 60% of the second surface 111B of the substrate 111, for example, 60% to 100% of the bottom surface area. In addition, the back metal layer 114 is selected from a metal material whose surface is easily wetted by liquid or molten solder. For example, at least 80% of the surface of the back metal layer 114 can be wetted by liquid or molten solder. Since the back metal layer 114 can form a solder joint with the solder, the back metal layer 114 is formed on the second surface 111B of the base 111 of the grain 110, which helps to subsequently use solder to solder the grain 110 to the lead frame 101.

[0022] In addition, the package structure 100 includes a plurality of bonding wires, which respectively electrically connect the plurality of bonding pads of the die 110 to the plurality of conductive pads of the lead frame 101, for example, the first bonding wire 121 electrically connects the first bonding pad 113-1 to the first conductive pad 105-1 of the lead frame 101, and the second bonding wire 122 electrically connects the second bonding pad 113-2 to the second conductive pad 105-2 of the lead frame 101. The package structure 100 further includes a molding material 130 to encapsulate the die 110 and the plurality of bonding wires, for example, the first bonding wire 121, the second bonding wire 122 and the other bonding wires, and the molding material 130 covers the top surface of the lead frame 101. In one embodiment, the molding material 130 may be a polymer resin, for example, an epoxy resin.

[0023] like Figure 1As shown, the package structure 100 further includes a first solder 115, such as solder, disposed between the back metal layer 114 and the groove 103 of the lead frame 101. The die 110 can be welded to the lead frame 101 through welding between the first solder 115 and the back metal layer 114. In addition, the package structure 100 can also include a printed circuit board 140 disposed below the lead frame 101, and a second solder 117, such as solder, disposed between the lead frame 101 and the printed circuit board 140. The lead frame 101 can be welded to the printed circuit board 140 through the second solder 117. In this embodiment, a through hole 104 is provided below the bottom surface of the groove 103 of the lead frame 101, and the second solder 117 fills the through hole 104 and contacts the back metal layer 114 and the first solder 115. In one embodiment, the second solder 117 and the first solder 115 can have the same composition, so that no obvious boundary is generated between the second solder 117 and the first solder 115. In another embodiment, the second solder 117 and the first solder 115 may have different compositions, and a boundary may be generated between the second solder 117 and the first solder 115. Since the back metal layer 114 can be soldered with the second solder 117, the base 111 of the die 110 can be directly soldered to the printed circuit board 140 through the second solder 117, and the second solder 117 can be disposed on a conductive pad (not shown) of the printed circuit board 140. In addition, the heat generated during the operation of the die 110 can also pass through the base 111, and directly dissipate the heat to the printed circuit board 140 through the through hole 104 of the lead frame 101 and the second solder 117, which helps to improve the heat dissipation effect of the package structure 100.

[0024] Figure 3 is a cross-sectional schematic diagram of a package structure 100 according to another embodiment of the present disclosure. Figure 3 In the package structure 100, no through hole is provided below the bottom surface of the groove 103 of the lead frame 101, and the first solder 115 can contact the entire bottom surface of the back metal layer 114 and the entire bottom surface of the groove 103. The second solder 117 is located between the lead frame 101 and the printed circuit board 140, and the second solder 117 does not contact the back metal layer 114 and the first solder 115. Figure 3 For details of other component features of the package structure 100, please refer to the aforementioned Figure 1 The relevant description of the packaging structure 100 will not be repeated here.

[0025] The conventional chip packaging structure uses silver glue to fix the chip on the lead frame. The thermal conductivity k value of the silver glue is about 2W / m·k. The thermal conductivity k value of the first solder 115 and the second solder 117 used in the packaging structure 100 of some embodiments of the present disclosure is about 64W / m·k, and its heat dissipation effect is about 30 times or more than that of the silver glue. Therefore, the packaging structure of some embodiments of the present disclosure uses the first solder 115 to replace the silver glue used in the conventional chip packaging structure, which can improve the heat dissipation effect of the packaging structure by about 30 times or more. In addition, in the packaging structure 100 of some embodiments of the present disclosure, a groove 103 is formed in the lead frame 101, and the chip 110 is placed in the groove 103, so the height of the packaging structure can be reduced. For example, compared with the packaging structure using a lead frame without a groove, the packaging structure of some embodiments of the present disclosure can reduce the height of the packaging structure by about 15% to 25%, which is conducive to the demand for miniaturization of the package size.

[0026] In addition, in some embodiments of the present disclosure, the base 111 of the crystal grain 110 can adopt a QST substrate instead of a silicon substrate, wherein the thermal conductivity k value of the silicon substrate is about 1.1W / m·k, while the thermal conductivity k value of the QST substrate is about 220W / m·k, so the use of a QST substrate can improve the heat dissipation effect. In addition, according to some embodiments of the present disclosure, a back metal layer 114 is formed on the back side of the QST substrate, whereby the crystal grain 110 can be soldered to the lead frame using a first solder 115 without the need to use silver glue, and the heat dissipation effect of the solder material of the first solder 115 is more than dozens of times that of silver glue. Therefore, the packaging structure of some embodiments of the present disclosure can greatly improve the heat dissipation effect by using a QST substrate, a back metal layer 114 and a first solder 115.

[0027] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 is a cross-sectional schematic diagram of some stages of a method for manufacturing a packaging structure according to an embodiment of the present disclosure, see Figure 4 In step S101, a lead frame 101 is provided, such as a copper lead frame. In some embodiments, the thickness T of the lead frame 101 is, for example, about 400 μm. Figure 4In step S103, an etching process is used to form a groove 103 in the lead frame 101. In some embodiments, the depth d of the groove 103 is, for example, about 100 μm, but not limited thereto, as long as the lead frame 101 formed with the groove 103 can provide sufficient support for the die during the packaging process, for example, when the thickness T of the lead frame 101 is larger, the depth d of the groove 103 can be deepened. Then, the lead frame 101 can be mechanically drilled to form a through hole 104 below the bottom surface of the groove 103, and the through hole 104 is connected to the groove 103. In addition, a plurality of conductive pads may be formed on the lead frame 101, such as a first conductive pad 105-1 and a second conductive pad 105-2, which are respectively located on the first portion 101-1 and the second portion 101-2 of the lead frame 101, wherein the first portion 101-1 and the second portion 101-2 corresponding to the same die are laterally separated from each other, and the area between the first portion 101-1 and the second portion 101-2 corresponding to adjacent die is a predetermined formation area for the cutting path 131.

[0028] See also Figure 5 In step S105, a plurality of crystal grains 110 are provided, and the crystal grains 110 are simultaneously and independently placed in the plurality of grooves 103 of the lead frame 101, and the crystal grains 110 are soldered to the lead frame 101 using a first solder 115. Regarding the production of the crystal grains 110, an epitaxial growth process can be used to form a semiconductor layer 112 on the first surface 111A of the base 111 of the crystal grains 110. In one embodiment, the semiconductor layer 112 can be a gallium nitride (GaN) layer, but is not limited thereto. Figure 2 In one embodiment, the substrate 111 may be a QST substrate 111Q2, whose core layer 111C is, for example, aluminum nitride (AlN), and the composite material layer 111D is located on the top surface of the core layer 111C. Then, deposition, photolithography and etching processes may be used to form a plurality of bonding pads on the semiconductor layer 112, such as a first bonding pad 113-1 and a second bonding pad 113-2. In addition, an insulating polymer layer (not shown) may be selectively formed between the semiconductor layer 112 and the plurality of bonding pads, such as polyimide (PI) or polymerized benzocyclobutene (BCB), but not limited thereto. In addition, a redistribution layer (RDL) may be formed between the insulating polymer layer and the semiconductor layer 112, comprising a plurality of dielectric layers and a plurality of conductive layers, the dielectric layer being, for example, a silicon oxide layer, and the conductive layer being, for example, a copper or aluminum wire layer.

[0029] In addition, a back metal layer 114 may be formed on the second surface 111B of the substrate 111 of the die 110 by using an evaporator, sputtering, electroless plating or plating process. In one embodiment, the back metal layer 114 is a multilayer structure of Ti / Ni / Ag, for example. For other details of the features of the components of the die 110, please refer to the aforementioned Figure 1 The relevant descriptions of the present invention will not be repeated here. According to the embodiment of the present disclosure, since a back metal layer 114 is formed on the back of the die 110, the die 110 can be soldered to the lead frame 101 through the first solder 115. After the first solder 115 is applied to the bottom surface of the groove 103 and the die 110 is placed in the groove 103, a reflow process can be performed to solder and fix the die 110 to the lead frame 101.

[0030] See also Figure 6 In step S107, after the die 110 is soldered and fixed to the lead frame 101 by the first solder 115, a wire bonding process is performed to form a plurality of bonding wires to electrically connect the plurality of bonding pads of the die 110 to the lead frame 101, for example, a first bonding wire 121 may be formed to electrically connect the first bonding pad 113-1 of the die 110 to the first conductive pad 105-1 of the lead frame 101, and a second bonding wire 121 may be formed to electrically connect the second bonding pad 113-2 of the die 110 to the second conductive pad 105-2 of the lead frame 101. In some embodiments, the bonding wire is, for example, a gold wire (Au wire), a copper wire (Cu wire), a palladium copper wire (PdCu wire), a silver wire (Ag wire), or other metal wires. Since the die 110 has been soldered and fixed to the lead frame 101 by the first solder 115, the position of the die 110 will not be skewed or offset during the wire bonding process, which helps to improve the yield and quality of the package structure. Next, a molding material 130 , such as a molding compound or other dielectric materials, is applied to encapsulate the plurality of dies 110 and the plurality of bonding wires, and the molding material 130 covers the lead frame 101 .

[0031] See also Figure 7 In step S109, after the plurality of dies 110 and the plurality of bonding wires are encapsulated with the molding material 130, a blade saw and a die break dicing process are used to cut and separate the molding material 130, the plurality of dies 110 and the lead frame 101 along the dicing lines 131 to form a package 150 of a plurality of single dies.

[0032] Afterwards, see Figure 8In step S111, a printed circuit board 140 is provided, a second solder 117 is applied to the printed circuit board 140, and then a plurality of single-chip packages 150 are placed on the printed circuit board 140, wherein the second solder 117 is located between the lead frame 101 and the printed circuit board 140. A reflow process is performed to solder the lead frame 101 to the printed circuit board 140 through the second solder 117, so that the plurality of single-chip packages 150 are soldered to the printed circuit board 140, thereby completing Figure 1 In this embodiment, after the reflow process, the second solder 117 fills the through hole 104 of the lead frame 101 , and the second solder 117 contacts the back metal layer 114 of the die 110 and the first solder 115 .

[0033] in addition, Figure 2 The package structure 100 may also be used Figures 4 to 8 The difference is that Figure 4 In step S103 , no through hole is formed below the groove 103 of the lead frame 101 .

[0034] The package structure of the embodiments disclosed herein may be applicable to various package types, such as a transistor outline (TO) package, a small outline integrated circuit (SOIC) package, a quad flat package (QFP), a dual flat no-lead (DFN) package, a quad flat no-lead (QFN) package, a ball grid array (BGA) package, or other types of packages.

[0035] According to some embodiments of the present disclosure, a groove is formed on the lead frame, a back metal layer is formed on the back of the grain, the grain is placed in the groove of the lead frame, and the back metal layer of the grain can be soldered to the lead frame by solder. The height of the package structure can be reduced by the groove of the lead frame, and the heat dissipation effect of the package structure can be improved by soldering the back metal layer. When the base of the grain adopts a QST substrate, the heat dissipation effect of the package structure can also be greatly improved. The package structure disclosed in the present disclosure is particularly suitable for semiconductor components operating at high voltage and high temperature, such as high-frequency, high-power semiconductor components made of III-V compound semiconductors. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the present invention.

Explanation of symbols

[0036] 100…Package structure 101…Lead rack 101-1…Part 1 101-2…Part 2 103…Groove 104…Through holes 105-1…first conductive pad 105-2…second conductive pad 110…Grain 111…base 111A…first surface 111B…Second surface 111C…Core layer 111D…Composite material layer 111D-1…First insulation layer 111D-2…Semiconductor bonding layer 111D-3…Second insulation layer 111Q1, 111Q2…QST substrate 113-1…first bonding pad 113-2…Second bonding pad 114…Back metal layer 115…First solder 117…Second solder 121…first bonding line 122…Second bonding line 130…Mold sealing material 131… Cutting Road 140…Printed circuit board 150…Single die package B…Bottom S…Side d…depth T…Thickness S101, S103, S105, S107, S109, S111…steps

Claims

1. A packaging structure, comprising: A wire frame including a groove; A die is disposed in the groove, and the die comprises: A substrate having a first surface and a second surface; a bonding pad disposed on the first surface; and A back metal layer is disposed on the second surface; a bonding wire electrically connecting the bonding pad to the lead frame; a first solder disposed between the back metal layer and the groove, the first solder soldering the die to the lead frame; and A molding material encapsulates the die and the bonding wire and covers the lead frame.

2. The package structure according to claim 1, further comprising: A printed circuit board is disposed below the lead frame; as well as A second solder is disposed between the lead frame and the printed circuit board, and the second solder solders the lead frame to the printed circuit board. 3 . The packaging structure as claimed in claim 2 , wherein the lead frame further comprises a through hole disposed under the bottom surface of the groove. 4 . The package structure as claimed in claim 3 , wherein the second solder fills the through hole, and the second solder contacts the back metal layer and the first solder. 5 . The packaging structure as claimed in claim 1 , wherein the base comprises a semiconductor substrate, or a core layer and a composite material layer wrapping the core layer. 6 . The packaging structure as claimed in claim 5 , wherein the semiconductor substrate is composed of silicon, the core layer is composed of aluminum nitride, silicon carbide, aluminum oxide or a combination thereof, and the composite material layer comprises an insulating layer and a semiconductor bonding layer. The package structure as claimed in claim 5 , wherein the back metal layer contacts a bottom surface of the core layer.

8. The package structure as claimed in claim 1, wherein the back metal layer comprises a single-layer structure or a multi-layer structure, the single-layer structure comprises Au, Ag, Cu or pre-solder, and the multi-layer structure is selected from the group consisting of Ti / Ni / Ag, Ti / NiV / Ag, Ti / Ni / Au, Ti / Cu, Ti / Au, Cu / Ni / Au, Ni / Pd / Au, Ni / Au, Au / As, Al / Ni / Ag and combinations thereof. 9 . The package structure as claimed in claim 1 , wherein the die further comprises a semiconductor layer disposed on the first surface of the substrate, and the bonding pad is located on the semiconductor layer, and the semiconductor layer is composed of silicon or III-V compound semiconductor. 10 . The package structure as claimed in claim 1 , wherein a depth of the groove is one quarter to one half of a thickness of the lead frame.

11. A method for manufacturing a packaging structure, comprising: Providing a lead frame and forming a groove in the lead frame; A die is provided, comprising: Providing a substrate having a first surface and a second surface; forming a bonding pad on the first surface; and forming a back metal layer on the second surface; placing the die in the groove; Using a first solder to solder the back metal layer of the die to the lead frame; forming a bonding wire to electrically connect the bonding pad to the lead frame; and A molding material is used to encapsulate the die and the bonding wires and cover the lead frame.

12. The method for manufacturing a package structure according to claim 11, further comprising: Providing a printed circuit board, placed below the lead frame; as well as The lead frame is soldered to the printed circuit board using a second solder. 13 . The method for manufacturing a package structure as claimed in claim 12 , further comprising forming a through hole under a bottom surface of the groove. 14 . The method for manufacturing a package structure as claimed in claim 13 , wherein the second solder fills the through hole and contacts the back metal layer and the first solder. 15 . The method for manufacturing a package structure as claimed in claim 13 , wherein forming the groove comprises an etching process, and forming the through hole comprises mechanical drilling. 16 . The method for manufacturing a package structure as claimed in claim 11 , wherein providing the base comprises providing a semiconductor substrate, or providing a core layer and forming a composite material layer to wrap the core layer. 17 . The method for manufacturing a package structure as claimed in claim 16 , wherein the semiconductor substrate is composed of silicon, the core layer is composed of aluminum nitride, silicon carbide, aluminum oxide or a combination thereof, and the composite material layer comprises an insulating layer and a semiconductor bonding layer.

18. The method for manufacturing a packaging structure as claimed in claim 11, wherein forming the back metal layer comprises an evaporation, sputtering or electroplating process, and the back metal layer comprises a single-layer structure or a multi-layer structure, the single-layer structure comprises Au, Ag, Cu or pre-solder, and the multi-layer structure is selected from the group consisting of Ti / Ni / Ag, Ti / NiV / Ag, Ti / Ni / Au, Ti / Cu, Ti / Au, Cu / Ni / Au, Ni / Pd / Au, Ni / Au, Au / As, Al / Ni / Ag and combinations thereof. 19 . The method for manufacturing a package structure as claimed in claim 11 , wherein providing the die further comprises forming a semiconductor layer on the first surface, and the bonding pad is formed on the semiconductor layer, and the semiconductor layer comprises silicon or a III-V compound semiconductor.

20. The method for manufacturing a package structure according to claim 12, wherein providing the lead frame comprises forming a plurality of grooves therein. The manufacturing method of the packaging structure also includes: Providing a plurality of dies, and placing the dies in the grooves simultaneously and independently; Using the first solder to solder the die to the lead frame; After encapsulating the die with the molding material, cutting and separating the molding material, the die and the lead frame to form a package of a plurality of single die; and The second solder is used to solder the packages of the single dies to the printed circuit board.

Images