Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the method comprises the steps: providing a substrate which comprises a bonding surface, the bonding surface comprises a plurality of unit regions, each unit region comprises a chip region, and a grounding welding pad is formed in the unit region at the side part of the chip region; providing a plurality of chips; bonding a chip on the chip area of the bonding surface; forming a first interconnection structure electrically connected with the grounding welding pad; a conductive heat dissipation cover is arranged at the top of the chip; and in the unit region, forming a second interconnection structure electrically connected with the corresponding conductive heat dissipation cover and the first interconnection structure. According to the invention, electromagnetic interference on a circuit or a signal of the chip is reduced, and the performance of the packaging structure is guaranteed.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a packaging method. Background Art

[0002] With the rapid development of communication technology, the operating frequency of digital IC (integrated circuit) chips is constantly increasing. Since the AC signal in the chip can be radiated to space in the form of an electromagnetic field, the frequency of the electromagnetic signal radiated outward during chip operation also increases, and the wavelength of the radiated electromagnetic signal decreases accordingly. In this way, there are many conductors in the chip whose sizes are comparable to the wavelength of the electromagnetic signal. At this time, these conductors can show antenna effect to the electrical signal, radiating the electrical signal with a wavelength comparable to the conductor length with greater intensity. Moreover, when a heat sink is provided on the chip package, this antenna effect will be aggravated by the presence of the heat sink, thereby causing electromagnetic interference to other circuits or signals, reducing the performance of communication products.

[0003] In the prior art, the chip heat sink is usually grounded at the corners with leads or screws to achieve electromagnetic interference shielding of the package. However, this method not only occupies too much layout space of the circuit board, but also produces higher impedance to high-frequency signals through the inductance effect generated by the leads or screws, so the shielding performance against high-frequency electromagnetic interference is poor. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are beneficial to ensuring the performance of the packaging structure.

[0005] To solve the above problems, the present invention provides a packaging structure, including: a substrate, including a bonding surface, the bonding surface including a chip area, and a grounding pad is formed on the substrate on the side of the chip area; a chip is bonded to the chip area of ​​the bonding surface; a conductive heat dissipation cover is located on the top of the chip; a first interconnection structure is located on the side of the chip and is electrically connected to the grounding pad; a second interconnection structure is located on the side of the chip and is electrically connected to the first interconnection structure and the conductive heat dissipation cover.

[0006] Optionally, the first interconnect structure is an interconnect line electrically connected to the ground pad.

[0007] Optionally, the packaging structure also includes: a plastic encapsulation layer covering the side walls of the chip, the plastic encapsulation layer and the chip forming a chip structure; a first interconnection structure is located in the plastic encapsulation layer, and the plastic encapsulation layer exposes a cross-section of the first interconnection structure; and the second interconnection structure is electrically connected to the first interconnection structure by contacting the cross-section of the first interconnection structure.

[0008] Optionally, the second interconnect structure covers a portion of the side wall of the chip structure from the location of the first interconnect structure to the conductive heat dissipation cover.

[0009] Optionally, the conductive heat dissipation cover is made of metal material.

[0010] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a substrate, including a bonding surface, the bonding surface including multiple unit areas, the unit area including a chip area, and a grounding pad is formed in the unit area on the side of the chip area; providing multiple chips; bonding the chips to the chip area of ​​the bonding surface; forming a first interconnection structure electrically connected to the grounding pad; setting a conductive heat dissipation cover on the top of the chip; and forming a second interconnection structure in the unit area that electrically connects the corresponding conductive heat dissipation cover to the first interconnection structure.

[0011] Optionally, the step of forming a first interconnection structure electrically connected to the ground pad includes: forming an interconnection line electrically connected to the ground pads of adjacent unit areas between opposite side walls of chips in adjacent unit areas, wherein, in each interconnection line, a portion of the length of the interconnection line connected to the ground pads at both ends serves as the first interconnection structure of the unit area corresponding to the ground pad; before forming a second interconnection structure electrically connecting the corresponding conductive heat dissipation cover to the first interconnection structure, it also includes: dividing each interconnection line so that the first interconnection structures of adjacent unit areas are spaced apart.

[0012] Optionally, a wire bonding process is used to form interconnection lines that electrically connect ground pads of adjacent unit areas.

[0013] Optionally, in the step of providing a substrate, multiple unit areas constitute a packaging area; in the step of forming interconnection lines that electrically connect ground pads of adjacent unit areas, the interconnection lines are also formed at the boundaries of the packaging area, and cross the boundaries and electrically connect the ground pads at the boundaries of the packaging area.

[0014] Optionally, after forming a first interconnection structure electrically connected to the ground pad and before setting a conductive heat dissipation cover on the top of the chip, the packaging method also includes: forming a plastic layer covering the side walls of the chip, and plastic-sealing the chips of multiple unit areas into an integrated structure located in the packaging area; before forming a second interconnection structure electrically connected to the conductive heat dissipation cover corresponding to the first interconnection structure, the method also includes: pre-cutting the integrated structure at the boundary of adjacent unit areas, removing a portion of the thickness of the plastic layer to form a notch, the notch dividing the interconnection line and exposing a cross-section of the first interconnection structure; in the step of forming a second interconnection structure electrically connected to the conductive heat dissipation cover corresponding to the first interconnection structure, the first interconnection structure contacts the second interconnection structure through the cross-section of the first interconnection structure, so that the first interconnection structure is electrically connected to the second interconnection structure.

[0015] Optionally, in the step of forming a second interconnect structure electrically connecting the corresponding conductive heat dissipation cover and the first interconnect structure, the second interconnect structure covers the sidewalls and the bottom of the recess.

[0016] Optionally, after forming a second interconnect structure electrically connecting the corresponding conductive heat dissipation cover and the first interconnect structure, the packaging method further includes: cutting the remaining plastic encapsulation layer and the substrate at the boundary of adjacent unit areas in the integrated structure along the notch to form a chip structure corresponding to a plurality of discrete unit areas.

[0017] Optionally, the step of providing a conductive heat dissipation cover on the top of the chip includes: forming a conductive heat dissipation layer covering the top of the integrated structure; and cutting the conductive heat dissipation layer at the boundary of adjacent unit areas to form a conductive heat dissipation cover separated from the top of each chip.

[0018] Optionally, in the step of pre-cutting the integrated structure, the conductive heat dissipation layer at the boundary between adjacent unit areas is cut.

[0019] Optionally, after forming a first interconnect structure electrically connected to the ground pad and before setting a conductive heat dissipation cover on the top of the chip, the packaging method also includes: forming a plastic layer covering the side walls of the chip, and plastic-sealing the chips of multiple unit areas into an integrated structure located in the packaging area; before forming a second interconnect structure electrically connected to the conductive heat dissipation cover corresponding to the first interconnect structure, the method also includes: dividing the interconnect lines by cutting the plastic layer and the substrate at the boundaries of adjacent chip areas in the integrated structure, and forming discrete chip structures corresponding to multiple unit areas, with the side walls of the chip structures exposing the cross-section of the first interconnect structure; in the step of forming the second interconnect structure electrically connected to the conductive heat dissipation cover corresponding to the first interconnect structure, the first interconnect structure is contacted with the second interconnect structure through the cross-section of the first interconnect structure, so that the first interconnect structure is electrically connected to the second interconnect structure.

[0020] Optionally, a sputtering process is used to form a second interconnect structure electrically connecting the corresponding conductive heat dissipation cover and the first interconnect structure.

[0021] Optionally, in the step of providing a conductive heat dissipation cover on the top of the chip, the conductive heat dissipation cover is made of metal material.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0023] An embodiment of the present invention provides a packaging structure, wherein a substrate comprises a bonding surface, the bonding surface comprises a chip area, a grounding pad is formed on the substrate at a side of the chip area, a chip is bonded to the chip area of ​​the bonding surface, a conductive heat dissipation cover is located at the top of the chip, a first interconnection structure is located at the side of the chip and is electrically connected to the grounding pad, and a second interconnection structure is located at the side of the chip and is electrically connected to the first interconnection structure and the conductive heat dissipation cover; in the embodiment of the present invention, the first interconnection structure is electrically connected to the grounding pad, and the second interconnection structure is electrically connected to the first interconnection structure and the conductive heat dissipation cover, so that the conductive heat dissipation cover is electrically connected to the grounding pad, and the conductive heat dissipation cover is grounded accordingly. During the operation of the packaging structure, it is helpful to avoid as much as possible that the conductive heat dissipation cover is not electrically connected and becomes a floating structure above the chip. The grounding of the conductive heat dissipation cover can drain current to form a loop, which is helpful to weaken the antenna effect presented by the conductive heat dissipation cover when the chip transmits signals or energy, thereby helping to reduce electromagnetic interference to the circuit or signal of the chip and ensure the performance of the packaging structure.

[0024] An embodiment of the present invention provides a packaging method, providing a substrate, including a bonding surface, the bonding surface including a plurality of unit areas, the unit areas including a chip area, a grounding pad formed in the unit area on the side of the chip area, providing a plurality of chips, bonding the chips to the chip area of ​​the bonding surface, forming a first interconnection structure electrically connected to the grounding pad, and arranging a conductive heat dissipation cover on the top of the chip; in the embodiment of the present invention, the first interconnection structure is electrically connected to the grounding pad, and the second interconnection structure is electrically connected to the first interconnection structure and the conductive heat dissipation cover, so that the conductive heat dissipation cover is electrically connected to the grounding pad, and the conductive heat dissipation cover is correspondingly grounded. During the operation of the packaging structure, it is helpful to avoid as much as possible that the conductive heat dissipation cover is not electrically connected and becomes a floating structure above the chip. The grounding of the conductive heat dissipation cover can drain current to form a loop, which is helpful to weaken the antenna effect presented by the conductive heat dissipation cover when the chip transmits a signal or energy, thereby helping to reduce electromagnetic interference to the circuit or signal of the chip and ensure the performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0026] Figures 2 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, with the rapid development of communication technology, the operating frequency of digital integrated circuit (IC) chips is constantly increasing. Since the alternating current signal in the chip can be radiated to the space in the form of an electromagnetic field, the frequency of the electromagnetic signal radiated outward during the chip operation also increases, and the wavelength of the radiated electromagnetic signal decreases accordingly. In this way, there are many conductors in the chip whose sizes are comparable to the wavelength of the electromagnetic signal. At this time, these conductors can show antenna effect to the electrical signal, and radiate the electrical signal with a wavelength comparable to the length of the conductor with greater intensity. Moreover, when a heat sink is provided on the chip package, this antenna effect will be aggravated by the presence of the heat sink, thereby forming electromagnetic interference to other circuits or signals, and reducing the performance of communication products.

[0028] The conductive heat dissipation cover in the packaging structure is not electrically connected, but becomes a floating structure above the chip. During the operation of the packaging structure, when the chip transmits signals or energy, the conductive heat dissipation cover exhibits an antenna effect, causing electromagnetic interference to the circuits or signals of the chip, thereby affecting the performance of the packaging structure.

[0029] In order to solve the technical problem, an embodiment of the present invention provides a packaging method, including: providing a substrate, including a bonding surface, the bonding surface including multiple unit areas, the unit area including a chip area, and a grounding pad is formed in the unit area on the side of the chip area; providing multiple chips; bonding the chips to the chip area of ​​the bonding surface; forming a first interconnection structure electrically connected to the grounding pad; setting a conductive heat dissipation cover on the top of the chip; and forming a second interconnection structure in the unit area that electrically connects the corresponding conductive heat dissipation cover and the first interconnection structure.

[0030] In the embodiment of the present invention, the first interconnection structure is electrically connected to the ground pad, and the second interconnection structure is electrically connected to the first interconnection structure and the conductive heat dissipation cover, so that the conductive heat dissipation cover is electrically connected to the ground pad, and the conductive heat dissipation cover is correspondingly grounded. During the operation of the packaging structure, it is beneficial to avoid as much as possible that the conductive heat dissipation cover is not electrically connected and becomes a floating structure above the chip. The grounding of the conductive heat dissipation cover can drain current to form a loop, which is beneficial to weaken the antenna effect of the conductive heat dissipation cover when the chip transmits signals or energy, thereby helping to reduce electromagnetic interference to the circuits or signals of the chip and ensure the performance of the packaging structure.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention.

[0033] The packaging structure includes: a substrate 100, including a bonding surface 100a, the bonding surface 100a includes a chip area 100c, and a grounding pad 110 is formed on the side of the substrate 100 of the chip area 100c; a chip 200 bonded to the chip area 100c of the bonding surface 100a; a conductive heat dissipation cover 510, located on the top of the chip 200; a first interconnection structure 310, located on the side of the chip 200 and electrically connected to the grounding pad 110; a second interconnection structure 320, located on the side of the chip 200 and electrically connecting the first interconnection structure 310 and the conductive heat dissipation cover 510.

[0034] The substrate 100 is used to provide a process operation basis for realizing the bonding of the chip 200 . Specifically, the bonding surface 100 a of the substrate 100 is a process operation platform.

[0035] The chip area 100 a is used for bonding the chip 200 .

[0036] In this embodiment, the substrate 100 includes a base and an interconnection structure layer located on the base, and the exposed surface of the interconnection structure layer is a bonding surface 100a.

[0037] The interconnection structure layer is used to achieve bonding with the chip 200, thereby achieving electrical connection with the chip 200. The interconnection structure layer is also used to achieve electrical connection with the substrate, and accordingly can achieve electrical connection between the chip 200 and the substrate.

[0038] In this embodiment, the interconnection structure layer is a redistribution structure. Specifically, the redistribution structure may include one or more redistribution layers. In this embodiment, the redistribution structure includes multiple redistribution layers as an example for description.

[0039] The substrate is used to achieve electrical connection with the chip 200 through the interconnection structure layer, and can correspondingly be electrically connected with the external structure, thereby achieving electrical connection between the chip 200 and the external structure.

[0040] Specifically, in this embodiment, the substrate is a packaging substrate, and the packaging substrate is a printed circuit board (Printed Circuit Board, PCB).

[0041] The ground pad 110 is used to be electrically connected to the first interconnect structure 310 , so that the first interconnect structure 310 is grounded.

[0042] In this embodiment, the ground pad 110 is located on the substrate 100 at the side of the chip region 100 c , so that the first interconnect structure 310 and the second interconnect structure 320 that electrically connect the conductive heat dissipation cover 510 to the ground pad 110 can be formed at the side of the chip 200 .

[0043] In this embodiment, the material of the ground pad 110 is a metal material. Specifically, the material of the ground pad 110 includes one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0044] The chip 200 is bonded to the chip region 100 c of the bonding surface 100 a , thereby achieving electrical integration of the chip 200 and the substrate 100 , and realizing normal functions of the chip 200 .

[0045] It should be noted that the number of chips 200 in the chip area 100c is not limited. In this embodiment, the chip area 100c is bonded with one chip 200 as an example for description. In other embodiments, the number of chips in the chip area may be other.

[0046] In this embodiment, the packaging structure further includes: a conductive bump, which is located between the chip 200 and the substrate 100 and electrically connects the chip 200 and the substrate 100 .

[0047] The conductive bumps are used to achieve bonding between the chip 200 and the substrate 100 , and to achieve electrical connection between the interconnection structure layer and the chip 200 .

[0048] In this embodiment, the material of the conductive bump includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the conductive bump is tin.

[0049] For example, the conductive bump can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, with the same conductive bump spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0050] The conductive heat dissipation cover 510 is used to achieve the functions of heat conduction and heat dissipation.

[0051] In this embodiment, the conductive heat dissipation cover 510 is made of metal material.

[0052] Metal materials have good heat dissipation performance, which is beneficial to improving the thermal conductivity and heat dissipation effect of the conductive heat dissipation cover 510.

[0053] The first interconnect structure 310 is used to be electrically connected to the ground pad 110 , so that after being electrically connected to the conductive heat dissipation cover 510 , the conductive heat dissipation cover 510 and the ground pad 110 are electrically connected.

[0054] In this embodiment, the first interconnect structure 310 is an interconnect line electrically connected to the ground pad 110 .

[0055] By using interconnection lines to electrically lead out the ground pad 110 , the second interconnect structure 320 can be easily electrically connected to the first interconnect structure 310 , thereby easily realizing electrical connection between the second interconnect structure 320 and the ground pad 110 .

[0056] Specifically, in the process of the packaging structure, after the chip 200 is bonded on the substrate 100, in the step of wire bonding the chip 200, an interconnection line electrically connected to the ground pad 110 is formed without introducing additional process steps, which is conducive to simplifying the process flow, improving process efficiency, and improving the process integration of the packaging structure.

[0057] In this embodiment, the material of the first interconnect structure 310 is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0058] The second interconnect structure 320 is used to realize the electrical connection between the first interconnect structure 310 and the conductive heat dissipation cover 510 , thereby realizing the grounding of the conductive heat dissipation cover 510 .

[0059] In this embodiment, the first interconnect structure 310 is electrically connected to the ground pad 110, and the second interconnect structure 320 is electrically connected to the first interconnect structure 310 and the conductive heat dissipation cover 510, so that the conductive heat dissipation cover 510 is electrically connected to the ground pad 110, and the conductive heat dissipation cover 510 is grounded accordingly. During the operation of the packaging structure, it is beneficial to avoid as much as possible that the conductive heat dissipation cover 510 is not electrically connected and becomes a floating structure above the chip 200. The grounding of the conductive heat dissipation cover 510 can drain and form a loop, which is beneficial to weaken the antenna effect of the conductive heat dissipation cover 510 when the chip 200 transmits signals or energy, thereby reducing the electromagnetic interference to the circuit or signal of the chip 200 and ensuring the performance of the packaging structure.

[0060] In this embodiment, the material of the second interconnect structure 320 is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0061] In this embodiment, the packaging structure further includes: a plastic encapsulation layer 400 covering the side wall of the chip 200 , and the plastic encapsulation layer 400 and the chip 200 form a chip structure 610 .

[0062] The plastic packaging layer 400 is used to protect the structure of the chip 200 .

[0063] In this embodiment, the material of the plastic encapsulation layer 400 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the plastic encapsulation layer can also be made of other suitable packaging materials.

[0064] In this embodiment, the first interconnect structure 310 is located in the plastic encapsulation layer 400 , and the plastic encapsulation layer 400 exposes a cross section of the first interconnect structure 319 .

[0065] Specifically, in the process of the packaging structure, after the chip 200 is bonded on the substrate 100, the first interconnection structure 310 electrically connected to the grounding pad 110 is formed, and then the chip 200 and the first interconnection structure 310 are plastic-sealed to form a plastic sealing layer 400. Therefore, the first interconnection structure 310 is located in the plastic sealing layer 400, which is beneficial to protecting the first interconnection structure 310, so that the electrical connection between the first interconnection structure 310 and the grounding pad 110 is relatively stable, and the plastic sealing layer 400 exposes the cross-section of the first interconnection structure 310, so that the second interconnection structure 320 can be electrically connected to the first interconnection structure 310 by contacting the exposed cross-section of the first interconnection structure 310.

[0066] In this embodiment, the second interconnect structure 320 is in contact with a cross section of the first interconnect structure 310 , thereby achieving electrical connection between the second interconnect structure 320 and the first interconnect structure 310 .

[0067] The plastic encapsulation layer 400 exposes a cross section of the first interconnect structure 310 , and the second interconnect structure 320 is in contact with the exposed cross section of the first interconnect structure 310 , so that the second interconnect structure 320 and the first interconnect structure 310 can be electrically connected.

[0068] In this embodiment, the second interconnect structure 320 covers a portion of the sidewall of the chip structure 610 from the location of the first interconnect structure 310 to the conductive heat dissipation cover 510 .

[0069] The second interconnect structure 320 covers a portion of the sidewall of the chip structure 610 from the location of the first interconnect structure 310 to the conductive heat dissipation cover 510 , so that the first interconnect structure 310 is electrically connected to the conductive heat dissipation cover 510 .

[0070] Specifically, in the process of the packaging structure, after the chip 200 is bonded to the substrate 100, an interconnection line electrically connected to the ground pad 110 is formed, and then the chip 200 and the interconnection line are plastic-sealed to form a plastic layer 400, and then the plastic layer 400 is pre-cut to remove a portion of the thickness of the plastic layer 400 between adjacent chip areas 100c to form a notch, the notch cuts the interconnection line, and the interconnection line in the plastic layer 400 is retained as a first interconnection structure 310, and the notch exposes the cross-section of the first interconnection structure 310, and then a second interconnection structure 320 is formed on the side wall of the notch, so that the second interconnection structure 320 covers the side wall of the chip structure 610, from the position of the first interconnection structure 310 to part of the side wall of the conductive heat dissipation cover 510.

[0071] In other embodiments, after the plastic encapsulation layer is formed, the plastic encapsulation layer can be directly cut to form a plurality of discrete chip structures, the side walls of the chip structures expose the cross-section of the first interconnection structure, and then the second interconnection structure is formed. Therefore, the second interconnection structure can also cover the entire side walls of the chip structure.

[0072] Figures 2 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention.

[0073] refer to Figure 2 A substrate 100 is provided, including a bonding surface 100a, the bonding surface 100a includes a plurality of unit areas 100p, the unit area 100p includes a chip area 100c, and a grounding pad 110 is formed in the unit area 100p on the side of the chip area 100c.

[0074] The substrate 100 is used to provide a process operation basis for subsequent chip bonding. Specifically, the bonding surface 100a of the substrate 100 is a process operation platform.

[0075] The chip area 100 a is used for bonding the chip 200 .

[0076] In this embodiment, the substrate 100 includes a base and an interconnection structure layer located on the base, and the exposed surface of the interconnection structure layer is a bonding surface 100a.

[0077] The interconnection structure layer is used for subsequent bonding with the chip, thereby achieving electrical connection with the chip. The interconnection structure layer is also used for achieving electrical connection with the substrate, and accordingly can achieve electrical connection between the chip and the substrate.

[0078] In this embodiment, the interconnection structure layer is a redistribution structure. Specifically, the redistribution structure may include one or more redistribution layers. In this embodiment, the redistribution structure includes multiple redistribution layers as an example for description.

[0079] The substrate is used to achieve electrical connection with the chip through the interconnection structure layer, and can correspondingly be electrically connected with the external structure, thereby achieving electrical connection between the chip and the external structure.

[0080] Specifically, in this embodiment, the substrate is a packaging substrate, and the packaging substrate is a printed circuit board (Printed Circuit Board, PCB).

[0081] In this embodiment, in the step of providing the substrate 100 , a plurality of unit regions 100 p constitute a packaging region 100 s .

[0082] The packaging area 100s is used as an area for subsequently plastic-sealing a plurality of chips.

[0083] The ground pad 110 is used to be subsequently electrically connected to the first interconnect structure, so that the first interconnect structure is grounded.

[0084] In this embodiment, the ground pad 110 is located on the substrate 100 at the side of the chip region 100 c , so that a first interconnection structure and a second interconnection structure electrically connecting the conductive heat dissipation cover and the ground pad 110 can be formed at the side of the chip.

[0085] In this embodiment, the material of the ground pad 110 is a metal material. Specifically, the material of the ground pad 110 includes one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0086] refer to Figure 3 , a plurality of chips 200 are provided.

[0087] The chip 200 is used to be bonded with the substrate 100 in the future to realize the normal function of the packaging structure.

[0088] refer to Figure 4 , the chip 200 is bonded to the chip region 100c of the bonding surface 100a.

[0089] The chip 200 is bonded to the chip region 100 c of the bonding surface 100 a , thereby achieving electrical integration of the chip 200 and the substrate 100 , and realizing normal functions of the chip 200 .

[0090] It should be noted that the number of chips 200 in the chip area 100c is not limited. In this embodiment, the chip area 100c is bonded with one chip 200 as an example for description. In other embodiments, the number of chips in the chip area may be other.

[0091] It should also be noted that the number of chip regions 100c in the unit region 100p is not limited, and in this embodiment, one chip region 100c in the unit region 100p is used as an example for description. In other embodiments, the number of chip regions in the unit region may be other.

[0092] In this embodiment, the step of bonding the chip 200 to the chip area 100c of the bonding surface 100a includes: forming a conductive bump at the bottom of the chip 200, or on the substrate 100 in the chip area 100c; bonding the chip 200 to the substrate 100 in the chip area 100c using the conductive bump, and electrically connecting the chip 200 and the substrate 100 through the conductive bump.

[0093] The conductive bumps are used to achieve bonding between the chip 200 and the substrate 100 , and to achieve electrical connection between the interconnection structure layer and the chip 200 .

[0094] In this embodiment, the material of the conductive bump includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the conductive bump is tin.

[0095] For example, the conductive bump can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, with the same conductive bump spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0096] refer to Figure 5 , forming a first interconnect structure 310 electrically connected to the ground pad 110.

[0097] The first interconnect structure 310 is used to be electrically connected to the ground pad 110 , so that after being subsequently electrically connected to the conductive heat dissipation cover, the conductive heat dissipation cover and the ground pad 110 are electrically connected.

[0098] In this embodiment, the step of forming a first interconnect structure 310 electrically connected to the ground pad 110 includes: forming an interconnect line 300 electrically connecting the ground pads 110 of adjacent unit areas 100p between opposite side walls of the chips 200 of adjacent unit areas 100p, wherein, in each interconnect line 300, a portion of the interconnect line 300 connected to the ground pads 110 at both ends serves as the first interconnect structure 310 of the unit area 100p corresponding to the ground pad 110.

[0099] An interconnection line 300 is formed to electrically connect the ground pads 110 of adjacent unit areas 100p. The first interconnection structure 310 of adjacent unit areas 100p can be electrically isolated by subsequently cutting the interconnection line 300 to obtain the first interconnection structure 310 of each unit area 100p. By using the interconnection line 300 to electrically lead out the ground pad 110, the first interconnection structure 310 of each unit area 100p can be obtained at the same time, which is beneficial to improving process efficiency. Moreover, the electrical property of the ground pad 110 is led out through the interconnection line 300, so that the subsequent second interconnection structure is easy to be electrically connected to the first interconnection structure 310, thereby easily realizing the electrical connection between the second interconnection structure and the ground pad 110.

[0100] It should be noted that, in the present embodiment, interconnection lines 300 are formed at the boundaries of adjacent unit areas 100p, that is, first interconnection structures 310 are formed on both sides of each chip area 100c, and the first interconnection structures 310 on both sides of the subsequent chip area 100c are electrically connected to the conductive heat dissipation cover, so that the conductive heat dissipation cover is grounded simultaneously through the first interconnection structures 310 on both sides of the chip area 100c, so that the number of grounding points of the conductive heat dissipation cover is large, which is beneficial to reducing the grounding impedance of the conductive heat dissipation cover, ensuring the reliability of the packaging structure, and making the electrical connection of the conductive heat dissipation cover more uniform, which is also beneficial to ensuring the electromagnetic interference reduction effect of the conductive heat dissipation cover.

[0101] In this embodiment, a wire bonding process is used to form the interconnection line 300 that electrically connects the ground pads 110 of the adjacent cell regions 100 p .

[0102] The wire bonding process uses metal wires (gold wires, aluminum wires, etc.) and utilizes heat pressing or ultrasonic energy to achieve connection between the chip 200 and the circuit or lead frame. The wire bonding process has a fast processing speed, is easy to operate, has high processing accuracy, and can obtain interconnection wires 300 with good surface finish.

[0103] Specifically, in this embodiment, in the same step of performing the wire bonding process between the chip 200 and the circuit, a wire bonding process is used to form an interconnection line 300 electrically connected to the ground pad 110, without introducing additional process steps. This is beneficial to simplifying the process flow, improving process efficiency, and improving the process integration of the packaging structure.

[0104] In this embodiment, the material of the first interconnect structure 310 is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0105] In this embodiment, in the step of forming the interconnection line 300 electrically connecting the ground pads 110 of the adjacent unit area 100p, the interconnection line 300 is also formed at the boundary of the packaging area 100s, and crosses the boundary and electrically connects the ground pads 110 at the boundary of the packaging area 100s.

[0106] The interconnection line 300 is also formed at the boundary of the packaging area 100s, and crosses the boundary and is electrically connected to the grounding pad 110 at the boundary of the packaging area 100s, so that in the unit area 100p located at the boundary of the packaging area 100s, both sides of the chip area 100c are formed with a first interconnection structure 310 electrically connected to the grounding pad 110, and subsequently in the unit area 100p located at the boundary of the packaging area 100s, the first interconnection structures 310 on both sides of the chip area 100c are electrically connected to the conductive heat dissipation cover. For the unit area 100p located at the boundary of the packaging area 100s, the conductive heat dissipation cover can also be grounded at the same time through the first interconnection structures 310 on both sides of the chip area 100c, so that the number of grounding points of the conductive heat dissipation cover is large, which is beneficial to reducing the grounding impedance of the conductive heat dissipation cover, ensuring the reliability of the packaging structure, and making the electrical connection of the conductive heat dissipation cover more uniform, which is also beneficial to ensuring the electromagnetic interference reduction effect of the conductive heat dissipation cover.

[0107] refer to Figure 6 After forming the first interconnect structure 310 electrically connected to the ground pad 110, and before subsequently setting a conductive heat dissipation cover on the top of the chip 200, the packaging method also includes: forming a plastic packaging layer 400 covering the side wall of the chip 200, and plastic packaging the chips 200 of the multiple unit areas 100p into an integrated structure 600 located in the packaging area 100s.

[0108] The plastic layer 400 is used to protect the structure of the chip 200, and is also used to plastic-encapsulate multiple chips 200 into an integrated structure of the packaging area 100s, so that subsequent process steps required for the chip 200 can be implemented by performing process steps on the integrated structure, which is beneficial to improving process efficiency.

[0109] In this embodiment, the material of the plastic encapsulation layer 400 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the plastic encapsulation layer can also be made of other suitable packaging materials.

[0110] Combined with reference Figure 7 and Figure 8 , a conductive heat dissipation cover 510 is disposed on the top of the chip 200 .

[0111] The conductive heat dissipation cover 510 is used to achieve the functions of heat conduction and heat dissipation.

[0112] In this embodiment, in the step of disposing the conductive heat dissipation cover 510 on the top of the chip 200 , the conductive heat dissipation cover 510 is made of metal material.

[0113] Metal materials have good heat dissipation performance, which is beneficial to improving the thermal conductivity and heat dissipation effect of the conductive heat dissipation cover 510.

[0114] Specifically, refer to Figure 7 The step of disposing a conductive heat dissipation cover 510 on the top of the chip 200 includes: forming a conductive heat dissipation layer 500 covering the top of the integrated structure 600 .

[0115] The conductive heat dissipation layer 500 is used to subsequently form a conductive heat dissipation cover 510 .

[0116] In this embodiment, a conductive heat dissipation layer 500 is first formed to cover the top of the integrated structure 600, and then the conductive heat dissipation layer 500 is directly cut to obtain a conductive heat dissipation cover 510 located on the top of each chip 200. Compared with a solution of forming a conductive heat dissipation cover separately on the top of each chip, this solution can simultaneously obtain the conductive heat dissipation covers 510 on the tops of all chips 200, which is beneficial to improving process efficiency, simplifying the process flow, and saving process costs.

[0117] refer to Figure 8 , the conductive heat dissipation layer 500 at the boundary of the adjacent unit area 100 p is cut to form a conductive heat dissipation cover 510 separated on the top of each chip 200 .

[0118] The conductive heat dissipation layer 500 at the boundary of the adjacent unit areas 100p is cut, and a conductive heat dissipation cover 510 is obtained separately on the top of each chip 200, which greatly improves the process efficiency.

[0119] In this embodiment, before subsequently forming the second interconnect structure electrically connecting the corresponding conductive heat dissipation cover 510 and the first interconnect structure 310, the process further includes: dividing each interconnect line 300 so that the first interconnect structures 310 of adjacent unit areas 100p are spaced apart.

[0120] Each interconnection line 300 is divided so that the first interconnection structures 310 of adjacent unit areas 100p are spaced apart, thereby achieving electrical isolation between the first interconnection structures 310 of adjacent unit areas 100p, so that in each subsequent unit area 100p, the first interconnection structure 310 is electrically connected to the conductive heat dissipation cover 510 corresponding to the unit area 100p.

[0121] In this embodiment, before subsequently forming a second interconnect structure that electrically connects the corresponding conductive heat dissipation cover 510 and the first interconnect structure 310, it also includes: pre-cutting the integrated structure 600 at the boundary of the adjacent unit area 100p, removing a portion of the thickness of the plastic encapsulation layer 400, and forming a notch 520, the notch 520 divides the interconnect line 300 and exposes the cross-section of the first interconnect structure 310.

[0122] At the boundary of the adjacent unit area 100p, the integrated structure 600 is pre-cut to prepare for the subsequent complete cutting of the integrated structure 600 to obtain a discrete chip structure, and a portion of the thickness of the plastic encapsulation layer 400 is removed to form a notch 520. The notch 520 electrically isolates the first interconnect structure 310 of the adjacent unit area 100p. The notch 520 also exposes the cross-section of the first interconnect structure 310, providing a process platform for the subsequent formation of a second interconnect structure electrically connected to the first interconnect structure 310.

[0123] Moreover, the integrated structure 600 is pre-cut to remove a portion of the thickness of the plastic sealing layer 400, and the remaining plastic sealing layer 400 allows the integrated structure 600 to maintain the integrity of the plastic sealing, so that in the subsequent step of forming the second interconnection structure, the integrated structure 600 can be processed at the same time, which improves the process efficiency, simplifies the process flow, and saves the process cost.

[0124] In this embodiment, in the step of pre-cutting the integrated structure 600 , the conductive heat dissipation layer 500 at the boundary between adjacent chip regions 100 c is cut.

[0125] In the same step, the integrated structure 600 is pre-cut and the conductive heat dissipation layer 500 is cut, which is beneficial to improving process efficiency and simplifying the process flow.

[0126] In other embodiments, before forming the second interconnect structure electrically connecting the corresponding conductive heat dissipation cover with the first interconnect structure, it also includes: dividing the interconnect lines by cutting the plastic packaging layer and the substrate at the boundaries of adjacent chip areas in the integrated structure, and forming chip structures corresponding to multiple discrete unit areas, and the side walls of the chip structure expose the cross-section of the first interconnect structure.

[0127] That is, without performing a pre-cutting step, the integrated structure is directly completely cut to obtain discrete chip structures, and accordingly, second interconnect structures electrically connecting the first interconnect structure and the conductive heat dissipation cover are subsequently formed on the side walls of each chip structure.

[0128] refer to Fig. 9 In the unit area 100 p , a second interconnect structure 320 electrically connecting the corresponding conductive heat dissipation cover 510 and the first interconnect structure 310 is formed.

[0129] The second interconnect structure 320 is used to realize the electrical connection between the first interconnect structure 310 and the conductive heat dissipation cover 510 , thereby realizing the grounding of the conductive heat dissipation cover 510 .

[0130] In this embodiment, the first interconnect structure 310 is electrically connected to the ground pad 110, and the second interconnect structure 320 is electrically connected to the first interconnect structure 310 and the conductive heat dissipation cover 510, so that the conductive heat dissipation cover 510 is electrically connected to the ground pad 110, and the conductive heat dissipation cover 510 is grounded accordingly. During the operation of the packaging structure, it is beneficial to avoid as much as possible that the conductive heat dissipation cover 510 is not electrically connected and becomes a floating structure above the chip 200. The grounding of the conductive heat dissipation cover 510 can drain and form a loop, which is beneficial to weaken the antenna effect of the conductive heat dissipation cover 510 when the chip 200 transmits signals or energy, thereby reducing the electromagnetic interference to the circuit or signal of the chip 200 and ensuring the performance of the packaging structure.

[0131] In this embodiment, the material of the second interconnect structure 320 is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0132] In this embodiment, in the step of forming the second interconnect structure 320 electrically connecting the corresponding conductive heat dissipation cover 510 and the first interconnect structure 310, the first interconnect structure 310 is electrically connected to the second interconnect structure 320 by contacting the cross section of the first interconnect structure 310 with the second interconnect structure 320.

[0133] The first interconnect structure 310 is electrically connected to the second interconnect structure 320 by contacting the cross section of the first interconnect structure 310 with the second interconnect structure 320 , so that the electrical connection between the first interconnect structure 310 and the second interconnect structure 320 is easy to achieve.

[0134] In this embodiment, in the step of forming the second interconnect structure 320 electrically connecting the corresponding conductive heat dissipation cover 510 and the first interconnect structure 310 , the second interconnect structure 320 covers the sidewall and the bottom of the recess 520 .

[0135] The notch 520 exposes the cross section of the first interconnect structure 310 , and the second interconnect structure 320 covers the sidewall and bottom of the notch 520 , so that the second interconnect structure 320 is in more complete contact with the first interconnect structure 310 , and accordingly the electrical connection between the second interconnect structure 320 and the first interconnect structure 310 is more complete.

[0136] Moreover, the recess 520 exposes the cross section of the first interconnect structure 310, and the second interconnect structure 320 covers the sidewalls and the bottom of the recess 520. Therefore, the electrical connection between the second interconnect structure 320 and the first interconnect structure 310 can be achieved without positioning the first interconnect structure 310 in the recess 520, making the electrical connection between the second interconnect structure 320 and the first interconnect structure 310 easy to achieve.

[0137] In this embodiment, in the step of covering the sidewalls and the bottom of the recess 520 , the second interconnect structure 320 also covers the conductive heat dissipation cover 510 , so that the first interconnect structure 310 is electrically connected to the conductive heat dissipation cover 510 through the second interconnect structure 320 .

[0138] In this embodiment, a sputtering process is used to form the second interconnect structure 320 electrically connecting the corresponding conductive heat dissipation cover 510 and the first interconnect structure 310 .

[0139] The sputtering process can form a thin film on the surface of the object, and accordingly can form the second interconnect structure 320 covering the sidewall and the bottom of the recess 520 .

[0140] The second interconnect structure 320 is formed by a sputtering process, and the process operation temperature is low, which is beneficial to reducing damage to other structures. The formed second interconnect structure 320 has a pure film quality, a uniform and dense structure, and good firmness, which is beneficial to obtaining a second interconnect structure 320 with good film quality, and the process has good reproducibility, making the formation of the second interconnect structure 320 suitable for wide application.

[0141] Furthermore, the second interconnect structure 320 is formed by a sputtering process, and the integrated structure 600 can be operated, and the second interconnect structure 320 in each unit area 100 c can be obtained at the same time, which is beneficial to improving process efficiency and simplifying the process flow.

[0142] refer to Fig.10 After forming the second interconnect structure 320 electrically connecting the corresponding conductive heat dissipation cover 510 and the first interconnect structure 310, the packaging method further includes: cutting the remaining plastic encapsulation layer 400 and the substrate 100 at the boundary of adjacent unit areas 100p in the integrated structure 600 along the notch 520 to form a chip structure 610 corresponding to a plurality of discrete unit areas 100p.

[0143] The remaining plastic encapsulation layer 400 and substrate 100 at the boundary of adjacent unit areas 100 p in the integrated structure 600 are cut along the notch 520 to form a chip structure 610 corresponding to a plurality of discrete unit areas 100 p , thereby obtaining a packaging structure corresponding to the unit area 100 p .

[0144] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: A substrate, comprising a bonding surface, wherein the bonding surface comprises a chip area, and a grounding pad is formed on the substrate at a side of the chip area; A chip bonded to the chip region of the bonding surface; A conductive heat dissipation cover, located on top of the chip; A first interconnect structure, located at a side of the chip and electrically connected to the ground pad; The second interconnect structure is located at the side of the chip and is electrically connected to the first interconnect structure and the conductive heat dissipation cover.

2. The packaging structure according to claim 1, characterized in that: The first interconnect structure is an interconnect line electrically connected to the ground pad.

3. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a plastic sealing layer covering the side wall of the chip, wherein the plastic sealing layer and the chip form a chip structure; The first interconnection structure is located in the plastic encapsulation layer, and the plastic encapsulation layer exposes a cross section of the first interconnection structure; The second interconnection structure is in contact with a cross section of the first interconnection structure, thereby achieving electrical connection between the second interconnection structure and the first interconnection structure.

4. The packaging structure according to claim 3, characterized in that: The second interconnect structure covers a portion of the side wall of the chip structure from the location of the first interconnect structure to the conductive heat dissipation cover.

5. The packaging structure according to claim 1, characterized in that: The conductive heat dissipation cover is made of metal material.

6. A packaging method, characterized in that: include: Providing a substrate, including a bonding surface, the bonding surface including a plurality of unit areas, the unit areas including a chip area, and a grounding pad is formed in the unit area on the side of the chip area; Provide multiple chips; Bonding the chip to the chip area of ​​the bonding surface; forming a first interconnect structure electrically connected to the ground pad; Disposing a conductive heat dissipation cover on top of the chip; In the unit area, a second interconnect structure is formed to electrically connect the corresponding conductive heat dissipation cover and the first interconnect structure.

7. The packaging method according to claim 6, characterized in that: The step of forming a first interconnection structure electrically connected to the ground pad comprises: forming an interconnection line electrically connecting the ground pads of adjacent unit areas between the opposite side walls of the chips of the adjacent unit areas, wherein a portion of the length of each interconnection line connected to the ground pads at both ends serves as the first interconnection structure of the unit area corresponding to the ground pad; Before forming the second interconnection structure electrically connecting the corresponding conductive heat dissipation cover and the first interconnection structure, the method further includes: dividing each of the interconnection lines so that the first interconnection structures of adjacent unit areas are spaced apart.

8. The packaging method according to claim 7, characterized in that: A wire bonding process is adopted to form interconnection lines electrically connecting the ground pads of the adjacent unit areas.

9. The packaging method according to claim 7, characterized in that: In the step of providing a substrate, a plurality of the unit areas constitute a packaging area; In the step of forming interconnection lines electrically connecting ground pads of adjacent unit regions, the interconnection lines are also formed at the boundaries of the packaging region, and cross the boundaries and electrically connect the ground pads at the boundaries of the packaging region.

10. The packaging method according to claim 9, characterized in that: After forming a first interconnect structure electrically connected to the ground pad and before providing a conductive heat dissipation cover on the top of the chip, the packaging method further comprises: forming a plastic packaging layer covering the side wall of the chip, and plastic packaging the chips of the plurality of unit areas into an integrated structure located in the packaging area; Before forming a second interconnection structure electrically connecting the corresponding conductive heat dissipation cover and the first interconnection structure, the method further includes: pre-cutting the integrated structure at the boundary of the adjacent unit area, removing a portion of the thickness of the plastic sealing layer, and forming a notch, wherein the notch divides the interconnection line and exposes a cross section of the first interconnection structure; In the step of forming a second interconnect structure electrically connecting the conductive heat dissipation cover and the first interconnect structure, the first interconnect structure is electrically connected to the second interconnect structure by contacting the second interconnect structure through a cross section of the first interconnect structure.

11. The packaging method according to claim 10, characterized in that: In the step of forming a second interconnect structure electrically connecting the corresponding conductive heat dissipation cover and the first interconnect structure, the second interconnect structure covers the sidewalls and the bottom of the recess.

12. The packaging method according to claim 10, characterized in that: After forming a second interconnect structure electrically connecting the conductive heat dissipation cover and the first interconnect structure, the packaging method further includes: cutting the remaining plastic encapsulation layer and substrate at the boundary of adjacent unit areas in the integrated structure along the notch to form a chip structure corresponding to a plurality of discrete unit areas.

13. The packaging method according to claim 10, characterized in that: The step of providing a conductive heat dissipation cover on the top of the chip includes: forming a conductive heat dissipation layer covering the top of the integrated structure; The conductive heat dissipation layer at the boundary of the adjacent unit areas is cut to form a conductive heat dissipation cover separated on the top of each chip.

14. The packaging method according to claim 13, characterized in that: In the step of pre-cutting the integrated structure, the conductive heat dissipation layer at the boundary between the adjacent unit areas is cut.

15. The packaging method according to claim 9, characterized in that: After forming a first interconnect structure electrically connected to the ground pad and before providing a conductive heat dissipation cover on the top of the chip, the packaging method further comprises: forming a plastic packaging layer covering the side wall of the chip, and plastic packaging the chips of the plurality of unit areas into an integrated structure located in the packaging area; Before forming a second interconnection structure electrically connecting the conductive heat dissipation cover and the first interconnection structure, the method further includes: dividing the interconnection line by cutting the plastic encapsulation layer and the substrate at the boundary of the adjacent chip areas in the integrated structure, and forming a plurality of discrete chip structures corresponding to the unit areas, wherein the side wall of the chip structure exposes the cross section of the first interconnection structure; In the step of forming a second interconnect structure electrically connecting the conductive heat dissipation cover and the first interconnect structure, the first interconnect structure is electrically connected to the second interconnect structure by contacting the second interconnect structure through a cross section of the first interconnect structure.

16. The packaging method according to claim 10 or 15, characterized in that: A sputtering process is used to form a second interconnect structure electrically connecting the corresponding conductive heat dissipation cover and the first interconnect structure.

17. The packaging method according to claim 6, characterized in that: In the step of providing a conductive heat dissipation cover on the top of the chip, the conductive heat dissipation cover is made of metal material.

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