Simple anti-shake timing circuit
By designing a simple anti-shake delay circuit, using edge signal detection and delay time metering technology, the problem of unstable comparator output in the existing technology is solved, and a thorough anti-shake function is achieved.
Patent Information
- Application Number
- CN202411729926.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-18
AI Technical Summary
The prior art cannot fully realize the anti-shake function of the comparator, especially when the input signal is unstable, the comparator output will experience jitter and oscillation.
A simple anti-shake delay circuit is designed, including an edge signal detection module, an RS trigger module, a delay timer module and an output module. By detecting the falling edge signal of the comparator output signal, triggering the delay enable signal, controlling the delay timing, and outputting the comparator output signal after the delay timing is full, realizing the anti-shake function.
This circuit can effectively prevent jitter and oscillation of the comparator output, and can realize anti-shake even if the input signal amplitude changes significantly, thereby completely realizing the anti-shake function of the comparator.
Smart Images
Figure CN119652292A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of integrated circuits, in particular to a simple anti-shake delay circuit. Background Art
[0002] In the switching power supply circuit, some protection circuits use comparators to detect trigger-related protection signals. However, when the input signal is at the critical protection threshold and the input signal is unstable, the comparator output will jitter, which may cause the system to work abnormally. In order to avoid this unstable output, the solution in the prior art is to introduce the Schmitt trigger principle into the comparator itself, especially at the input end, to delay the comparison value of the input end signal, so as to avoid multiple switching jitters or even oscillations of the comparator output. Figure 1 The common hysteresis comparator shown in FIG. 4 realizes the comparison function by using different reference voltage values. Figure 2 The figure shows the comparison result waveform of the common hysteresis comparator. Although the common hysteresis comparator can alleviate the output jitter oscillation caused by the instability of the comparator input signal to a certain extent, it cannot avoid the situation where the input signal amplitude does change significantly. Therefore, the traditional solution cannot completely realize the anti-shake function of the comparator. Summary of the invention
[0003] The technical problem to be solved by the present invention is to provide a simple anti-shake delay circuit, by which the anti-shake function of the comparator can be completely realized.
[0004] In order to solve the above problems, the following technical solutions are provided:
[0005] The simple anti-jitter timing circuit of the present invention is characterized by:
[0006] An edge signal detection module, used to detect the falling edge signals of the output signals Y and Y_N of the hysteresis comparator;
[0007] An RS trigger module, adapted to be connected with the edge signal detection module, for receiving the falling edge signal and generating a delay enable signal according to the falling edge signal;
[0008] A delay timing module, adapted to be connected with the RS trigger module, is used to receive the delay enable signal, and perform delay timing according to the delay enable signal, and generate an output enable after the delay timing is full;
[0009] The output module is adaptively connected with the delay timing module and the RS trigger module, and is used to receive the output enable. The output module is used to be connected to the output signal Y of the hysteresis comparator. After receiving the output enable, the output module outputs the output signal Y of the hysteresis comparator, and at the same time, generates a reset signal to reset the RS trigger module and clear the delay timing time of the delay timing module.
[0010] Among them, the edge signal detection module includes two detection units and an OR gate, the output ends of the two detection units are connected to the two input ends of the OR gate in a one-to-one correspondence, and the output end of the OR gate is adaptively connected to the RS trigger module to send a falling edge signal to the RS trigger module; the input end of one of the detection units is used to be connected to the output signal Y of the hysteresis comparator, and the input end of the other detection unit is used to be connected to the output signal Y_N of the hysteresis comparator.
[0011] The detection unit includes a NOR gate and three inverters, the input end of the first inverter is the input end of the detection unit, the output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter through an RC delay unit, the output end of the third inverter is connected to one input end of the NOR gate, the other input end of the NOR gate is used to be connected to the output signal Y of the hysteresis comparator, and the output end of the NOR gate is the output end of the detection unit.
[0012] The RS trigger module contains an RS trigger and an inverter INV7. The S end of the RS trigger is adapted to be connected to the delay timing module for receiving the falling edge signal. The R end of the RS trigger is adapted to be connected to the output module for receiving the reset signal. The output end of the RS trigger is connected to the input end of the inverter INV7, and the output end of the inverter INV7 is adapted to be connected to the delay timing module for generating the delay enable signal.
[0013] The delay timing module includes a PMOS tube Q1 and an NMOS tube Q2; the source of the PMOS tube Q1 is connected to the power supply VDD through a current mirror I, the drain of the PMOS tube Q1 is respectively connected to the drain of the NMOS tube Q2 and one end of the capacitor C3, and the source of the NMOS tube Q2 and the other end of the capacitor C3 are grounded; the RS trigger modules are adaptively connected to the gates of the PMOS tube Q1 and the NMOS tube Q2, and are used to send a delay enable signal to the gates of the PMOS tube Q1 and the NMOS tube Q2; the drain of the PMOS tube Q1 is adaptively connected to the output module, and is used to send the output enable to the output module.
[0014] The output module includes a D flip-flop, the D end of the D flip-flop is connected to the output signal Y of the hysteresis comparator, and the CP end of the D flip-flop is adaptively connected to the delay timing module for receiving the output enable.
[0015] The above solution has the following advantages:
[0016] Since the simple anti-shake delay circuit of the present invention adds an edge signal detection module, an RS trigger module, a delay timing module and an output module at the output end of the comparator, the edge signal detection module is used to detect the falling edge signal of the comparator output signals Y and Y_N, and the falling edge signal is used to trigger the RS trigger module to generate a delay enable signal to control the delay timing module to perform delay timing, and after the delay timing is full, the output module is controlled to output the comparator output signal Y, even if the input signal amplitude does change significantly, anti-shake can be achieved, thereby completely realizing the anti-shake function of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a structural diagram of a common hysteresis comparator;
[0018] Figure 2 This is the comparison result waveform of a common hysteresis comparator;
[0019] Figure 3 The schematic diagram is a structural diagram of a simple anti-shake delay circuit of the present invention.
[0020] Figure 4 The figure is a signal waveform diagram of the simple anti-shake delay circuit of the present invention. DETAILED DESCRIPTION
[0021] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.
[0022] like Figure 3 The simple anti-shake timing circuit of the present invention shown in the figure includes an edge signal detection module 101, an RS trigger module 102, a delay timing module 103 and an output module 104. The edge signal detection module 101 is connected to the output signals Y and Y_N of the hysteresis comparator to detect the falling edge signals of the output signals Y and Y_N of the hysteresis comparator. The RS trigger module 102 is connected to the edge signal detection module 101, receives the falling edge signal, and generates a delay enable signal according to the falling edge signal. The delay timing module 103 is connected to the RS trigger module 102, receives the delay enable signal, and performs delay timing according to the delay enable signal. After the delay timing is full, an output enable is generated. The output module 104 is connected to the delay timing module 103 and the RS trigger module 102, receives the output enable, and the output module 104 is connected to the output signal Y of the hysteresis comparator. After receiving the output enable, the output module 104 outputs the output signal Y of the hysteresis comparator, and at the same time, generates a reset signal to reset the RS trigger module 102, and clears the delay timing time of the delay timing module 103.
[0023] like Figure 3As shown, the edge signal detection module 101 includes two detection units and an OR gate, the output ends of the two detection units are connected to the two input ends of the OR gate in a one-to-one correspondence, and the output end of the OR gate is adaptively connected to the RS trigger module 102, and is used to send a falling edge signal to the RS trigger module 102. The input end of one of the detection units is used to be connected to the output signal Y of the hysteresis comparator, and the input end of the other detection unit is used to be connected to the output signal Y_N of the hysteresis comparator.
[0024] like Figure 3 As shown, the detection unit includes a NOR gate and three inverters, the input end of the first inverter is the input end of the detection unit, the output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter through the RC delay unit, the output end of the third inverter is connected to one input end of the NOR gate, the other input end of the NOR gate is used to be connected to the output signal Y of the hysteresis comparator, and the output end of the NOR gate is the output end of the detection unit.
[0025] like Figure 3 As shown, in this embodiment, the detection unit connected to the output signal Y of the hysteresis comparator includes an inverter INV1, an inverter INV2, an inverter INV3 and a NOR gate NOR1, the input end of the inverter INV1 is connected to the output signal Y of the hysteresis comparator, the output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to one end of the capacitor C1 and the input end of the inverter INV3, the other end of the capacitor C1 is grounded, and the resistor R1 and the capacitor C1 constitute the RC delay unit of the detection unit. An input end of the NOR gate NOR1 of the inverter INV3 is connected, the other input end of the NOR gate NOR1 is connected to the output signal Y of the hysteresis comparator, and the output end of the NOR gate NOR1 is connected to an input end of the OR gate OR.
[0026] like Figure 3As shown, in this embodiment, the detection unit connected to the output signal Y_N of the hysteresis comparator includes an inverter INV4, an inverter INV5, an inverter INV6 and an NOR gate NOR2. The input end of the inverter INV4 is connected to the output signal Y_N of the hysteresis comparator, the output end of the inverter INV4 is connected to the input end of the inverter INV5, the output end of the inverter INV5 is connected to one end of the resistor R2, the other end of the resistor R2 is respectively connected to one end of the capacitor C3 and the input end of the inverter INV6, the other end of the capacitor C2 is grounded, and the resistor R2 and the capacitor C2 constitute the RC delay unit of the detection unit. The inverter INV6 is connected to one input end of the NOR gate NOR2, the other input end of the NOR gate NOR2 is connected to the output signal Y_N of the hysteresis comparator, and the output end of the NOR gate NOR2 is connected to the other input end of the OR gate OR. The output end of the OR gate OR sends a falling edge signal
[0027] like Figure 3 As shown, the RS trigger module 102 includes an RS trigger and an inverter INV7, the RS trigger S end is connected to the delay timing module 103, that is, the RS trigger S end is connected to the output end of the OR gate OR. The output end of the RS trigger is connected to the input end of the inverter INV7, and the output end of the inverter INV7 generates a delay enable signal.
[0028] The delay timing module 103 includes a PMOS tube Q1 and an NMOS tube Q2. The source of the PMOS tube Q1 is connected to the power supply VDD through a current mirror I, the drain of the PMOS tube Q1 is connected to the drain of the NMOS tube Q2 and one end of the capacitor C3, and the source of the NMOS tube Q2 and the other end of the capacitor C3 are grounded. The RS trigger module 102 is adapted to be connected to the gates of the PMOS tube Q1 and the NMOS tube Q2, that is, the output end of the inverter INV7 is connected to the gates of the PMOS tube Q1 and the NMOS tube Q2. The drain of the PMOS tube Q1 generates an output enable.
[0029] The output module 104 includes a D flip-flop, the D terminal of the D flip-flop is connected to the output signal Y of the hysteresis comparator, the CP terminal of the D flip-flop is connected to the drain of the PMOS tube Q1, and the CP terminal of the D flip-flop is connected to the R terminal of the RS flip-flop.
[0030] During operation, when the input signal Sample at the positive phase end of the hysteresis comparator changes from low to high and the voltage is greater than Vref1, the output signal Y becomes high and Y_N becomes low. The falling edge signal of Y_N is detected by the detection unit connected to the output signal Y_N of the hysteresis comparator, and a falling edge signal is generated and sent to the S end of the RS trigger. The inverter INV outputs a low level to form a delay enable signal. The PMOS tube Q1 of the delay timing module 103 is turned on, and the NMOS tube Q2 is turned off. Under the action of VDD and the current mirror I, the capacitor C3 starts to charge and the delay timing is performed. After the delay timing is full, the voltage at the upper end of the capacitor C3 is high, and the output enable is generated to enter the CP end of the D trigger, triggering the D trigger to output the high level of the output signal Y of the hysteresis comparator. At the same time, the output enable returns the R signal to the R end of the RS trigger, resets the RS trigger, and the inverter INV outputs a high level, the PMOS tube Q1 is closed, and the NMOS tube Q1 is turned on, and the capacitor C3 is discharged to achieve the delay timing reset.
[0031] When the input signal Sample at the positive end of the hysteresis comparator changes from high to low, and the voltage is less than Vref2, the output signal Y becomes low, and Y_N becomes high. The falling edge signal of Y is detected by the detection unit connected to the output signal Y of the hysteresis comparator. After detection, a falling edge signal is generated and sent to the S end of the RS trigger. The inverter INV outputs a low level to form a delay enable signal. The PMOS tube Q1 of the delay timing module 103 is turned on, and the NMOS tube Q2 is turned off. Under the action of VDD and the current mirror I, the capacitor C3 starts to charge and delay timing is performed. After the delay timing is full, the voltage at the upper end of the capacitor C3 is a high level, and an output enable is generated to enter the CP end of the D trigger, triggering the D trigger to output the low level of the output signal Y of the hysteresis comparator. At the same time, the output enable returns the R signal to the R end of the RS trigger, resets the RS trigger, and the inverter INV outputs a high level, the PMOS tube Q1 is closed, and the NMOS tube Q1 is turned on, and the capacitor C3 is discharged to achieve the delay timing reset.
[0032] The signal waveform diagram of this embodiment is as follows Figure 4 As shown, the edge signal detection module is used to detect the falling edge signals of the comparator output signals Y and Y_N, and the falling edge signal is used to trigger the RS trigger module to generate a delay enable signal to control the delay timing module to perform delay timing. After the delay timing is over, the output module is controlled to output the comparator output signal Y. Even if the input signal amplitude does change significantly, anti-shake can be achieved, thereby completely realizing the anti-shake function of the comparator.
Claims
1. A simple anti-shake timing circuit, characterized in that: include: An edge signal detection module, used to detect the falling edge signals of the output signals Y and Y_N of the hysteresis comparator; An RS trigger module, adapted to be connected with the edge signal detection module, for receiving the falling edge signal and generating a delay enable signal according to the falling edge signal; A delay timing module, adapted to be connected with the RS trigger module, is used to receive the delay enable signal, and perform delay timing according to the delay enable signal, and generate an output enable after the delay timing is full; The output module is adaptively connected with the delay timing module and the RS trigger module, and is used to receive the output enable. The output module is used to be connected to the output signal Y of the hysteresis comparator. After receiving the output enable, the output module outputs the output signal Y of the hysteresis comparator, and at the same time, generates a reset signal to reset the RS trigger module and clear the delay timing time of the delay timing module.
2. The simple anti-jitter timing circuit as claimed in claim 1, characterized in that: The edge signal detection module includes two detection units and an OR gate, the output ends of the two detection units are connected to the two input ends of the OR gate in a one-to-one correspondence, and the output end of the OR gate is adaptively connected to the RS trigger module to send a falling edge signal to the RS trigger module; the input end of one of the detection units is used to be connected to the output signal Y of the hysteresis comparator, and the input end of the other detection unit is used to be connected to the output signal Y_N of the hysteresis comparator.
3. The simple anti-jitter timing circuit as claimed in claim 2, characterized in that: The detection unit includes a NOR gate and three inverters, the input end of the first inverter is the input end of the detection unit, the output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter through an RC delay unit, the output end of the third inverter is connected to one input end of the NOR gate, the other input end of the NOR gate is used to be connected to the output signal Y of the hysteresis comparator, and the output end of the NOR gate is the output end of the detection unit.
4. The simple anti-shake timing circuit as claimed in claim 1, characterized in that: The RS trigger module contains an RS trigger and an inverter INV7. The S end of the RS trigger is adapted to be connected to the delay timing module for receiving the falling edge signal. The R end of the RS trigger is adapted to be connected to the output module for receiving the reset signal. The output end of the RS trigger is connected to the input end of the inverter INV7, and the output end of the inverter INV7 is adapted to be connected to the delay timing module for generating the delay enable signal.
5. The simple anti-jitter timing circuit as claimed in claim 1, characterized in that: The delay timing module includes a PMOS tube Q1 and an NMOS tube Q2; the source of the PMOS tube Q1 is connected to the power supply VDD through a current mirror I, the drain of the PMOS tube Q1 is respectively connected to the drain of the NMOS tube Q2 and one end of the capacitor C3, and the source of the NMOS tube Q2 and the other end of the capacitor C3 are grounded; the RS trigger modules are adaptively connected to the gates of the PMOS tube Q1 and the NMOS tube Q2, and are used to send a delay enable signal to the gates of the PMOS tube Q1 and the NMOS tube Q2; the drain of the PMOS tube Q1 is adaptively connected to the output module, and is used to send the output enable to the output module.
6. The simple anti-shake timing circuit as claimed in claim 1, characterized in that: The output module includes a D flip-flop, the D end of the D flip-flop is connected to the output signal Y of the hysteresis comparator, and the CP end of the D flip-flop is adaptively connected to the delay timing module for receiving the output enable.