Semiconductor element driving device

Abstract

The purpose of the present invention is to provide a technique capable of externally recognizing the type of error state in advance on the basis of a recognition signal. The semiconductor element drive device includes: a plurality of error state detection circuits that generate error signals corresponding to error states; an error state recognition signal generation circuit that generates, for each type of error state, an error state recognition signal having a different waveform and a smaller pulse width than each error signal, on the basis of the plurality of error signals generated by each of the plurality of error state detection circuits; and an error state identification signal output terminal that outputs an error state identification signal.

Description

Technical Field

[0001] The present invention relates to a semiconductor element driving device. Background Art

[0002] Various technologies have been proposed for semiconductor element driving devices that drive semiconductor elements. For example, Patent Document 1 proposes a technology in which the semiconductor element driving device generates an identification signal with a different pulse width for each error state, so that an external control device can identify the type of the error state based on the identification signal.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2017-93065

[0004] However, in the prior art, the pulse width of the identification signal is larger than the pulse width of the error signal of each error state, so the time from the start to the end of the output of the identification signal is long. Therefore, there is a problem that the external control device cannot recognize the type of the error state early based on the identification signal. Summary of the invention

[0005] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a technology capable of early identifying the type of an error state based on an external identification signal.

[0006] The semiconductor element driving device of the present invention drives a semiconductor element, and the semiconductor element driving device comprises: a plurality of error state detection circuits, which respectively detect the error state of the semiconductor element or the semiconductor element driving device and generate an error signal corresponding to the detected error state; an error state identification signal generating circuit, which generates an error state identification signal with a different waveform and a smaller pulse width than each error signal for each type of the error state based on the plurality of error signals respectively generated by the plurality of error state detection circuits; an error state identification signal output terminal, which outputs the error state identification signal; a protection action signal generating circuit, which generates a protection action signal for protecting the semiconductor element based on the error state identification signal; a protection action signal output terminal, which outputs the protection action signal; and a protection circuit, which protects the semiconductor element based on the protection action signal.

[0007] Effects of the Invention

[0008] According to the present invention, an error state identification signal having a smaller pulse width than each error signal is generated.

[0009] Therefore, the type of the error state can be recognized early from the outside based on the recognition signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a diagram showing the structure of the semiconductor element driving device according to the first embodiment.

[0011] Figure 2 : is a circuit diagram showing the structure of the error state identification signal generating circuit involved in Embodiment 1.

[0012] Figure 3 This is a timing chart showing the operation of the error state identification signal generating circuit according to the first embodiment.

[0013] Figure 4 This is a circuit diagram showing the configuration of a protection action signal generating circuit according to the first embodiment.

[0014] Figure 5 This is a timing chart showing the operation of the protection operation signal generating circuit according to the first embodiment.

[0015] Figure 6 This is a diagram showing the structure of a semiconductor element driving device according to a second embodiment.

[0016] Figure 7 This is a diagram showing the structure of a semiconductor element driving device according to a third embodiment.

[0017] Figure 8 This is a diagram showing the structure of a semiconductor element driving device according to a fourth embodiment. DETAILED DESCRIPTION

[0018] Below, while referring to the attached Figure 1 The embodiments are described below. The features described in the following embodiments are examples, and not all features are required. In addition, in the following description, the same or similar reference numerals are used for the same structural elements in multiple embodiments, and the different structural elements are mainly described.

[0019] <Implementation method 1>

[0020] Figure 1 1 is a diagram showing the structure of a semiconductor element driving device 81 according to the first embodiment. The semiconductor element driving device 81 drives the semiconductor element 1. A temperature detection diode 2 embedded in the chip and a current detection transistor 3 for detecting a current correlated with a current between the collector and the emitter of the semiconductor element 1 are provided on a chip (not shown).

[0021] In addition, Figure 1In the embodiment, the semiconductor element 1 and the current detection transistor 3 are IGBTs (Insulated Gate Bipolar Transistors), but they can also be MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or RC-IGBTs (Reverse Conducting-IGBTs). In addition, the semiconductor element 1 and the current detection transistor 3 can be made of ordinary silicon (Si), or they can be made of wide-bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and diamond. When the semiconductor element 1 and the current detection transistor 3 are made of wide-bandgap semiconductors, stable operation at high temperatures and high voltages and high switching speeds can be achieved.

[0022] The semiconductor element driving device 81 has an input terminal IN, an output terminal OUT, error terminals ERR1, ERR2, ERR3, ERR4, a protection action signal output terminal FO, and an error state identification signal output terminal FOI. The input terminal IN is a terminal for inputting a pulse signal for driving from an external control device (not shown), and the output terminal OUT is a terminal for outputting a driving signal to the gate of the semiconductor element 1. The error terminals ERR1, ERR2, ERR3, and ERR4 are terminals for detecting an error state of the semiconductor element 1 or the semiconductor element driving device 81. The protection action signal output terminal FO is a terminal for outputting a protection action signal described later, and the error state identification signal output terminal FOI is a terminal for outputting an error state identification signal described later.

[0023] Figure 1 The semiconductor element driving device 81 includes an error state recognition signal generating circuit 9, a protection action signal generating circuit 10, a protection circuit 11, an amplifier 12, and a plurality of error state detection circuits.

[0024] The plurality of error state detection circuits involved in the present embodiment 1 include a power supply voltage abnormality detection circuit 4, an unsaturated state detection circuit 5, a gate abnormality detection circuit 6, a temperature abnormality detection circuit 7, and a current abnormality detection circuit 8. The plurality of error state detection circuits each detect an error state of the semiconductor element 1 or the semiconductor element driving device 81, and generate an error signal corresponding to the detected error state.

[0025] When the power supply voltage abnormality detection circuit 4 detects an abnormal state of the power supply voltage of the semiconductor element driving device 81 as an error state, it generates an error signal corresponding to the error state. For example, when the power supply voltage abnormality detection circuit 4 detects an abnormal state in which the power supply voltage VCC of the semiconductor element driving device 81 is less than or equal to a predetermined voltage, it generates and outputs the error signal err0.

[0026] The unsaturated state detection circuit 5 generates an error signal corresponding to the error state when detecting the unsaturated state of the semiconductor element 1 when the semiconductor element 1 is in the on state as an error state. For example, when the unsaturated state detection circuit 5 detects an abnormal state in which the collector-emitter voltage of the semiconductor element 1 does not drop to a predetermined saturation voltage when the semiconductor element 1 is in the fully on state, the error signal err1 is generated and output.

[0027] The gate abnormality detection circuit 6 generates an error signal corresponding to the error state when detecting the abnormal state of the gate of the semiconductor element 1 as an error state. For example, when the gate abnormality detection circuit 6 detects an abnormal state in which the gate voltage of the semiconductor element 1 does not rise to a voltage greater than or equal to a predetermined voltage within a predetermined time when the semiconductor element 1 is turned on, the error signal err2 is generated and output. In addition, for example, when the gate abnormality detection circuit 6 detects an abnormal state in which the gate voltage of the semiconductor element 1 does not drop to a voltage less than or equal to a predetermined voltage within a predetermined time when the semiconductor element 1 is turned off, the error signal err2 is generated and output.

[0028] When the temperature abnormality detection circuit 7 detects an abnormal state of the temperature of the semiconductor element 1 as an error state, it generates an error signal corresponding to the error state. For example, when the temperature abnormality detection circuit 7 detects the chip temperature based on the voltage between the terminals of the temperature detection diode 2 and detects an abnormal state in which the detected chip temperature is greater than or equal to a predetermined temperature, it generates and outputs an error signal err3.

[0029] When the abnormal state of the current of the semiconductor element 1 is detected as an error state, the current abnormality detection circuit 8 generates an error signal corresponding to the error state. For example, when the abnormal state that the current flowing between the collector and the emitter of the current detection transistor 3 is greater than or equal to a predetermined current is detected, the current abnormality detection circuit 8 determines that the abnormal state of the current of the semiconductor element 1 is detected, and generates and outputs the error signal err4.

[0030] The error state identification signal generating circuit 9 generates an error state identification signal having a different waveform for each type of error state based on a plurality of error signals err0, err1, err2, err3, and err4 respectively generated by a plurality of error state detection circuits, and the details will be described later. Hereinafter, a case where the error state identification signal generating circuit 9 generates an error state identification signal having a different duty ratio (also referred to as duty rate) for each type of error state will be described. In addition, as described later, the error state identification signal has a smaller pulse width than each error signal err0, err1, err2, err3, and err4.

[0031] The error state identification signal generating circuit 9 outputs the error state identification signal to the error state identification signal output terminal FOI and the protection action signal generating circuit 10, and the error state identification signal is output from the error state identification signal output terminal FOI to the outside of the semiconductor element driving device 81. Thus, the external control device can identify the type of the error state based on the error state identification signal.

[0032] The protection action signal generating circuit 10 generates a protection action signal for protecting the semiconductor element 1 based on the error state identification signal. For example, the protection action signal generating circuit 10 generates a protection action signal having a pulse width greater than or equal to the output period of the error state identification signal by filtering the error state identification signal.

[0033] The protection operation signal generating circuit 10 outputs the protection operation signal to the protection operation signal output terminal FO and the protection circuit 11 , and the protection operation signal is output from the protection operation signal output terminal FO to the outside of the semiconductor element driving device 81 .

[0034] The protection circuit 11 protects the semiconductor element 1 based on the protection action signal. For example, when the protection action signal generating circuit 10 does not output the protection action signal, the protection circuit 11 drives the semiconductor element 1 by outputting the driving pulse signal input from the input terminal IN to the semiconductor element 1 via the amplifier 12. On the other hand, when the protection action signal generating circuit 10 outputs the protection action signal, the protection circuit 11 stops outputting the driving pulse signal to the semiconductor element 1 via the amplifier 12, and performs an error protection action to stop driving the semiconductor element 1. Thus, the semiconductor element 1 is protected. In addition, Figure 1 In the example of , the protection circuit 11 includes an AND circuit that outputs a signal generated by a logical AND between the inverted protection operation signal and the driving pulse signal, but the present invention is not limited thereto.

[0035] The amplifier 12 amplifies the output of the protection circuit 11 , and outputs the amplified output from the output terminal OUT to the gate of the semiconductor element 1 .

[0036] Figure 2 1 is a circuit diagram showing the structure of the error state identification signal generating circuit 9 involved in the present embodiment 1. The error state identification signal generating circuit 9 includes a priority circuit 13, an OR circuit 18, a clock signal generating circuit 19, a D flip-flop circuit 20, a quinary counter circuit 21, a pulse signal generating circuit 22, AND circuits 28, 29, 30, 31, and an OR circuit 32.

[0037] The priority circuit 13 includes AND circuits 14, 15, 16, and 17, and generates prioritized error signals err0a, err1a, err2a, err3a, and err4a to which priorities are given in the order of error signals err0, err1, err2, err3, and err4. For example, when the error signal err0 is on (High; high level), the prioritized error signal err0a is on, and the prioritized error signals err1a, err2a, err3a, and err4a are all off (Low; low level) regardless of whether the error signals err1, err2, err3, and err4, which have lower priorities than the error signal err0, are on or off. For example, when the error signal err0 is off and the error signal err1 is on, the error signal err0a becomes off after priority, and the error signal err1a becomes on after priority, and regardless of whether the error signals err2, err3, and err4, which have a lower priority than the error signal err1, are on or off, the error signals err2a, err3a, and err4a become off after priority.

[0038] The error signals err0a, err1a, err2a, and err3a after being prioritized are input to AND circuits 28 , 29 , 30 , and 31 , and the error signal err4a after being prioritized is input to an OR circuit 32 .

[0039] Independently of the priority circuit 13, the error signals err0, err1, err2, err3, and err4 are input to the OR circuit 18. The output signal of the OR circuit 18 and the clock signal clk generated by the clock signal generating circuit 19 are input to the D terminal and the CLK terminal of the D flip-flop circuit 20, respectively.

[0040] The quinary counter circuit 21 outputs counter circuit output signals Q0 , Q1 , and Q2 based on the output signal of the Q terminal of the D flip-flop circuit 20 and the clock signal clk.

[0041] The pulse signal generating circuit 22 includes an inverter circuit 26, an OR circuit 27, and AND circuits 23, 24, and 25 whose inputs are all inverted. The pulse signal generating circuit 22 generates a pulse signal d20 with a duty cycle of 20%, a pulse signal d40 with a duty cycle of 40%, a pulse signal d60 with a duty cycle of 60%, and a pulse signal d80 with a duty cycle of 80% based on the counter circuit output signals Q0, Q1, and Q2. In addition, the pulse signals d20, d40, d60, and d80 have substantially the same frequency as each other, and have a frequency that is approximately 1 / 5 times the frequency of the clock signal clk.

[0042] Prioritized error signals err0a, err1a, err2a, err3a and pulse signals d20, d40, d60, d80 are respectively input to AND circuits 28, 29, 30, 31. OR circuit 32 outputs an error state identification signal based on output signals of AND circuits 28, 29, 30, 31 and prioritized error signal err4a.

[0043] Figure 3 1 is a timing chart showing the operation of the error state recognition signal generating circuit 9 according to the first embodiment.

[0044] like Figure 3 As shown, the error state identification signal generating circuit 9 outputs a pulse signal whose duty ratio corresponds to the error signal as an error state identification signal. In addition, the duty ratios of 20%, 40%, 60%, 80%, and 100% correspond to the error signals err0, err1, err2, err3, and err4, respectively. In this way, the error state identification signal generating circuit 9 generates an error state identification signal with a different duty ratio for each type of error state based on the multiple error signals err1, err2, err3, and err4 generated by the multiple error state detection circuits.

[0045] In addition, if Figure 3 As shown, the error state identification signal has a smaller pulse width than the error signals err0, err1, err2, err3, and err4. Therefore, the time from the start to the end of the output of the error state identification signal is short, so the external control device can identify the type of the error state early based on the error state identification signal output from the error state identification signal output terminal FOI.

[0046] In addition, when multiple error signals are output simultaneously, a pulse signal of a duty ratio corresponding to the error signal with the highest priority among the multiple error signals output is output as an error state identification signal. For example, during the period T1 to T2 when the error signals err0 and err1 are output, a pulse signal of a duty ratio of 20% corresponding to the error signal err0 with a higher priority than the error signal err1 is output as an error state identification signal. For example, during the period T3 to T4 when the error signals err2, err3, and err4 are output, a pulse signal of a duty ratio of 60% corresponding to the error signal err2 with a higher priority than the error signals err3 and err4 is output as an error state identification signal.

[0047] Figure 4 : is a circuit diagram showing the configuration of the protection operation signal generating circuit 10 according to the present embodiment 1. The protection operation signal generating circuit 10 includes a transistor 33 , a current source 34 , a capacitor 35 , a power supply 36 , and a comparator 37 .

[0048] The transistor 33 and the current source 34 charge and discharge the capacitor 35 based on the error state recognition signal. The comparator 37 outputs an output signal that is a protection operation signal based on a comparison result between the voltage of the capacitor 35 and the voltage of the power source 36.

[0049] Figure 5 2 is a timing chart showing the operation of the protection action signal generating circuit 10 according to the first embodiment. Figure 5 : shows the error state identification signal of the error state identification signal output terminal FOI, the voltage cin of the capacitor 35 and the protection action signal of the protection action signal output terminal FO.

[0050] like Figure 5 As shown in FIG. 1 , the current value flowing in the current source 34 and the capacitance value of the capacitor 35 are set so that the voltage cin of the capacitor 35 does not rise to the voltage V of the power supply 36 during the output period of the error state recognition signal. The protection action signal generating circuit 10 configured in this way can output the protection action signal during a period greater than or equal to the output period of the error state recognition signal, and thus can generate a protection action signal having a pulse width greater than or equal to the output period of the error state recognition signal.

[0051] <Summary of Implementation Method 1>

[0052] According to the semiconductor element driving device 81 involved in the present embodiment 1, an error state identification signal with a different waveform is generated for each type of error state, a protection action signal is generated based on the error state identification signal, and the error state identification signal and the protection action signal are output from the error state identification signal output terminal FOI and the protection action signal output terminal FO, respectively. According to such a structure, the external control device can identify the error state in the protection action caused by the error. In addition, since the error state identification signal has a smaller pulse width than each error signal, the external control device can identify the type of the error state early. In addition, the error state identification signal is output from one error state identification signal output terminal FOI, so it is not necessary to set a terminal for each type of error state, and the number of terminals can be reduced.

[0053] <Variation of Embodiment 1>

[0054] In the first embodiment, the case where the plurality of error state detection circuits include the power supply voltage abnormality detection circuit 4, the unsaturated state detection circuit 5, the gate abnormality detection circuit 6, the temperature abnormality detection circuit 7, and the current abnormality detection circuit 8 is described. However, the plurality of error state detection circuits may include at least two of the above circuits, or may include circuits for detecting abnormal states other than the above. That is, even if the types and numbers of the plurality of error state detection circuits are not limited to the above, the same effect as in the first embodiment can be obtained. In addition, in this specification, for example, at least any one (two) of A, B, C, ..., and Z means any one (two) of all combinations of one type or more (two types) extracted from the group of A, B, C, ..., and Z.

[0055] Furthermore, the temperature detection diode 2 and the current detection transistor 3 may not be provided in accordance with the configuration of the plurality of error state detection circuits.

[0056] In addition, in Embodiment 1, the error state identification signal generating circuit 9 generates an error state identification signal having a different duty cycle for each type of error signal. However, the error state identification signal generating circuit 9 may be a circuit that generates a signal capable of identifying an error state, and may be, for example, a circuit that generates an error state identification signal having a different duty cycle, frequency, and amplitude for each type of error signal.

[0057] The protection action signal generating circuit 10 may be any circuit as long as it generates a protection action signal having a pulse width greater than or equal to the output period of the error state identification signal. Figure 4 The same effect as in Embodiment 1 can be obtained by using a circuit of the same embodiment. Figure 2circuit.

[0058] <Implementation method 2>

[0059] Figure 6 1 is a diagram showing a configuration of a semiconductor element driving device 81 according to Embodiment 2. The semiconductor element driving device 81 according to Embodiment 2 includes a primary side circuit 81A, a secondary side circuit 81B, and level shift circuits 38 , 39 , 40 , 41 , 42 , and 43 .

[0060] The primary side circuit 81A includes Figure 1 The error state identification signal generating circuit 9, the error state identification signal output terminal FOI, the protection action signal generating circuit 10, the protection action signal output terminal FO, the protection circuit 11 and the input terminal IN involved in the embodiment 1 shown. The primary side circuit 81A transmits signals to the outside of the semiconductor element driving device 81, that is, the external control device, and receives a driving signal for driving the semiconductor element 1 from the external control device through the input terminal IN.

[0061] The primary side circuit 81A includes a power supply voltage abnormality detection circuit 44 , an OR circuit 45 , and an AND circuit 46 in which one side input is inverted.

[0062] When the power supply voltage abnormality detection circuit 44 detects an abnormal state of the power supply voltage VCC1 of the primary side circuit 81A, it generates and outputs an error signal err5. The OR circuit 45 outputs a signal indicating a logical sum of the error signal err5 output from the power supply voltage abnormality detection circuit 44 and the protection action signal output from the protection action signal generation circuit 10 to the protection circuit 11 and the protection action signal output terminal FO. The AND circuit 46 outputs a signal indicating a logical sum of the error signal err5 output from the power supply voltage abnormality detection circuit 44 and the inverted error signal and the error state identification signal output from the error state identification signal generation circuit 9 to the error state identification signal output terminal FOI.

[0063] According to such a configuration, when the error signal err5 is not output from the power supply voltage abnormality detection circuit 44, the protection action signal and the error state identification signal can be output from the protection action signal output terminal FO and the error state identification signal output terminal FOI as in the first embodiment.

[0064] On the other hand, when the error signal err5 is output from the power supply voltage abnormality detection circuit 44, an on signal is output from the protection action signal output terminal FO, and an off signal is output from the error state identification signal output terminal FOI instead of an error state identification signal.

[0065] The secondary side circuit 81B drives the semiconductor element 1 based on the driving signal substantially received from the primary side circuit 81A. The secondary side circuit 81B includes Figure 1 The first embodiment shown includes a power supply voltage abnormality detection circuit 4, an unsaturated state detection circuit 5, a gate abnormality detection circuit 6, a temperature abnormality detection circuit 7, a current abnormality detection circuit 8, and an amplifier 12. In addition, the power supply voltage abnormality detection circuit 4 generates and outputs an error signal err0 when an abnormal state of the power supply voltage VCC2 of the secondary side circuit 81B is detected.

[0066] The level shift circuit 43 performs level shifting on the driving signal received by the primary side circuit 81A and transmits it to the secondary side circuit 81B. The level shift circuits 38, 39, 40, 41, 42 perform level shifting on the multiple error signals err0, err1, err2, err3, err4 generated by the secondary side circuit 81B and transmit them to the primary side circuit 81A.

[0067] <Summary of Implementation Method 2>

[0068] According to the semiconductor element driving device 81 involved in the present embodiment 2 as described above, through the level shift circuits 38, 39, 40, 41, 42, and 43, the secondary side circuit 81B can drive the semiconductor element 1 based on the driving signal received by the primary side circuit 81A, and the primary side circuit 81A can identify the error state detected by the secondary side circuit 81B.

[0069] In addition, when the signal of the error state identification signal output terminal FOI is off and the signal of the protection action signal output terminal FO is on, the external control device can determine that the primary side circuit 81A has detected an abnormal power supply voltage. Therefore, the external control device can identify the error state detected by the primary side circuit 81A and the error state detected by the secondary side circuit 81B. In addition, there is no need to provide a dedicated terminal for the error state of the primary side circuit 81A, and the number of terminals can be reduced.

[0070] <Variation of Embodiment 2>

[0071] In the second embodiment, a configuration is described in which the error state identification signal from the error state identification signal generating circuit 9 and the protection action signal from the protection action signal generating circuit 10 are changed based on the output of the power supply voltage abnormality detecting circuit 44. However, the error state identification signal generating circuit 9 may generate an error state identification signal corresponding to the error state of the primary side circuit 81A and the secondary side circuit 81B based on the output of the power supply voltage abnormality detecting circuit 44 and the error signal of the secondary side circuit 81B. According to such a configuration, even without using the OR circuit 45 and the AND circuit 46, the protection action signal can be output from the protection action signal output terminal FO, and the error state identification signal can be output from the error state identification signal output terminal FOI.

[0072] <Implementation method 3>

[0073] Figure 7 1 is a diagram showing the structure of a semiconductor element driving device 81 according to the third embodiment. Figure 6 The structure of the second embodiment shown is the same as that of the error state identification signal generation circuit 9 included in the secondary side circuit 81B, and the level shift circuit 47 is provided instead of the level shift circuits 38, 39, 40, 41, 42. The level shift circuit 47 performs level shifting on the error state identification signal generated by the secondary side circuit 81B and transmits it to the primary side circuit 81A.

[0074] <Summary of Implementation Method 3>

[0075] According to the semiconductor element driving device 81 of the third embodiment, the error state identification signal generating circuit 9 is included in the secondary side circuit 81B, so there is no need to provide a level shift circuit for each error state. As a result, it is expected that the circuit area and current consumption of the semiconductor element driving device 81 can be reduced.

[0076] <Implementation method 4>

[0077] Figure 8 1 is a diagram showing the structure of a semiconductor element driving device 81 according to the fourth embodiment. Figure 7 The structure of the third embodiment shown is the same as that in which a transmission circuit 48, a transformer 49, and a reception circuit 50 are provided in place of the level shift circuit 47, and a transmission circuit 51, a transformer 52, and a reception circuit 53 are provided in place of the level shift circuit 43. The transmission circuits 48, 51, the transformers 49, 52, and the reception circuits 50, 53 are included in the concept of the insulating element.

[0078] The transmission circuit 48, transformer 49 and receiving circuit 50 transmit the error state identification signal generated by the secondary circuit 81B to the primary circuit 81A as an AC signal. In addition, the transmission circuit 48, transformer 49 and receiving circuit 50 insulate the DC signals of the primary circuit 81A and the secondary circuit 81B.

[0079] The transmission circuit 51, transformer 52 and receiving circuit 53 transmit the driving signal received by the primary circuit 81A to the secondary circuit 81B as an AC signal. In addition, the transmission circuit 51, transformer 52 and receiving circuit 53 insulate the DC signals of the primary circuit 81A and the secondary circuit 81B.

[0080] <Summary of Implementation Method 4>

[0081] According to the semiconductor element driving device 81 according to the third embodiment as described above, it is possible to transmit signals while insulating the DC signals of the primary side circuit 81A and the secondary side circuit 81B.

[0082] <Variation of Embodiment 4>

[0083] In the fourth embodiment, the insulating element includes transformers 49 and 52, but as long as the signal can be transmitted while the DC signal of the primary circuit 81A and the secondary circuit 81B is insulated, the transformers 49 and 52 may not be included. For example, the insulating element may include a capacitor instead of the transformers 49 and 52. In addition, the insulating element may include an optical coupler that can transmit an optical signal instead of a DC signal. In this case, the same effect as that of the fourth embodiment is obtained.

[0084] In addition, the embodiments and the modifications can be freely combined, and the embodiments and the modifications can be appropriately modified or omitted.

[0085] Hereinafter, each aspect of the present invention will be described collectively as supplementary notes.

[0086] (Note 1)

[0087] A semiconductor element driving device drives a semiconductor element.

[0088] The semiconductor element driving device comprises:

[0089] a plurality of error state detection circuits, which respectively detect error states of the semiconductor element or the semiconductor element driving device and generate error signals corresponding to the detected error states;

[0090] an error state identification signal generating circuit, which generates, for each type of the error state, an error state identification signal having a different waveform and a smaller pulse width than each of the error signals, based on the plurality of error signals respectively generated by the plurality of error state detection circuits;

[0091] An error state identification signal output terminal, which outputs the error state identification signal;

[0092] a protection action signal generating circuit, which generates a protection action signal for protecting the semiconductor element based on the error state identification signal;

[0093] a protection action signal output terminal that outputs the protection action signal; and a protection circuit that protects the semiconductor element based on the protection action signal.

[0094] (Note 2)

[0095] The semiconductor element driving device according to Supplementary Note 1, wherein:

[0096] The plurality of error state detection circuits include at least two of the following circuits:

[0097] a power supply voltage abnormality detection circuit that detects an abnormal state of the power supply voltage of the semiconductor element driving device as the error state;

[0098] an unsaturated state detection circuit for detecting an unsaturated state of the semiconductor element when the semiconductor element is in an on state as the error state;

[0099] a gate abnormality detection circuit that detects an abnormal state of a gate of the semiconductor element as the error state;

[0100] a temperature abnormality detection circuit that detects an abnormal state of the temperature of the semiconductor element as the error state; and

[0101] The current abnormality detection circuit detects an abnormal state of the current of the semiconductor element as the error state.

[0102] (Note 3)

[0103] The semiconductor element driving device according to Supplement 1 or 2, wherein:

[0104] At least any one of the duty ratio, the frequency, and the amplitude of the error state identification signal is different for each of the types of the error state, so that the waveform of the error state identification signal is different.

[0105] (Note 4)

[0106] The semiconductor element driving device according to any one of Supplementary Notes 1 to 3, wherein:

[0107] The pulse width of the protection action signal is greater than or equal to the output period of the error state identification signal.

[0108] (Note 5)

[0109] The semiconductor element driving device according to any one of Supplementary Notes 1 to 4, wherein:

[0110] The error state identification signal generating circuit, the error state identification signal output terminal, the protection action signal generating circuit, the protection action signal output terminal, and the protection circuit are included in a primary side circuit that receives a driving signal for driving the semiconductor element from outside the semiconductor element driving device.

[0111] The plurality of error state detection circuits are included in a secondary side circuit for driving the semiconductor element,

[0112] The semiconductor element driving device further includes a level shift circuit that level-shifts the driving signal received by the primary side circuit and transmits it to the secondary side circuit, and level-shifts the plurality of error signals generated by the secondary side circuit and transmits them to the primary side circuit.

[0113] (Note 6)

[0114] The semiconductor element driving device according to any one of Supplementary Notes 1 to 4, wherein:

[0115] The error state identification signal output terminal, the protection action signal generation circuit, the protection action signal output terminal and the protection circuit are included in a primary side circuit that receives a drive signal for driving the semiconductor element from outside the semiconductor element driving device.

[0116] The plurality of error state detection circuits and the error state identification signal generation circuit are included in a secondary side circuit that drives the semiconductor element.

[0117] The semiconductor element driving device further includes a level shift circuit that level-shifts the driving signal received by the primary side circuit and transmits it to the secondary side circuit, and level-shifts the error state identification signal generated by the secondary side circuit and transmits it to the primary side circuit.

[0118] (Note 7)

[0119] The semiconductor element driving device according to any one of Supplementary Notes 1 to 4, wherein:

[0120] The error state identification signal output terminal, the protection action signal generation circuit, the protection action signal output terminal and the protection circuit are included in a primary side circuit that receives a drive signal for driving the semiconductor element from outside the semiconductor element driving device.

[0121] The plurality of error state detection circuits and the error state identification signal generation circuit are included in a secondary side circuit that drives the semiconductor element.

[0122] The semiconductor element driving device also has an insulating element, which transmits the driving signal received by the primary side circuit to the secondary side circuit as a signal other than a DC signal, transmits the error state identification signal generated by the secondary side circuit to the primary side circuit as a signal other than a DC signal, and insulates the DC signals between the primary side circuit and the secondary side circuit.

[0123] (Note 8)

[0124] The semiconductor element driving device according to any one of Supplementary Notes 5 to 7, wherein:

[0125] A power supply voltage abnormality detection circuit is further provided. The power supply voltage abnormality detection circuit is included in the primary side circuit and detects an abnormal state of the power supply voltage of the primary side circuit.

[0126] Description of the label

[0127] 1 semiconductor element, 4, 44 power supply voltage abnormality detection circuit, 5 unsaturated state detection circuit, 6 gate abnormality detection circuit, 7 temperature abnormality detection circuit, 8 current abnormality detection circuit, 9 error state identification signal generation circuit, 10 protection action signal generation circuit, 11 protection circuit, 38, 39, 40, 41, 42, 43, 47 level shift circuit, 48, 51 transmission circuit, 49, 52 transformer, 50, 53 receiving circuit, 81 semiconductor element driving device, 81A primary side circuit, 82B secondary side circuit, FO protection action signal output terminal, FOI error state identification signal output terminal.

Claims

1. A semiconductor element driving device, which drives a semiconductor element. The semiconductor element driving device comprises: a plurality of error state detection circuits, which respectively detect error states of the semiconductor element or the semiconductor element driving device and generate error signals corresponding to the detected error states; an error state identification signal generating circuit, which generates, for each type of the error state, an error state identification signal having a different waveform and a smaller pulse width than each of the error signals, based on the plurality of error signals respectively generated by the plurality of error state detection circuits; An error state identification signal output terminal, which outputs the error state identification signal; a protection action signal generating circuit, which generates a protection action signal for protecting the semiconductor element based on the error state identification signal; A protection action signal output terminal, which outputs the protection action signal; as well as A protection circuit protects the semiconductor element based on the protection action signal.

2. The semiconductor element driving device according to claim 1, wherein: The plurality of error state detection circuits include at least two of the following circuits: a power supply voltage abnormality detection circuit that detects an abnormal state of the power supply voltage of the semiconductor element driving device as the error state; an unsaturated state detection circuit for detecting an unsaturated state of the semiconductor element when the semiconductor element is in an on state as the error state; a gate abnormality detection circuit that detects an abnormal state of a gate of the semiconductor element as the error state; a temperature abnormality detection circuit that detects an abnormal state of the temperature of the semiconductor element as the error state; as well as The current abnormality detection circuit detects an abnormal state of the current of the semiconductor element as the error state.

3. The semiconductor element driving device according to claim 1 or 2, wherein: At least any one of the duty ratio, the frequency, and the amplitude of the error state identification signal is different for each of the types of the error state, so that the waveform of the error state identification signal is different.

4. The semiconductor element driving device according to any one of claims 1 to 3, wherein: The pulse width of the protection action signal is greater than or equal to the output period of the error state identification signal.

5. The semiconductor element driving device according to any one of claims 1 to 4, wherein: The error state identification signal generating circuit, the error state identification signal output terminal, the protection action signal generating circuit, the protection action signal output terminal, and the protection circuit are included in a primary side circuit that receives a driving signal for driving the semiconductor element from outside the semiconductor element driving device. The plurality of error state detection circuits are included in a secondary side circuit for driving the semiconductor element. The semiconductor element driving device further includes a level shift circuit that level-shifts the driving signal received by the primary side circuit and transmits it to the secondary side circuit, and level-shifts the plurality of error signals generated by the secondary side circuit and transmits them to the primary side circuit.

6. The semiconductor element driving device according to any one of claims 1 to 4, wherein: The error state identification signal output terminal, the protection action signal generation circuit, the protection action signal output terminal and the protection circuit are included in a primary side circuit that receives a drive signal for driving the semiconductor element from outside the semiconductor element driving device. The plurality of error state detection circuits and the error state identification signal generation circuit are included in a secondary side circuit that drives the semiconductor element. The semiconductor element driving device further includes a level shift circuit that level-shifts the driving signal received by the primary side circuit and transmits it to the secondary side circuit, and level-shifts the error state identification signal generated by the secondary side circuit and transmits it to the primary side circuit.

7. The semiconductor element driving device according to any one of claims 1 to 4, wherein: The error state identification signal output terminal, the protection action signal generation circuit, the protection action signal output terminal and the protection circuit are included in a primary side circuit that receives a drive signal for driving the semiconductor element from outside the semiconductor element driving device. The plurality of error state detection circuits and the error state identification signal generation circuit are included in a secondary side circuit that drives the semiconductor element. The semiconductor element driving device also has an insulating element, which transmits the driving signal received by the primary side circuit to the secondary side circuit as a signal other than a DC signal, transmits the error state identification signal generated by the secondary side circuit to the primary side circuit as a signal other than a DC signal, and insulates the DC signals between the primary side circuit and the secondary side circuit.

8. The semiconductor element driving device according to any one of claims 5 to 7, wherein: A power supply voltage abnormality detection circuit is further provided. The power supply voltage abnormality detection circuit is included in the primary side circuit and detects an abnormal state of the power supply voltage of the primary side circuit.

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