Data processing method, network card and host

Abstract

The embodiment of the application provides a data processing method, a network card and a host. The data processing method comprises the following steps: a controller divides a to-be-processed message to obtain control plane information and data payload; the controller sends the control plane information to a communication protocol stack in the host based on a computer fast link protocol between the network card and the communication protocol stack; an accelerator performs data processing on the data payload to obtain processed data; the controller acquires updated control plane information obtained by updating the control plane information by the communication protocol stack; and the controller encapsulates the updated control plane information and the processed data to obtain target data.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and includes, but is not limited to, a data processing method, a network interface card (NIC), and a host. Background Technology

[0002] Transmission Control Protocol / Internet Protocol (TCP / IP) is currently the mainstream data communication method in computer systems, and is widely used in industries such as data centers, industrial control, and video surveillance.

[0003] TCP / IP networks are implemented in the host's operating system (OS). During data communication, the network interface card (NIC) acts as a bridge between the host and the communication network. The NIC receives network data and uploads it to the OS's network protocol stack for processing through the host's Peripheral Component Interconnect Express (PCIe) interface. After processing, the OS sends the data back to the NIC through the PCIe interface, and the NIC then transmits it to the communication network. In this process, the data packet undergoes two PCIe I / O transmissions, which greatly increases the data transmission latency.

[0004] Related technologies address the issue of high latency when the host TCP / IP network protocol stack processes large amounts of data by offloading the functions of the TCP / IP network protocol stack to a Field Programmable Gate Array (FPGA). However, FPGA processors have the characteristics of strong data processing and weak control, which limits their data processing capabilities and prevents them from fully realizing all the functions of the TCP / IP network. Summary of the Invention

[0005] To address the problems existing in the related technologies, embodiments of this application provide a data processing method, a network interface card (NIC), and a host.

[0006] In a first aspect, this application provides a data processing method applied to a network interface card (NIC), the NIC including a controller and an accelerator, the data processing method comprising:

[0007] The controller segments the message to be processed to obtain control plane information and data payload;

[0008] The controller sends control plane information to the communication protocol stack based on the computer fast link protocol between the network card and the communication protocol stack in the host.

[0009] The accelerator processes the data payload to obtain processed data.

[0010] The controller obtains the updated control plane information obtained by updating the control plane information through the communication protocol stack;

[0011] The controller encapsulates the updated control surface information and processing data to obtain the target data.

[0012] In some embodiments,

[0013] The controller segments the message to be processed to obtain control plane information and data payload, including:

[0014] In response to a data acceleration request sent by the accelerator or a delay in the host's data processing that does not meet the data processing conditions, the controller extracts data from the header of the message to be processed to obtain control plane information. The control plane information includes various types of byte information transmitted based on the computer fast link protocol.

[0015] The controller identifies the message body in the message to be processed as the data payload.

[0016] In some embodiments,

[0017] The network card also includes network card memory; data processing methods also include:

[0018] Upon receiving a message to be processed, the controller stores the message in the network interface card's memory.

[0019] Correspondingly, the controller sends control plane information to the communication protocol stack based on the Computer Fast Link protocol between the network interface card and the host communication protocol stack, including:

[0020] The controller sends control plane information to the communication protocol stack in sequence based on the order in which the packets to be processed are stored in the network card's memory.

[0021] In some embodiments,

[0022] The accelerator processes the data payload to obtain processed data, including:

[0023] The accelerator analyzes the data payload to obtain the data processing requirements of the data payload;

[0024] The accelerator performs accelerated logic processing on the data payload based on data processing requirements to obtain processed data.

[0025] In some embodiments, the data processing method further includes:

[0026] In response to the connection request issued by the accelerator, the controller sends a connection establishment request to the communication protocol stack based on the computer fast link protocol. The connection request is used to establish a connection between the controller and the host, and the connection establishment request information includes various types of byte information transmitted based on the computer fast link protocol.

[0027] The controller obtains the updated connection establishment request information sent by the communication protocol stack based on the computer fast link protocol. The updated connection establishment request information is obtained by the communication protocol stack after establishing a connection between the host and the network card based on the connection request information.

[0028] In some embodiments, the data processing method further includes:

[0029] The accelerator sends the processed data to the controller, or sends the processed data to the network card's memory;

[0030] The controller obtains the updated control plane information obtained by updating the control plane information through the communication protocol stack, including:

[0031] In response to receiving the processed data sent by the accelerator, the controller sends a data acquisition request to the communication protocol stack;

[0032] The controller obtains the updated control plane information sent by the communication protocol stack in response to the data acquisition request;

[0033] The updated control plane information is the data after the communication protocol stack updates the receive window size, protocol number, flag bits, and sequence number in the control plane information.

[0034] Secondly, embodiments of this application provide a network interface card (NIC), the NIC comprising:

[0035] Controller; and

[0036] An accelerator coupled to a controller; wherein the controller is configured to:

[0037] The message to be processed is segmented to obtain control plane information and data payload; and

[0038] Based on the computer fast link protocol between the network card and the communication protocol stack in the host, control plane information is sent to the communication protocol stack;

[0039] The accelerator is configured to: process the data payload to obtain processed data;

[0040] The controller is configured to: obtain updated control plane information obtained by updating the control plane information using the communication protocol stack; and

[0041] The updated control plane information and processing data are encapsulated to obtain the target data.

[0042] In some embodiments, the accelerator is configured to:

[0043] Send a connection request to the controller; the connection request is used to establish a connection between the controller and the host.

[0044] The controller is configured to: in response to a connection request, send a connection establishment request message to the communication protocol stack; the connection establishment request message includes various types of byte information transmitted based on the computer's fast link protocol; and

[0045] Based on the computer fast link protocol, the updated connection establishment request information sent by the communication protocol stack is obtained; the updated connection establishment request information is obtained by the communication protocol stack after establishing a connection between the host and the network card based on the connection request information.

[0046] In some embodiments, the accelerator is configured to:

[0047] The processed data is sent to the controller, or to the network card's memory.

[0048] The controller is configured to:

[0049] In response to receiving processed data from the accelerator, the controller sends a data acquisition request to the communication protocol stack; and

[0050] Obtain the updated control plane information sent by the communication protocol stack in response to the data acquisition request.

[0051] Thirdly, embodiments of this application provide a host, the host comprising:

[0052] Communication protocol stack; and

[0053] Host memory, coupled to a communication protocol stack, which is configured to:

[0054] In response to control plane information sent by the network interface card (NIC) based on the Computer Fast Link Protocol (CLP) between the NIC and the communication protocol stack, the control plane information is updated to obtain updated control plane information; the control plane information is obtained by the NIC segmenting the packets to be processed; and

[0055] Based on the computer fast link protocol, the updated control plane information is sent to the network card, so that the network card can encapsulate the updated control plane information and processing data to obtain the target data; the processing data is obtained by the network card from the data payload obtained by segmenting the packet to be processed.

[0056] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0057] Figure 1 This is a flowchart of TCP / IP communication on the host OS in related technologies;

[0058] Figure 2 This is an optional flowchart illustrating the data processing method provided in the embodiments of this application;

[0059] Figure 3 This is a schematic diagram of the data structure for the interaction between the network card and the host via Cacheline, provided in an embodiment of this application.

[0060] Figure 4 This is a flowchart illustrating the interaction between the network card and the host in establishing a connection, as provided in an embodiment of this application.

[0061] Figure 5 This is a flowchart illustrating the interaction between the controller and the accelerator in the network card provided in this application embodiment;

[0062] Figure 6 This is a diagram of the TCP / IP offloading structure based on CXL acceleration provided in the embodiments of this application;

[0063] Figure 7 This is a flowchart illustrating the data processing method provided in the embodiments of this application. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application pertain. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit the application.

[0066] Figure 1This is a flowchart of TCP / IP communication on the host OS in related technologies, such as... Figure 1 As shown, network card 101 receives network data and uploads it to the network protocol stack 1031 of OS 103 through the PCIe interface 102 of host 10 for processing. After the processing is completed in the network protocol stack 1031, OS 103 will send the data back to network card 101 through memory 1032 and PCIe interface 102, and network card 101 will transmit the processed data to the communication network.

[0067] While host OS-based TCP / IP networks can support tens of thousands of concurrent connections, they consume significant CPU resources and experience substantial data processing latency. This is especially true with the rise of heterogeneous computing, where accelerators like FPGAs are increasingly offloading CPU tasks. In traditional host OS-based TCP / IP networks, all data packets must first pass through the accelerator network card (NIC) of the FPGA, reach the host network protocol stack, undergo protocol processing, and then return to the FPGA NIC. This results in two additional PCIe I / O transfers, significantly increasing transmission latency and limiting processing bandwidth, thus failing to fully utilize the parallel and real-time computing advantages of accelerators like FPGAs.

[0068] To address the issues of high latency and low bandwidth in FPGA accelerators when using the host TCP / IP network protocol stack for data processing, related technologies typically offload the TCP / IP network protocol stack functionality onto the FPGA. This approach eliminates the need to send data to the OS, bypassing the overhead of PCIe and the host CPU, significantly reducing processing latency and increasing bandwidth. However, due to the complexity of the TCP / IP network protocol and the limitations of FPGA processing capabilities, hardware-offloaded TCP / IP networks often suffer from the following problems:

[0069] First, the data-driven, control-independent nature of FPGA processors means that FPGAs cannot fully implement all the functions of TCP / IP networks. As a stateful data communication method, TCP / IP requires significant complexity to fully offload the protocol. FPGAs typically only implement the basic functions of TCP / IP, making it difficult to implement complex congestion control algorithms. Furthermore, as a continuously updated and evolving protocol, TCP / IP's update algorithms are difficult to implement on FPGAs in a timely manner. Second, as a resource-intensive device, the resources consumed in maintaining TCP / IP state limit the number of connections an FPGA can support. Compared to the tens of thousands of connections that a host computer can support, an FPGA typically supports only a few hundred connections. Finally, because FPGAs completely bypass the OS, the host cannot perceive the TCP / IP network status implemented on the FPGA in real time. Once a connection error occurs, the recovery and location of TCP / IP network faults implemented on the FPGA cannot be achieved.

[0070] Based on the problems existing in related technologies, the embodiments of this application can provide a data processing method applied to a network interface card (NIC), i.e., an FPGA, which includes a controller and an accelerator. The controller segments the packets to be processed to obtain control plane information and data payload. Based on the Compute Express Link (CXL) protocol between the NIC and the communication protocol stack in the host, the controller sends the control plane information to the communication protocol stack and sends the data payload to the accelerator for processing. This achieves separation of the control plane and data plane when processing data, reducing the burden on the host CPU while still allowing the host to implement complex congestion control algorithms and realize the complex functions of the TCP / IP network protocol. At the same time, the FPGA's accelerator processes the data payload, reducing the amount of data processing on the host, improving data processing efficiency, and reducing latency.

[0071] In the embodiments of this application, the network card can be a hardware structure capable of data processing, such as an FPGA, a system-on-chip (SoC), an application-specific integrated circuit (ASIC), or a network processing unit (NPU).

[0072] A network interface card (NIC) can include a controller and an accelerator. The controller (TCP / IP controller) is the core component of the NIC, responsible for handling data transmission and reception, executing various protocols, and managing data flow. The accelerator is used to improve network performance and efficiency by implementing specific functions through hardware acceleration technologies, such as offloading encryption, compression, and traffic analysis. Based on the controller and accelerator, the NIC can offload processing tasks from the host, freeing up CPU resources to handle other applications.

[0073] CXL is an interconnect technology used between the host CPU and the FPGA. It provides a cache-based coherence protocol, where the host and accelerators such as the FPGA share a cache and ensure data consistency. Data interaction and transfer between the host and accelerators such as the FPGA can be achieved through a cache line, thus bypassing the copy operation from PCIe I / O to memory, greatly reducing data transfer latency and increasing transmission bandwidth. Here, a cache line refers to the basic unit for tracking and managing data between the network card and the host during transmission, using 64-byte units.

[0074] The technical solution of this application will now be described in detail with reference to the accompanying drawings.

[0075] Figure 2 This is an optional flowchart illustrating a data processing method provided in an embodiment of this application. The execution entity of the data processing method provided in this embodiment is a network interface card (NIC) including a controller and an accelerator, such as... Figure 1 As shown, the data processing method provided in this application embodiment can be implemented through steps S201 to S205:

[0076] Step S201: The controller segments the message to be processed to obtain control plane information and data payload.

[0077] In this embodiment, the message to be processed can originate from the application layer, i.e., a network application on the host or other devices. These applications are responsible for generating the data to be transmitted and passing it to the transport layer (usually TCP) for processing. The TCP layer divides the data into multiple data packets, adds TCP header information to each data packet, and then passes these data packets to the network layer (usually IP). At the IP layer, the data packets are further encapsulated, and IP header information is added to form a complete IP datagram, i.e., the message to be processed, which is transmitted to the network interface card (NIC) via the network.

[0078] In some embodiments, after receiving a packet to be processed, the network interface card (NIC) controller can segment the packet, separating the control plane and data plane of the packet. The control plane data is sent to the communication protocol stack in the host, and the data payload is sent to the accelerator for acceleration logic processing, so as to achieve separate processing of the control plane and data plane.

[0079] In this embodiment, when the network interface card (NIC) and the host communication protocol stack interact via the cacheline, only a portion of the header bytes of the message to be processed need to be transmitted. To ensure data consistency, these bytes must maintain the same format as the cacheline. Therefore, during data segmentation, the byte data in the control plane information has the same data structure as the cacheline.

[0080] Control plane data primarily contains signaling information from network protocols. This includes sequence numbers (identifying packet positions within the data stream), acknowledgment numbers (ACKs), window sizes for flow control, protocol numbers identifying upper-layer application protocols, and flags controlling the establishment, acknowledgment, and termination of TCP connections. This information is used to establish, maintain, and release network connections. For example, control plane data handles tasks such as session control, connection management, and resource allocation. This data typically needs to be sent to the communication protocol stack for processing.

[0081] The data payload is the actual, valid data being transmitted, such as user data or file transfer content. During network interface card (NIC) processing, the data payload is sent to an accelerator for high-speed processing to improve data transmission efficiency. The data payload typically does not require complex protocol processing and is directly transmitted to the target device or user application.

[0082] Step S202: The controller sends control plane information to the communication protocol stack based on the computer fast link protocol between the network card and the communication protocol stack in the host.

[0083] In this embodiment, after the controller divides the message to be processed into control plane data and data payload, it sends the control plane data of the message to be processed to the communication protocol stack of the host based on the CXL protocol between the network card and the communication protocol stack in the host. The communication protocol stack parses the control plane data to obtain key information such as source address, destination address, and port number. Based on the above information, the communication protocol stack makes routing decisions to determine the forwarding path of the data packet.

[0084] Step S203: The accelerator processes the data payload to obtain processed data.

[0085] In this embodiment, the accelerator's data processing of the data payload can refer to performing logical processing such as filtering, compression, and optimization (e.g., interpolation and gradient descent) on the data to obtain processed data. Here, the type of processing performed on the data payload can be determined by the application or device sending the message to be processed, which carries a data processing request characterizing the data processing type when sending the message to be processed.

[0086] In some embodiments, when the controller receives multiple messages to be processed, the FPGA's accelerator can process the data payload sent by the controller in parallel to improve data processing efficiency.

[0087] Step S204: The controller obtains the updated control plane information obtained by updating the control plane information through the communication protocol stack.

[0088] In this embodiment, the communication protocol stack updates the control plane information to obtain updated control plane information. For example, the communication protocol stack updates the sequence number to ensure the sequential transmission and correct reassembly of data, updates the ACK number to inform the sender of the pending message that the data has been successfully received, updates the window size according to the buffer capacity, updates the protocol number according to the message content, and updates the flag bits according to the current communication status.

[0089] In this embodiment of the application, after the communication protocol stack updates the control plane data, it can store the updated control plane information in the host's memory. When the network card needs to send out the processed data, it can obtain the updated control plane information in the host's memory, encapsulate it with the processed data, and then send it out.

[0090] Step S205: The controller encapsulates the updated control surface information and processing data to obtain the target data.

[0091] In this embodiment of the application, during the encapsulation process, the controller may calculate a checksum or use other error detection and correction mechanisms, such as Cyclic Redundancy Check (CRC), to ensure the reliability of the target data transmission.

[0092] In this embodiment of the application, after obtaining the target data, it can be sent out through the network interface of the FPGA.

[0093] In this embodiment, the network interface card (NIC) segments the packets to be processed to obtain control plane information and data payload. The control plane information is sent to the communication protocol stack, and the data payload is sent to the accelerator for processing. This achieves separation of the control plane and data plane during data processing. While reducing the burden on the host CPU, the host still implements complex congestion control algorithms, enabling the implementation of complex functions of the TCP / IP network protocol. At the same time, the PGFA accelerator processes the data payload, reducing the amount of data processing on the host, improving data processing efficiency, and reducing latency.

[0094] In some embodiments, when there is data to be sent and processed in the accelerator, the data may be data in the FPGA memory. The accelerator sends the data to the controller. The controller obtains the updated control plane information corresponding to the data, such as sequence number information and window information, from the host OS's communication protocol stack through the CXL's cacheline. The controller then encapsulates and packages the data obtained by the controller into a TCP / IP protocol data packet and sends it to the network.

[0095] In some embodiments, to improve the host's processing efficiency, in this embodiment, when the network interface card receives any packet, the controller can segment the packet, sending only the control plane information to the controller and the data payload to the accelerator for processing. Alternatively, the controller can segment some packets when the host cannot process them all or when the accelerator sends a data acceleration request to the controller. Therefore, step S201 can be implemented through steps S2011 and S2022.

[0096] Step S2011: In response to the data acceleration request sent by the accelerator or the data processing delay of the host not meeting the data processing conditions, the controller extracts data from the header of the message to be processed to obtain control plane information. The control plane information includes various types of byte information transmitted based on the computer fast link protocol.

[0097] In this embodiment, after the controller acquires the message to be processed, it can determine whether the accelerator has sent a data acceleration request. This request instructs the controller to segment the message to be processed and send the segmented data payload to the accelerator for logical acceleration processing. Alternatively, after acquiring the message to be processed, the controller can monitor the current CPU operation status, i.e., the load status, including CPU utilization and memory usage, to determine whether the CPU has sufficient resources to process the currently received message to be processed. If the CPU resources are insufficient, it will cause data latency when the CPU is processing data. Therefore, the controller can indicate that the CPU resources are insufficient when the latency of host data processing does not meet the data processing conditions, i.e., the latency of data processing is greater than a preset threshold (e.g., 500 milliseconds). At this time, the message to be processed can be segmented. Here, the separation of the control plane and data plane of the message to be processed can also be performed at other times, and this application does not limit this.

[0098] In this embodiment, when the FPGA and the host transmit data via the CXL protocol, they have a fixed data structure. Figure 3 This is a schematic diagram of the data structure for the interaction between the network card and the host via Cacheline, as provided in the embodiments of this application. Figure 3 As shown, when the network card and the host transmit data via the CXL protocol, it does so through methods such as... Figure 3 The cacheline shown transmits partial byte information, such as the source Internet Protocol (IP) address, destination IP address, IP checksum, source port, destination port, TCP checksum, sequence number, ACK number, window size, protocol number, flag, and timestamp. Figure 3 The "Reserved" option can be used to add additional byte information.

[0099] In this context, the source IP address represents the IP address of the sender of the message to be processed, used to identify the source; the destination IP address represents the IP address of the target receiver; the IP checksum is used to verify the integrity of the IP header, ensuring that the data has not been tampered with or corrupted during transmission; the source port identifies the port number of the sender, used to distinguish communication between multiple applications on the same computer; the destination port identifies the port number of the receiver, used to distinguish communication between multiple applications on the same computer; the sequence number identifies the order of each byte in the data stream sent in the TCP connection, ensuring that data is received in sequence; the ACK number represents the sequence number of the next data segment that the receiver expects to receive, used to confirm that data has been successfully received; and the timestamp records the time of sending and receiving, often used to diagnose network latency and jitter issues.

[0100] In this embodiment of the application, segmenting the message to be processed by the controller means extracting data from the header of the message to be processed to obtain control plane information, which includes various types of byte information transmitted based on the computer fast link protocol. The control plane information includes, but is not limited to, the byte information mentioned above. Other byte information in the header can be deleted, not sent, and not stored.

[0101] Step S2012: The controller determines the message body in the message to be processed as the data payload.

[0102] In this embodiment of the application, the message body of the message to be processed is determined as the data payload, and the data payload is sent to the accelerator, which performs logical acceleration processing.

[0103] In this embodiment, the controller separates the control plane and data plane of the pending message when the host's resources are unable to process data or after receiving a request from the accelerator. This enhances the flexibility of data processing, utilizes resources more efficiently, and improves network performance and quality of service. At the same time, the network card and the host only need to transmit a portion of the data packet information, which greatly reduces the size of the data packet and the transmission latency, avoids unnecessary data redundancy and transmission overhead, and improves efficiency.

[0104] In some embodiments, the network card will continuously receive pending messages, or receive multiple pending messages at once. However, when the communication protocol stack between the network card and the host transmits data through the CXL's cacheline, only one cacheline can be transmitted at a time. Therefore, the network card also includes network card memory. When multiple pending messages are received, the controller will store the messages in the network card memory and then send them out in sequence.

[0105] The data processing method provided in this application embodiment further includes step S1:

[0106] Step S1: In response to receiving a message to be processed, the controller stores the message to be processed in the network card memory.

[0107] In this embodiment of the application, when the controller receives a message to be processed, it stores the message in the network card memory, and the controller segments and sends it out in the order of storage.

[0108] Correspondingly, step S202 can be achieved through step S2021:

[0109] Step S2021: The controller sends the control plane information to the communication protocol stack in sequence based on the order in which the packets to be processed are stored in the network card memory.

[0110] In this embodiment of the application, since the CXL protocol can only transmit one cacheline at a time, the controller will send the control plane information to the communication protocol stack in sequence based on the storage order of the packets to be processed in the network card memory.

[0111] In this embodiment, the controller can send control plane information in the order of storage, which can reduce concurrent conflicts when sending information at the same time, avoid packet loss, and at the same time help optimize resource allocation and communication process, ensuring the efficiency and reliability of data transmission.

[0112] In some embodiments, the accelerator can be used to improve network performance and efficiency, implementing specific functions through hardware acceleration technology, such as offloading encryption, compression, traffic analysis, etc. Therefore, step S203 can be achieved through steps S2031 and S2032:

[0113] Step S2031: The accelerator parses the data payload to obtain the data processing requirements of the data payload.

[0114] In this embodiment of the application, the accelerator can parse the data payload, that is, analyze the data payload and require other data processing such as filtering, compression or encryption of the data payload.

[0115] Alternatively, after receiving the message to be processed, the controller can write the data processing requirements of the data payload into the control register of the accelerator, and the accelerator can process the data payload according to these data processing requirements.

[0116] Alternatively, after the accelerator parses the data payload, it can obtain the type of the data payload and determine the data processing requirements, such as filtering, compression, or encryption, based on the type.

[0117] Step S2032: Based on data processing requirements, the accelerator performs accelerated logic processing on the data payload to obtain processed data.

[0118] In this embodiment of the application, after receiving the data processing requirements, the accelerator performs corresponding acceleration logic processing on the data payload, such as filtering, compression, or encryption, to obtain the processed data.

[0119] Here, after receiving the processed data, if the accelerator needs to send the processed data out, it can send the processed data to the controller. The controller obtains the updated control plane information corresponding to the encrypted data from the host, encapsulates it, and then sends it out. If the processed data does not need to be sent out, it can be stored in the network card memory.

[0120] In this embodiment, when the accelerator receives the data payload and performs acceleration logic processing, the accelerator can process multiple tasks simultaneously, reducing computation time and improving data processing efficiency and response speed. This is especially important in application scenarios such as autonomous driving and edge computing that require real-time processing of large amounts of data.

[0121] In this embodiment of the application, a connection needs to be established between the network card and the host before data transmission occurs between the network card and the controller. Figure 4 This is a flowchart illustrating the interaction between the network card and the host in establishing a connection, as provided in the embodiments of this application. Figure 4 As shown, the network card and the host can establish a connection through steps S401 to S404:

[0122] Step S401: The accelerator sends a connection request to the controller.

[0123] In this embodiment, when the network card is working, the accelerator on the FPGA first initiates a TCP / IP connection as needed. Then, the FPGA and the host exchange TCP / IP control plane information through the CXL Cacheline. Therefore, the establishment of the connection between the network card and the host is initiated by the accelerator, which sends a connection request to the controller, instructing the controller to initiate a connection establishment request to the communication protocol stack.

[0124] Step S402: In response to the connection request issued by the accelerator, the controller sends a connection establishment request to the communication protocol stack based on the computer fast link protocol.

[0125] In this embodiment, in response to a connection request from the accelerator, the controller sends a connection establishment request message to the communication protocol stack based on the CXL protocol. The connection request message is used to request the host to establish a connection between the controller and the host.

[0126] In some embodiments, the connection establishment request information is transmitted based on the CXL protocol, and the connection request information includes... Figure 3The various types of byte information shown.

[0127] Step S403: Based on the connection request information, the communication protocol stack establishes a connection between the host and the network card, and updates the connection request information to obtain the updated connection request information.

[0128] In this embodiment of the application, after receiving the connection request information, the communication protocol stack verifies the byte information in the connection request information. If the verification passes, a connection is established between the host and the network card, and the connection establishment request information is updated to obtain the updated connection establishment request information.

[0129] Here, "update" can refer to updating byte information such as sequence number, ACK number, window size, protocol number, and flag.

[0130] In this embodiment of the application, after the communication protocol stack establishes a connection, it sends an updated connection establishment request to the controller.

[0131] Step S404: The controller obtains the updated connection establishment request information sent by the communication protocol stack based on the computer fast link protocol.

[0132] In this embodiment, the controller obtains the updated connection establishment request information sent by the communication protocol stack based on the CXL protocol to determine that the connection between the controller and the network card has been established.

[0133] In some embodiments, after the accelerator processes the data payload to obtain processed data, it can send the data out or store the data. Therefore, the data processing method provided in this application embodiment further includes step S2:

[0134] Step S2: The accelerator sends the processed data to the controller, or sends the processed data to the network card memory.

[0135] In this embodiment, after the accelerator receives the processed data, if the accelerator needs to send the processed data out, it can send the processed data to the controller. The controller obtains the updated control plane information corresponding to the encrypted data from the host, encapsulates it, and then sends it out. If the accelerator does not need to send the processed data out, it can store the processed data in the network card memory.

[0136] Correspondingly, step S205 can be achieved through steps S2051 and S2052:

[0137] Step S2051: In response to receiving the processing data sent by the accelerator, the controller sends a data acquisition request to the communication protocol stack.

[0138] Here, if the controller receives the processing data sent by the accelerator, it means that the processing data needs to be sent. At this time, the controller sends a data acquisition request to the communication protocol stack to obtain the updated control plane information corresponding to the processing data.

[0139] Step S2052: The controller obtains the updated control plane information sent by the communication protocol stack in response to the data acquisition request; wherein, the updated control plane information is the data after the communication protocol stack updates the receive window size, protocol number, flag bits and sequence number in the control plane information.

[0140] In this embodiment, after receiving control plane information, the communication protocol stack updates the sequence number to ensure the sequential transmission and correct reassembly of data, updates the ACK number to inform the sender of the pending message that the data has been successfully received, updates the window size according to the buffer capacity, updates the protocol number according to the message content, and updates the flag bit according to the current communication status to obtain the updated control plane information, which can be saved to the host's memory.

[0141] After receiving a data acquisition request, the communication protocol stack sends the updated control plane information to the controller. The controller acquires the updated control plane information based on the CXL protocol, encapsulates the updated control plane information and processing data, and then sends it out.

[0142] Figure 5 This is a flowchart illustrating the interaction between the controller and accelerator in the network card provided in this application embodiment, such as... Figure 5 As shown, the network interface card includes a controller 501 and an accelerator 502, with the accelerator 502 coupled to the controller 501, as follows: Figure 5 As shown:

[0143] The controller 501 is configured to: segment the message to be processed to obtain control plane information and data payload; and send the control plane information to the communication protocol stack based on the computer fast link protocol between the network card and the communication protocol stack in the host; the accelerator 502 is configured to: process the data payload to obtain processed data; the controller 501 is configured to: obtain the updated control plane information obtained by the communication protocol stack updating the control plane information; and encapsulate the updated control plane information and processed data to obtain target data.

[0144] In some embodiments, the accelerator 502 is configured to: send a connection request to the controller 501, the connection request being used to establish a connection between the controller 501 and the host; the controller 501 is configured to: in response to the connection request, send connection establishment request information to the communication protocol stack; the connection establishment request information includes various types of byte information transmitted based on the computer fast link protocol; and based on the computer fast link protocol, obtain the updated connection establishment request information sent by the communication protocol stack; the updated connection establishment request information is obtained by the communication protocol stack updating the connection establishment request information after establishing a connection between the host and the network card based on the connection request information.

[0145] In some embodiments, the accelerator 502 is configured to: send processing data to the controller 501, or send processing data to the network interface card memory of the network interface card; the controller 501 is configured to: in response to receiving the processing data sent by the accelerator 502, the controller 501 sends a data acquisition request to the communication protocol stack; and acquire the updated control plane information sent by the communication protocol stack in response to the data acquisition request.

[0146] In some embodiments, the controller 501 is configured to: extract data from the header of the message to be processed in response to a data acceleration request sent by the accelerator 502 or a delay in the host's data processing that does not meet the data processing conditions, to obtain control plane information, the control plane information including various types of byte information transmitted based on the computer fast link protocol; and determine the message body in the message to be processed as the data payload.

[0147] In some embodiments, the controller 501 is configured to: store the message to be processed in the network interface card (NIC) memory in response to receiving the message to be processed; and send control plane information to the communication protocol stack in sequence based on the order in which the messages to be processed are stored in the NIC memory.

[0148] In some embodiments, the accelerator 502 is configured to: parse the data payload to obtain the data processing requirements of the data payload; and perform accelerated logic processing on the data payload based on the data processing requirements to obtain processed data.

[0149] The description of the network card in this embodiment is similar to that of the aforementioned data processing method, and has similar beneficial effects; therefore, it will not be repeated here. For technical details not disclosed in the embodiments, please refer to the description of the data processing method in this application for understanding.

[0150] In this embodiment, a host is provided, comprising a communication protocol stack and host memory coupled to the communication protocol stack. The communication protocol stack is configured to: update the control plane information in response to control plane information sent by the network interface card (NIC) based on the Computer Fast Link Protocol (CFLP) between the NIC and the communication protocol stack, to obtain updated control plane information; the control plane information is obtained by the NIC segmenting the packets to be processed; and send the updated control plane information to the NIC based on the CFLP, so that the NIC encapsulates the updated control plane information and processing data to obtain target data; the processing data is obtained by the NIC processing the data payload obtained by the NIC segmenting the packets to be processed.

[0151] The description of the host in this embodiment is similar to that of the aforementioned data processing method, and has similar beneficial effects; therefore, it will not be repeated here. For technical details not disclosed in the embodiments, please refer to the description of the data processing method in this application for understanding.

[0152] The following provides an application of the data processing method in a practical scenario. To address the problems existing in related technologies, this application provides a new TCP / IP network offloading implementation method. Utilizing CXL technology, the control plane and data plane of TCP / IP are separated. The host OS handles the connection state maintenance of the TCP / IP network, while the FPGA directly processes the TCP / IP payload data (i.e., data payload) to accelerate task processing. This application utilizes the cache coherency function defined by the CXL type1 or type2 protocol to transmit partial data and status information (i.e., control plane information) of the TCP / IP header between the host OS and the FPGA accelerator.

[0153] This application addresses the problem of complex functions being unable to be implemented when the FPGA offloads TCP / IP network traffic. By placing the control plane functions of the TCP / IP protocol on the host OS, it can fully inherit the functions of the existing network protocol stack, achieving a fully reliable TCP / IP network protocol with a high connection count. The cache coherency of the CXL protocol solves the latency problem of data transmission between the host and the FPGA accelerator. Simultaneously, the processing of TCP / IP payload data (i.e., data payload) is offloaded to the FPGA accelerator, allowing for parallel processing with the host, reducing the FPGA's data waiting time, and improving bandwidth processing capabilities.

[0154] Figure 6 This is a diagram of the TCP / IP offloading structure based on CXL acceleration provided in the embodiments of this application, such as... Figure 6As shown, host 601 includes a communication protocol stack (TCP / IP Stack) 6011 and host memory 6012, and network interface card (FPGA) 602 includes a controller (TCP / IP Controller) 6021, an accelerator 6022, network interface card memory 6023, and a media access control and physical layer (MAC & Phy) 6024.

[0155] The connection between network card 602 and host 601 is achieved through CXL's cache consistency protocol. Host 601 and network card 602 share the cache, ensuring data consistency. Data interaction and transmission between host 601 and network card 602 can be achieved by directly manipulating the cacheline between accelerators such as host 601 and network card 602, bypassing the copy operation from PCIe IO to memory, reducing the latency problem of data transmission between host 601 and network card 602 and improving the transmission bandwidth.

[0156] This application embodiment utilizes CXL technology to separate the control plane and data plane of the TCP / IP network. The control plane is handled by the TCP / IP protocol stack (i.e., the communication protocol stack) of the host OS, while the data plane is accelerated by the accelerator on the FPGA.

[0157] Here, the control plane and data plane separation operations of the received data packets are handled by the FPGA. When TCP / IP is working, the communication protocol stack on the host OS is responsible for all TCP / IP connection state processing, including connection requests, sequence number allocation, window size processing, and congestion control, etc., and stores the state information of the high number of TCP / IP connections in the host memory. The controller on the FPGA is responsible for the disassembly and assembly of data packets, and stores the TCP / IP data packets in the FPGA memory and distributes them to the accelerator for acceleration logic processing.

[0158] In some embodiments, when there is data to be received and processed in the network, the controller on the FPGA extracts the bytes of the header portion of the received message to obtain control plane information, synchronizes it to the host's communication protocol stack through the CXL's cacheline for TCP / IP state processing, and submits the data portion of the received message to the acceleration module application (i.e., accelerator) inside the FPGA for data processing.

[0159] In some embodiments, when there is data to be sent and processed in the accelerator inside the FPGA (which may be data in the FPGA memory), the controller on the FPGA obtains the TCP / IP connection status information, such as sequence number information and window information, from the communication protocol stack of the host OS through the CXL's cacheline, and packages it with the payload data that has been processed or not processed by the internal acceleration module into a TCP / IP protocol data packet and sends it to the network.

[0160] In some embodiments, it is only necessary to pass such as Figure 3 The partial TCP / IP header byte information shown is consistent with the CXL Cacheline (in terms of format and size, ensuring efficient and consistent data transmission and avoiding unnecessary data redundancy and transmission overhead). Compared to related technologies where the TCP / IP communication protocol stack is fully implemented on the host OS, this application eliminates the need to copy all TCP / IP data packets. Transmitting partial byte information through the CXL Cacheline significantly reduces both the size of data packets and transmission latency. Compared to related technologies that completely offload TCP / IP from the FPGA, this application sends control plane information to the host for processing. The TCP / IP on the host can implement a more complete protocol stack, and because the TCP / IP connection state information is maintained on the host, the host can more quickly detect, locate, and respond to TCP / IP connection failures.

[0161] Figure 7 This is a flowchart illustrating the data processing method provided in the embodiments of this application, such as... Figure 7 As shown, in the data processing method of this application embodiment, data interacts between the host communication protocol stack, the network card controller, and the network card accelerator. The data processing method includes steps S701 to S713:

[0162] S701, the accelerator initiates a connection request.

[0163] Here, the accelerator on the FPGA initiates a TCP / IP network connection request and sends the connection request to the controller.

[0164] S702, the controller transmits connection request information through Cacheline.

[0165] In response to a connection request initiated by the accelerator, the controller transmits the IP address and connection request information to the host via the CXL Cacheline, in order to request the host to establish a connection with the network card.

[0166] S703, establish a connection using the communication protocol stack.

[0167] Here, the host TCP / IP protocol stack establishes a connection and synchronizes the connection information to the FPGA controller via the CXL Cacheline.

[0168] S704, the communication protocol stack synchronizes connection information through Cacheline.

[0169] S705, the controller receives the data to be processed.

[0170] The FPGA controller receives the data to be processed, decodes the data, extracts some bytes from the TCP / IP header information such as IP address, port number and sequence number, and passes them to the host protocol stack through the CXL Cacheline.

[0171] S706: The controller transmits header bytes via Cacheline.

[0172] Here, the header byte information is as shown above. Figure 3 The byte information is shown in the figure.

[0173] S707: The controller extracts the payload portion and sends it to the accelerator.

[0174] The controller extracts the payload portion from the data to be processed and sends it to the accelerator for processing.

[0175] S708, the communication protocol stack maintains the connection status.

[0176] Here, the host TCP / IP protocol stack maintains connection information (i.e., control plane information) and obtains updated connection information, including congestion control information such as updated ACK sequence numbers and receive window sizes.

[0177] S709, the accelerator processes the payload.

[0178] S710, the accelerator sends a request for data to be sent.

[0179] Here, the data request to be sent is used to indicate that the processed payload part needs to be sent.

[0180] S711, the controller obtains connection information through Cacheline.

[0181] After receiving the processed payload data from the accelerator, the controller interacts with the host through the CXL Cacheline to obtain updated connection information, such as the sending sequence number, ACK sequence number, window size information, and other byte information.

[0182] S712, the controller encapsulates the header and payload into network data packets.

[0183] The controller takes the updated connection information it acquires, assembles it into a TCP / IP header, combines it with the processed payload data provided by the accelerator, and encapsulates it into a TCP / IP network data packet.

[0184] S713, the controller sends network data packets.

[0185] The controller sends the encapsulated data packet out via the Ethernet interface.

[0186] This application's embodiments place the control plane functions of the TCP / IP protocol in the host OS processing, which can fully inherit the functions of the existing network protocol stack. This solves the problem that the FPGA cannot implement complex functions when offloading TCP / IP network, and realizes a reliable TCP / IP network protocol with a high connection count. The cache coherence of the CXL protocol solves the latency problem of data transmission between the host and the FPGA accelerator. At the same time, the processing of TCP / IP payload data (i.e., data payload) is offloaded to the FPGA accelerator, which can process it in parallel with the host, reducing the FPGA's waiting time for data and improving bandwidth processing capabilities.

[0187] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

[0188] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0189] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not performed.

[0190] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method applied to a network interface card (NIC), the NIC including a controller and an accelerator, the data processing method comprising: The controller segments the message to be processed to obtain control plane information and data payload; The controller sends the control plane information to the communication protocol stack based on the cache consistency mechanism provided by the computer fast link protocol between the network card and the communication protocol stack in the host. The accelerator processes the data payload to obtain processed data. The controller obtains the updated control plane information obtained by the communication protocol stack updating the control plane information; The controller encapsulates the updated control surface information and the processed data to obtain the target data.

2. The data processing method according to claim 1, wherein the controller segments the message to be processed to obtain control plane information and data payload, including: In response to a data acceleration request sent by the accelerator or if the data processing delay of the host does not meet the data processing conditions, the controller extracts data from the header of the message to be processed to obtain the control plane information, which includes various types of byte information transmitted based on the computer's fast link protocol. The controller identifies the message body in the message to be processed as the data payload.

3. The data processing method according to claim 1, wherein the network card further includes network card memory; the data processing method further includes: In response to receiving the message to be processed, the controller stores the message to be processed in the network interface card memory; Correspondingly, the controller sends the control plane information to the communication protocol stack based on the computer fast link protocol between the network card and the communication protocol stack in the host, including: The controller sends the control plane information to the communication protocol stack in sequence based on the order in which the packets to be processed are stored in the network card memory.

4. The data processing method according to any one of claims 1 to 3, wherein the accelerator processes the data payload to obtain processed data, comprising: The accelerator parses the data payload to obtain the data processing requirements of the data payload; The accelerator performs accelerated logic processing on the data payload based on the data processing requirements to obtain the processed data.

5. The data processing method according to any one of claims 1 to 3, further comprising: In response to the connection request issued by the accelerator, the controller sends a connection establishment request to the communication protocol stack based on the computer fast link protocol; The connection request is used to establish a connection between the controller and the host, and the connection request information includes various types of byte information transmitted based on the computer's fast link protocol; The controller obtains the updated connection establishment request information sent by the communication protocol stack based on the computer's fast link protocol. The updated connection establishment request information is obtained by updating the connection establishment request information after the communication protocol stack establishes a connection between the host and the network card based on the connection request information.

6. The data processing method according to any one of claims 1 to 3, further comprising: The accelerator sends the processed data to the controller, or sends the processed data to the network card memory of the network card; The controller obtains the updated control plane information obtained by the communication protocol stack updating the control plane information, including: In response to receiving the processing data sent by the accelerator, the controller sends a data acquisition request to the communication protocol stack; The controller acquires the updated control plane information sent by the communication protocol stack in response to the data acquisition request; The updated control plane information is the data updated by the communication protocol stack after modifying the receive window size, protocol number, flag bits, and sequence number in the control plane information.

7. A network interface card (NIC), the NIC comprising: Controller; and An accelerator coupled to the controller; The controller is configured to: The message to be processed is segmented to obtain control plane information and data payload; and Based on the cache coherency mechanism provided by the computer fast link protocol between the network card and the communication protocol stack in the host, the control plane information is sent to the communication protocol stack; The accelerator is configured to: process the data payload to obtain processed data; The controller is configured to: obtain updated control plane information obtained by updating the control plane information using the communication protocol stack; and The updated control plane information and the processed data are encapsulated to obtain the target data.

8. The network interface card according to claim 7, The accelerator is configured to: A connection request is sent to the controller, the connection request being used to establish a connection between the controller and the host; The controller is configured to send, to the communication protocol stack, connection establishment request information in response to the connection request; the connection establishment request information includes a plurality of types of byte information transmitted based on the computer fast link protocol; and Based on the computer fast link protocol, obtain the updated connection establishment request information sent by the communication protocol stack; The updated connection establishment request information is obtained by updating the connection establishment request information after the communication protocol stack establishes a connection between the host and the network card based on the connection request information.

9. The network interface card according to claim 7 or 8, The accelerator is configured to: The processed data is sent to the controller, or the processed data is sent to the network card memory of the network card; The controller is configured to: In response to receiving the processed data sent by the accelerator, the controller sends a data acquisition request to the communication protocol stack; and Obtain the updated control plane information sent by the communication protocol stack in response to the data acquisition request.

10. A host computer, the host computer comprising: Communication protocol stack; and Host memory, coupled to the communication protocol stack, wherein the communication protocol stack is configured to: In response to the control plane information sent by the network interface card (NIC) based on the cache coherency mechanism provided by the computer fast link protocol between the NIC and the communication protocol stack, the control plane information is updated to obtain the updated control plane information. The control plane information is obtained by segmenting the packets to be processed by the network interface card. and Based on the computer fast link protocol, the updated control plane information is sent to the network card, so that the network card encapsulates the updated control plane information and processing data to obtain the target data; The processing data is obtained by processing the data payload of the segmented packet to be processed by the network card.

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