Embedded printed circuit board layout structure and electronic device

Abstract

The application provides an embedded printed circuit board layout structure and electronic equipment, and belongs to the technical field of semiconductors. In the layout structure, a plurality of chip arrays are arranged in a chip region of a first insulating layer. A circuit board DC terminal is located in the chip region in a DC projection region of the first insulating layer. A circuit board AC terminal is located in the chip region in an AC projection region of the first insulating layer. The AC projection region and the DC projection region are arranged at intervals. The DC projection region and the AC projection region are located at intervals in the chip region, so that the circuit board DC terminal and the circuit board AC terminal are arranged close to the plurality of chips, are more closely arranged relative to each other, the space in the chip region can be fully utilized, the space occupied by the printed circuit board is small, the board area of the printed circuit board is reduced, and the problem of excessive board area in the conventional technology is solved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to an embedded printed circuit board layout structure and electronic device. Background Technology

[0002] Printed Circuit Boards (PCBs) are an essential component of electronic devices. A PCB consists of an insulating substrate, conductive lines, and various electronic components (such as chips, resistors, and capacitors). The proper arrangement of these components (chips, resistors, capacitors, inductors, etc.) and the placement of the wiring (conductive lines connecting the components) on the surface of the PCB are particularly important.

[0003] However, in the traditional layout, the DC input terminals and AC output terminals are located on opposite sides of the edge of the printed circuit board, resulting in an excessively large board area. Summary of the Invention

[0004] The purpose of this application is to provide an embedded printed circuit board layout structure and an electronic device, which aims to solve the problem of excessively large board area in traditional printed circuit board layout structures.

[0005] This application provides an embedded printed circuit board layout structure, including:

[0006] Multiple chips are arranged in an array within the chip area of ​​the first insulating layer;

[0007] The DC terminal of the circuit board is located within the chip area in the DC projection region of the first insulating layer.

[0008] The AC terminals of the circuit board are located within the chip area in the AC projection area of ​​the first insulating layer, and the AC projection area and the DC projection area are arranged alternately.

[0009] In one embodiment, within the chip region, a plurality of the chip arrays are arranged in a first concave region;

[0010] The DC projection area is located between the first concave area and the chip area.

[0011] In one embodiment, the DC terminal of the circuit board includes:

[0012] The first sub-DC terminal, in the first sub-DC projection area of ​​the first insulating layer, is located between the first concave area and the chip area;

[0013] The second sub-DC terminal, in the second sub-DC projection area of ​​the first insulating layer, is located between the first concave area and the chip area;

[0014] The second sub-DC projection area is located close to the first sub-DC projection area, and the second sub-DC projection area and the first sub-DC projection area are arranged side by side with a gap between them.

[0015] In one embodiment, the second sub-DC projection region is disposed between two adjacent chips.

[0016] In one embodiment, within the chip region, a plurality of the chip arrays are arranged in a first convex region;

[0017] The DC projection area is located between the first convex area and the chip area.

[0018] In one embodiment, the DC terminal of the circuit board includes:

[0019] The first sub-DC terminal, in the first sub-DC projection area of ​​the first insulating layer, is located between the first convex area and the chip area;

[0020] The first terminal is located between the first convex region and the chip region in the first projection area of ​​the first insulating layer.

[0021] The second terminal is located in the second projection area of ​​the first insulating layer between the first convex area and the chip area;

[0022] The first sub-DC projection area is located close to the first projection area and the second projection area, and the first sub-DC projection area is arranged side by side with the first projection area and the second projection area at intervals.

[0023] In one embodiment, the first projection area and the second projection area are disposed in the same column or the same row, and at least one of the chips is disposed between the first projection area and the second projection area.

[0024] In one embodiment, within the chip region, a plurality of the chip arrays are arranged in a second concave region;

[0025] The AC projection area is located between the second concave area and the chip area.

[0026] In one embodiment, the AC projection area is located between two adjacent chips.

[0027] In one embodiment, within the chip region, a plurality of the chip arrays are arranged in a second convex region;

[0028] The AC projection area is located between the second convex area and the chip area.

[0029] In one embodiment, the circuit board AC terminals include:

[0030] The first sub-AC terminal forms a first sub-AC projection (231) on the first insulating layer;

[0031] The second sub-AC terminal forms a second sub-AC projection on the projection of the first insulating layer;

[0032] The first sub-AC projection and the second sub-AC projection are arranged in the same column or the same row, and at least one of the chips is arranged between the first sub-AC projection and the second sub-AC projection.

[0033] In one embodiment, the DC terminals and AC terminals of the circuit board are disposed on the first insulating layer.

[0034] In one embodiment, the embedded printed circuit board layout structure further includes:

[0035] The second insulating layer is stacked on top of the first insulating layer;

[0036] The second insulating layer is provided with the DC terminals of the circuit board and / or the AC terminals of the circuit board.

[0037] In one embodiment, the embedded printed circuit board layout structure further includes:

[0038] At least one conductive layer is stacked with the first insulating layer;

[0039] The chips are respectively connected to the DC terminals and AC terminals of the circuit board via metal traces on the conductive layer.

[0040] This application provides an electronic device including the embedded printed circuit board layout structure described in any of the above embodiments.

[0041] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows:

[0042] By dividing the chip area on the first insulating layer, multiple chips can be arranged in an array, shortening the connection lines between them and thus improving the space utilization and wiring efficiency of the printed circuit board. The DC projection area and AC projection area are spaced apart within the chip area, allowing the DC and AC terminals of the circuit board to be placed close to the chips, resulting in a more compact layout. This spacing between the DC and AC projection areas within the chip area maximizes space utilization, minimizes the footprint of the printed circuit board, and reduces the board area.

[0043] The DC and AC projection areas are located within the chip area, which shortens the relative distance between the DC and AC terminals of the circuit board and multiple chips, thereby shortening the connection lines between them and enabling rapid connection through shorter paths. Furthermore, the shortened connection lines between the multiple chips and the DC and AC terminals of the circuit board reduce the board area occupied by these connection lines. Therefore, the embedded printed circuit board layout structure provided in this application reduces the board area from multiple dimensions, solving the problem of excessively large board area in traditional technologies.

[0044] Furthermore, the embedded printed circuit board layout structure provided in this application achieves a highly integrated layout design, which can shorten the connection lines between the DC terminals and AC terminals of the circuit board and multiple chips, thereby reducing the parasitic inductance generated by the connection lines. Moreover, the embedded printed circuit board layout structure provided in this application reduces the board area of ​​the printed circuit board, which can further reduce manufacturing costs and improve production efficiency. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the embedded printed circuit board layout structure in some embodiments provided in this application.

[0046] Figure 2 A concave layout schematic diagram of the embedded printed circuit board layout structure provided in some embodiments of this application.

[0047] Figure 3 The diagram shows the connection structure between the external positive terminal connection structure and the external negative terminal connection structure and the first sub-DC terminal and the second sub-DC terminal, respectively, in some embodiments provided in this application.

[0048] Figure 4 This is a cross-sectional schematic diagram of the front view of the external positive electrode connection structure and the external negative electrode connection structure in some embodiments provided in this application.

[0049] Figure 5 Schematic diagrams of convex and concave layouts provided in some embodiments of this application.

[0050] Figure 6 The diagram shows the structure of the DC terminals and AC terminals of the circuit board in some embodiments provided in this application.

[0051] Figure 7 The diagram shows a convex layout and a schematic diagram of a convex layout in some embodiments provided in this application.

[0052] Figure 8The diagram shows the connection structure between the external positive terminal connection structure and the external negative terminal connection structure and the first sub-DC terminal, the first terminal and the second terminal, respectively, in some embodiments provided in this application.

[0053] Figure 9 Schematic diagrams of convex and concave layouts provided in some embodiments of this application.

[0054] Figure 10 The diagrams provided in this application illustrate concave and convex layouts in some embodiments.

[0055] Figure 11 The diagram shows the structure of the DC terminals and AC terminals of the circuit board in some embodiments provided in this application.

[0056] Figure 12 The diagram shows a convex layout and a schematic diagram of a convex layout in some embodiments provided in this application.

[0057] Figure 13 The diagram shows the connection structure between the external load connection structure and the first sub-AC terminal and the second sub-AC terminal in some embodiments provided in this application.

[0058] Figure 14 A schematic diagram of the structure of the DC terminal and AC terminal of the circuit board in the second insulating layer in some embodiments provided in this application.

[0059] Figure 15 The diagram shows the structure of the conductive layer, the first insulating layer, and the second insulating layer of the embedded printed circuit board layout in some embodiments provided in this application. Detailed Implementation

[0060] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0061] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0062] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0063] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0064] Please see Figure 1 This application provides an embedded printed circuit board layout structure 100. The embedded printed circuit board layout structure 100 includes a plurality of chips 10, a first insulating layer 20, a DC terminal 30 of the circuit board, and an AC terminal 40 of the circuit board.

[0065] Multiple chips 10 are arrayed within the chip region 210 of the first insulating layer 20. The DC terminal 30 of the circuit board is located within the chip region 210 in the DC projection region 220 of the first insulating layer 20. The AC terminal 40 of the circuit board is located within the chip region 210 in the AC projection region 230 of the first insulating layer 20. The AC projection region 230 and the DC projection region 220 are arranged alternately.

[0066] In this embodiment, multiple chips 10 are arranged in an array within the first insulating layer 20. The first insulating layer 20 serves to insulate the multiple chips 10 from each other. The chip region 210 can be understood as the area where the multiple chips 10 are arranged in an array. By dividing the chip region 210 on the first insulating layer 20, multiple chips 10 can be concentrated together in an array, shortening the connection lines between the multiple chips 10, thereby improving the space utilization and wiring efficiency of the printed circuit board.

[0067] The DC terminal 30 on the circuit board can be understood as a DC input terminal, an interface component used to connect an external DC power supply. Through the DC terminal 30, current from external devices (such as an external DC voltage source or external capacitors) can be introduced into the circuitry inside the PCB, providing the necessary power to various electronic components (such as multiple chips 10) within the PCB. The DC projection area 220 of the DC terminal 30 on the first insulating layer 20 can be understood as the area occupied by the DC terminal 30 on the first insulating layer 20. The DC terminal 30 can be disposed on the same layer as the multiple chips 10, or on different layers. In this application, the projection area can be the projection area corresponding to the DC terminal 30 when it is disposed on the first insulating layer 20, or it can be the projection area formed on the first insulating layer 20 when the DC terminal 30 is disposed on other insulating layers.

[0068] The AC projection area 230 of the circuit board AC terminal 40 on the first insulating layer 20 can be understood as the area occupied by the circuit board AC terminal 40 on the first insulating layer 20. The circuit board AC terminal 40 can be disposed on the same layer as multiple chips 10, or it can be disposed on different layers. In this application, the projection area can be the projection area corresponding to the circuit board AC terminal 40 when it is disposed on the first insulating layer 20, or it can be the projection area formed on the first insulating layer 20 when the circuit board AC terminal 40 is disposed on other insulating layers. When the circuit board DC terminal 30 and the circuit board AC terminal 40 are respectively connected to multiple chips 10, the connection is achieved through vias between the various film layers in the printed circuit board.

[0069] The DC projection area 220 and the AC projection area 230 are spaced apart within the chip area 210, allowing the DC terminals 30 and AC terminals 40 of the circuit board to be positioned close to multiple chips 10, resulting in a more compact layout. The spacing between the DC projection area 220 and the AC projection area 230 within the chip area 210 fully utilizes the space within the chip area 210, minimizing the space occupied on the printed circuit board and reducing the surface area of ​​the printed circuit board.

[0070] The DC projection area 220 and AC projection area 230 are located within the chip area 210, which shortens the relative distance between the DC terminals 30 and AC terminals 40 of the circuit board and the multiple chips 10, thereby shortening the connection lines between them and enabling faster connection through shorter paths. Furthermore, the shortened connection lines between the multiple chips 10 and the DC terminals 30 and AC terminals 40 of the circuit board reduce the board area occupied by these connection lines. Therefore, the embedded printed circuit board layout structure 100 provided in this application reduces the board area of ​​the printed circuit board from multiple dimensions, solving the problem of excessively large board area in conventional technologies.

[0071] Furthermore, the embedded printed circuit board layout structure 100 provided in this application achieves a highly integrated layout design, which can shorten the connection lines between the DC terminals 30 and AC terminals 40 of the circuit board and the multiple chips 10, thereby reducing the parasitic inductance generated by the connection lines. Moreover, the embedded printed circuit board layout structure 100 provided in this application reduces the board area of ​​the printed circuit board, which can further reduce manufacturing costs and improve production efficiency.

[0072] Furthermore, the embedded printed circuit board layout structure 100 provided in this application enables multiple chips 10, circuit board DC terminals 30, and circuit board AC terminals 40 to be concentrated and evenly arranged within the chip area 210, thus avoiding the problem of printed circuit board warping caused by unbalanced weight distribution.

[0073] Please see Figure 2 In one embodiment, within chip region 210, a plurality of chips 10 are arrayed to form a first concave region 211. A DC projection region 220 is located between the first concave region 211 and chip region 210.

[0074] In this embodiment, the first concave region 211 can be understood as a concave-shaped region formed by multiple chips 10 disposed within the first insulating layer 20 and arranged in combination. For example... Figure 2 As shown, the multiple chips 10 on the left are arranged in a concave shape. Furthermore, an additional accommodating area is formed between the first concave region 211 and the chip region 210. Within this additional accommodating area, a DC projection region 220 can be arranged.

[0075] Therefore, the DC terminal 30 of the circuit board can be disposed within the DC projection area 220 of the first insulating layer 20. The DC terminal 30 of the circuit board and the plurality of chips 10 are disposed within the same insulating layer. Alternatively, the DC terminal 30 of the circuit board can be disposed within another insulating layer stacked with the first insulating layer 20, and the DC terminal 30 of the circuit board forms a DC projection area 220 on the first insulating layer 20.

[0076] By arranging the DC projection area 220 between the first concave area 211 and the chip area 210, the area outside the space occupied by the chip in the chip area 210 is fully utilized, so that the DC terminals 30 and multiple chips 10 on the circuit board are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0077] Furthermore, the DC projection area 220 is located between the first concave area 211 and the chip area 210, allowing the DC terminal 30 of the circuit board to be positioned close to the multiple chips 10. Since the connection between the DC terminal 30 of the circuit board and the multiple chips 10 needs to be achieved through metal traces on the conductive layer and vias between the conductive layer and the insulating layer, positioning the DC terminal 30 close to the multiple chips 10 can shorten the connection lines between the DC terminal 30 of the circuit board and the multiple chips 10. Consequently, the reduction in connection lines reduces the board area occupied by the connection lines and also reduces the parasitic inductance generated by the connection lines.

[0078] In one embodiment, the circuit board DC terminal 30 includes a first sub-DC terminal 310 and a second sub-DC terminal 320. The first sub-DC terminal 310 is located between the first concave region 211 and the chip region 210 in the first sub-DC projection area 221 of the first insulating layer 20. The second sub-DC terminal 320 is located between the first concave region 211 and the chip region 210 in the second sub-DC projection area 222 of the first insulating layer 20. The second sub-DC projection area 222 is disposed close to the first sub-DC projection area 221. Furthermore, the second sub-DC projection area 222 and the first sub-DC projection area 221 are arranged side-by-side with a gap between them.

[0079] In this embodiment, the DC terminal 30 of the circuit board includes two DC terminals. The first sub-DC terminal 310 can be the positive terminal of the circuit board, and the second sub-DC terminal 320 can be the negative terminal of the circuit board. Alternatively, the first sub-DC terminal 310 can be the negative terminal of the circuit board, and the second sub-DC terminal 320 can be the positive terminal of the circuit board. The first sub-DC terminal 310 and the second sub-DC terminal 320 are respectively used to connect to the positive and negative terminals (or both ends) of external devices (such as external DC voltage sources or external capacitors).

[0080] The first sub-DC projection area 221 is located between the first concave area 211 and the chip area 210, making full use of the area outside the space occupied by the chip in the chip area 210, so that the first sub-DC terminal 310 and multiple chips 10 are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0081] The second sub-DC projection area 222 is located between the first concave area 211 and the chip area 210. It makes full use of the area in the chip area 210 other than the space occupied by the chip, so that the second sub-DC terminal 320 and multiple chips 10 are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0082] The second sub-DC projection area 222 is close to and spaced apart from the first sub-DC projection area 221, which allows the second sub-DC terminal 320 to be close to and spaced apart from the first sub-DC terminal 310, making the layout of the entire printed circuit board more compact and thus reducing the board area.

[0083] Please see Figure 3 The first sub-DC terminal 310 is connected to the positive terminal of an external device, forming an external positive connection structure 710. The second sub-DC terminal 320 is connected to the negative terminal of the external device, forming an external negative connection structure 720. The external positive connection structure 710 flows out through the external negative connection structure 720 after passing through the printed circuit board, thus forming an external connection loop between the external positive connection structure 710 and the external negative connection structure 720. The second sub-DC projection area 222 is positioned close to the first sub-DC projection area 221, allowing the second sub-DC terminal 320 to be positioned close to the first sub-DC terminal 310, thereby bringing the positive and negative terminals of the circuit board closer together. When the second sub-DC terminal 320 is close to the first sub-DC terminal 310, the external connection loop formed between the two DC terminals is shortened, thereby reducing the parasitic inductance formed by the external connection loop.

[0084] The second sub-DC projection area 222 is arranged close to and spaced apart from the first sub-DC projection area 221, allowing the second sub-DC terminal 320 to be arranged close to and spaced apart from the first sub-DC terminal 310. This creates a stacked structure between the external negative terminal connection structure 720 formed when the second sub-DC terminal 320 is connected to the negative terminal of an external device and the external positive terminal connection structure 710 formed when the first sub-DC terminal 310 is connected to the positive terminal of an external device. This stacked structure can be understood as having overlapping portions between the external negative terminal connection structure 720 and the external positive terminal connection structure 710. For example... Figure 4 As shown, since the current flows in opposite directions between the external negative terminal connection structure 720 and the external positive terminal connection structure 710, they will form magnetic fields in opposite directions that superimpose and cancel each other out, which will reduce the induced electromotive force caused by the change in magnetic field and reduce the parasitic inductance formed by the external connection circuit.

[0085] Furthermore, the first sub-DC terminal 310 is located in the first sub-DC projection area 221 of the first insulating layer 20 between the first concave area 211 and the chip area 210, and the second sub-DC terminal 320 is located in the second sub-DC projection area 222 of the first insulating layer 20 between the first concave area 211 and the chip area 210. This allows for full utilization of the chip area 210 and avoids the problem of printed circuit board warping caused by excess space in the chip area 210.

[0086] In one embodiment, when the first sub-DC terminal 310 is connected to the external positive terminal connection structure 710, the electrical connection is made by soldering. When the second sub-DC terminal 320 is connected to the external negative terminal connection structure 720, the electrical connection is made by soldering. Furthermore, the external positive terminal connection structure 710 and the external negative terminal connection structure 720 are insulated from each other.

[0087] In one embodiment, the second sub-DC projection region 222 is disposed between two adjacent chips 10.

[0088] In this embodiment, a second sub-DC projection area 222 is provided between two adjacent chips 10 within the first concave region 211, so that the two adjacent chips 10 serve as the concave positions of the U-shaped layout structure. Furthermore, the second sub-DC projection area 222 can fill the chip area outside the first concave region 211, making the distribution of various devices in the printed circuit board more concentrated and uniform, reducing the board area, and improving the space utilization of the printed circuit board.

[0089] In one embodiment, when the second sub-DC terminal 320 and multiple chips 10 are located in the same first insulating layer 20, the second sub-DC terminal 320 is spaced apart from two adjacent chips 10.

[0090] In one embodiment, when the second sub-DC terminal 320 and the plurality of chips 10 are located in different insulating layers, the second sub-DC projection area 222 of the second sub-DC terminal 320 in the first insulating layer 20 falls exactly between two adjacent chips 10.

[0091] Please see Figure 5 In one embodiment, within chip region 210, a plurality of chips 10 are arrayed to form a first convex region 212. A DC projection region 220 is located between the first convex region 212 and chip region 210.

[0092] In this embodiment, the first convex region 212 can be understood as a convex-shaped region formed by multiple chips 10 disposed within the first insulating layer 20 and arranged in combination. For example... Figure 5 As shown, the multiple chips 10 on the left are arranged in a convex shape. Furthermore, an additional accommodating area is formed between the first convex region 212 and the chip region 210. Within this additional accommodating area, a DC projection region 220 can be arranged.

[0093] Therefore, the DC terminal 30 of the circuit board can be disposed within the DC projection area 220 of the first insulating layer 20. By arranging the DC projection area 220 between the first convex area 212 and the chip area 210, the area outside the space occupied by the chip in the chip area 210 is fully utilized, so that the DC terminal 30 of the circuit board and multiple chips 10 are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0094] Furthermore, the DC projection area 220 is located between the first convex area 212 and the chip area 210, which allows the DC terminal 30 of the circuit board to be positioned close to the multiple chips 10, thereby shortening the connection lines between the DC terminal 30 of the circuit board and the multiple chips 10. Consequently, the reduction in connection lines reduces the board area occupied by the connection lines and also reduces the parasitic inductance generated by the connection lines.

[0095] Please see Figure 6 In one embodiment, the DC terminal 30 of the circuit board includes a first sub-DC terminal 310, a first terminal 321, and a second terminal 322. The first sub-DC terminal 310 is located between the first convex region 212 and the chip region 210 in the first sub-DC projection area 221 of the first insulating layer 20. The first terminal 321 is located between the first convex region 212 and the chip region 210 in the first projection area 223 of the first insulating layer 20. The second terminal 322 is located between the first convex region 212 and the chip region 210 in the second projection area 224 of the first insulating layer 20.

[0096] Please see Figure 7 The first sub-DC projection area 221 is positioned close to the first projection area 223 and the second projection area 224. Furthermore, the first sub-DC projection area 221 is positioned side-by-side with the first projection area 223 and the second projection area 224 at intervals.

[0097] In this embodiment, the DC terminal 30 of the circuit board includes two DC terminals, with the first terminal 321 and the second terminal 322 serving as different portions of a single DC terminal. The first sub-DC terminal 310 can be the positive terminal of the circuit board, and the first terminal 321 and the second terminal 322 together serve as the negative terminal. Alternatively, the first sub-DC terminal 310 can be the negative terminal of the circuit board, and the first terminal 321 and the second terminal 322 together serve as the positive terminal. The first sub-DC terminal 310, the first terminal 321, and the second terminal 322 are respectively used to connect to the positive and negative terminals (or both ends) of external devices (such as an external DC voltage source or an external capacitor).

[0098] The first sub-DC projection area 221 is located between the first convex area 212 and the chip area 210, making full use of the area outside the space occupied by the chip in the chip area 210. This allows the first sub-DC terminal 310 and multiple chips 10 to be arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0099] The second projection area 224 and the first projection area 223 are spaced apart between the first convex area 212 and the chip area 210. This makes full use of the area in the chip area 210 other than the space occupied by the chip, so that the first terminal 321, the second terminal 322 and multiple chips 10 are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0100] The first sub-DC projection area 221 is close to and spaced apart from the first projection area 223 and the second projection area 224, respectively. This allows the first sub-DC terminal 310 to be close to and spaced apart from the first terminal 321 and the second terminal 322, respectively. This makes the layout of the entire printed circuit board more compact and reduces the area of ​​the printed circuit board.

[0101] Please see Figure 8 The first DC terminal 310 is connected to the positive terminal of an external device, forming an external positive terminal connection structure 710. The first terminal 321 is connected to the negative terminal of an external device, and the second terminal 322 is connected to the negative terminal of an external device, forming an external negative terminal connection structure 720.

[0102] The external positive connection structure 710 flows out from the external negative connection structure 720 after passing through the printed circuit board, thus forming an external connection loop between the external positive connection structure 710 and the external negative connection structure 720. The first sub-DC projection area 221 is positioned close to the first projection area 223 and the second projection area 224, respectively, so that the first sub-DC terminal 310 is positioned close to the first terminal 321 and the second terminal 322, respectively, thereby bringing the positive terminal and the negative terminal of the circuit board closer together. When the first sub-DC terminal 310 is close to the first terminal 321 and the second terminal 322, the external connection loop formed between the DC terminals can be shortened, thereby reducing the parasitic inductance formed by the external connection loop.

[0103] The first sub-DC projection area 221 is arranged close to and spaced apart from the first projection area 223 and the second projection area 224, respectively, so that the first sub-DC terminal 310 is arranged close to and spaced apart from the first terminal 321 and the second terminal 322, respectively. Thus, as... Figure 4As shown, a stacked structure is formed between the external negative terminal connection structure 720 and the external positive terminal connection structure 710, which will generate magnetic fields in opposite directions that superimpose and cancel each other out, reducing the parasitic inductance formed by the external connection circuit.

[0104] Furthermore, the first terminal 321 and the second terminal 322 are arranged separately, which allows the corresponding external negative terminal connection structure 720 and external positive terminal connection structure 710 to cover more of the stacked area, thereby reducing parasitic inductance.

[0105] Furthermore, the first sub-DC terminal 310 is located between the first convex region 212 and the chip region 210 in the first sub-DC projection area 221 of the first insulating layer 20, and the first terminal 321 is located between the first convex region 212 and the chip region 210 in the first projection area 223 of the first insulating layer 20, and the second terminal 322 is located between the first convex region 212 and the chip region 210 in the second projection area 224 of the first insulating layer 20. This allows for full utilization of the chip region 210 and avoids the problem of printed circuit board warping caused by excess space in the chip region 210.

[0106] In one embodiment, when the first terminal 321 and the second terminal 322 are connected to the external negative electrode connection structure 720, the electrical connection is made by soldering. Due to the layout of the first terminal 321 and the second terminal 322, the external negative electrode connection structure 720 can be configured as a U-shaped structure. Figure 3 As shown, both the external negative electrode connection structure 720 and the external positive electrode connection structure 710 can be configured as I-shaped structures.

[0107] In one embodiment, the first projection area 223 and the second projection area 224 are arranged in the same column (e.g., Figure 7 (as shown) or on the same line (such as) Figure 9 As shown), at least one chip 10 is disposed between the first projection area 223 and the second projection area 224.

[0108] In this embodiment, at least one chip 10 is disposed within the first convex region 212, between the first projection region 223 and the second projection region 224, such that the at least one chip 10 between the first projection region 223 and the second projection region 224 forms a convex portion of the U-shaped layout structure. Furthermore, the first projection region 223 and the second projection region 224 can fill the chip area outside the first convex region 212, making the distribution of various components on the printed circuit board more concentrated and uniform, reducing the board area, and improving the space utilization of the printed circuit board.

[0109] In one embodiment, when the first terminal 321 and the second terminal 322 are located in the same first insulating layer 20 as a plurality of chips 10, the first terminal 321 and the second terminal 322 are spaced apart from at least one chip 10 between them.

[0110] In one embodiment, when the first terminal 321 and the second terminal 322 are located in different insulating layers from the plurality of chips 10, the first terminal 321 and the second terminal 322 fall exactly on both sides of at least one chip 10 in the first projection area 223 and the second projection area 224 of the first insulating layer 20.

[0111] Please see Figure 9 In one embodiment, within chip region 210, a plurality of chips 10 are arrayed to form a second concave region 213. An AC projection region 230 is located between the second concave region 213 and chip region 210.

[0112] In this embodiment, the second concave region 213 can be understood as a concave region formed by multiple chips 10 disposed within the first insulating layer 20 and arranged in a concave shape. For example... Figure 9 As shown, the multiple chips 10 on the right are arranged in a concave shape. Furthermore, an additional accommodating area is formed between the second concave region 213 and the chip region 210. An AC projection region 230 can be arranged within this additional accommodating area.

[0113] Therefore, the AC terminal 40 of the circuit board can be disposed within the AC projection area 230 of the first insulating layer 20. The AC terminal 40 of the circuit board and the plurality of chips 10 are disposed within the same insulating layer. Alternatively, the AC terminal 40 of the circuit board can be disposed within another insulating layer that is stacked with the first insulating layer 20, and the AC terminal 40 of the circuit board forms the AC projection area 230 on the first insulating layer 20.

[0114] By arranging the AC projection area 230 between the second concave area 213 and the chip area 210, the area outside the space occupied by the chip in the chip area 210 is fully utilized, so that the AC terminals 40 and multiple chips 10 on the circuit board are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0115] Furthermore, the AC projection area 230 is located between the second concave area 213 and the chip area 210, allowing the AC terminal 40 of the circuit board to be positioned close to the multiple chips 10. Since the connection between the AC terminal 40 of the circuit board and the multiple chips 10 needs to be achieved through metal traces on the conductive layer and vias between the conductive layer and the insulating layer, positioning the AC terminal 40 close to the multiple chips 10 can shorten the connection lines between the AC terminal 40 of the circuit board and the multiple chips 10. Consequently, the reduction in connection lines reduces the board area occupied by the connection lines and also reduces the parasitic inductance generated by the connection lines.

[0116] In one embodiment, the AC projection area 230 is disposed between two adjacent chips 10.

[0117] In this embodiment, an AC projection area 230 is provided between two adjacent chips 10 within the second concave region 213, so that the two adjacent chips 10 serve as the concave positions of the U-shaped layout structure. Furthermore, the AC projection area 230 can fill the chip area outside the second concave region 213, making the distribution of various devices in the printed circuit board more concentrated and uniform, reducing the board area, and improving the space utilization of the printed circuit board.

[0118] Furthermore, the AC projection area 230 is positioned between two adjacent chips 10, which allows for full utilization of the chip area 210 and avoids the problem of printed circuit board warping caused by excess space in the chip area 210.

[0119] Please see Figure 10 In one embodiment, within chip region 210, a plurality of chips 10 are arrayed to form a second convex region 214. An AC projection region 230 is located between the second convex region 214 and chip region 210.

[0120] In this embodiment, the second convex region 214 can be understood as a convex-shaped region formed by multiple chips 10 disposed within the first insulating layer 20 and arranged in combination. For example... Figure 10 As shown, the multiple chips 10 on the right are arranged in a convex shape. Furthermore, an additional accommodating area is formed between the second convex region 214 and the chip region 210. An AC projection region 230 can be arranged within this additional accommodating area.

[0121] Therefore, the AC terminal 40 of the circuit board can be disposed within the AC projection area 230 of the first insulating layer 20. By arranging the AC projection area 230 between the second convex area 214 and the chip area 210, the area outside the space occupied by the chip in the chip area 210 is fully utilized, so that the AC terminal 40 and multiple chips 10 of the circuit board are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0122] Furthermore, the AC projection area 230 is located between the second convex area 214 and the chip area 210, which allows the AC terminal 40 of the circuit board to be positioned close to the multiple chips 10, thereby shortening the connection lines between the AC terminal 40 of the circuit board and the multiple chips 10. Consequently, the reduction in connection lines reduces the board area occupied by the connection lines and also reduces the parasitic inductance generated by the connection lines.

[0123] Please see Figure 10 and Figure 11 In one embodiment, the circuit board AC terminal 40 includes a first sub-AC terminal 410 and a second sub-AC terminal 420. The first sub-AC terminal 410 projects onto the first insulating layer 20 to form a first sub-AC projection 231. The second sub-AC terminal 420 projects onto the first insulating layer 20 to form a second sub-AC projection 232. The first sub-AC projection 231 and the second sub-AC projection 232 are arranged in the same column (e.g., ...). Figure 10 (as shown) or on the same line (such as) Figure 12 (As shown). At least one chip 10 is disposed between the first sub-AC projection 231 and the second sub-AC projection 232.

[0124] In this embodiment, the first sub-AC terminal 410 and the second sub-AC terminal 420 together serve as the AC terminal 40 of the circuit board. Alternatively, the first sub-AC terminal 410 and the second sub-AC terminal 420 can be understood as two different parts of the AC terminal 40 of the circuit board, connected to external AC loads (such as motors in vehicle inverter systems or other loads requiring AC signals). The AC terminal 40 of the circuit board serves as the output terminal of the printed circuit board.

[0125] Within the second convex region 214, at least one chip 10 is disposed between the first sub-AC projection 231 and the second sub-AC projection 232, such that the at least one chip 10 between the first sub-AC projection 231 and the second sub-AC projection 232 forms a convex portion of a U-shaped layout structure. Furthermore, the first sub-AC projection 231 and the second sub-AC projection 232 can fill the chip area outside the second convex region 214, resulting in a more concentrated and uniform distribution of components on the printed circuit board, reducing the board area and improving the space utilization of the printed circuit board.

[0126] In one embodiment, when the first sub-AC terminal 410 and the second sub-AC terminal 420 are located in the same first insulating layer 20 as a plurality of chips 10, the first sub-AC terminal 410 and the second sub-AC terminal 420 are spaced apart from at least one chip 10 between them.

[0127] In one embodiment, when the first sub-AC terminal 410 and the second sub-AC terminal 420 are located in different insulating layers with the plurality of chips 10, the first sub-AC projection 231 and the second sub-AC projection 232 of the first sub-AC terminal 410 and the second sub-AC projection 232 of the first insulating layer 20 fall exactly on both sides of at least one chip 10.

[0128] Furthermore, at least one chip 10 is disposed between the first sub-AC projection 231 and the second sub-AC projection 232, which can make full use of the chip area 210 and avoid the problem of printed circuit board warping caused by excess space in the chip area 210.

[0129] Please see Figure 13 In one embodiment, both the first sub-AC terminal 410 and the second sub-AC terminal 420 are connected to an external load, forming an external load connection structure 730. The first sub-AC terminal 410 and the second sub-AC terminal 420 are electrically connected to the external load connection structure 730 by soldering. Due to the layout of the first sub-AC terminal 410 and the second sub-AC terminal 420, the external load connection structure 730 can be configured as a U-shaped structure. Alternatively, as... Figure 6 The layout of the AC terminal 40 on the circuit board shown can also be configured as an I-shaped structure for the external load connection structure 730.

[0130] In one embodiment, the DC terminal 30 and the AC terminal 40 of the circuit board are disposed on the first insulating layer 20.

[0131] In this embodiment, the DC terminal 30 and AC terminal 40 of the circuit board can be disposed in the same insulating layer, and together with multiple chips 10, are disposed within the first insulating layer 20. When the DC terminal 30 and AC terminal 40 of the circuit board are disposed in the first insulating layer 20, the space within the first insulating layer 20 can be fully utilized, reducing the complexity and difficulty of wiring in the printed circuit board. Furthermore, when the DC terminal 30 and AC terminal 40 of the circuit board are disposed in the first insulating layer 20, the external connection lines are more compact, which is beneficial for centralized management and allocation.

[0132] In one embodiment, the DC terminal 30 and AC terminal 40 of the circuit board are disposed at the edge of the first insulating layer 20, which can shorten the length of the connection structure (which can also be understood as the length of the connection line) when the DC terminal 30 and AC terminal 40 of the circuit board are connected to external devices, thereby reducing the parasitic inductance of the external connection structure.

[0133] Please see Figure 14 In one embodiment, the embedded printed circuit board layout structure 100 further includes:

[0134] The second insulating layer 50 is stacked with the first insulating layer 20;

[0135] The second insulating layer 50 is provided with a circuit board DC terminal 30 and / or a circuit board AC terminal 40.

[0136] In this embodiment, the second insulating layer 50 is provided with a circuit board DC terminal 30 and / or a circuit board AC terminal 40. This can be understood as the second insulating layer 50 being provided with a circuit board DC terminal 30, or the second insulating layer 50 being provided with a circuit board AC terminal 40, or the second insulating layer 50 being provided with both a circuit board DC terminal 30 and a circuit board AC terminal 40.

[0137] The DC terminal 30 and AC terminal 40 of the circuit board can be set in the same second insulating layer 50 or in different insulating layers, depending on the actual application scenario.

[0138] In one embodiment, the DC terminal 30 of the circuit board is disposed on the first insulating layer 20, and the AC terminal 40 of the circuit board is disposed on the second insulating layer 50. Alternatively, the AC terminal 40 of the circuit board is disposed on the first insulating layer 20, and the DC terminal 30 of the circuit board is disposed on the second insulating layer 50.

[0139] In one embodiment, the embedded printed circuit board layout structure 100 further includes a third insulating layer, with the circuit board DC terminal 30 disposed on the third insulating layer and the circuit board AC terminal 40 disposed on the second insulating layer 50. Alternatively, the circuit board AC terminal 40 is disposed on the third insulating layer and the circuit board DC terminal 30 is disposed on the second insulating layer 50.

[0140] By placing the DC terminal 30, AC terminal 40, and chip 10 on different insulating layers, the risk of crosstalk between the DC terminal 30, AC terminal 40, and chip 10 can be reduced, thereby improving safety.

[0141] Please see Figure 15 In one embodiment, the embedded printed circuit board layout structure 100 further includes:

[0142] At least one conductive layer 60 is stacked with the first insulating layer 20;

[0143] Multiple chips 10 are connected to the DC terminal 30 and AC terminal 40 of the circuit board via metal traces on the conductive layer 60.

[0144] In this embodiment, the DC terminal 30 and AC terminal 40 of the circuit board can be connected to multiple chips 10 through the metal traces on the conductive layer 60. Furthermore, by creating vias and setting metal traces in the stacked structure such as the conductive layer 60, the first insulating layer 20, and the second insulating layer 50, circuit connections between different stacks can be achieved.

[0145] Furthermore, by using at least one conductive layer 60, heat dissipation can be achieved for multiple chips 10, ensuring that multiple chips 10 can function normally.

[0146] In one embodiment, the DC terminal 30, AC terminal 40, and multiple chips 10 of the circuit board are disposed on the first insulating layer 20. Conductive layers 60 are disposed on both the upper and lower surfaces of the first insulating layer 20. The two conductive layers 60 on the upper and lower surfaces dissipate heat from the DC terminal 30, AC terminal 40, and multiple chips 10 of the circuit board, and can better transfer heat to the heat sink, thereby achieving heat dissipation of the printed circuit board and ensuring that the multiple chips 10 can work normally.

[0147] This application provides an electronic device, including the embedded printed circuit board layout structure 100 in any of the above embodiments.

[0148] In this embodiment, the electronic device can be a wireless charger, a switching power supply, a motor driver, an inverter, and an audio power amplifier, etc.

[0149] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units, regions, and modules is merely an example. In practical applications, the above functions can be assigned to different functional units, regions, and modules as needed. Furthermore, the specific names used in the above embodiments are merely for easy distinction and are not intended to limit the scope of protection of this application.

[0150] In the above embodiments, the descriptions of each embodiment have different focuses. Parts not described in detail in a particular embodiment can be found in the relevant descriptions of other embodiments. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0151] The division of modules or units is merely a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0152] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An embedded printed circuit board layout structure, characterized in that, include: Multiple chips are arranged in an array within the chip area of ​​the first insulating layer; The DC terminal of the circuit board is located within the chip area in the DC projection region of the first insulating layer. The AC terminals of the circuit board are located within the chip area in the first insulating layer, and the AC projection area and the DC projection area are arranged at intervals. Within the chip region, multiple chip arrays are arranged to form a first concave region; the DC projection region is located between the first concave region and the chip region. The DC terminals of the circuit board include: The first sub-DC terminal, in the first sub-DC projection area of ​​the first insulating layer, is located between the first concave area and the chip area; The second sub-DC terminal, in the second sub-DC projection area of ​​the first insulating layer, is located between the first concave area and the chip area; The second sub-DC projection area is located close to the first sub-DC projection area, and the second sub-DC projection area and the first sub-DC projection area are arranged side by side with a gap between them; Within the chip region, multiple chip arrays are arranged in a second concave region, and the AC projection region is located between the second concave region and the chip region; or, within the chip region, multiple chip arrays are arranged in a second convex region, and the AC projection region is located between the second convex region and the chip region.

2. The embedded printed circuit board layout structure as described in claim 1, characterized in that, The second sub-DC projection area is located between two adjacent chips.

3. An embedded printed circuit board layout structure, characterized in that, include: Multiple chips are arranged in an array within the chip area of ​​the first insulating layer; The DC terminal of the circuit board is located within the chip area in the DC projection region of the first insulating layer. The AC terminals of the circuit board are located within the chip area in the first insulating layer, and the AC projection area and the DC projection area are arranged at intervals. Within the chip region, multiple chip arrays are arranged to form a first convex region; the DC projection region is located between the first convex region and the chip region. The DC terminals of the circuit board include: The first sub-DC terminal, in the first sub-DC projection area of ​​the first insulating layer, is located between the first convex area and the chip area; The first terminal is located between the first convex region and the chip region in the first projection area of ​​the first insulating layer. The second terminal is located in the second projection area of ​​the first insulating layer between the first convex area and the chip area; The first sub-DC projection area is located close to the first projection area and the second projection area, and the first sub-DC projection area is arranged side by side with the first projection area and the second projection area at intervals.

4. The embedded printed circuit board layout structure as described in claim 3, characterized in that, The first projection area and the second projection area are arranged in the same column or the same row, and at least one of the chips is arranged between the first projection area and the second projection area.

5. An electronic device, characterized in that, Includes the embedded printed circuit board layout structure as described in any one of claims 1 to 4.

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