Printed circuit boards including impedance-controlled traces for significantly low impedance applications and methods for fabricating same

Abstract

PCBs having ultra-wide impedance-controlled traces (e.g., 200-1200 mils wide), formed on one or more conductor layers of a multilayer PCB stack-up, to implement PCB transmission lines having a significantly low characteristic impedance (e.g., less than or equal to approximately 10 ohms, 5 ohms, 2 ohms) over at least a portion of the radio frequency (RF) signal range. In some examples, such PCBs are fabricated using conventional dielectric materials and using one (1) ounce per square foot copper for conductive layers, whereby the PCB transmission line handles peak voltages up to 600V and peak currents up to 300A. Such PCB transmission lines may be incorporated into RF power amplifiers (e.g., for cellular base stations), electric vehicles (inverters / motors), medical equipment (MRI equipment), industrial automation and robotics, pulsed power generators for various pulsed power applications, and renewable energy systems (e.g., involving catalytic reactions and high-frequency / high-power phonon stimulation).

Description

Attorney Docket No.: BRLN-008W001PRIM ED CIRCUIT BOARDS INCLUDING IMPEDANCE-CONTROLLED TRACES FOR SIGNIFICANTLY LOW IMPEDANCE APPLICATIONS AND METHODS FORFABRICATING SAMECROSS-REFERENCE TO RELATED APPLICATION(0001] The present application claims a priority benefit to U.S. Provisional Application Serial No. 63 / 730,433, filed December 10, 2024, entitled “Printed Circuit Boards Including Impedance-Controlled Traces for Significantly Low Impedance Applications and Methods for Fabricating Same.” The entirety of the aforementioned provisional application is hereby incorporated herein by reference.BACKGROUND

[0002] A Printed Circuit Board (PCB) is a flat, rigid board used to mechanically support and electrically connect electronic components. The base material or substrate used in conventional PCBs (e.g., fiberglass) provides mechanical strength and electrical insulation for the PCB (i.e., the substrate is a dielectric). The electrical connections on PCBs are made using conductive pathways etched or printed from electrically conducting layers (e.g., copper sheets) laminated onto the electrically insulating substrate. PCBs can be single-sided (one conductive layer on a substrate), double-sided (top and bottom conductive layers on a middle substrate), or multilayered (multiple conductive layers respectively separated by insulating material). Electrical components such as resistors, capacitors, inductors, diodes, transistors, transformers and microchips (integrated circuits) are mounted on the PCB and interconnected by the pathways formed in the conductive layer(s). A soldermask typically is applied over the outermost (e.g., top and bottom) conductive layers as a protective layer to prevent short circuits and corrosion. A silkscreen often may be employed for labeling components on the PCB and / or providing assembly instructions for the PCB.

[0003] In connection with PCB design and fabrication, a conventional design process includes creation of an electrical circuit diagram or schematic coupled with a PCB layout design of how the electrical circuit will be physically implemented on the PCB (e.g., where respective components of the circuit will be placed and where conductive pathways interconnecting respective components will be formed in one or more copper layers of the PCB). PCB layout design often is facilitated by conventional software tools (e.g, KiCAD, Eagle, or Altium Designer) according to specified “design rules” (discussed further below).Attorney Docket No.: BRLN-008W001

[0004] Regarding the materials conventionally employed in PCBs, copper is employed ubiquitously as the conductive material to interconnect respective circuit components on a PCB and provide input and output electrical connections to the PCB. By way of example, a 1 -ounce copper thickness (~35pm) often is employed for many conventional PCB boards. The substrate (also referred to as “base material”) of the PCB may be fiberglass-reinforced epoxy (e.g., FR4), polyimide, or in some instances a flexible material. FR4 is a common and versatile substrate that serves as the non-conductive base material of many PCBs (single-sided, double-sided, and multilayer PCBs), providing strong and lightweight mechanical support and insulation for the conductive copper layer(s). FR4 is a glass-reinforced epoxy laminate made of woven fiberglass fabric (that provides strength and rigidity) and an epoxy resin binder (that provides insulation and flame retardancy).

[0005] Regarding the thermal properties of FR4, “standard FR4,” used for general -purpose circuit applications such as consumer electronics, has a glass transition temperature (Tg) of approximately 130°C; thus, it has relatively good thermal stability for many electronics applications. One FR4 “variant” includes higher glass transition temperature FR4 or “high-Tg FR4,” which is conventionally used in applications requiring higher operating temperatures, such as industrial or automotive electronics. Regarding the electrically insulating properties of FR4, the dielectric constant of FR4 typically ranges from 4.2 to 4.8 at 1 GHz (or even as low as 3.7 for some FR4 variants), which may be relevant to impedance control in circuits involving appreciably high-speed signals, discussed further below. Another FR4 variant with a lower dielectric loss for improved signal integrity in high-speed designs is referred to as “low-loss FR4.” In some very high-frequency RF or microwave applications, specialized base materials other than FR4 or FR4 variants may be employed for a PCB (e.g., Rogers laminates or hydrocarbon ceramics, PTFE-based materials such as Taconic or Arion, Isola).

[0006] Conventional manufacturing steps for PCBs involve “laminating,” where one or more conductive (e.g., copper) sheets are bonded to the substrate, “photolithography,” where a lightsensitive photoresist is applied to the copper sheet and exposed to UV light through a mask to define conductive pathways constituting the circuit pattern, and “etching” to remove excess copper using chemical etchants, leaving behind the desired conductive pathways. “Drilling” is typically employed to create holes for mounting components and forming vias (connections between conductive layers), after which “plating” is employed to deposit conductive material inside drilled holes to create interconnections. As noted above, a soldermask may be applied to outer layers and cured to provide protection for the PCB, after which silkscreen printing isAttorney Docket No.: BRLN-008W001 used to add labels and markings. To facilitate soldering of components to the PCB, a surface finish such as Electroless Nickel Immersion Gold (ENIG) or Hot Air Solder Leveling (HASL) may be employed. PCB assembly typically involves attaching circuit components to the PCB using Surface-Mount Technology (SMT) or Through-Hole Technology (THT) and using reflow ovens or wave soldering machines to secure components. Assembled PCBs are then electrically tested for short circuits and continuity, and visually inspected to verify the quality of conductive pathways, component placement, and integrity of solder joints.(0007] For multilayer PCBs, additional materials are required to create a “stack-up” of multiple electrically conductive (e.g., copper) layers and intervening dielectric materials (e.g., FR4). Regarding the respective layers in a multilayer PCB stack-up, “core” and “prepreg” are two significant constituents used in the conventional construction of multilayer PCBs, but they serve different purposes and have distinct characteristics.(0008] In particular, a core is a pre-manufactured rigid layer of PCB material that includes a dielectric substrate (typically FR4) and a thin layer of copper foil laminated on each side of the dielectric (i.e., the dielectric is sandwiched between two copper foil laminates). The core acts as the structural base for the multilayer PCB by providing mechanical strength and serves as the foundation for the initial conductive layers. A core typically is used as an internal layer in multilayer PCBs and, by way of example, generally has a thickness in a range of from 0.2 mm to 1.6 mm (8 mils to 63 mils), which is often design-dependent. In contrast, “prepreg” (also sometimes referred to as “pre-impregnated") is a sheet of fiberglass fabric impregnated with partially-cured epoxy resin (i.e., prepreg is essentially uncured FR4). The semi-cured state of prepreg allows is to be flexible and sticky at room temperature. Prepreg is hardened during the lamination process under heat and pressure and acts as an adhesive to bond one or more core layers and additional copper layers together to form a unified PCB, thereby helping to define the layer stack-up in multilayer PCBs. Because prepreg is essentially uncured FR4, it also provides electrical insulation between conductive layers. Prepreg conventionally is available in varying thicknesses and resin contents to allow customization of a PCB’s dielectric spacing in a given PCB design’s stack-up.(0009] To provide examples of some conventional multilayer PCBs, FIG. 1 illustrates a typical 4-layer PCB stack-up that includes two inner copper layers formed using one core, and two additional “outer” copper layers (one additional copper layer on either side of the core). Each outer copper layer is bonded to the core via a corresponding prepeg layer (one prepeg layer on the top inner copper layer, another prepeg layer on the bottom inner copper layer). The Stack-Attorney Docket No.: BRLN-008W001 up shown in FIG. 1 also includes a top soldermask covering the top outer copper layer and a bottom soldermask covering the bottom outer copper layer. Respective layer designations and example thicknesses (in mils) are shown to the left of the stack-up in FIG. 1.

[0010] Similarly, FIG. 2 illustrates an example of a conventional 6-layer PCB stack-up. In the 6-layer PCB stack-up shown in FIG. 2, two cores are employed which respectively provide inner copper layers (e.g., layers 2 / 3 and 4 / 5), and multiple prepreg sheets are also employed to attach outer copper layers (e.g., copper foil on layers 1 and 6) during lamination. Heat and pressure are used to cure the prepreg sheets, thereby bonding the respective layers into a rigid, unified structure. Like FIG. 1, the 6-layer stack-up shown in FIG. 2 also includes a top soldermask covering the top outer copper layer and a bottom soldermask covering the bottom outer copper layer. Respective layer designations and example thicknesses (in mils) are shown to the left of the stack-up in FIG. 2.

[0011] Some noteworthy design considerations for the fabrication of conventional PCBs include selecting appropriate dimensions and spacing of conductive pathways on a given copper layer (e.g., to ensure adequate current-carrying capacity and prevent short circuits), as well as designing a particular stack-up for a multilayer PCB (e.g., number of layers, thickness of respective layers and spacing between layers, dielectric constants of respective core and prepreg constituents) that takes into consideration the types of signals (e.g., voltage, current, frequency) that will propagate in respective layers and the electromagnetic compatibility of the stack-up with such signals. Other salient design considerations for the fabrication of PCBs may include thermal management (e.g., using thermal vias and / or significant amounts of copper on one or more layers for heat dissipation) and impedance matching of signal lines to and / or from the PCB for compatibility with particular electric circuit applications (often required for high-speed signal integrity).

[0012] Different types of conductive pathways are implemented on a given copper layer of a PCB to carry electric signals and power between components. For example, a “trace” conventionally refers to a relatively narrow line of copper having a specified width and length that interconnects two or more electrical components on the PCB to carry electrical signals or power. More specifically, a “signal trace” is used to carry signals to facilitate communication between components, while a “power trace” or a “ground trace” may be a relatively wider line that can handle higher currents to provide power to a given component. Lower-current signal traces generally have a width in a given copper layer of from about 3-10 mils (0.0762-0.25 mm), whereas higher-current power traces generally have a width of from about 20-200 milsAttorney Docket No.: BRLN-008W001(0.5-5 mm) depending on current requirements. A typical spacing between traces is typically on the order of 3-10 mils (0.0762-0.25 mm) for most designs, although high-voltage circuit designs may require a trace spacing of 10-20 mils (0.25-0.5 mm) or more. A standard copper thickness of 1 oz / ft2(35 pm or 1.4 mils) is typically employed for traces, although alternative options include 0.5 oz / ft2, 2 oz / ft2, or 3 oz / ft2for increased current capacity or other design considerations.[00.13] An “impedance-controlled trace” is a signal trace designed with precise dimensions and particular material properties for the dielectric materials of the PCB to ensure signal integrity, particularly in high-speed or RF circuits. The width of an impedance-controlled trace is determined in part by the specific impedance requirements of the signaling application but is typically on the order of 5-20 mils (0.13-0.5 mm). Impedance-controlled traces for differential pairs may have a trace spacing defined by coupling requirements, typically on the order of 3- 20 mils (0.076-0.5 mm) between the traces of the pair.

[0014] A “plane” is a relatively larger continuous area of copper that serves to distribute ground or power to multiple components (e.g., a “ground plane” provides a common return path for current, and a “power plane” distributes operating power uniformly to respective electrical components on the PCB). In some instances, a plane is implemented as an entire PCB layer in a multilayer design (with an edge clearance typically on the order of about 10-20 mils (0.25-0.5 mm) from the PCB edges). The options for copper thickness of a plane are essentially the same as those for a trace. Conventionally, a PCB designer does not specify a width or a length for a plane (as would be done for a trace); rather, the PCB designer uses an appropriate software tool to instead draw a shape generally around an area in which they wish to create a plane, and the software tool would specify that copper be placed in the designated area (referred to as a “copper flood”) according to applicable design rules (discussed further below). In particular, for PCB design software to execute a copper flood to create a plane, a clearance on the order of from about 2-20 mils (0.05-0.5 mm) typically is specified (in the design rules) around traces, pads, or other conductive features that are in or traverse the area designated by the designer for the plane.

[0015] In some specialized PCB applications involving high-current loads, a “busbar” is a relatively wider and thicker area of copper that is employed to handle large DC (or near-DC) currents and / or distribute DC power or near-DC (e.g., 60-400 Hz) sine-wave power across a PCB. In conventional implementations a PCB busbar typically takes the form of a plane depending on the current load. A busbar generally is implemented on a copper layer oftenAttorney Docket No.: BRLN-008W001 having a thickness of 2 oz / ft2(70 gm) or more and is generally disposed on an outer layer of a PCB to effectively dissipate heat. Busbars are not conventionally used to carry signals on a PCB (and particularly not radio frequency or RF signals, which are generally considered to be in a frequency range of from 3 kHz to 300 GHz); accordingly, concepts germane to impedance- controlled traces on a PCB do not pertain to (and are irrelevant to) a busbar. Rather, the primary purpose of a PCB busbar, when conventionally implemented, is to handle DC or near-DC high currents in applications with significant electrical loads requiring significant power.(0016] Another salient element of a multilayer PCB is a “via.” Vias are small holes plated with copper that connect two or more copper layers in a multilayer PCB stack-up. A “through- hole via” passes through all layers of the PCB, where as a “blind via” connects an outer copper layer to one or more inner copper layers. A “buried via” interconnects only inner layers and is invisible from the top and bottom surfaces of a multilayer PCB. A standard drill size for vias is on the order of 6-20 mils (0.152-0.5 mm), although “microvias” may have a drill size on the order of 4-6 mils (0.1-0.152 mm).(0017] As noted above, PCB layout design often is facilitated by software tools (e.g., KiCAD, Eagle, or Altium Designer) according to specified “design rules.” Such design rules establish the constraints and guidelines that ensure manufacturability, functionality, and reliability of the PCB. Accordingly, design rules encompass all aspects of PCB design, including trace routing, material selection, and component placement. Examples of design rules include:• Trace design rules (governing appropriate width of traces based on current-carrying and / or controlled-impedance requirements and minimum spacing to prevent shorts and comply with voltage isolation requirements);• Component placement rules (governing placement of components close to related circuitry to minimize trace lengths and reduce signal delays, alignment of similar components in the same direction for consistent soldering and inspection, adequate clearance between components for soldering and heat dissipation);• Layer stack-up rules (governing the number of layers based on circuit complexity and signal requirements, definition of power and ground planes, and selection of materials with suitable dielectric constants);• Power and ground distribution rules (governing placement and clearance between power and ground planes for isolation, low impedance, and effective noise suppression);Attorney Docket No.: BRLN-008W001• Via design rules (governing appropriate via sizes for routing and manufacturability and via placement to maintain signal integrity for high speed traces);• Signal integrity rules (governing trace lengths and timing constraints, adequate spacing to mitigate crosstalk and electromagnetic coupling, low-impedance return paths and proper termination to prevent reflections);• Thermal management rules (governing copper thickness for high-current paths to reduce heat generation, thermal relief patterns for solderability on large copper areas, thermal vias);• Manufacturing rules (governing minimum feature dimensions to adhere to a manufacturer’s size capabilities, and ensure silkscreen clearance so text does not overlap pads or traces);• Assembly rules (governing the accessibility of components for assembly, soldering, and testing, providing adequate clearance for pick-and-place machines, soldering irons, and inspection tools, and including test points for electrical testing during production); and• High-speed design rules (governing spacing and length-matching of traces for differential signals, precise impedance values for high-speed communication, and use of back-drilling or blind vias to mitigate signal degradation).(0018] The central tenets of PCB design rules aim to ensure manufacturability, reliability, and performance; in particular, design rules often are particularly specified to match the capabilities of a given PCB fabricator. Accordingly, design rules help designers balance trade-offs between cost, functionality, and durability within a given fabricator’s capabilities while meeting application-specific requirements.(0019] With respect to visual representations of a PCB design and, more particularly, respective levels of a multilevel PCB design, PCB designers as well as manufacturers conventional rely on “Gerber files.” Gerber files are open ASCII vector format files that contain information on each physical layer of a PCB design. Circuit board objects, like copper traces, vias, pads, soldermasks, and silkscreen images, are all represented by a flash or draw code and defined by a series of vector coordinates. PCB manufacturers use these Gerber files to translate the details of a PCB design into the physical properties of the PCB. The PCB design software typically generates Gerber files. Accordingly, Gerber files store all of the shape andAttorney Docket No.: BRLN-008W001 location data for every element in a PCB layout. In general, the layout of each layer in a multilayer PCB will be placed into its own Gerber file. The idea is that respective Gerber files corresponding to different layers of a multilayer PCB stack-up can be used to prepare stencils for each step in the PCB fabrication and assembly process.|0020| For conventional PCB circuits designed for high-speed / high-frequency signaling applications (e.g., involving RF signals), the concept of “impedance matching” is important for maintaining signal integrity within the PCB circuit as well as the PCB’s input and output signal connections. High-speed signals with fast rise times have higher frequency components, making them sensitive to impedance changes along a signal path; in particular, an abrupt impedance change or discontinuity along a signal path can cause reflections, signal loss, and distortion. A signal trace on a PCB carrying a high-speed / high-frequency signal acts as a transmission line (in concert with a return conductor or ground plane). Common forms of conventional PCB transmission lines include a “microstrip,” where the signal trace is on an outer copper layer with a ground plane on an adjacent inner copper layer, a “stripline,” where the signal trace is sandwiched between two ground planes on copper layers above and below the signal trace, and a “coplanar waveguide,” where the signal trace is flanked on the same copper layer by ground traces. The impedance of a signal trace serving as a transmission line on a PCB generally is dictated based at least in part by the trace width (e.g., conventionally on the order of 5-20 mils / 0.13-0.5 mm), the trace height (i.e., copper thickness), the distance of the signal trace from a ground plane or a ground trace, and the dielectric constant of the PCB insulating material (i.e., core or prepreg) between the signal trace and the ground plane / ground trace.[0021 Accordingly, the concept of “controlled-impedance design” is often employed in conventional PCB fabrication related to high-speed / high-frequency signaling to ensure an appropriate characteristic impedance of signal traces serving as transmission lines to carry high-speed / high-frequency signals. Controlled-impedance design techniques for PCB fabrication also contemplate mitigation of significant impedance discontinuities at a PCB’s high-speed / high-frequency signal input and output connections. Common examples of target impedances for signal traces pursuant to controlled-impedance design include 50Q (for “single- ended” transmission lines constituted by a single signal line and a return ground plane) or 100Q (for a “differential” transmission line constituted by a pair of signal lines and a return ground plane) for compatibility with most high-speed standards for electronic signaling.Attorney Docket No.: BRLN-008W001

[0022] Controlled-impedance design considerations include ensuring consistent trace width from layer-to-layer, consistent spacing, consistent height and consistent dielectric material along the entire trace to avoid impedance discontinuities, using rounded or chamfered comers instead of 90° bends to minimize impedance changes as traces change direction in a given layer, and using adjacent ground or power planes in a multilayer stack-up to create a reference (return) for the signal traces serving as transmission lines. For the signal return path, a solid uninterrupted ground plane is typically employed to minimize impedance variation and reduce noise. Particular placement of vias also may influence impedance changes, as vias along or through a return path, if required, can be disruptive and create impedance mismatches. As part of controlled-impedance design for PCBs, signal simulation and / or validation tools are often employed to simulate or measure actual impedances of the signal traces and PCB connections to facilitate identification of impedance mismatches and / or discontinuities. Examples of some tools relevant to controlled-impedance PCB design include SPICE, HyperLynx, or Ansys HFSS to simulate signal behavior, measure impedance, and verify design compliance, as well as using time-domain reflectometry (TDR) to measure actual impedance.

[0023] In conventional high-speed / high-frequency PCB design, the available transmission line impedances for signal lines intended to carry high-speed / high frequency signals depend in part on the fabrication capabilities, stack-up design, and the materials used. Common impedances for signal traces are designed to meet the requirements of specific communication standards or high-speed signal protocols for various applications of electronic signaling. As noted above, a standard single-ended transmission line impedance of 50 is commonly used for PCBs carrying high-speed digital signals, general RF / microwave circuits, Ethernet, and USB. A standard differential transmission line impedance of 100Q is commonly used for differential pairs such as Ethernet (e.g., 100BASE-TX, 1000BASE-T), USB (high-speed and above), HDMI, and LVDS. A more specific differential transmission line impedance of 90Q is particularly used for USB 2.0 and USB 3.x (as the USB protocol explicitly defines this impedance for signal integrity). Another more specific differential transmission line impedance of 85 is used for HDMI and DisplayPort (as specified by applicable standards for video interfaces). A 75Q single-ended transmission line impedance is commonly used for many video signals (e.g., composite video, SDI, cable television) and some RF circuits, as this impedance matches the characteristic impedance of coaxial cables commonly used in video transmission.[0024 In some instances, PCBs designed for specialized high-frequency applications may require dielectric materials other than FR4 having particular electrical and thermalAttorney Docket No.: BRLN-008W001 characteristics to ensure signal integrity and performance. In general, example materials for high-frequency applications (e.g., Rogers 4350B, Taconic RF-35) often have a low and stable dielectric constant (e.g., 2.2-3.0) to mitigate signal distortion and ensure predictable propagation speeds. Additionally, a low dissipation factor (Df) reduces energy loss and heat generation, which may be an important consideration at GHz frequencies (e.g., Rogers 5880 or Arion 85N have reported Df < 0.005). High-frequency applications tend to generate significant heat, so materials should maintain consistent properties over a wide temperature range. To this end, some specialized dielectric materials for PCBs offer low thermal expansion (CTE), thereby reducing warping and delamination risks (e.g., PTFE-based laminates such as Teflon). Moreover, absorption of moisture can alter dielectric properties and lead to performance degradation; accordingly, some high-frequency dielectric materials for PCBs are designed to mitigate water uptake (e.g., Isola Astra MT77). Finally, some specialized dielectric materials for PCBs have appreciable thermal conductivity to dissipate heat more efficiently, which is particularly important in RF power amplifiers or high-power circuits (e.g., Ceramic-filled PTFE composites like Rogers RT / duroid 6010).SUMMARY

[0025] Various inventive concepts disclosed herein relate to PCBs having ultra-wide impedance-controlled traces, formed on one or more conductor layers of a multilayer PCB stack-up (e.g., four layers, six layers, or more than six layers). In some example implementations, such ultra-wide impedance-controlled traces are employed to implement PCB transmission lines having a significantly low characteristic impedance (also referred to herein as “ultra-low impedance” PCB transmission lines). By way of example, the ultra-low characteristic impedance of PCB transmission lines according to the inventive concepts disclosed herein is less than or equal to approximately 10 ohms, more preferably less than or equal to approximately 5 ohms, and more preferably less than or equal to approximately 2 ohms. The range of frequencies over which a PCB transmission line according to the inventive concepts disclosed herein maintains an ultra-low characteristic impedance generally is within the radio frequency (RF) signal range from approximately 3 kHz to 300 GHz (and, in some examples, over a range of frequencies from approximately 100 kHz to 1 GHz).

[0026] In some example implementations, ultra-low impedance PCB transmission lines including one or more ultra-wide traces according to the concepts disclosed herein generally are also configured to carry high-frequency power signals (e.g., having peak voltages in a range of from between 20 Volts to 1000 Volts and corresponding peak currents in a range of fromAttorney Docket No.: BRLN-008W001 between 10 Amperes to 500 Amperes). Thus, at least some examples of ultra-low impedance PCB transmission lines including ultra-wide traces according to the concepts disclosed herein are capable of delivering peak powers on the order of up to 100 W to 200 kW from high- frequency power signals.|0027| The Inventors have appreciated that conventional DC power distribution conductors on PCBs typically require significantly thick and wide conductors (e.g., “planes”) that carry relatively high currents (at or near DC). The width and thickness of such conductors often are driven by the need to minimize the resistance of the conductors so as to mitigate heat generation, power loss and voltage drops while carrying an appreciable current. Moreover, high-current DC or near-DC power distribution applications typically require that such conductors are disposed on an outer layer of a PCB to effectively dissipate heat. Such conductors are not conventionally used on inner layers of a PCB and are not used to carry signals on a PCB (and particularly not radio frequency or RF signals). Accordingly, the ultrawide traces employed in ultra-low impedance PCB transmission lines according to the concepts disclosed herein are significantly different in multiple respects from the conductors conventionally employed in PCBs for power distribution / high DC or near-DC currents; in particular, controlled-impedance PCB concepts relating to RF signals do not pertain to conventional high-current and / or power distribution conductors on a PCB.

[0028] Separately from high-current and / or power distribution conductors, the Inventors also have appreciated that conventional PCB manufacturers implement controlled-impedance designs to form PCB transmission lines having various characteristic impedances (e.g., over a range generally from about 25Q to 125Q). Such controlled-impedance PCB transmission lines may include traces of various widths and thicknesses and may be employed for a variety of RF applications. However, the ultra-wide traces according to the concepts disclosed herein involve trace widths that are an order (or multiple orders) of magnitude wider than those employed in conventional controlled-impedance designs for PCB transmission lines (e.g., 195-1180 mils / 5- 30 millimeters wide for ultra-wide traces as opposed to 5-20 mils / 0.13-0.5 mm wide for conventional traces); in fact, the ultra-wide traces disclosed herein would not even be considered as “traces” in the conventional parlance of PCB designers. At the same time, the characteristic impedances of the ultra-low impedance PCB transmission lines according to the concepts disclosed herein are in some instances an order of magnitude lower than the characteristic impedances of conventional PCB transmission lines (e.g., 2 ohms as opposed toAttorney Docket No.: BRLN-008W00125 ohms). Accordingly, ultra-low impedance PCB transmission lines and ultra-wide traces according to the concepts disclosed herein represent novel categories of PCB design elements.(0029] To underscore the uniqueness of ultra-wide PCB traces and ultra-low impedance PCB transmission lines incorporating such traces, the Inventors also have recognized and appreciated that conventional PCB design software tools do not contemplate the specification of trace widths in the ranges for the impedance-controlled ultra-wide traces considered according to the concepts disclosed herein (e.g., 195-1180 mils or 5-30 millimeters). Similarly, conventional PCB manufacturers presently would not consider designing or building a controlled-impedance PCB with the characteristic impedances contemplated herein (e.g., 10 ohms or less). Multiple examples of conventional PCB transmission line impedance calculators (e.g., available online from various sources) provide non-sensical answers for characteristic impedance (e.g., a negative characteristic impedance) when provided with ultrawide trace widths for transmission line conductors in the ranges contemplated herein. Thus, the Inventors have fashioned unconventional techniques for using conventional PCB design software tools to facilitate implementation of ultra-wide traces in PCB designs; furthermore, they have also developed unconventional characteristic impedance calculators for ultra-low impedance PCB transmission lines, relying on alternative approximations of Maxwell’s Equations that are better-adapted to the ranges of ultra-wide trace widths and ultra-low impedances contemplated herein.(0030] In non-limiting example implementations, PCBs including ultra-low impedance transmission lines according to the concepts disclosed herein are fabricated using conventional FR4 dielectric materials (e.g., core and prepreg for multilayered implementations) and using one (1) ounce per square foot copper for conductive layers (e.g., so as to benefit from the ubiquitous availability and use of FR4 and industry-standard copper foils). Regardless of the choice of dielectric materials, however, in various example implementations an ultra-wide trace (e.g., used in an ultra-low impedance PCB transmission line) may have a width on the order of at least 200 mils (5 millimeters), or on the order of at least 300 mils (7.6 millimeters), or on the order of at least 400 mils (10.2 millimeters), or on the order of at least 500 mils (12.7 millimeters), or on the order of at least 800 mils (approximately 20 millimeters), and may be as wide as approximately 1200 mils (approximately 30 millimeters).(0031] In one example, an ultra-low impedance PCB transmission line is configured to carry a high-frequency signal including a sequence of temporally short, broad frequency spectrum pulses. Examples of such pulses are square or essentially square pulses, though other pulseAttorney Docket No.: BRLN-008W001 shapes are possible. The pulses constituting the high-frequency signal carried by the ultra-low impedance PCB transmission line can have a repetition frequency / with a duty cycle D (ratio of the pulse’s on time to period T= Mf). In some aspects, the rise time Tr of the pulses can be less than approximately or exactly 50 ns (e.g., between approximately or exactly 1 ns and approximately or exactly 50 ns), though shorter rise times can be used in some implementations. The repetition frequency / can be between approximately or exactly 3 kHz and approximately or exactly 10 MHz and the duty cycle D can be between approximately or exactly 0.01% and 50%. As noted above, in another aspect the peak amplitude of the pulses can be between approximately or exactly 20 V and approximately or exactly 1000 V.

[0032] In yet another example, the pulses constituting the high-frequency signal each rise to a peak value and fall to an initial value without a sustained duration of the peak value. Examples of such pulses are Gaussian pulses, though other pulse shapes are possible. The temporal full- width-half-maximum value To of the pulses can be less than approximately or exactly 200 ns (e.g., between approximately or exactly 1 ns and approximately or exactly 200 ns), though shorter pulses can be used in some implementations. The repetition frequency / can be between approximately or exactly 3 kHz and approximately or exactly 10 MHz and the duty cycle D can be between approximately or exactly 0.01% and 50%. The peak amplitude of the excitation pulses can be between approximately or exactly 20 V and approximately or exactly 1000 V.

[0033] In yet another example, the characteristic impedance of the PCB transmission line is approximately or exactly 2 ohms, and the pulses constituting the high-frequency signal have a peak voltage on the order of approximately 600 Volts and a peak current on the order of approximately 300 Amperes.

[0034] In some examples, the ultra-low impedance PCB transmission line may be implemented on a multilayer PCB stack-up, wherein the stack-up includes four layers, six layers, or more than six layers. In one example, an ultra-low impedance PCB transmission line may include one ultra-wide trace on one layer of the stack-up and at least one return plane on another layer of the stack-up to form the transmission line. In another example, an ultra-low impedance PCB transmission line may include two or more ultra-wide traces (including one trace on a first inner layer of the stack-up, and another trace on a second inner layer of the stack-up) that are electrically coupled together (e.g., by one or more vias). The two (or more) ultra-wide traces function in tandem with at least one return plane on another layer of the stack-up adjacent to the inner layer(s) to form the transmission line. In various aspects, employing two or more ultra-wide traces on respective inner layers of the stack-up to form the transmission line allowsAttorney Docket No.: BRLN-008W001 for a balanced stack-up including an even number of layers, and also provides for increased current conducting capability of the transmission line while at the same time using industry standard one ounce per square foot copper foil for respective layers.

[0035] In some aspects, to implement an ultra-wide trace using conventional PCB software tools (e.g, KiCAD, Eagle, or Altium Designer), a PCB designer needs to particularly specify the ultra-wide trace not as a trace but rather as a plane, as the conventional PCB software tools generally limit power distribution trace widths (not for controlled-impedance) to a maximum of 250 mils (6.35 millimeters). To this end, the PCB designer instead uses the PCB software tool to specify an ultra-wide trace by outlining a plane having particular dimensions based at least in part on a target characteristic impedance, the copper thickness, the distance of the plane / ultra-wide trace from a ground plane or a ground trace, and the dielectric constant of the PCB insulating material (e.g., core, prepreg or other specialty dielectric material) between the plane / ultra-wide trace and the ground plane / ground trace. The PCB software tool then creates a copper flood based on the specified outline of the plane. Accordingly, an ultra-wide trace according to the concepts disclosed herein may advantageously exploit attributes of a copper flood (e.g., including the particular clearances around vias, pads, or other conductive features that are in or traverse the area designated by the designer for the plane, as specified by corresponding design rules for copper floods). According to yet another aspect, the PCB designer may specify one or more additional planes on one or more layers of the PCB, in addition to those serving as an ultra-wide trace, and thereby use copper floods in these additional planes to balance the copper distribution from layer-to-layer. Such a layer-to-layer balancing of copper distribution in the multilayer stack-up may improve impedance consistency, PCB manufacturability, and durability (e.g., by preventing warping of the PCB).

[0036] The Inventors have also recognized and appreciated that the ultra-wide traces and ultralow impedance PCB transmission line concepts disclosed herein may bring specific advantages to a variety of applications that require high-bandwidth and / or high frequency signals and also have significant current and / or power requirements. One example of a high-bandwidth and high-power application that may benefit from the ultra-wide traces and / or ultra-low impedance PCB transmission lines according to the concepts disclosed herein includes a heat generation system in which a catalyst is stimulated with a high-bandwidth and high-power signal (e.g., a series of intense current spikes) to facilitate heat-generating reactions (e.g., arising from increased phonon activity in the catalysts as a result of the applied high-bandwidth / high-power signal). Other example applications include, but are not limited to, power amplifiers (e.g., forAttorney Docket No.: BRLN-008W001RF and microwave cellular base stations), laser-drivers (e.g., for long distance signal transmission, including repeaters), power LIDAR systems, electric vehicles (e.g., power distribution and signal routing in battery management systems, and high-power signal lines in EV inverters), industrial automation and robotics (e.g., motor controllers, industrial power supplies and actuators for factory automation systems), renewable energy systems (pulsed power and fusion applications), medical equipment (e.g., high-powered MRI imaging systems that require both high power and significant signal integrity for sensitive imaging functions), RF testing equipment (e.g., time domain reflectometry systems), fuel cells and hydrogenation catalysts (e.g., involving high-frequency and high-power phonon stimulation).(0037] It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS[0038 The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).(0039] FIG. 1 shows a cross-sectional view of a conventional multilayer PCB having a four- layer stack-up.(0040] FIG. 2 shows a cross-sectional view of a conventional multilayer PCB having a six- layer stack-up.

[0041] FIG. 3 shows a cross-sectional view of a multilayer PCB including an ultra-wide impedance-controlled conductive (e.g., copper) trace on a first layer and a return conductor onAttorney Docket No.: BRLN-008W001 a second layer to constitute at least a portion of an ultra-low impedance PCB radio frequency (RF) transmission line according to one inventive example implementation.(0042] FIG. 4 shows another cross-sectional view of a multilayer PCB including an ultra-wide impedance-controlled conductive (e.g., copper) trace on a first layer and a return conductor on a second layer to constitute at least a portion of an ultra-low impedance PCB radio frequency (RF) transmission line according to one inventive example implementation, wherein the second layer is not a neighboring layer of the first layer in the multilayer PCB stack-up.(0043] FIG. 5 shows a top-down view of the multilayer PCB of either FIG. 3 or FIG. 4, illustrating the ultra-wide impedance-controlled trace on the first layer (in black) superimposed on the return conductor on the second layer (in gray) to constitute at least a portion of the ultralow impedance PCB radio frequency (RF) transmission line.(0044] FIG. 6 shows a cross-sectional view of a multilayer PCB including an ultra-wide impedance-controlled conductive (e.g., copper) trace on a first layer, a first return conductor on a second layer, and a second return conductor on a third layer to constitute at least a portion of an ultra-low impedance PCB radio frequency (RF) stripline transmission line according to one inventive example implementation.(0045] FIG. 7 shows a cross-sectional view of a multilayer PCB similar to that shown in FIG. 6, in which one or more additional outer layers of the multilayer PCB are employed to facilitate electrical connections to the PCB RF transmission line according to inventive example implementations.(0046| FIG. 8 shows a bottom-up view of at least a portion of the multilayer PCB of FIG. 7, illustrating an annular contact portion on the fourth (outer) layer (in black) superimposed on the ultra-wide impedance-controlled trace on the first layer (in gray), according to one inventive example implementation.(0047] FIG. 9 shows a bottom-up view of at least a portion of the multilayer PCB of FIG. 7, illustrating the bottom soldermask (in white, with black representing openings in the soldermask), superimposed on an annular contact portion on the fourth (outer) layer and the ultra-wide impedance-controlled trace on the first layer (in gray), according to one inventive example implementation.(0048] FIG. 10 is a stylized drawing showing the interconnection of a coaxial transmission line to a planar PCB RF transmission line of a multilayer PCB according to the inventive concepts disclosed herein.Attorney Docket No.: BRLN-008W001

[0049] FIG. 11A illustrates a bottom outer layer annular first contact portion and associated first lugs and alternating sets of first vias of the multilayer PCB of FIG. 7, according to one inventive example implementation.

[0050] FIG. 1 IB illustrates a top outer layer annular second contact portion and associated second lugs and alternating sets of second vias of the multilayer PCB of FIG. 7, according to one inventive example implementation.

[0051] FIG. 11C illustrates a bottom opening in a bottom soldermask of the multilayer PCB of FIG. 7 to allow access to the annular first contact portion in the bottom outer layer shown in FIG. 11 A.

[0052] FIG. 1 ID illustrates a top opening in a top soldermask of the multilayer PCB of FIG. 7 to allow access to the annular second contact portion in the top outer layer shown in FIG. 1 IB.

[0053] FIG. 12 illustrates a cross-sectional view of another example of a multilayer PCB comprising a six -layer stack-up, in which multiple ultra-wide impedance-controlled traces are formed, together with multiple return conductors, to provide a modified stripline ultra-low impedance PCB RF transmission line according to inventive example implementations.

[0054] FIG. 13 shows an example of a customized six-layer stack-up, according to one example implementation, which may be employed to fabricate the modified stripline configuration shown in FIG. 12.

[0055] FIG. 14 shows a cellular base station that includes one or more PCB RF transmission lines or one or more PCBs with at least one ultra-wide impedance-controlled trace, according to the inventive concepts disclosed herein.

[0056] FIG. 15 shows an electric vehicle that includes one or more PCB RF transmission lines or one or more PCBs with at least one ultra-wide impedance-controlled trace, according to the inventive concepts disclosed herein.

[0057] FIG. 16 shows a medical imager that includes one or more PCB RF transmission lines or one or more PCBs with at least one ultra-wide impedance-controlled trace, according to the inventive concepts disclosed herein.

[0058] FIG. 17 shows an industrial robot that includes one or more PCB RF transmission lines or one or more PCBs with at least one ultra-wide impedance-controlled trace, according to the inventive concepts disclosed herein.Attorney Docket No.: BRLN-008W001

[0059] FIG. 18 shows a particle accelerator that includes one or more PCB RF transmission lines or one or more PCBs with at least one ultra-wide impedance-controlled trace, according to the inventive concepts disclosed herein.

[0060] FIG. 19 shows a plasma generator and a plasma etching system that includes one or more PCB RF transmission lines or one or more PCBs with at least one ultra-wide impedance- controlled trace, according to the inventive concepts disclosed herein.

[0061] FIG. 20 shows a pulsed power generator that includes one or more PCB RF transmission lines or one or more PCBs with at least one ultra-wide impedance-controlled trace, according to the inventive concepts disclosed herein.DETAILED DESCRIPTION

[0062] Following below are more detailed descriptions of various concepts related to, and embodiments of, printed circuit boards including ultra-wide impedance-controlled traces for significantly low impedance applications and methods of fabricating same. It should be appreciated that various concepts introduced above and discussed in further detail below may be implemented in multiple ways. Examples of specific implementations and applications are provided primarily for illustrative purposes so as to enable those skilled in the art to practice the implementations and alternatives apparent to those skilled in the art.

[0063] The figures and example implementations described herein are not meant to limit the scope of the present implementations to a single embodiment. Other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the disclosed example implementations may be partially or fully implemented using known components, in some instances only those portions of such known components that are necessary for an understanding of the present implementations are described, and detailed descriptions of other portions of such known components are omitted so as not to obscure the present implementations.

[0064] Various examples of printed circuit board concepts and elements are set forth in greater detail below, wherein a given example or set of examples showcases one or more features of an implementation for significantly low impedance applications and / or a related fabrication method. It should be appreciated that one or more features discussed in connection with a given example may be employed in other examples of printed circuit boards and associated fabrication methods according to the present disclosure, such that the various features disclosedAttorney Docket No.: BRLN-008W001 herein may be readily combined in multiple ways according to the present disclosure (provided that respective features are not mutually inconsistent).(0065] Certain dimensions and features of printed circuit boards according to the present disclosure are described herein using the terms “approximately,” “about,” “substantially,” and / or “similar.” As used herein, the terms “approximately,” “about,” “substantially,” and / or “similar” indicates that each of the described dimensions or features is not a strict boundary or parameter and does not exclude functionally similar variations. Unless context or the description indicates otherwise, the use of the terms “approximately,” “about,” “substantially,” and / or “similar” in connection with a numerical parameter indicates that the numerical parameter includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.(0066] FIG. 3 shows a cross-sectional view of a multilayer PCB 100 including an ultra-wide impedance controlled conductive (e.g., copper) trace 120 according to one inventive example implementation. In the illustration of FIG. 3, the cross-sectional view is taken along ay-z plane of the multilayer PCB (where the z axis represents a height or thickness dimension of the multilayer PCB). Generally speaking, in the various figures, the position along the x-axis of a multilayer PCB at which a given cross-sectional view is taken may not strictly correspond to any one specific PCB design example discussed later in this disclosure; rather, respective cross-sectional views are provided to conceptually illustrate constituent elements of the multilayer architecture germane to the inventive subject matter disclosed herein.(0067] FIG. 3 shows an example of a multilayer PCB having a stack-up 110 including four conductive layers (designated generically in the figure by LI, L2, L3 and L4). It should be appreciated, however, that the various inventive concepts disclosed herein similarly apply to PCBs with only two conductive layers, as well as multilayer PCBs having a stack-up of greater than four layers (e.g., as discussed further below in connection with FIG. 12). In the various figures, conductive layers of a stack-up generally are shown in solid white, whereas electrically-insulating materials between conductive layers generally are shown with grayscale cross-hatching (e.g., darker gray-scale cross-hatching for core, lighter gray-scale crosshatching for prepreg). Also, for purposes of this disclosure, respective conductive layers of a given stack-up may be referred to herein for convenience as “copper layers” or simply “layers;” however, it should be appreciated that the various concepts disclosed herein may be implemented with conductive layers employing copper or other materials (e.g., aluminum,Attorney Docket No.: BRLN-008W001 gold, silver, nickel, tin, lead, carbon). Additionally, when referring to respective layers and electrically-insulating material of a given stack-up, the use of ordinal adjectives may not necessarily correspond to generic layer designations (e.g., such as LI, L2, L3, and L4) shown in the various figures; instead, ordinal adjectives generally refer to the sequential order in which a given layer or electrically-insulating material of a stack-up is introduced in the following discussion.

[0068] As shown in FIG. 3, the stack-up 110 of the multilayer PCB 100 in this example includes a first electrically insulating material 124 (e.g., “core”) and a first layer 112 (Z2) (e.g., comprising first copper), wherein the first layer 112 and the first electrically-insulating material 124 are contiguous. A first ultra-wide impedance-controlled trace 120A is formed in the first layer 112. In one inventive aspect, the ultra-wide trace 120A has a width 122 in a range of from approximately or equal to 200 mils (or 5 millimeters) to approximately or equal to 1200 mils (or 30 millimeters). As noted earlier, this range for the width 122 of the ultra-wide trace 120A is an order (or multiple orders) of magnitude wider than the width of a conventional impedance-controlled trace (i.e., 5-20 mils / 0.13-0.5 mm wide for conventional traces); given this width 122, at the time of this disclosure, the ultra-wide trace 120A would not be considered as an impedance-controlled trace in the conventional parlance of PCB designers. Accordingly, the ultra- wide impedance-controlled trace 120 A constitutes a novel PCB design element.[0069| As also shown in FIG. 3, the ultra-wide trace 120A has a trace thickness 118. In implementations employing copper for conductive layers, in one example the trace thickness 118 of an ultra-wide copper trace is at least 0.5 ounces per square foot (i.e., at least 0.67 to 0.7 mils of copper) and less than 2.0 ounces per square foot (i.e., less than 2.7 to 2.8 mils of copper). Accordingly, while in one aspect the ultra-wide trace 120A is significantly wider than a conventional impedance-controlled trace, in another aspect it may be thinner than conductive elements typically employed for high-current DC or near-DC power distribution applications on a PCB (which typically employ at least 2.0 ounce per square foot or greater of copper and are often disposed on an outer layer of a PCB to effectively dissipate heat). The Inventors have also recognized and appreciated that, in consideration of RF signals being carried by the ultrawide trace 120, there is not necessarily a need for relatively thicker copper; the skin effect arising from RF signals often limits the depth of current being carried by the ultra-wide trace to less than (and in some instance significantly less than) the thickness of the trace.

[0070] In FIG. 3, the multiplayer PCB 100 also includes a first return conductor 126 formed in a second layer 114 of the stack-up (e.g., comprising second copper). As shown in FIG. 3, atAttorney Docket No.: BRLN-008W001 least a portion of the first electrically-insulating material 124 of the stack-up (e.g., the core) is disposed between the ultra-wide trace 120A and the return conductor 126. In such an arrangement, the ultra- wide trace 120 A and the return conductor 126 constitute at least a portion of a PCB radio frequency (RF) transmission line 130. A characteristic impedance of the PCB RF transmission line 130 is based at least in part on the width 122 of the ultra-wide trace 120A, the thickness 118 of the ultra-wide trace 120A, a first dielectric constant (En) 132A of the first electrically-insulating material 124, and a first thickness 134A of the first electrically-insulating material 124.

[0071] In one inventive aspect, one or more of the width 122 of the ultra-wide impedance- controlled trace 120A, the thickness 118 of the ultra-wide trace 120A, the first dielectric constant 132A of the first electrically-insulating material 124 or the first thickness 134A of the first electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line 130 is less than or equal to 10 ohms. In other inventive aspects, one or more of the foregoing parameters may be selected such that the characteristic impedance of the PCB RF transmission line 130 is less than or equal to 5 ohms, or less than or equal to 2 ohms. As also noted earlier, at the time of this disclosure, conventional PCB manufacturers would not consider designing or building a controlled-impedance PCB with the characteristic impedances contemplated herein (e.g., 10 ohms or less). Moreover, multiple examples of conventional PCB transmission line impedance calculators (e.g., available online from various sources) provide non-sensical answers for characteristic impedance (e.g., a negative characteristic impedance) when provided with ultra-wide impedance-controlled trace widths for transmission line conductors in the ranges contemplated herein (e.g., 5 millimeters to 30 millimeters).

[0072] In the example of FIG. 3, the first layer 112 in which the ultra-wide trace 120A is implemented and the second layer 114 in which the return conductor 126 is implemented are “neighboring” layers of the stack-up 110 (e.g., there is only one intervening electrically- insulating material 124). It should be appreciated, however, that an ultra- wide trace and a return conductor constituting at least a portion of a PCB transmission line need not necessarily be implemented on neighboring layers of the stack-up. To this end, FIG. 4 shows another cross-sectional view of a multilayer PCB 100 in which the ultra- wide trace and the return conductor are not formed on neighboring layers of the stack-up.

[0073] More specifically, in the example shown in FIG. 4, the layer of the stack-up 110 designated generically as L3 constitutes an intervening layer 114 (e.g., intervening copper) ofAttorney Docket No.: BRLN-008W001 the stack-up (rather than being referred to as the “second layer” in the example of FIG. 3). Consequently, in FIG. 4, the layer designated generically as L4 constitutes the second layer 116 in which the first return conductor 128 is formed, such that the intervening layer 114 is disposed between the first layer 112 and the second layer 116. At least a portion of second electrically-insulating material 136 is disposed between the intervening layer 114 and the second layer 116. However, as shown in FIG. 4, some of the intervening layer 114 has been etched away in the fabrication process in an area generally below the ultra -wide trace 120 A, such that the first electrically-insulating material 124 and the second electrically-insulating material 136 are contiguous in this area. The second electrically-insulating material 136 has a second dielectric constant (Er?) 132B (which may be the same or different as the first dielectric constant En of the first electrically-insulating material 124), and has a second thickness 134B (which may be the same or different as the first thickness 134A of the first electrically- insulating material 124).|0074| In the example arrangement shown in FIG. 4 in which the ultra-wide trace 120A and the return conductor 128 constituting a portion of the PCB RF transmission line 130 are not formed on neighboring layers of the stack-up 110, the characteristic impedance of the transmission line 130 is based not only on the first dielectric constant 132A and the first thickness 134A of the first electrically-insulating material 124, but also needs to take into consideration the addition of the second electrically-insulating material 136. Thus, the characteristic impedance of the transmission line 130 shown in the example of FIG. 4 is based at least in part on the width 122 of the ultra-wide trace 120A, the thickness 118 of the ultrawide trace, the first dielectric constant 132A of the first electrically-insulating material 124, the second dielectric constant 132B of the second electrically-insulating material 136, the first thickness 134A of the first electrically-insulating material, and the second thickness 134B of the second electrically-insulating material. In a manner similar to that discussed above in connection with FIG. 3, one or more of the foregoing parameters is selected such that the characteristic impedance of the PCB RF transmission line 130 is less than or equal to 10 ohms (or less than or equal to 5 ohms, or less than or equal to 2 ohms).}0075| FIG. 5 shows a top-down view (i.e., in the x-y plane) of at least a portion the multilayer PCB of either FIG. 3 or FIG. 4, illustrating the ultra-wide impedance-controlled trace 120 A formed in the first layer (shown in FIG. 5 in black), superimposed on the return conductor 128 formed in the second layer (shown in FIG. 5 in gray) to constitute at least a portion of the ultralow impedance PCB radio frequency (RF) transmission line 130. It should be appreciated thatAttorney Docket No.: BRLN-008W001 the top-down view of FIG. 5 is created using respective Gerber files for the first layer (shown in black) and the second layer (shown in gray); accordingly, other layers of the PCB stack-up shown in either FIG. 3 or FIG. 4 are not reflected in FIG. 5. As an exemplary frame of reference, the cross-sectional views of FIG. 3 and FIG. 4 are taken along the dashed line A-A shown in FIG. 5. From the perspective of the x-y plane, the significant width 122 of the ultrawide trace 120A vis a vis the return conductor 128 may be readily appreciated.

[0076] In both of the cross-sectional views shown in FIG. 3 and FIG. 4, the PCB RF transmission line 130 is an embedded microstrip transmission line. It should be appreciated, however, that the inventive concepts disclosed in connection with FIG. 3 and FIG. 4 may be applied to other configurations of PCB transmission lines (e.g., stripline, co-planar waveguide), implemented on one or more layers of a multilayer PCB stack-up having various numbers of layers (e.g., 4 layers, 6 layers, 8 layers, etc.).

[0077] For example, FIG. 6 shows a cross-sectional view of a multilayer PCB 100 including an ultra- wide impedance-controlled trace 120 A on the first layer 112, the first return conductor 126 on the second layer 114, and a second return conductor 144 on a third layer 142 of the stack-up 110. The PCB RF transmission line 130 comprises the ultra-wide trace 120A, the first return conductor 126, and the second return conductor 144; this arrangement of elements constitutes a stripline configuration for the transmission line 130. In the example of FIG. 6, a third electrically-insulating material 146 of the stack-up is at least partially disposed between the ultra-wide trace 120A and the second return conductor 144. The third electrically- insulating material 146 has a third dielectric constant (En) 132C (which may be the same or different as the first dielectric constant Eri of the first electrically-insulating material 124), and has a third thickness 134C (which may be the same or different as the first thickness 134A of the first electrically-insulating material 124).

[0078] In the stripline configuration shown in FIG. 6, the characteristic impedance of the PCB RF transmission line 130 is based at least in part on the width 122 of the ultra-wide trace 120A, the thickness 118 of the ultra- wide trace, the first dielectric constant 132A of the first electrically-insulating material 124, the first thickness 134A of the first electrically-insulating material, the third dielectric constant 132C of the third electrically-insulating material, and the third thickness 134C of the third electrically-insulating material. In a manner similar to that discussed above in connection with FIG. 3, one or more of the foregoing parameters is selected such that the characteristic impedance of the PCB RF transmission line 130 is less than or equal to 10 ohms (or less than or equal to 5 ohms, or less than or equal to 2 ohms).Attorney Docket No.: BRLN-008W001(0079] FIG. 7 shows a cross-sectional view of a multilayer PCB 100 similar to that shown in FIG. 6, in which one or more additional outer layers of the multilayer PCB are employed to facilitate electrical connections to the PCB RF transmission line according to inventive example implementations. In the example of FIG. 7, the stack-up 110 further comprises a fourth layer 116 (e.g., comprising fourth copper) and a second electrically-insulating material 136 at least partially disposed between the fourth layer 116 and the second layer 114. The ultrawide trace 120A is electrically coupled to the fourth layer 116 by one or more first vias 154. In one aspect, the first via(s) 154 traverse(s) the first electrically-insulating material 124 and the second electrically-insulating material 136, as well as a small portion of the first return conductor 126 on the second layer 114; to this end, as can be seen in FIG. 7, some of second electrically-insulating material 136 surrounds a portion of the depicted first via 154 and insulates the first via from the first return conductor 126. The fourth layer 116 shown in FIG. 7 constitutes a first outer layer of the stack-up 110. In one aspect, the fourth / outer layer includes one or more first contact portions 156A (shown with light dotted fill) coupled to the first via(s) 154 to facilitate electrical connection to the ultra-wide trace 120A of the PCB RF transmission line 130.(0080] The Inventors have recognized and appreciated that at least one design and fabrication advantage of the ultra-wide trace 120A as well as the return conductors is that small holes drilled through these conductors during fabrication to create one or more vias (e.g., the first via 154 shown in FIG. 7, passing through the second layer 114 in which the first return conductor 126 is formed) can be accommodated without significant impact on the controlled-impedance of the conductors; furthermore, as discussed above, using a copper flood to define an ultrawide trace instead of a conventional software trace (which does not permit for ultra-wide traces of the widths contemplated herein) allows formation of the ultra-wide trace to automatically accommodate insulating voids around vias through the trace as may be required by a particular design (e.g., as seen in FIG. 7).(0081] As also shown in FIG. 7, the first return conductor 126 on the second layer 114 is electrically coupled to the second return conductor 144 on the third layer 142 by one or more second vias 152 that traverse(s) both the first electrically-insulating material 124 and the third electrically-insulating material 146. In the example of FIG. 7, the third layer 142 in which the second return conductor 144 is formed is already an outer layer of the depicted stack -up 110 (i.e., a second outer layer); accordingly, an electrical connection to the second return conductor 144 may be readily made (e.g., via a variety of electrical contact techniques that would beAttorney Docket No.: BRLN-008W001 readily appreciated by one of skill in the art). For example, the third / outer layer 142 may include one or more second contact portions 156B (shown with light dotted fill) to facilitate electrical connection to the first and second return conductors of the PCB RF transmission line 130.[00821 FIG. 7 also shows a bottom soldermask 172 (dark gray hatching) disposed on the first outer layer (i.e., the fourth layer 116) of the stack-up 110, and a top soldermask 176 (dark gray hatching) disposed on the second outer layer (i.e., the third layer 142) of the stack-up 110. As discussed above, soldermasks are applied over the outermost (e.g., top and bottom) conductive layers of a multilayer PCB as a protective layer to prevent short circuits and corrosion, as well as to define points of electrical connection to the multilayer PCB 100 (e.g., where the soldermask is selectively patterned and removed). More specifically, a soldermask is a photosensitive material that is applied to an outer layer, dried, and developed (e.g., exposed to light in a particular pattern), such that portions of the soldermask (e.g., corresponding to one or more electrical contact points on the outer layer) may be washed away. In this manner, specific portions of the soldermask are removed, thereby allowing access to the electrical contact point(s) on the outer layer beneath (contiguous with) the soldermask. With the foregoing in mind, FIG. 7 shows that the bottom soldermask 172 has been developed with a pattern so as to provide for a first opening 174 to allow access to the first contact portion 156A formed in the fourth layer 116. Similarly, the top soldermask 176 has been developed with a pattern so as to provide for a second opening 178 to allow access to the second contact portion 156B formed in the third layer 142 (together with the second return conductor 144).(0083] In general, the number and respective shapes of contacts on a given outer layer of a multilayer PCB (and corresponding openings in a soldermask to allow access to an outer layer) that facilitate electrical connection to a PCB RF transmission line 130 according to various example implementations disclosed herein may depend, at least in part, on the application(s) for which the transmission line 130 is being employed. For example, one application for which a PCB RF transmission line according to the inventive concepts disclosed herein may be employed relates to a cylindrical catalytic tube for heat-generating reactions, as described for example in U.S. Publication 2025 / 0369653, published December 4, 2025, entitled “Heating System and Methods,” which publication is incorporated herein by reference in its entirety (hereafter referred to as the “’653 Publication”).

[0084] In one disclosed example, the ‘653 Publication discusses a transmission line implemented on a PCB (e.g., see FIG. 4B of the ‘653 Publication and associated text in theAttorney Docket No.: BRLN-008W001 publication) that is coupled to a cylindrical catalytic tube having a coaxial transmission line running along a length of the catalytic tube (e.g., see FIG. 4A, 5, 6A and 6B of the ‘653 Publication and the associated text in the publication). The transmission line implemented on the PCB in the ‘653 application is employed to apply a series of high-current / high-voltage pulses to the coaxial transmission line along the catalytic tube. The ‘653 Publication explains that the transmission line implemented on the PCB may be connected to annular contacts located on opposing surfaces of the PCB for making electrical connections to the coaxial transmission line running along the cylindrical catalytic tube (e.g., when the coaxial transmission line of the catalytic tube is physically mated to the annular contacts coupled to the transmission line implemented on the PCB).

[0085] With the foregoing in mind, a PCB RF transmission line 130 according to the inventive concepts disclosed herein may serve as one example of a planar PCB RF transmission line that may be coupled to a coaxial transmission line (e.g., as employed in the catalytic tube of the ‘653 publication). To this end, one or more of the outer layers of a multilayer PCB in which the PCB RF transmission line 130 is implemented, as well as one or more corresponding soldermasks, may include an annular or circular contact portion (and / or an annular or circular opening in a corresponding soldermask) to facilitate electrical connection between the respective conductive elements of the planar PCB RF transmission line 130 and corresponding conductive elements of a coaxial transmission line.

[0086] For example, with reference again to FIG. 7, the contact portion 156A formed in the fourth layer 116 constituting the first outer layer of the stack-up 110 may comprise an annular or circular first contact portion to facilitate electrical connection to the ultra- wide trace 120 A of the PCB RF transmission line 130 (e.g., and thereby facilitate electrical connection between the ultra-wide trace 120A and one of the conductors of a coaxial transmission line). Additionally, the first opening 174 in the bottom soldermask 172 may be an annular or circular first opening substantially corresponding to (e.g. overlapping along the z-axis with) the annular or circular first contact portion 156A.

[0087] Similarly, the third layer 142 in which the second return conductor 144 is formed (which constitutes the second outer layer of the stack-up 110) may comprise an annular or circular second contact portion 156B to facilitate electrical connection to the first and second return conductors 126 and 144 of the PCB RF transmission line 130 (e.g., and thereby facilitate electrical connection between these return conductors and another of the conductors of a coaxial transmission line). Additionally, the second opening 178 in the top soldermask 176Attorney Docket No.: BRLN-008W001 may be an annular or circular second opening substantially corresponding to (e.g. overlapping along the z-axis with) the annular or circular second contact portion 156B on the second outer layer.

[0088] To illustrate an example of an annular or circular contact portion on an outer layer of a multilayer PCB, FIG. 8 shows a bottom-up view (i.e., in the x-y plane) of at least a portion of the multilayer PCB of FIG. 7. It should be appreciated that the bottom-up view of FIG. 8 is created using respective Gerber files for the fourth (outer) layer (shown in black) and the first layer (shown in gray) of the stack-up 110; accordingly, other layers of the PCB stack-up of FIG. 7 (as well as the soldermasks) are not reflected in FIG. 8. As shown in FIG. 8, the first contact portion 156A formed in the fourth layer 116 (the first outer layer of the stack-up, shown in FIG. 8 in black and dark gray hatching) is illustrated as a annular first contact portion 156A, superimposed on the ultra-wide impedance-controlled trace 120A on the first layer of the stack- up (shown in FIG. 8 in gray).

[0089] FIG. 8 also shows multiple first vias 154 that electrically connect the annular first contact portion 156A on the fourth / outer layer to the ultra-wide trace 120A on the first layer. More specifically, FIG. 8 shows eight sets of first vias 154 distributed around a circumference of the annular first contact portion 156A and electrically connected to the annular first contact portion by multiple conductive first “lugs” 155 A (outward extensions) of the annular first contact portion 156A. FIG. 8 also shows other sets of second vias 152 alternating between respective first lugs 155 A and the first vias 154 and electrically insulated from the annular first contact portion 156A and the first lugs 155A / first vias 154; these sets of second vias 152 functionally correspond to the second via 152 shown in FIG. 7 that electrically interconnects the first return conductor 126 and the second return conductor 144 of the PCB transmission line 130 (the second vias 152 shown in FIG. 8 are discussed further below in connection with FIG. 11 A and FIG. 1 IB). It should be appreciated that the particular arrangement of the first vias 154 and the second vias 152 shown in the bottom-up view of FIG. 8 does not precisely correspond to the cross-sectional view of FIG. 7. Instead, FIG. 7 conceptually illustrates at least one first via 154 electrically interconnecting the first contact portion 156 and the ultra-wide trace 120A, and at least one second via 152 electrically interconnecting the first return conductor 126 and the second return conductor 144; however, FIG. 7 is not intended to illustrate in cross-section the particular arrangement of multiple first vias 154 and multiple second vias 152 specifically shown in the more detailed example of FIG. 8 (and discussed further below in connection with FIG. 11 A and FIG. 1 IB).Attorney Docket No.: BRLN-008W001

[0090] FIG. 9 shows another bottom -up view of the multilayer PCB 100 of FIG. 7, illustrating the bottom soldermask 172 with a circular first opening 174 (shown as a large black circle), superimposed on the fourth / outer layer (in which the annular first contact portion 156A is formed), which is in turn superimposed on the first layer (in which the ultra-wide impedance- controlled trace 120A is formed). As with FIG. 8, it should be appreciated that the bottom-up view of FIG. 9 is created using respective Gerber files for the bottom soldermask (shown in white and black), as well as the fourth / outer layer and the first layer (both shown in gray); accordingly, other layers of the PCB stack-up of FIG. 7 are not reflected in FIG. 9. More specifically, in FIG. 9 the soldermask 172 is shown in white (to the extent of an outer edge of the multilayer PCB 100), with black circles (including the circular first opening 174) and squares representing openings in the soldermask (to provide access to electrical contact points on the fourth / outer layer contiguous with the bottom soldermask 172). As noted above, in FIG. 9 the fourth / outer layer itself and the underlying first layer are both shown in light gray.[00911 From FIG. 8 and FIG. 9, it may be readily appreciated that a similar arrangement for an annular or circular second contact portion 156B in the third / outer layer 142 on the opposite side of the stack-up 110, as well as an annular or circular second opening 178 in the top soldermask 176 shown in FIG. 7, may be provided on the other side of the multilayer PCB 110 opposite to that shown in FIG. 8 and FIG. 9 (i.e., the top side). In this manner, two annular or circular electrical contacts may be provided on opposite sides of the multilayer PCB 100 to facilitate electrical connection between the planar PCB RF transmission line 130 (multiple examples of which are disclosed herein) and a coaxial transmission line (e.g., as described in the ‘653 Publication in connection with a cylindrical catalytic tube).

[0092] To provide an illustrative conceptual example, FIG. 10 is a stylized drawing showing a catalytic tube 170 having a coaxial transmission line (e.g., as described in the ‘653 Publication) being coupled to a multilayer PCB 100 according to the inventive concepts disclosed herein. A particular mechanical coupling arrangement in which the catalytic tube 170 is orthogonally joined to a PCB is shown and described in connection with FIGS. 4A-4E, 6A and 6B of the ’653 Publication; in the described examples, the coaxial transmission line of the catalytic tube 170 is electrically coupled to a transmission line on a PCB via two conductive collets. More generally, it may be appreciated from both FIG. 10 (as well as the non-limiting examples provided in the ‘653 Publication) that the inventive concepts disclosed herein provide for effective coupling of respective RF transmission lines having significantly different geometries. For example, a planar ultra-low impedance PCB RF transmission line 130Attorney Docket No.: BRLN-008W001 including at least one ultra-wide impedance controlled trace 120A may be effectively coupled to an ultra-low impedance coaxial transmission line according to the inventive concepts disclosed herein.

[0093] FIG. 11 A illustrates an enlarged view of the annular first contact portion 156A shown in FIG. 8, which is formed in the bottom outer layer (i.e., the fourth layer 116) of the multilayer PCB shown in cross-section in FIG. 7. As discussed above in connection with FIG. 8 and shown in greater detail in FIG. 11 A, the annular first contact portion 156A includes multiple conductive first lugs 155 A that extend outward from an annulus of the annular first contact portion 156A and are distributed around a circumference of the annulus. Each of the first lugs 155 A overlaps with (and thereby electrically connects to) a corresponding set of first vias 154. Each of the first vias 154 in each set of vias electrically couples the annular first contact portion 156A to the first layer 112 of the stack-up 110 (in which the ultra-wide trace 120A is formed). As discussed above, an example first via 154 is conceptually shown in the cross-sectional view of FIG. 7. In FIG. 11 A, each set of first vias 154 is shown as including eight first vias; however, it should be appreciated that a given set of first vias 154 may have a different number of first vias than what is shown in FIG. 11 A.

[0094] FIG. 11A also shows multiple sets of second vias 152 that appear in the bottom outer layer (i.e., the fourth layer 116) of the multilayer PCB 100 according to one example implementation. These sets of second vias 152 are not electrically coupled to the annular first contact portion 156 A; rather, they are distributed around the circumference of the annulus of the annular first contact portion 156A in an alternating manner with the respective first lugs 155 A and corresponding sets of first vias 154 and electrically insulated from the first lugs 155A / first vias 154. In FIG. 11 A, as with the first vias 154, each set of second vias 152 is shown as including eight second vias; however, it should be appreciated that a given set of second vias 152 may have a different number of second vias than what is shown in FIG. 11 A.

[0095] As discussed above, an example second via 152 is conceptually shown in the cross- sectional view of FIG. 7. As may be observed in the outer / fourth layer 116 of the cross- sectional view of FIG. 7, the example second via 152 is adjacent to the annular first contact portion 156A in the outer / fourth layer 116 (and similarly adj acent to the example first via 154), but nonetheless is electrically insulated from the annular first contact portion 156A and the first via 154 by the second electrically-insulating material 136.Attorney Docket No.: BRLN-008W001

[0096] FIG. 1 IB illustrates an enlarged view of an annular second contact portion 156B that is formed in the top outer layer (i.e., the third layer 142) of the multilayer PCB shown in crosssection in FIG. 7, according to one example implementation (accordingly, the annular second contact portion 156B shown in FIG. 1 IB is not visible in the bottom-up view of FIG. 8, as it is on the opposite outer layer of the multilayer PCB). As discussed above in connection with FIG. 7, the annular second contact portion 156B provides for electrical connection to the second return conductor 144, which is in turn electrically connected to the first return conductor 126 of the PCB RF transmission line 130 by the example second via 152. As shown in FIG. 1 IB, the annular second contact portion 156B includes multiple conductive second lugs 155B that extend outward from an annulus of the annular second contact portion 156B and are distributed around a circumference of the annulus. Each of the second lugs 155B overlaps with (and thereby electrically connects to) a corresponding set of second vias 152. Each of the second vias 152 in each set of vias electrically couples the annular second contact portion 156B to the third layer 142 and the second layer 114 of the stack-up 110 (in which the second and first return conductors respectively are formed).

[0097] FIG. 11B also shows multiple sets of first vias 154 that appear in the top outer layer (i.e., the third layer 142) of the multilayer PCB 100 according to one example implementation. These sets of first vias 154 are not electrically coupled to the annular second contact portion 156B; rather, they are distributed around the circumference of the annulus of the annular second contact portion 156B in an alternating manner with the respective second lugs 155B and corresponding sets of second vias 152 and electrically insulated from the second lugs 155B / second vias 152.

[0098] As discussed above, an example first via 154 is conceptually shown in the cross- sectional view of FIG. 7. As may be observed in the outer / third layer 142 of the cross-sectional view of FIG. 7, the example first via 154 is adjacent to the annular second contact portion 156B in the outer / third layer 142 (and similarly adjacent to the example second via 152), but nonetheless is electrically insulated from the annular second contact portion 156B and the second via 152 (as well as the second return conductor 144) by the third electrically-insulating material 146.

[0099] It should be appreciated that, in one example implementation, the annular first contact portion 156A shown in FIG. 11 A and the annular second contact portion 156B shown in FIG. 11B overlap along a z-axis through the multilayer PCB 100 (e.g., as if FIG. 11A were superimposed over FIG. 1 IB). In this manner, it may be readily understood that each first viaAttorney Docket No.: BRLN-008W001154 and each second via 152 traverses all of the layers of the stack-up 110, as shown for example in the cross-sectional view of FIG. 7 (i.e., there are no “blind vias” implemented in the stack-up 110 in this example implementation).

[0100] The arrangement of respective sets of multiple vias distributed around the annular first contact portion 156A and the annular second contact portion 156B shown in FIG. 11A and FIG. 1 IB facilitates increased current-carrying capability between the respective conductors of the PCB RF transmission line 130 and corresponding conductors of another transmission line electrically coupled to the first annular contact portion 156A and the second annular contact portion 156B. Accordingly, the configurations shown in FIG 11A and FIG. 11B are particularly well-suited for applications that require the transmission line to carry high current / high-power RF signals. Additionally, the arrangement of respective sets of multiple vias distributed around and proximate to the annular first contact portion 156A and the annular second contact portion 156B also facilitates impedance-matching (and, more particularly, impedance-matching in an ultra-low characteristic impedance regime) between the planar PCB RF transmission line 130 and another transmission line of a different geometry (e.g., a coaxial transmission line). In one aspect, the regular and even distribution of respective conductors provided by the dense and alternating / interleaved arrangement of first vias and second vias shown in FIG. 11 A and FIG. 1 IB, and their proximity to the respective annuli of the annular contact portions 156A and 156B, mitigates significant impedance discontinuities arising from physical and / or material disruptions in the signal path (as informed, at least in part, by conceptual current tracing and capacitance tuning). Thus, for at least the foregoing reasons, the respective configurations of the annular first contact portion 156A and the annular second contact portion 156B (including the alternating distributions of the sets of first and second vias around the circumferences of the respective annuli of the annular contact portions) provide a novel, advantageous, compact and readily-fabricated technique for providing an impedance- matched interconnection, with significant current-carrying capability, between the planar PCB RF transmission line 130 and another transmission line of a different geometry (e.g., a coaxial transmission line as discussed above).

[0101] For completeness, FIG. 11C illustrates the first opening 174 in the bottom soldermask of the multilayer PCB of FIG. 7 to allow access to the annular first contact portion 156A shown in FIG. 11 A. Similarly, FIG. 1 ID illustrates the second opening 178 in the top soldermask of the multilayer PCB of FIG. 7 to allow access to the annular second contact portion 156B shown in FIG. 1 IB. In a manner similar to that shown in FIG. 9, in FIGS. 11C and 1 ID the circularAttorney Docket No.: BRLN-008W001 first opening 174 and circular second opening 178 are shown in black, whereas the underlying annular first contact portion 156A and annular second contact portion 156B are shown in gray.(0102] In connection with the types of signals that may be carried by different examples of the inventive PCB RF transmission lines 130 disclosed herein (and particularly in connection with the application of the catalytic tube disclosed in the ‘653 Publication), the ultra-wide trace 120 A (and hence the PCB RF transmission line 130) may be configured to carry a radio frequency (RF) signal having a peak current in a range from approximately or equal to 10 Amperes to approximately or equal to 300 Amperes. Additionally, such an RF signal may have a peak voltage in a range from approximately or equal to 20 Volts to approximately or equal to 600 Volts. In another aspect, such an RF signal may comprise one or more frequencies over a range of frequencies (e.g., a power spectral density) from approximately 100 kHz to 1 GHz. Accordingly, it may be appreciated that the ultra-low impedance PCB RF transmission lines 130 disclosed herein are particularly well-suited for applications that may require both high bandwidth spectral content at high frequencies, as well as high-current / high-voltage / high- power signaling.(0103] FIG. 12 illustrates a cross-sectional view of another example of a multilayer PCB 100- 1 according to the inventive concepts disclosed herein. The multiplayer PCB 100-1 of FIG. 12 comprises a stack-up 110 having six conductive layers (designated generically in the figure by LI, L2, L3, L4, L5 and 1.6), in which multiple ultra-wide impedance-controlled traces 120 A and 120B are formed, together with two return conductors 126 and 144, to provide a modified stripline ultra-low impedance PCB RF transmission line 130.(0104] In the following discussion of FIG. 12, ordinal adjectives for respective layers of the stack-up 110 build upon the previous description above of implementation examples involving four-layer stack-ups 110. Accordingly, whereas the first layer 112 of the four-layer stack-up shown in FIGS. 3, 4, 6 and 7 corresponds to the generic level designation L2 of the four-layer stack-up, the first layer 112 of the six-layer stack-up shown in FIG. 12 (in which the first ultrawide trace 120A is formed) instead corresponds to the generic level designation L4 in the six- layer stack-up. Similarly, the second layer 114 corresponds to the generic level designation L5 in the six-layer stack up (as opposed to generic level designation L3 in the four-layer stack-up), the third layer 142 corresponds to the generic level designation L2 in the six-layer stack-up (as opposed to the generic level designation LI in the four-layer stack-up), and the fourth layer 116 corresponds to the generic level designation L6 in the six-layer stack-up (as opposed to the generic level designation L4 in the four-layer stack-up). Respective elements that appear inAttorney Docket No.: BRLN-008W001 the various examples of a four-layer stack-up discussed above and that also appear in the six- level stack-up shown in FIG. 12 are designated with the same reference numbers.(0105] With reference now to FIG. 12, and building upon what has been already described above in connection with FIG. 7, the six-level stackup shown in FIG. 12 further includes a fifth layer 148 (e.g., comprising fifth copper), and a fourth electrically-insulating material 150 at least partially disposed between the fifth layer 148 and the first layer 112. As can be seen in FIG. 12, the multilayer PCB 100-1 further comprises a second ultra-wide impedance-controlled copper trace 120B formed in the fifth layer 148 of the stack-up. Accordingly, the PCB RF transmission line 130 comprises the first ultra-wide trace 120A, the second ultra-wide trace 120B, the first return conductor 126, and the second return conductor 148. In the example depicted in FIG. 12, the second ultra- wide trace 120B has the same width 122 as the first ultrawide trace 120A (and the same thickness 118 as the first ultra-wide trace 120A).(0106] In the configuration shown in FIG. 12, the characteristic impedance of the PCB RF transmission line 130 is based at least in part on the width 122 of the first ultra-wide trace 120A and the second ultra-wide trace 120B, the thickness 118 of the first ultra-wide trace, the first dielectric constant 132A of the first electrically-insulating material 124, the first thickness 134A of the first electrically-insulating material, the third dielectric constant 132C of the third electrically-insulating material 146, the third thickness 134C of the third electrically-insulating material, a fourth dielectric constant 164 of the fourth electrically-insulating material, and a fourth thickness 166 of the fourth electrically-insulating material. In one aspect, one or more of the foregoing parameters is selected such that the characteristic impedance of the PCB RF transmission line 130 is less than or equal to 10 ohms (or less than or equal to 5 ohms, or less than or equal to 2 ohms).|0t07| In a manner similar to that shown in the cross-sectional view of FIG. 7, in the six-layer stack-up 110 shown in FIG. 12, the respective return conductors 126 and 144 are electrically interconnected by one or more second vias 152. Notably, however, in the configuration shown in FIG. 12, the respective ultra-wide traces 120 A and 120B are electrically interconnected by one or more first vias 154. As in FIG. 7, in FIG. 12 the fourth layer 116 constitutes a first outer layer of the stack-up and comprises the first contact portion 156 A coupled to at least the first via 154 to facilitate electrical connection to the first ultra-wide trace 120 A and the second ultrawide trace 120B. As discussed above in connection with FIGS. 8, 9, and 11 A, in some examples the first contact portion 156A may be an annular first contact portion to facilitate the electrical connection to the first and second ultra-wide traces. FIG 12 also shows a bottomAttorney Docket No.: BRLN-008W001 soldermask 172, in which a first opening 174 is made to allow access to the first contact portion 156A (e.g., in a manner similar to that discussed above in connection with FIGS. 7, 9 and 11C). As with the example four-layer stack-up discussed above, an annular first contact portion 156A may have an annulus, multiple lugs, and corresponding sets of vias distributed around the annulus, and the first opening 174 may be annular or circular.

[0108] In FIG.12, the stack-up 110 further comprises a sixth layer 158 (e.g., comprising sixth copper), and a fifth electrically-insulating material 160 at least partially disposed between the sixth layer 158 and the third layer 142. The sixth layer constitutes a second outer layer of the stack-up 110 and comprises at least the second contact portion 156B. As can be seen in FIG. 12, the second contact portion 156B is coupled to the second via 152 to facilitate electrical connection to the first return conductor 126 and the second return conductor 144. FIG. 12 also shows a top soldermask 176, in which a second opening 178 is made to allow access to the second contact portion 156A (e.g., in a manner similar to that discussed above in connection with FIGS. 7, 9 and 1 ID). As shown in FIG. 1 IB, in one example the second contact portion 156B may be an annular second contact portion. As with the example four-layer stack-up discussed above, an annular second contact portion 156B may have an annulus, multiple lugs, and corresponding sets of vias distributed around the annulus, and the second opening 178 may be annular or circular.

[0109] Although multiple salient aspects of the discussion above involve ultra-wide impedance-controlled traces and / or ultra-low characteristic impedance PCB transmission lines, the Inventors have recognized and appreciated that the modified stripline transmission line configuration shown in FIG. 12 provides multiple novel advantages, irrespective of the width of respective traces and range of characteristic impedance.

[0110] For example, the design of a transmission line using a six-layer stack-up, with two inner layers of the stack-up electrically coupled together as the “signal” conductors of the transmission line, allows for a “dielectrically-balanced” implementation. With reference again for the moment to the stripline configuration shown in the four-layer stack-up of FIG. 6, the intervening electrically-insulating materials 124 and 146, between the center “signal” conductor (the trace 120A) and the respective return conductors 126 and 144, are different and may have correspondingly different dielectric constants 132 A (Eri) and 132C (En). More specifically, in one example implementation of the four-layer stack-up shown in FIG. 6, the electrically-insulating material 124 may be core and the electrically-insulating material 146 may be prepreg. As discussed above, core is a substantially rigid layer providing a dielectricAttorney Docket No.: BRLN-008W001 substrate with mechanical strength, whereas prepreg is more flexible and becomes somewhat more hardened under heat and pressure (which may alter one or more of its thickness or dielectric constant). Thus, there is an explicit asymmetry in the overall structure of the stripline transmission line configuration shown in FIG. 6, which may in some instances give rise to some degree of variability (e.g., given the different natures of core and prepreg as dielectic materials) as well as asymmetric current flow (e.g., in the respective return conductors).[01 / 1.1] Returning now to FIG. 12, the Inventors have recognized and appreciated that a six- layer stack-up provides for a dielectrically-balanced transmission line design. More specifically, in one example implementation, the electrically-insulating material 124, between the first trace 120 A (a first “signal” conductor) and the first return conductor 126, as well as the electrically-insulating material 146 between the second trace 120B (a second “signal” conductor) and the second return conductor 144, both may be core and have the same dielectric constant (i.e., Eri = En). The thickness and dielectric constant of core is relatively more stable and predictable during the fabrication process, thus arguably leading to more predictable outcomes in target characteristic impedance. Also, the symmetrical arrangement of core as the dielectric material between each signal conductor and a corresponding return conductor arguably provides for a more symmetric current flow in the respective return conductors. Additionally, in one example, the electrically-insulating material 164 between the first trace 120 A (the first “signal” conductor) and the second trace 120B (the second “signal” conductor) may be prepreg. Even though the dielectric constant and / or thickness of this prepreg may vary to some extent during fabrication, arguably any such variation would have an attenuated affect on the resulting characteristic impedance of the transmission line (as the first signal conductor and the second signal conductor are electrically interconnected). Thus, the dielectrically- balanced design of FIG. 12 may not only facilitate a more balanced current flow in the respective conductors, but may further facilitate a more predictable characteristic impedance (across multiple manufacturing runs).

[0112] Another prospective advantage of the six-layer stack-up shown in FIG. 12 for a modified stripline transmission line design involving two signal conductors relates to increased current-carrying capability. In some examples, the increased current-carrying capability relates, at least in part, to the well-known “skin effect” arising from RF signals carried on the transmission line. As known in the relevant arts, the “skin effect” is an alternating-current (AC) phenomenon where, at relatively higher frequencies, current concentrates near a conductor's surface rather than in the center of the conductor. This occurs because the changingAttorney Docket No.: BRLN-008W001 magnetic field induces opposing currents (eddy currents) inside the conductor, thereby increasing resistance and power loss, especially at higher frequencies - essentially, the conductor behaves as if it has a smaller cross-section.

[0113] With reference again to FIG. 6 and the four-layer stack up, in the depicted stripline configuration of FIG. 6 there is only one center conductor (the “signal” conductor), i.e., the trace 120A. When this “signal” conductor carries an RF signal (particularly at relatively higher frequencies), the current in the trace 120 A will in some instances be concentrated more along the bottom surface of the trace 120 A (i.e., facing the first return conductor 126) as well as the top surface of the trace 120 A (i.e., facing the second return conductor 144). In contrast, in the configuration shown in FIG. 12 in which there are two signal conductors electrically coupled together (i.e., the trace 120A and the trace 120B), current in the trace 120A will in some instances be concentrated along the bottom surface of the trace (i.e., facing the first return conductor 126), but generally not along the top surface of the trace 120 A (which faces the other signal trace 120B). Similarly, current in the trace 120B will be concentrated along the top surface of the trace (i.e., facing the second return conductor 144), but generally not along the bottom surface of the trace 120B (which faces the other signal trace 120A). Accordingly, it may be appreciated from the foregoing that the respective signal conductors in the configuration of FIG. 12 (i.e., the traces 120A and 120B) each may carry on the order of half of the current that would otherwise be carried on both the top and bottom surfaces of the single signal trace in the configuration shown in FIG. 6.

[0114] Thus, for at least the foregoing reasons, it may be appreciated that the modified stripline transmission line configuration shown in FIG. 12 (e.g., involving two electrically-connected signal traces on respective inner layers of a multilayer stack-up) provides multiple novel advantages, irrespective of the specific width of the respective traces serving as signal conductors (i.e., even if the width of the traces falls within a conventional range of impedance- controlled traces on the order of 5-20 mils), and irrespective of the characteristic impedance of the transmission line (i.e., even if the characteristic impedance falls within a conventional range of 25 ohms or above). Of course, it may be appreciated from the disclosure herein that these and other possible advantages may be provided in example implementations involving ultra-wide impedance controlled traces and / or ultra-low characteristic impedance transmission lines. It should further be appreciated that although the example of a modified stripline transmission line involving two signal conductors was shown in FIG. 12 using a six-layer stack- up, a similar configuration of two electrically-connected signal conductors on respective innerAttorney Docket No.: BRLN-008W001 layers of a stack-up, surrounded by respective return conductors, similarly may be implemented in a four-layer stack-up (e.g., similar to that shown in FIGS. 3, 4, 6 and 7), or a stack-up having more than six layers.

[0115] With reference again for the moment to FIG. 1 and FIG. 2, as discussed above a variety of different stack-ups are available from different PCB manufacturers for different numbers of layers (e.g., four layers, six layers, eight layers) and different types of PCB design applications. FIG. 1 shows one example of a four-layer stack-up available from a conventional PCB manufacturer, and FIG. 2 shows another example of a six-layer stack-up available from a conventional PCB manufacturer (different PCB manufacturers may offer different stack-ups). As also discussed above, FR4 and FR4 variants are common dielectric materials used in a variety of stack-ups, and generally have a dielectric constant in a range of from approximately 3.7 to 4.8 (other types of specialty dielectric materials, as discussed above, may be employed in different examples of conventionally available stack-ups or customized stack-ups available from different PCB manufacturers).

[0116] One non-limiting example of a stack-up that may be used to implement the embedded microstrip configuration shown in FIG. 3 or FIG. 4, the stripline configuration shown in FIG. 6 and FIG. 7, as well as the modified stripline configuration shown in FIG. 12 is provided below for purposes of illustration as Table 1.Attorney Docket No.: BRLN-008W001Table 1

[0117] Although Table 1 shows a six-layer stack-up, only four of the indicated layers may be employed to fabricate the configurations shown in FIG. 3, FIG. 4, FIG. 6 and FIG. 7 (and all six layers are employed to fabricate the configuration shown in FIG. 12). Based on the stack- up given in Table 1, various samples of microstrip, stripline and modified stripline configurations of PCB transmission lines according to the inventive concepts disclosed herein have been fabricated, in which selected widths have been chosen for a given ultra-wide trace in a range of from about 5 millimeters to 30 millimeters (e.g., 12.5 mm, 18.5 mm 22 mm), resulting in characteristic impedances for the fabricated transmission lines generally in a range of from about 1.5 ohms to 3 ohms. FIG. 13 shows another example of a customized six-layer stack-up involving one or more blind vias, which has been used to fabricate multiple samples of the modified stripline configuration shown in FIG. 12 (as well as an alternative arrangement of first vias 154 and second vias 152, which exploit the blind vias, for the respective contact portions on the outer layers of the stack-up). Using the stack-up of FIG. 13, similar widths for ultra-wide traces as noted above provided similar characteristic impedance results. Additional samples of PCB RF transmission lines according to the inventive concepts disclosed herein and fabricated using the custom stack-up of FIG. 13 are shown and described in U.S. Provisional Application Serial No. 63 / 730,433, filed December 10, 2024, entitled “Printed Circuit Boards Including Impedance-Controlled Traces for Significantly Low Impedance Applications and Methods for Fabricating Same,” which is hereby incorporated herein by reference in its entirety (and to which the present application claims a priority benefit).

[0118] As noted above, the Inventors also have recognized and appreciated that conventional PCB design software tools do not contemplate the specification of trace widths in the ranges for the impedance-controlled ultra-wide traces considered according to the concepts disclosed herein (e.g., 195-1180 mils or 5-30 millimeters). Similarly, conventional PCB manufacturers presently would not consider designing or building a controlled-impedance PCB with the characteristic impedances contemplated herein (e.g., 10 ohms or less). Multiple examples of conventional PCB transmission line impedance calculators (e.g., available online from various sources) provide non-sensical answers for characteristic impedance (e.g., a negative characteristic impedance) when provided with ultra-wide trace widths for transmission line conductors in the ranges contemplated herein. Thus, the Inventors have fashioned unconventional techniques for using conventional PCB design software tools to facilitate implementation of ultra-wide traces in PCB designs; furthermore, they have also developedAttorney Docket No.: BRLN-008W001 unconventional characteristic impedance calculators for ultra-low impedance PCB transmission lines, relying on alternative approximations of Maxwell’s Equations that are better-adapted to the ranges of ultra-wide trace widths and ultra-low impedances contemplated herein.|O119| For example, to implement an ultra-wide trace according to the inventice concepts disclosed herein using conventional PCB software tools (e.g, KiCAD, Eagle, or Altium Designer), the Inventors needed to particularly specify the ultra-wide trace not as a trace but rather as a plane, as the conventional PCB software tools generally limit power distribution trace widths (not for controlled-impedance) to a maximum of 250 mils (6.35 millimeters). To this end, the Inventors instead use the PCB software tool to specify an ultra-wide trace by outlining a plane having particular dimensions based at least in part on a target characteristic impedance, the copper thickness, the distance of the plane / ultra-wide trace from a ground plane or a ground trace, and the dielectric constant of the PCB insulating material (e.g., core, prepreg or other specialty dielectric material) between the plane / ultra-wide trace and the ground plane / ground trace. The PCB software tool then creates a copper flood based on the specified outline of the plane. Accordingly, an ultra-wide trace according to the concepts disclosed herein may advantageously exploit attributes of a copper flood (e.g., including the particular clearances around vias, pads, or other conductive features that are in or traverse the area designated by the designer for the plane, as specified by corresponding design rules for copper floods). According to yet another aspect, in some examples the Inventors specify one or more additional planes on one or more layers of the PCB, in addition to those serving as an ultrawide trace, and thereby use copper floods in these additional planes to balance the copper distribution from layer-to-layer. Such a layer-to-layer balancing of copper distribution in the multilayer stack-up may in some examples improve impedance consistency, PCB manufacturability, and durability (e.g., by preventing warping of the PCB).|0120] The Inventors have also recognized and appreciated that the ultra-wide traces and ultralow impedance PCB transmission line concepts disclosed herein may bring specific advantages to a variety of applications that require high-bandwidth and / or high frequency signals and also have significant current and / or power requirements. One example of a high-bandwidth and high-power application that may benefit from the ultra-wide traces and / or ultra-low impedance PCB transmission lines according to the concepts disclosed herein has already been discussed above in connection with FIG. 10, and includes a heat generation system in which a catalyst is stimulated with a high-bandwidth and high-power signal (e.g., a series of intense currentAttorney Docket No.: BRLN-008W001 spikes) to facilitate heat-generating reactions (e.g., arising from increased phonon activity in the catalysts as a result of the applied high-bandwidth / high-power signal). Other example applications include, but are not limited to, power amplifiers (e.g., for RF and microwave cellular base stations), laser-drivers (e.g., for long distance signal transmission, including repeaters), power LIDAR systems, electric vehicles (e.g., power distribution and signal routing in battery management systems, and high-power signal lines in EV inverters), industrial automation and robotics (e.g., motor controllers, industrial power supplies and actuators for factory automation systems), renewable energy systems (pulsed power and fusion applications), medical equipment (e.g., high-powered MRI imaging systems that require both high power and significant signal integrity for sensitive imaging functions), RF testing equipment (e.g., time domain reflectometry systems), fuel cells and hydrogenation catalysts (e.g., involving high-frequency and high-power phonon stimulation).

[0121] More specifically, FIG. 14 shows a cellular base station 400 that includes one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance- controlled trace 120A, according to the inventive concepts disclosed herein. As shown in FIG. 14 by way of example, one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra- wide impedance-controlled trace 120 A may be employed in one or more power amplifiers or low-noise amplifiers of the cellular base station 400.

[0122] FIG. 15 shows an electric vehicle 500 that includes one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance-controlled trace 120A, according to the inventive concepts disclosed herein. As shown in FIG. 15 by way of example, one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance-controlled trace 120A may be employed in an inverter of the electric vehicle 500.

[0123] FIG. 16 shows a medical imager 600 (e.g., an MRI imager) that includes one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance- controlled trace 120A, according to the inventive concepts disclosed herein. As shown in FIG. 16 by way of example, one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance-controlled trace 120 A may be employed in an RF amplifier or a gradient amplifier of the medical imager 600.

[0124] FIG. 17 shows an industrial robot 700 that includes one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance-controlled trace 120A, according to the inventive concepts disclosed herein. As shown in FIG. 17 by way of example,Attorney Docket No.: BRLN-008W001 one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance-controlled trace 120A may be employed in an actuator of the industrial robot 700.(0125] FIG. 18 shows a particle accelerator 800 that includes one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance-controlled trace 120A, according to the inventive concepts disclosed herein. As shown in FIG. 18 by way of example, one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra- wide impedance-controlled trace 120 A may be employed in an RF amplifier or a transmission line coupling the RF amplifier to a circulator of the particle accelerator 800. Particle accelerators are used to accelerate charged particles to very high speeds using high power RF before the beam of charged particles collides with a chosen target. A particle accelerator includes cylindrical RF cavities placed in tandem and connected via drift tubes through which a particle beam accelerates. A certain mode of a cylindrical cavity is used in the transfer of power into the beam via its longitudinal electric field and thereby accelerating the charged particles. Particle accelerators are employed in diverse applications such as as physics research, electronics manufacturing, food safety, cancer treatments and art verification.(0126] FIG. 19 shows a plasma generator 900 A and a plasma etching system 900B that includes one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra- wide impedance-controlled trace 120 A, according to the inventive concepts disclosed herein. As shown in FIG. 19 by way of example, one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance-controlled trace 120A may be employed in an RF power supply and / or impedance matcher of the plasma generator 900A or the plasma etching system 900B. The plasma generator 900 A and the plasma etching system 900B may be employed for processing semiconductor wafers in the production of integrated circuits, solar cells, batteries, fuel cells, and flat panel displays.|0127| Another general application area for the inventive concepts disclosed herein relates to “pulsed power.” Pulsed power involves the generation and use of short and powerful electrical pulses. To create high-energy pulses, a pulsed power generator may draw relatively low-power electricity (e.g., from a wall outlet), and this low-power electrical energy is stored in a bank of capacitors. The stored energy is then released as one or more short pulses with a much higher power. As the pulse is shortened at a steady pace, the power increases, resulting in a very short but potent burst of energy. Accordingly, a pulsed power generator is capable of achieving significant (if not immense) power levels (like terawatts) by significantly reducing the time of energy release. Salient components of a pulse generator typically include one or more capacitorAttorney Docket No.: BRLN-008W001 banks (e.g., a Marx Generator, which charges in parallel and discharges in series), pulseforming line, or inductive adders. These various design configurations operate to significantly compress the pulse duration (e.g., down to nanoseconds or picoseconds).

[0128] Examples of pulsed power generators include Marx Generators, where capacitors are charged in parallel and then switched to discharge in series, adding their voltages to create a very high-voltage pulse. Pulse-forming Lines (PFLs) utilize coaxial cables or other transmission lines that stretch and then sharpen the voltage / current pulse as it travels, compressing it in time before it hits the load. A magnetic pulse compression (MPC) pulsed power generator uses magnetic materials (ferrite) and switches to compress the pulse in stages, achieving incredibly short durations (like 100 picoseconds) and high power. An inductive adder pulsed power generator combines the outputs of multiple pulse sources (like transformers or PFLs) to add their power, creating a single, powerful output pulse.

[0129] A pulsed power system using a transmission line Pulse Forming Line (PFL) generally comprises the following components: 1) Primary Energy Storage: This initial stage uses a high- voltage (HV) power supply, often a Marx generator or a Tesla transformer, to store a large amount of energy over a relatively long time (microseconds); 2) High-Voltage Switch (Input Switch): A switch, typically a spark gap (gas or pressurized water insulated), connects the primary energy storage to the PFL. This switch is crucial for initiating the rapid charging of the PFL; 3) Pulse Forming Line (PFL): This is the core component, consisting of a specific length of transmission line (often coaxial cable filled with deionized water or oil for high power applications). It is designed with a characteristic impedance to shape the stored energy into a controlled, approximately rectangular pulse of a specific duration (determined by its electrical length; 4) Output Switch: A second fast-acting high-voltage switch (which can also be a spark gap, or sometimes a magnetic switch for further pulse compression) is positioned at the output end of the PFL to rapidly discharge the stored energy into the load; 5) Load: The component or system that receives the high-power pulse, such as a pulsed laser, particle accelerator, or klystron tube. The PFL must be impedance-matched to the load to prevent reflections and ensure maximum power transfer. A pulse transformer might be used here to match impedances if necessary. This system efficiently compresses the energy from a long-duration, lower-power input into a short-duration, high-power output pulse, with peak power in the megawatts or even terawatts range.

[0130] FIG. 20 shows a pulsed power generator 1000 that includes one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra-wide impedance-controlledAttorney Docket No.: BRLN-008W001 trace 120A, according to the inventive concepts disclosed herein. As shown in FIG. 20 by way of example, one or more PCB RF transmission lines 130 or one or more PCBs with at least one ultra- wide impedance-controlled trace 120 A may be employed in one or more of the high- voltage switch, the output switch, or the load of the pulsed power generator 1000. Various types of pulsed power generators 1000 are employed for applications in automotive manufacturing, food processing / food and water safety (sterilization / purification), medical treatments (X-ray generation for medical diagnostics, radiation treatment and cell membrane manipulation / electroporation for cancer), and military equipment (military lasers, pulsed radar, high-power micro-wave systems).CONCLUSION

[0131] All parameters, dimensions, materials, and configurations described herein are meant to be example and the actual parameters, dimensions, materials, and / or configurations may in some instances depend upon the specific application or applications for which the inventive teachings is / are used. It is to be understood that the foregoing embodiments are presented primarily by way of example and that inventive embodiments may be practiced otherwise than as specifically described. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein.(0132] In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions and arrangement of respective elements of the example implementations without departing from the scope of the present disclosure. The use of a numerical range does not preclude equivalents that fall outside the range that fulfill the same function, in the same way, to produce the same result.(0133] The above-described embodiments can be implemented in multiple ways. For example, embodiments may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on a suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.(0134] Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tabletAttorney Docket No.: BRLN-008W001 computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electrical device.

[0135] Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible format.

[0136] Such computers may be interconnected by one or more networks in a suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet. Such networks may be based on a suitable technology, may operate according to a suitable protocol, and may include wireless networks, wired networks or fiber optic networks.

[0137] The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and / or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine. Some implementations may specifically employ one or more of a particular operating system or platform and a particular programming language and / or scripting tool to facilitate execution.

[0138] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0139] All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.Attorney Docket No.: BRLN-008W001

[0140] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0141] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0142] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0143] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e., “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0144] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition alsoAttorney Docket No.: BRLN-008W001 allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0145] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

Attorney Docket No.: BRLN-008W001CLAIMS1. A multilayer printed circuit board (PCB) (100) having a stack-up (110) including a first layer (112) comprising first copper and a first electrically-insulating material (124), wherein the first layer and the first electrically-insulating material are contiguous, the multilayer PCB comprising: a first ultra-wide impedance-controlled copper trace (120A) formed in the first copper of the first layer of the stack-up, the first ultra-wide impedance-controlled copper trace having a width (122) in a range of from approximately or equal to 200 mils or 5 millimeters to approximately or equal to 1200 mils or 30 millimeters and a copper thickness (118) of at least 0.5 ounces per square foot and less than 2.0 ounces per square foot; and a first return copper conductor (126, 128), formed in a second layer (114, 116) of the stack-up comprising second copper, such that at least the first electrically-insulating material of the stack-up is at least partially disposed between the first ultra-wide impedance-controlled copper trace formed in the first layer of the stack-up and the first return copper conductor formed in the second layer of the stack-up; wherein: the first ultra-wide impedance-controlled copper trace and the first return copper conductor constitute at least a portion of a PCB radio frequency (RF) transmission line (130) having a characteristic impedance based at least in part on the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance- controlled copper trace, a first dielectric constant (132A) of the first electrically-insulating material, and a first thickness (134A) of the first electrically-insulating material; and at least one of the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, or the first thickness of the first electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 10 ohms.

2. The multilayer printed circuit board of claim 1, wherein: at least one of the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, or the first thickness of the firstAttorney Docket No.: BRLN-008W001 electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 5 ohms.

3. The multilayer printed circuit board of claim 1, wherein: at least one of the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, or the first thickness of the first electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 2 ohms.

4. The multilayer printed circuit board of claim 1, wherein the PCB RF transmission line has a microstrip transmission line configuration.

5. The multilayer printed circuit board of claim 1, wherein: the stack-up includes: at least one intervening layer (114) comprising intervening copper disposed between the first layer (112) and the second layer (116) in which the first return copper conductor (128) is formed; and a second electrically-insulating material (136) at least partially disposed between the at least one intervening layer and the second layer, the second electrically-insulating material having a second dielectric constant (132B); the characteristic impedance of the RF PCB transmission line is based at least in part on the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, the second dielectric constant of the second electrically- insulating material, the first thickness of the first electrically-insulating material, and a second thickness (134B) of the second electrically-insulating material; and at least one of the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, the second dielectric constant of the second electrically-insulating material, the first thickness of the first electrically-insulating material, or the second thickness of the second electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 10 ohms.Attorney Docket No.: BRLN-008W0016. The multilayer printed circuit board of claim 1, wherein the PCB RF transmission line has a microstrip transmission line configuration.

7. The multilayer printed circuit board of claim 1, further comprising: a second return copper conductor (144), formed in a third layer (142) of the stack-up comprising third copper, such that a third electrically-insulating material (146) of the stack- up is at least partially disposed between the first ultra-wide impedance-controlled copper trace formed in the first layer of the stack-up and the second return copper conductor formed in the third layer of the stack-up, wherein: the PCB radio frequency (RF) transmission line (130) comprises the first ultra-wide impedance-controlled copper trace, the first return copper conductor, and the second return copper conductor; the characteristic impedance of the PCB RF transmission line is based at least in part on the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, the first thickness of the first electrically-insulating material, a third dielectric constant (132C) of the third electrically-insulating material, and a third thickness (134C) of the third electrically-insulating material; and at least one of the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, the first thickness of the first electrically- insulating material, the third dielectric constant of the third electrically-insulating material, or the third thickness of the third electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 10 ohms.

8. The multilayer printed circuit board of claim 7, wherein: at least one of the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, the first thickness of the first electrically- insulating material, the third dielectric constant of the third electrically-insulating material, or the third thickness of the third electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 5 ohms.Attorney Docket No.: BRLN-008W0019. The multilayer printed circuit board of claim 7, wherein: at least one of the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, the first thickness of the first electrically- insulating material, the third dielectric constant of the third electrically-insulating material, or the third thickness of the third electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 2 ohms.

10. The multilayer printed circuit board of claim 7, wherein: the stack-up further comprises: a fourth layer (116) comprising fourth copper; and a second electrically-insulating material (136) at least partially disposed between the fourth layer and the second layer (114); the first ultra-wide impedance-controlled copper trace is electrically coupled to the fourth layer by at least one first via (154); and the first return copper conductor is electrically coupled to the second return copper conductor by at least one second via (152).

11. The multilayer printed circuit board of claim 10, wherein: the fourth layer constitutes a first outer layer of the stack-up and comprises at least one contact portion (156A) formed in the fourth copper and coupled to the at least one first via to facilitate electrical connection to the PCB RF transmission line.

12. The multiplayer printed circuit board of claim 11, wherein the at least one contact portion formed in the fourth copper of the fourth layer constituting the first outer layer of the stack-up comprises an annular first contact portion on the first outer layer of the stack-up to facilitate the electrical connection to the PCB RF transmission line.

13. The multilayer printed circuit board of claim 7, wherein: the stack-up further comprises: a fourth layer (116) comprising fourth copper; a second electrically-insulating material (136) at least partially disposed between the fourth layer and the second layer (114);Attorney Docket No.: BRLN-008W001 a fifth layer (148) comprising fifth copper; and a fourth electrically-insulating material (150) at least partially disposed between the fifth layer and the first layer (112); the multilayer printed circuit board further comprises a second ultra-wide impedance- controlled copper trace (120B) formed in the fifth copper of the fifth layer of the stack-up; and the PCB radio frequency (RF) transmission line (130) comprises the first ultra-wide impedance-controlled copper trace, the second ultra-wide impedance-controlled trace, the first return copper conductor, and the second return copper conductor.

14. The multilayer printed circuit board of claim 13, wherein: the characteristic impedance of the PCB RF transmission line is based at least in part on the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, the first thickness of the first electrically-insulating material, the third dielectric constant of the third electrically-insulating material, the third thickness of the third electrically-insulating material, a fourth dielectric constant (164) of the fourth electrically-insulating material, and a fourth thickness (166) of the fourth electrically- insulating material; and at least one of the width of the first ultra-wide impedance-controlled copper trace, the copper thickness of the first ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, the first thickness of the first electrically- insulating material, the third dielectric constant of the third electrically-insulating material, the third thickness of the third electrically-insulating material, the fourth dielectric constant of the fourth electrically-insulating material, or the fourth thickness of the fourth electrically- insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 10 ohms.

15. The multilayer printed circuit board of claim 13, wherein: the first return copper conductor is electrically coupled to the second return copper conductor by at least one second via (152); and the first ultra-wide impedance-controlled copper trace is electrically coupled to the second ultra-wide impedance-controlled copper trace by at least one first via (154).Attorney Docket No.: BRLN-008W00116. The multilayer printed circuit board of claim 15, wherein: the fourth layer constitutes a first outer layer of the stack-up and comprises at least one first contact portion (156A) formed in the fourth copper and coupled to the at least one first via (154) to facilitate electrical connection to the first ultra-wide impedance controlled copper trace and the second ultra-wide impedance-controlled trace.

17. The multiplayer printed circuit board of claim 16, wherein the at least one first contact portion formed in the fourth copper of the fourth layer constituting the first outer layer of the stack-up comprises an annular first contact portion on the first outer layer of the stack-up to facilitate the electrical connection to the first ultra-wide impedance controlled copper trace and the second ultra-wide impedance-controlled trace.

18. The multilayer printed circuit board of claim 16, wherein: the stack-up further comprises: a sixth layer (158) comprising sixth copper; a fifth electrically-insulating material (160) at least partially disposed between the sixth layer and the third layer (142); the sixth layer constitutes a second outer layer of the stack-up and comprises at least one second contact portion (156B) formed in the sixth copper and coupled to the at least one second via (152) to facilitate electrical connection to the first return copper conductor and the second return copper conductor.

19. The multiplayer printed circuit board of claim 18, wherein the at least one first contact portion formed in the fourth copper of the fourth layer constituting the first outer layer of the stack-up comprises an annular first contact portion on the first outer layer of the stack-up to facilitate the electrical connection to the first ultra-wide impedance controlled copper trace and the second ultra-wide impedance-controlled trace.

20. The multiplayer printed circuit board of claim 19, wherein the at least one second contact portion formed in the sixth copper of the sixth layer constituting the second outer layer of the stack-up comprises an annular second contact portion on the second outer layer of the stack-up to facilitate the electrical connection to the first return copper conductor and the second return copper conductor.Attorney Docket No.: BRLN-008W00121. The multilayer printed circuit board of claim 1, wherein: the first electrically-insulating material comprises FR4 or an FR4 variant.

22. The multilayer printed circuit board of claim 1, wherein: the first electrically-insulating material is a first core of the stack-up.

23. The multilayer printed circuit board of claim 1, wherein: the first dielectric constant is in a range of from approximately or equal to 3.7 to approximately or equal to 4.8.

24. The multilayer printed circuit board of claim 1, wherein: the at least one ultra-wide impedance-controlled copper trace is configured to carry a radio frequency (RF) signal having a peak current in a first range from approximately or equal to 10 Amperes to approximately or equal to 300 Amperes, and a peak voltage in a second range from approximately or equal to 20 Volts to approximately or equal to 600 Volts.

25. The multilayer printed circuit board of claim 1, wherein: the at least one ultra-wide impedance-controlled copper trace is configured to carry a radio frequency (RF) signal comprising one or more frequencies over a range of frequencies from approximately 100 kHz to 1 GHz.

26. The multilayer printed circuit board of claim 25, wherein: the RF signal for which the at least one ultra-wide impedance-controlled copper trace is configured to carry has a peak current in a first range from approximately or equal to 10 Amperes to approximately or equal to 300 Amperes, and a peak voltage in a second range from approximately or equal to 20 Volts to approximately or equal to 600 Volts.

27. The multilayer printed circuit board of claim 26, wherein: at least one of the width of the at least one ultra-wide impedance-controlled copper trace, the copper thickness of the at least one ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, or the first thickness of the first electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 5 ohms.Attorney Docket No.: BRLN-008W00128. The multilayer printed circuit board of claim 26, wherein: at least one of the width of the at least one ultra-wide impedance-controlled copper trace, the copper thickness of the at least one ultra-wide impedance-controlled copper trace, the first dielectric constant of the first electrically-insulating material, or the first thickness of the first electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line is less than or equal to 2 ohms.

29. A printed circuit board (PCB) (100), comprising: an ultra-wide impedance-controlled copper trace (120) having a width (122) of at least approximately or equal to 200 mils or at least approximately or equal to 5 millimeters and a copper thickness of at least 0.5 ounces per square foot and less than 2.0 ounces per square foot.

30. The printed circuit board of claim 29, wherein the width of the ultra-wide impedance- controlled copper trace is at least approximately or equal to 300 mils or at least approximately or equal to 7.5 millimeters.

31. The printed circuit board of claim 29, wherein the width of the ultra- wide impedance- controlled copper trace is at least approximately or equal to 800 mils or at least approximately or equal to 20 millimeters.

32. The printed circuit board of claim 29, wherein the width of the ultra-wide impedance- controlled copper trace is in a range of from approximately or equal to 200 mils or 5 millimeters to approximately or equal to 1200 mils or 30 millimeters.

33. The printed circuit board of claim 29, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material has a dielectric constant in a range from approximately or equal to 3.7 to approximately or equal to 4.8.

34. The printed circuit board of claim 29, wherein: the printed circuit board includes an electrically insulating base material; andAttorney Docket No.: BRLN-008W001 the electrically insulating base material comprises FR4 or an FR4 variant.

35. The printed circuit board of claim 29, wherein: the ultra-wide impedance-controlled copper trace constitutes a portion of a transmission line having a characteristic impedance of approximately ten (10) ohms or less.

36. The printed circuit board of claim 35, wherein the characteristic impedance of the transmission line is approximately five (5) ohms or less.

37. The printed circuit board of claim 35, wherein the characteristic impedance of the transmission line is approximately two (2) ohms or less.

38. The printed circuit board of claim 35, wherein the printed circuit board is a multilayer printed circuit board comprising: a first inner layer including the ultra-wide impedance-controlled copper trace; and a second layer adjacent to the first inner layer, the second layer including a return conductor, wherein the transmission line includes the ultra-wide impedance-controlled copper trace and the return conductor.

39. The printed circuit board of claim 35, wherein the multilayer printed circuit board further comprises: a second inner layer adjacent to the first inner layer, the second inner layer including a second ultra-wide impedance-controlled copper trace electrically coupled to the ultra-wide impedance-controlled copper trace on the first inner layer, wherein the transmission line includes the ultra-wide impedance-controlled copper trace on the first inner layer, the second ultra-wide impedance-controlled copper trace on the second inner layer, and the return conductor.

40. The printed circuit board of claim 35, wherein: the ultra-wide impedance-controlled trace is configured to carry a power signal having a peak current in a first range from approximately or equal to 10 Amperes to approximately or equal to 300 Amperes, and a peak voltage in a second range from approximately or equal to 20 Volts to approximately or equal to 600 Volts.Attorney Docket No.: BRLN-008W00141. The printed circuit board of claim 40, wherein the power signal for which the ultrawide impedance controlled trace is configured to carry is an RF power signal.

42. A printed circuit board (PCB) (100), comprising: a radio frequency (RF) transmission line (130) having a characteristic impedance of approximately ten (10) ohms or less.

43. The printed circuit board of claim 42, wherein the characteristic impedance of the RF transmission line is approximately five (5) ohms or less.

44. The printed circuit board of claim 42, wherein the characteristic impedance of the RF transmission line is approximately two (2) ohms or less.

45. The printed circuit board of any of claims 42 to 44, wherein the RF transmission line is a microstrip transmission line.

46. The printed circuit board of any of claims 42 to 44, wherein the RF transmission line is a stripline transmission line.

47. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak current of at least ten (10) amperes.

48. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak current of at least twenty (20) Amperes.

49. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak current of at least one hundred (100) Amperes.

50. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak current of at least three hundred (300) Amperes.Attorney Docket No.: BRLN-008W00151. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak voltage of at least twenty (20) Volts.

52. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak voltage of at least one hundred (100) Volts.

53. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak voltage of at least two hundred and fifty (250) Volts.

54. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak voltage of at least five hundred (500) Volts.

55. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak power of at least one hundred (100) Watts.

56. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak power of at least one thousand (1,000) Watts.

57. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak power of at least ten thousand (10,000) Watts.

58. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak power of at least one hundred thousand (100,000) Watts.

59. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak power of at least one hundred fifty thousand (150,000) Watts.Attorney Docket No.: BRLN-008W00160. The printed circuit board of any of claims 42 to 46, wherein the RF transmission line is configured to carry a power signal having a peak current of approximately 300 Amperes and a peak voltage of approximately 600 Volts.

61. The printed circuit board of any of claims 42 to 60, wherein the RF transmission line includes an ultra-wide trace.

62. The printed circuit board of claim 42, wherein the RF transmission line includes an ultra- wide trace.

63. The printed circuit board of claim 62, wherein the ultra- wide trace has a width of at least 200 mils or at least 5 millimeters.

64. The printed circuit board of claim 62, wherein the ultra-wide trace has a width of at least 300 mils or at least 7.5 millimeters.

65. The printed circuit board of claim 62, wherein the ultra- wide trace has a width of at least 400 mils or at least 10 millimeters.

66. The printed circuit board of claim 62, wherein the ultra-wide trace has a width of at least 500 mils or at least 12 millimeters.

67. The printed circuit board of claim 62, wherein the width of the ultra-wide trace is at least 800 mils or at least 20 millimeters.

68. The printed circuit board of claim 62, wherein the width of the ultra-wide trace is at least 1200 mils or at least 30 millimeters.

69. The printed circuit board of any of claims 62 to 68, wherein: the ultra-wide trace is an ultra-wide copper trace; and the ultra- wide copper trace has a thickness of 0.5 ounce per square foot or approximately 0.68 mils.Attorney Docket No.: BRLN-008W00170. The printed circuit board of any of claims 62 to 68, wherein: the ultra-wide trace is an ultra-wide copper trace; and the ultra-wide copper trace has a thickness of 1 ounce per square foot or approximately 1.37 mils.

71. The printed circuit board of any of claims 62 to 68, wherein: the ultra-wide trace is an ultra-wide copper trace; and the ultra- wide copper trace has a thickness of 1.5 ounce per square foot or approximately 2 mils.

72. The printed circuit board of any of claims 42 through 71, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material has a dielectric constant in a range from approximately or equal to 4.2 to approximately or equal to 4.8.

73. The printed circuit board of claim 42, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material has a dielectric constant in a range from approximately or equal to 4.2 to approximately or equal to 4.8.

74. The printed circuit board of any of claims 42 through 71, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material comprises FR4 or an FR4 variant.

75. The printed circuit board of claim 42, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material comprises FR4 or an FR4 variant.

76. The printed circuit board of claim 72 or 74, wherein at least some of the electrically insulating base material comprises prepreg.

77. The printed circuit board of any of claims 42 through 71 wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material comprises only FR4.Attorney Docket No.: BRLN-008W00178. The printed circuit board of claim 42, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material comprises only FR4.

79. The printed circuit board of any of claims 42 to 77, 72, 74, or 75, wherein the printed circuit board is a multilayer printed circuit board.

80. The printed circuit board of claim 79, wherein the multilayer printed circuit board has a stack-up of at least six layers.

81. The printed circuit board of claim 79 or claim 80, wherein the multilayer printed circuit board comprises: a first inner layer including a first ultra-wide trace; a second inner layer adjacent to the first inner layer, the second inner layer including a second ultra-wide trace electrically coupled to the first ultra-wide trace on the first inner layer; and a third layer adjacent to the first inner layer, the third layer including a first return plane, wherein the first ultra-wide trace, the second ultra-wide trace and the first return plane form the RF transmission line.

82. The printed circuit board of claim 42, wherein the printed circuit board is a multilayer printed circuit board comprising: a first inner layer including a first ultra-wide trace; a second inner layer adjacent to the first inner layer, the second inner layer including a second ultra-wide trace electrically coupled to the first ultra-wide trace on the first inner layer; and a third layer adjacent to the first inner layer, the third layer including a first return plane, wherein the first ultra-wide trace, the second ultra-wide trace and the first return plane form the RF transmission line.Attorney Docket No.: BRLN-008W00183. The printed circuit board of claim 82, wherein the RF transmission line includes an annular portion on at least one outer layer of the stack-up to facilitate electrical connection to the RF transmission line.

84. The printed circuit board of claim 83, further comprising a plurality of blind vias electrically connecting the annular portion and at least one conductor of the RF power signal transmission line on at least one inner layer of the stack-up.

85. A multiplayer printed circuit board (PCB) having at least a four layer stack-up, comprising: a first inner layer including a first trace; a second inner layer adjacent to the first inner layer, the second inner layer including a second trace electrically coupled to the first trace on the first inner layer; and a third layer adjacent to the first inner layer, the third layer including a first return plane, wherein the first trace, the second trace and the first return plane form a PCB transmission line.

86. The multiplayer printed circuit board of claim 85, further comprising: a fourth layer adjacent to the second inner layer, the fourth layer including a second return plane electrically coupled to the first return plane, wherein the first trace, the second trace, the first return plane and the second return plane form the PCB transmission line.

87. A base station (400) for transmitting and receiving RF signals, the base station comprising: an antenna feeder system; and an RF unit comprising: at least one antenna; a power amplifier for transmitting first RF signals; and a low noise amplifier for receiving second RF signals, wherein at least one of the power amplifier or the low noise amplifier comprises at least one printed circuit board (PCB), wherein the at least one PCB comprises:Attorney Docket No.: BRLN-008W001 an ultra-wide impedance-controlled trace (120 A) having a width (122) of at least approximately or equal to 200 mils or at least approximately or equal to 5 millimeters.

88. The base station of claim 87, wherein: the ultra-wide impedance-controlled trace constitutes a portion of a transmission line (130) having a characteristic impedance of approximately ten (10) ohms or less.

89. An electric vehicle (500), comprising:A DC / DC converter; an electric motor; and an inverter electrically coupled to the DC / DC converter and the electric motor, wherein at least one of the DC / DC converter, the inverter, or the electric motor comprises at least one printed circuit board (PCB), wherein the at least one PCB comprises: an ultra-wide impedance-controlled trace (120 A) having a width (122) of at least approximately or equal to 200 mils or at least approximately or equal to 5 millimeters.

90. The electric vehicle of claim 89, wherein: the ultra-wide impedance-controlled trace constitutes a portion of a transmission line (130) having a characteristic impedance of approximately ten (10) ohms or less.

91. A magnetic resonance imaging system (600), comprising: at least one magnet; at least one gradient coil; at least one RF coil; a radio frequency (RF) amplifier; and a gradient amplifier, wherein at least one of the RF amplifier or the gradient amplifier comprises at least one printed circuit board (PCB), wherein the at least one PCB comprises: an ultra-wide impedance-controlled trace (120 A) having a width (122) of at least approximately or equal to 200 mils or at least approximately or equal to 5 millimeters.Attorney Docket No.: BRLN-008W00192. The magnetic resonance imaging system of claim 91, wherein: the ultra-wide impedance-controlled trace constitutes a portion of a transmission line (130) having a characteristic impedance of approximately ten (10) ohms or less.

93. An industrial robot (700), comprising: a control unit; at least one internal sensor coupled to the control unit; at least one mechanical structure; and at least one actuator coupled to the at least one mechanical structure and the control unit, wherein at least one actuator comprises at least one printed circuit board (PCB), wherein the at least one PCB comprises: an ultra-wide impedance-controlled trace (120 A) having a width (122) of at least approximately or equal to 200 mils or at least approximately or equal to 5 millimeters.

94. The industrial robot of claim 93, wherein: the ultra-wide impedance-controlled trace constitutes a portion of a transmission line (130) having a characteristic impedance of approximately ten (10) ohms or less.

95. A particle accelerator (800), comprising: a transmitter; a high voltage power supply; a radio frequency (RF) amplifier coupled to the transmitter and the high voltage power supply; and a first transmission line coupled to the RF amplifier, wherein at least the RF amplifier comprises at least one printed circuit board (PCB), wherein the at least one PCB comprises: an ultra-wide impedance-controlled trace (120 A) having a width (122) of at least approximately or equal to 200 mils or at least approximately or equal to 5 millimeters.

96. The particle accelerator of claim 95, wherein:Attorney Docket No.: BRLN-008W001 the ultra-wide impedance-controlled trace constitutes a portion of a PCB transmission line (130) having a characteristic impedance of approximately ten (10) ohms or less; and the PCB transmission line is coupled to the first transmission line.

97. A plasma generator (900A, 900B), comprising: a radio frequency (RF) power supply; an impedance matching unit; an electrode; and an anode coupled to ground, wherein: upon operation of the plasma generator, a plasma is generated between the electrode and the anode for processing a sample; and at least one of the RF power supply or the impedance matching unit comprises at least one printed circuit board (PCB), wherein the at least one PCB comprises: an ultra-wide impedance-controlled trace (120 A) having a width (122) of at least approximately or equal to 200 mils or at least approximately or equal to 5 millimeters.

98. The plasma generator of claim 97, wherein: the ultra-wide impedance-controlled trace constitutes a portion of a PCB transmission line (130) having a characteristic impedance of approximately ten (10) ohms or less.

99. The plasma generator of claim 97, wherein: the plasma generator is a plasma etching system (900b); and the sample is a semiconductor wafer.

100. A pulsed power generator (1000), comprising: a power supply; a capacitor or capacitor bank; and at least one pulse compression stage, wherein the at least one pulse compression stage comprises at least one printed circuit board (PCB), wherein the at least one PCB comprises:Attorney Docket No.: BRLN-008W001 an ultra-wide impedance-controlled trace (120 A) having a width (122) of at least approximately or equal to 200 mils or at least approximately or equal to 5 millimeters.

101. The pulsed power generator of claim 100, wherein: the ultra-wide impedance-controlled trace constitutes a portion of a PCB transmission line (130) having a characteristic impedance of approximately ten (10) ohms or less.

102. The pulsed power generator of claim 100, wherein: the at least one pulse compression stage comprises: a high-voltage switch; a pulse forming line; and an output switch coupled to a load, wherein at least one of the high-voltage switch, the pulse forming line, the output switch, or the load comprises the at least one printed circuit board (PCB) including the ultrawide impedance-controlled trace.

Images