Intelligent control method and system for PCB board patch processing

Abstract

The present invention relates to the technical field of PCB board processing, and discloses an intelligent control method and system for PCB board patch processing, the method comprising obtaining circuit board layout information, component information and equipment parameter information; performing digital coding according to the circuit board layout information to obtain a coding layout diagram; performing weight calculation according to the coding layout diagram and the component information to obtain a weighted adjacency matrix; performing path planning according to the weighted adjacency matrix to obtain an optimal patch path; performing mounting force calculation according to the equipment parameter information and the component information to obtain an optimal mounting force; and installing patch components according to the optimal patch path and the optimal mounting force. The method has the following effects: the method can plan an optimal patch path and improve patch processing efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB board processing, and in particular to an intelligent control method and system for PCB board patch processing. Background Art

[0002] With the rapid development of the electronics industry, the demand for PCB boards has shown a strong growth trend. Against this background, the processing of patch components on PCB boards has gradually introduced more automated means to meet the requirements of efficient production and high quality. Automated patch technology not only improves production efficiency, but also ensures patch accuracy and reliability, making large-scale, high-density electronic assembly a trend. For example, in modern SMT (surface mount technology) production lines, automatic dispensing machines are widely used to fix patch components on PCB boards. By pre-applying special glue at the location where the patch is required, it can be ensured that the components can be firmly adhered to the PCB board after curing.

[0003] One method of processing patch components in the prior art is to use a fully imported fully automatic patch line. Through multiple fully imported fully automatic patch lines, it has the ability to mount micro components such as 0201, 01005 (CHIP parts). The specific steps include: first, the PCB board enters the patch area through the conveyor system; then, the visual system quickly locates the PCB board and compares it with the pre-stored design data to determine the exact position of each component; then, the patch machine accurately places the components from the tray or tubular packaging to the specified position according to the instructions; finally, the PCB board that has completed the patch will pass through the inspection system to confirm that all components have been correctly installed before being sent to the next process.

[0004] Although the above automation methods have improved the speed and accuracy of PCB board SMD component processing to a certain extent, they are not perfect. When the number of SMD components is large, different paths require different soldering times, so the lack of path planning will lead to low production efficiency of PCB board SMD processing. Summary of the invention

[0005] The present invention provides an intelligent control method and system for PCB board patch processing, so as to improve the efficiency of PCB board patch processing.

[0006] In the first aspect, in order to solve the above technical problems, the present invention provides an intelligent control method for PCB board patch processing, comprising:

[0007] Get circuit board layout information, component information and device parameter information;

[0008] Perform digital coding according to the circuit board layout information to obtain a coding layout diagram;

[0009] Performing weight calculation according to the coding layout diagram and the component information to obtain a weighted adjacency matrix;

[0010] Performing path planning according to the weighted adjacency matrix to obtain an optimal patch path;

[0011] Calculate the placement force according to the device parameter information and the component information to obtain an optimal placement force;

[0012] The patch component is mounted according to the optimal patch path and the optimal mounting force.

[0013] In an optional implementation, the digital encoding is performed according to the circuit board layout information to obtain a coding layout diagram, including:

[0014] Determine the lower left corner of the circuit board as the coordinate origin;

[0015] Dividing the circuit board into grids according to a preset grid size;

[0016] Calculate the patch coordinates of each patch according to the circuit board layout information, wherein the abscissa of the patch coordinates is the column number of the grid, and the ordinate of the patch coordinates is the row number of the grid;

[0017] Assign a unique integer code to each patch coordinate to obtain a coding layout map.

[0018] In an optional implementation, performing weight calculation according to the coding layout diagram and the component information to obtain a weighted adjacency matrix includes:

[0019] The elements of the weighted adjacency matrix are calculated using the following formula:

[0020]

[0021] in, is the element in the i-th row and j-th column of the weighted adjacency matrix, is the time required for the displacement process from the i-th patch coordinate to the j-th patch coordinate, is the startup time required to move the i-th patch coordinate to the j-th patch coordinate, is the penalty coefficient, is a nozzle replacement indicator function for moving the i-th patch coordinate to the j-th patch coordinate, where i and j are the numbers of the patch coordinates;

[0022] Among them, the elements of the main diagonal of the weight adjacency matrix are all set to 0.

[0023] In an optional implementation, performing path planning according to the weighted adjacency matrix to obtain an optimal patch path includes:

[0024] Initialize a distance table and set the distance from all nodes to the starting point to the preset upper limit;

[0025] Create an access list to record the access status of the node;

[0026] Select the node with the shortest known distance from the unvisited nodes as the current node;

[0027] For all unvisited neighbor nodes of the current node, calculate the current distance from the current node to all the neighbor nodes;

[0028] When the current distance is less than the original distance in the distance table, the current distance is used as the original distance, and the current node is recorded as a predecessor node;

[0029] When all the neighboring nodes of the current node are processed, updating the access status of the current node to visited;

[0030] Continue to select the next unvisited node as the current node until the entire visit list is traversed;

[0031] Starting from the end point, according to the predecessor node information recorded by each node, the optimal patch path is constructed by gradually tracing back to the starting point.

[0032] In an optional implementation, the calculating the placement force according to the device parameter information and the component information to obtain the optimal placement force includes:

[0033] The optimal placement force is calculated by the following formula:

[0034]

[0035] in, For optimal placement force, is the quality of the patch component, is the elastic modulus of the patch element, is the thickness of the circuit board, is the device acceleration, is the number of pins of the SMD component, , , , , is the proportionality coefficient.

[0036] In an optional implementation, the step of installing the patch component according to the optimal patch path and the optimal placement force includes:

[0037] The patch equipment starts from the origin and installs each patch coordinate according to the optimal placement force along the optimal patch path.

[0038] In an optional implementation, the circuit board layout information includes: circuit board thickness, circuit board image, precise coordinates of components on the circuit board, and outlines of components.

[0039] In a second aspect, the present invention provides an intelligent control system for PCB board patch processing, comprising:

[0040] A data acquisition module is used to obtain circuit board layout information, component information and device parameter information;

[0041] A digital encoding module, used for performing digital encoding according to the circuit board layout information to obtain a coding layout diagram;

[0042] A weight calculation module, used to perform weight calculation according to the coding layout diagram and the component information to obtain a weight adjacency matrix;

[0043] A path planning module, used to perform path planning according to the weighted adjacency matrix to obtain an optimal patch path;

[0044] A mounting force calculation module, used to calculate the mounting force according to the device parameter information and the component information to obtain an optimal mounting force;

[0045] The patch mounting module is used to mount the patch component according to the optimal patch path and the optimal mounting force.

[0046] In a third aspect, the present invention further provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the intelligent control method for PCB board patch processing described in any one of the above is implemented.

[0047] In a fourth aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute any one of the above-mentioned intelligent control methods for PCB board patch processing.

[0048] Compared with the prior art, the present invention has the following beneficial effects: the present invention discloses an intelligent control method and system for PCB board patch processing, the method comprising obtaining circuit board layout information, component information and equipment parameter information; performing digital coding according to the circuit board layout information to obtain a coding layout diagram; performing weight calculation according to the coding layout diagram and the component information to obtain a weighted adjacency matrix; performing path planning according to the weighted adjacency matrix to obtain an optimal patch path; performing mounting force calculation according to the equipment parameter information and the component information to obtain an optimal mounting force; and installing patch components according to the optimal patch path and the optimal mounting force. The present method has the following effects: the present method can plan an optimal patch path and improve patch processing efficiency.

[0049] Specifically, the present method digitally encodes the circuit board layout information to obtain a coding layout diagram. This method is implemented by steps such as determining a coordinate system, dividing the circuit board into a grid, calculating the patch coordinates, and assigning integer codes, aiming to improve the automation level and accuracy in the PCB board patch processing process. First, the lower left corner of the circuit board is set as the coordinate origin. This measure ensures the consistency and accuracy of all subsequent coordinate positioning. Then, the circuit board is divided according to the preset grid size. This step enables each area on the circuit board to be accurately identified and quantified, thereby simplifying the description of the patch position. Then, the specific patch coordinates of each patch are calculated based on the circuit board layout information, where the horizontal coordinate corresponds to the column number of the grid, and the vertical coordinate corresponds to the row number of the grid. Such a coordinate system is directly related to the actual physical position, ensuring the accuracy of the patch operation. Finally, a unique integer code is assigned to each patch coordinate to form a coding layout diagram. This code can not only uniquely identify the position of each patch, but also facilitate computer processing and instruction execution, greatly improving the efficiency and flexibility of patch processing.

[0050] Furthermore, the method proposes a method for performing weight calculation to construct a matrix. The method introduces specific rules for calculating the elements of the matrix, taking into account the time required to move from one patch position to another, the startup time required to move between different patch positions, and the influence of whether the tool needs to be changed during the movement. It is worth noting that for any patch position itself, there is no movement time and startup time, so the corresponding matrix elements are set to 0. This method reasonably considers the time cost of the patch machine in operating between different patch positions, and further quantifies the impact of the special event of tool replacement on the overall efficiency, making the model closer to the actual situation. This not only helps to accurately predict the actual time consumption of each patch operation, but also helps to optimize the patch path, reduce unnecessary operation time, and thus improve the overall efficiency of patch processing. Compared with the prior art, this matrix-based method provides a more refined estimate of the operation time, and takes into account the complex factors in the actual operation through reasonable modeling. Such improvements have a significant effect on improving the automation level and efficiency in the PCB patch processing process.

[0051] Furthermore, this method proposes a calculation formula for the optimal placement force, and its scientific nature in mathematical physics is reflected in the following aspects: First, it quantifies the main factors that affect the placement force in actual operation and expresses them in the form of linear combinations, which makes the calculation process simple and clear, while ensuring the interpretability of the results. Secondly, by introducing the proportionality coefficient, the degree of influence of different parameters on the final result can be flexibly adjusted to adapt to different types of components and processing environments. Finally, taking into account factors such as component quality, material properties, circuit board characteristics, equipment performance and component structure, such comprehensive considerations help to achieve more accurate and personalized placement force settings, thereby ensuring the best placement effect. Compared with the existing technology, this formulaic method provides a more systematic and scientific way to determine the optimal placement force, which can not only improve the placement accuracy, but also effectively avoid damage to components or circuit boards caused by improper force, thereby improving the overall production efficiency and consistency of product quality.

[0052] Furthermore, the method embodies the effective improvement and application of the traditional path planning algorithm by performing path planning based on the weighted adjacency matrix to obtain the technical solution of the optimal patch path. The method adopts a strategy similar to the Dijkstra algorithm to find the shortest path from the starting point to the end point, which is specifically embodied in the following points: First, the distance table is initialized and a preset upper limit is set as the initial distance of all nodes to the starting point, and the access list is created to track the node access status, which ensures that each node has a reasonable starting value before processing, and at the same time ensures that the algorithm can effectively distinguish between visited and unvisited nodes. Then, the node with the shortest known distance is selected from the unvisited nodes as the current node, and the distance from the current node to all unvisited neighbor nodes is calculated for the current node. If the newly calculated distance is less than the original distance recorded in the distance table, the distance table is updated and the current node is recorded as the predecessor node. This mechanism ensures that the shortest path to each node can be found in each iteration, thereby gradually building a global optimal solution. When all neighbor nodes of a node have been processed, the node is marked as visited to avoid repeated calculations. This process continues until the entire access list is traversed, that is, all paths have been evaluated. Finally, starting from the end point, the path is reversely constructed based on the predecessor node information recorded by each node, and the optimal patch path from the start point to the end point can be accurately restored. This method not only improves the efficiency of path planning, but also ensures the quality of the path optimization results, making the patch processing process more efficient and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a schematic flow chart of an intelligent control method for PCB board patch processing provided by the first embodiment of the present invention;

[0054] Figure 2 It is a schematic diagram of the structure of an intelligent control system for PCB board patch processing provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] To solve the above problems, refer to Figure 1 The first embodiment of the present invention provides an intelligent control method for PCB board patch processing, comprising the following steps:

[0057] S11, obtaining circuit board layout information, component information and device parameter information;

[0058] S12, performing digital coding according to the circuit board layout information to obtain a coding layout diagram;

[0059] S13, performing weight calculation according to the coding layout diagram and the component information to obtain a weighted adjacency matrix;

[0060] S14, performing path planning according to the weighted adjacency matrix to obtain an optimal patch path;

[0061] S15, calculating the placement force according to the device parameter information and the component information to obtain an optimal placement force;

[0062] S16, installing the patch component according to the optimal patch path and the optimal mounting force.

[0063] In step S11, circuit board layout information, component information and device parameter information are obtained.

[0064] In one embodiment, the circuit board layout information includes: circuit board thickness, circuit board image, precise coordinates of components on the circuit board, and component outlines. Component information includes: component size, component quality, and number of component pins. Equipment parameter information includes: patch speed, nozzle type, and acceleration.

[0065] It is worth noting that the placement speed determines how many components can be placed per unit time and is used to calculate the subsequent path movement time. The nozzle is a key component used by the placement machine to pick up and place components. Different components require different types of nozzles to ensure the best pick-up and placement effect due to their different sizes, shapes, weights and pin layouts. For example, the type of nozzle required for small passive components (such as 0402 or 0603 resistors) and larger IC chips will be different. For example: There are three different types of components on a PCB board: a large number of 0402 resistors (micro), some SOIC-8 packaged logic chips (medium), and several LGA packaged processors (large). At the beginning, the placement machine will use a micro nozzle suitable for 0402 resistors to quickly place a large number of small components. When it reaches the position of the LGA packaged processor, it is replaced with a special nozzle suitable for large components. The circuit board image is to determine the position and relative relationship of each component on the circuit board through image recognition technology. The number of pins and component quality affect the calculation of placement force, because components with different pin numbers have different requirements for placement force.

[0066] In one embodiment, modern placement machines are equipped with various types of sensors, including displacement sensors, force sensors, temperature sensors, etc., to monitor their own status and record relevant parameters. Detailed specifications of specific components, such as size, weight, pin spacing, etc., can be obtained through online databases or internally maintained component libraries. For existing physical circuit boards, they can be scanned by high-resolution cameras and image processing algorithms can be used to extract feature points, component locations, and contour information on the circuit board.

[0067] In step S12, digital encoding is performed according to the circuit board layout information to obtain a coding layout diagram.

[0068] In one implementation, the lower left corner of the circuit board is determined as the coordinate origin; the circuit board is divided into grids according to a preset grid size; the patch coordinates of each patch are calculated based on the circuit board layout information, wherein the horizontal coordinate of the patch coordinate is the column number of the grid, and the vertical coordinate of the patch coordinate is the row number of the grid; each patch coordinate is assigned a unique integer code to obtain a coding layout diagram.

[0069] It is worth noting that the lower left corner of the circuit board is selected as the origin of the coordinate system (0, 0). The circuit board is divided according to the preset grid size. The choice of grid size depends on the capability of the placement machine and the size of the components. The number of grids will be minimized to reduce the computational complexity while ensuring accuracy. For example, there is a rectangular PCB board with a size of 100mm x 80mm, and different types of SMD (surface mount device) components are distributed on it, including small resistors, capacitors, and larger IC chips. Small passive components are only about 1.0mm×0.5mm, so a grid size of 1mm×1mm can be selected. Based on the circuit board layout information, the specific position of each patch component is determined and represented as the row and column number in the grid. For example, for a component located in the 3rd row and the 4th column, its coordinates can be represented as (3, 4). Then a unique integer code is assigned to each patch coordinate to form a coding layout diagram. This step is to facilitate subsequent algorithm processing, such as the corresponding position information can be quickly found directly through the code during path planning. The encoding methods include allocation according to layout order, allocation according to row and column positions, and hash allocation. For example, this method uses the hash allocation method, using a hash function to convert row and column coordinates into a unique integer code. This method can ensure the uniqueness of the code and can be calculated quickly.

[0070] In step S13, weight calculation is performed according to the coding layout diagram and the component information to obtain a weighted adjacency matrix.

[0071] In one implementation, the elements of the weighted adjacency matrix are calculated using the following formula:

[0072]

[0073] in, is the element in the i-th row and j-th column of the weighted adjacency matrix, is the time required for the displacement process from the i-th patch coordinate to the j-th patch coordinate, is the startup time required to move the i-th patch coordinate to the j-th patch coordinate, is the penalty coefficient, is a nozzle replacement indicator function for moving the i-th patch coordinate to the j-th patch coordinate, where i and j are the numbers of the patch coordinates;

[0074] Among them, the elements of the main diagonal of the weight adjacency matrix are all set to 0.

[0075] It is worth noting that the number of rows and columns of the weighted adjacency matrix are the total number of components. This process aims to quantify the total time required to move from one patch position to another and other related factors. The actual moving time takes into account the distance between the two positions and the speed of the placement machine. This is the most basic component and directly affects the time efficiency of the entire path. The startup time reflects the time required to readjust or prepare when the patch head moves from one position to another. Although this part of time is short, it will significantly affect the overall efficiency when accumulated in the case of frequent movement. The reason for setting the main diagonal elements to 0 is that no movement is required from one position to itself, so the corresponding weight should be zero. Setting the main diagonal elements to 0 can avoid the existence of self-loops, making the subsequent shortest path algorithm easier to implement and the results more intuitive. The core purpose of constructing the weighted adjacency matrix is ​​to support the selection of the optimal path. In this process, each element in the matrix represents the cost from one node to another. For path planning, this means minimizing the total time: when using shortest path algorithms such as Dijkstra's algorithm or A* algorithm, they will find a path that passes through all specified nodes and has the lowest total time based on the weighted adjacency matrix.

[0076] It is worth noting that the calculation of the moving time first calculates the Manhattan distance between two points using the following formula:

[0077]

[0078] in, For point To point The Manhattan distance of for The horizontal axis of for The vertical coordinate of for The horizontal axis of for The vertical coordinate of .

[0079] Then, by dividing the Manhattan distance by the device moving speed, we can calculate .

[0080] It is worth noting that the startup time includes the time required for operations such as acceleration or deceleration, positioning correction, etc. This part of time is a fixed value provided by the manufacturer of the placement machine because it is closely related to the hardware characteristics of the machine. If the two positions are very close, there will be a small or even no obvious startup time; conversely, if the distance is far, a longer startup time is required. The penalty coefficient is used to represent the extra time brought about by changing the nozzle. This value can be determined based on the time required to change the nozzle each time. A high penalty coefficient means that the system will try to avoid frequent nozzle changes to improve efficiency. The nozzle replacement indication function is a binary variable (0 or 1) that indicates whether the nozzle needs to be replaced from i to j. It is determined based on the type of nozzle currently in use and the type of component to be processed. If the next component requires a different type of nozzle, the value is 1; otherwise it is 0.

[0081] In step S14, path planning is performed according to the weighted adjacency matrix to obtain an optimal patch path.

[0082] In one implementation, a distance table is initialized, and the distances from all nodes to the starting point are set to a preset upper limit; an access list is created to record the access status of the nodes; a node with a known shortest distance is selected from unvisited nodes as the current node; for all unvisited neighbor nodes of the current node, the current distance from the current node to all the neighbor nodes is calculated; when the current distance is less than the original distance in the distance table, the current distance is used as the original distance, and the current node is recorded as a predecessor node; when all the neighbor nodes of the current node are processed, the access status of the current node is updated to visited; the next unvisited node is selected as the current node until the entire access list is traversed; starting from the end point, according to the predecessor node information recorded by each node, the optimal patch path is constructed by stepping back to the starting point.

[0083] It is worth noting that the process of path planning based on the weighted adjacency matrix to obtain the optimal patch path is actually applying a classic Dijkstra algorithm. This algorithm gradually explores the connection relationship between nodes and eventually finds the shortest path from the starting point to the end point. For example, there are four points A, B, C, and D; in the first round of iteration, A is selected as the current node, and the distances to B, C, and D are calculated respectively, and the point B with the smallest distance is selected as the predecessor node; in the second round of iteration, B, which has not been visited and has the smallest distance, is selected as the current node, and the cycle is repeated to finally obtain the path ABCD.

[0084] In step S15, the placement force is calculated according to the equipment parameter information and the component information to obtain the optimal placement force.

[0085] In one implementation, the optimal placement force is calculated by the following formula:

[0086]

[0087] in, For optimal placement force, is the quality of the patch component, is the elastic modulus of the patch element, is the thickness of the circuit board, is the device acceleration, is the number of pins of the SMD component, , , , , is the proportionality coefficient.

[0088] It is worth explaining that the optimal placement force is the best force required to ensure that the component is correctly and safely installed on the circuit board. The mass (weight) of the patch component. Components with larger mass require greater force to ensure their stability and good contact. The elastic modulus of the patch component reflects the material's ability to resist deformation; a high elastic modulus means that the material is harder and requires less force to achieve the same deformation effect. The thickness of the circuit board. Thicker circuit boards can withstand greater pressure and are less likely to be damaged. Equipment acceleration refers to the rate of change of speed of the patch machine when placing components; higher accelerations will generate impact force, so the placement force needs to be adjusted to avoid damage. The number of pins of the patch component. More pins mean that a larger area and force are required to ensure that all pins are in good contact with the circuit board. Exemplarily, this method will The value 10 is used to convert mass from kg to Newton. The value of 0.000001 is used to convert the elastic modulus from Pascal to Newton, γ is taken as 50 to convert the thickness from meter to Newton, and δ=1 is used to keep the acceleration unit unchanged. The value is 0.5, which indicates the force increment corresponding to each pin. For example, for a 0.05g device, an elastic modulus of 70 GPa, a circuit board thickness of 1.6 mm, a device acceleration of 2 m / s², and a component with 2 pins, the calculated optimal placement force is 0.0815 Newton.

[0089] In step S16, the patch component is mounted according to the optimal patch path and the optimal mounting force.

[0090] In one implementation, the patch device starts from the origin and installs each patch coordinate according to the optimal placement force along the optimal patch path.

[0091] It is worth noting that the placement machine moves step by step to each designated placement coordinate position according to the optimal placement path. During this process, the placement machine monitors its current position in real time and adjusts its own motion trajectory through a feedback mechanism to ensure that it strictly follows the predetermined path. If any abnormal situation is detected (such as deviation from the predetermined path or encountering an obstacle), the placement machine automatically pauses and re-evaluates the optimal path, and adjusts the strategy if necessary to continue moving forward. When approaching the next placement coordinate, the control system selects the appropriate suction nozzle according to the type of component to be processed and prepares the corresponding picking action. The placement head moves accurately to the tray or tubular packaging to remove the component, and uses vacuum adsorption or other methods to fix the component to ensure that it is stable and does not fall. After reaching the target position, the placement machine carefully places the component on the circuit board according to the calculated optimal placement force. At this time, the placement machine briefly applies the set force value to make the component in close contact with the pad, but not to cause damage. After placement, the built-in visual system checks whether the component is correctly installed in place. If there is a problem, submit feedback. When all components have been successfully installed, the control system sends an end signal, indicating that this placement task has been successfully completed. The placement machine returns to its initial position (origin) to prepare for the next batch of processing tasks.

[0092] In summary, the present invention discloses an intelligent control method for PCB board patch processing, which aims to optimize the patch path and placement force through a series of precise calculation and planning steps, thereby improving the efficiency of PCB board patch processing. First, the system obtains circuit board layout information, component information and equipment parameter information as input data. This information includes but is not limited to circuit board thickness, image, exact coordinates of components and their outer contours; component size, quality and number of pins; as well as patch speed, nozzle type and equipment acceleration. This step lays the foundation for subsequent processing and ensures that all necessary parameters are taken into account.

[0093] Next, digital encoding is performed based on the circuit board layout information to generate a coded layout diagram. Specifically, the lower left corner of the circuit board is used as the coordinate origin, and the circuit board is divided into multiple grid units according to the preset grid size. Then, based on the actual component position information, the patch coordinates corresponding to each component are calculated, and a unique integer code is assigned to each coordinate. This encoding method can not only uniquely identify the position of each patch, but also facilitate computer processing and instruction execution.

[0094] Subsequently, the weights are calculated based on the coding layout diagram and component information to construct a weighted adjacency matrix. A specific formula is introduced here to calculate the matrix elements, which comprehensively considers factors such as the time required to move from one patch position to another, the startup time, and whether the tool (such as the nozzle) needs to be changed. It is worth noting that for any patch position itself, there is no moving time and startup time, so the corresponding matrix elements are set to 0. This method reasonably quantifies the time cost of the patch machine in operating between different patch positions, and further quantifies the impact of the special event of tool replacement on the overall efficiency, making the model closer to the actual situation. This not only helps to accurately predict the actual time consumption of each patch operation, but also helps to optimize the patch path and reduce unnecessary operation time, thereby improving the overall efficiency of patch processing.

[0095] On this basis, the weighted adjacency matrix constructed above is used for path planning to obtain the optimal patch path. This method uses a strategy similar to the Dijkstra algorithm to find the shortest path from the starting point to the end point. Initialize the distance table and set a preset upper limit as the initial distance from all nodes to the starting point, and create an access list to track the node access status. Select the node with the shortest known distance from the unvisited nodes as the current node, and calculate the distance from the current node to all unvisited neighbor nodes. If the newly calculated distance is less than the original distance recorded in the distance table, update the distance table and record the current node as the predecessor node. When all neighbor nodes of a node have been processed, mark this node as visited to avoid repeated calculations. This process continues until the entire access list is traversed, that is, all paths have been evaluated. Finally, starting from the end point, the path is reversely constructed based on the predecessor node information recorded by each node, and the optimal patch path from the starting point to the end point can be accurately restored.

[0096] At the same time, the present invention also provides a method for calculating the optimal placement force, which determines the optimal placement force through a mathematical formula. The formula takes into account multiple influencing factors such as the mass of the patch component, the elastic modulus, the thickness of the circuit board, the acceleration of the device, and the number of pins of the component, and adjusts the importance of different parameters through the proportional coefficient. Such comprehensive considerations help to achieve a more accurate and personalized placement force setting, thereby ensuring the best placement effect.

[0097] Finally, the SMT equipment will start from the origin and install each SMT coordinate in sequence along the predetermined path according to the calculated optimal SMT path and optimal placement force. The SMT machine will monitor its current position in real time and adjust the motion trajectory through the feedback mechanism to ensure that the predetermined path is strictly followed. When approaching the next SMT coordinate, the control system will select the appropriate nozzle according to the type of component to be processed and prepare the corresponding picking action. After reaching the target position, the SMT machine carefully places the component on the circuit board according to the calculated optimal placement force, ensuring that the component is in close contact with the pad but not damaged. After placement, the built-in visual system checks whether the component is correctly installed in place. If there is a problem, feedback is submitted until all components are successfully installed.

[0098] In summary, the intelligent control method for PCB board patch processing proposed in the present invention realizes the optimization of the patch path and the placement force through digital encoding of circuit board layout information, weight calculation, path planning and scientific calculation of placement force, thereby significantly improving the efficiency of the PCB board patch processing process.

[0099] Reference Figure 2 The second embodiment of the present invention provides an intelligent control system for PCB board patch processing, including:

[0100] A data acquisition module is used to obtain circuit board layout information, component information and device parameter information;

[0101] A digital encoding module, used for performing digital encoding according to the circuit board layout information to obtain a coding layout diagram;

[0102] A weight calculation module, used to perform weight calculation according to the coding layout diagram and the component information to obtain a weight adjacency matrix;

[0103] A path planning module, used to perform path planning according to the weighted adjacency matrix to obtain an optimal patch path;

[0104] A mounting force calculation module, used to calculate the mounting force according to the device parameter information and the component information to obtain an optimal mounting force;

[0105] The patch mounting module is used to mount the patch component according to the optimal patch path and the optimal mounting force.

[0106] Preferably, the data acquisition module is used to:

[0107] Get circuit board layout information, component information and device parameter information;

[0108] The circuit board layout information includes: circuit board thickness, circuit board image, precise coordinates of components on the circuit board and the outline of the components.

[0109] Preferably, the digital encoding module is used for:

[0110] Digital encoding is performed according to the circuit board layout information to obtain a coding layout diagram, including:

[0111] Determine the lower left corner of the circuit board as the coordinate origin;

[0112] Dividing the circuit board into grids according to a preset grid size;

[0113] Calculate the patch coordinates of each patch according to the circuit board layout information, wherein the abscissa of the patch coordinates is the column number of the grid, and the ordinate of the patch coordinates is the row number of the grid;

[0114] Assign a unique integer code to each patch coordinate to obtain a coding layout map.

[0115] Preferably, the weight calculation module is used to perform weight calculation according to the coding layout diagram and the component information to obtain a weight adjacency matrix, including:

[0116] The elements of the weighted adjacency matrix are calculated using the following formula:

[0117]

[0118] in, is the element in the i-th row and j-th column of the weighted adjacency matrix, is the time required for the displacement process from the i-th patch coordinate to the j-th patch coordinate, is the startup time required to move the i-th patch coordinate to the j-th patch coordinate, is the penalty coefficient, is a nozzle replacement indicator function for moving the i-th patch coordinate to the j-th patch coordinate, where i and j are the numbers of the patch coordinates;

[0119] Among them, the elements of the main diagonal of the weight adjacency matrix are all set to 0.

[0120] Preferably, the path planning module is used to perform path planning according to the weighted adjacency matrix to obtain an optimal patch path, including:

[0121] Initialize a distance table and set the distance from all nodes to the starting point to the preset upper limit;

[0122] Create an access list to record the access status of the node;

[0123] Select the node with the shortest known distance from the unvisited nodes as the current node;

[0124] For all unvisited neighbor nodes of the current node, calculate the current distance from the current node to all the neighbor nodes;

[0125] When the current distance is less than the original distance in the distance table, the current distance is used as the original distance, and the current node is recorded as a predecessor node;

[0126] When all the neighboring nodes of the current node are processed, updating the access status of the current node to visited;

[0127] Continue to select the next unvisited node as the current node until the entire visit list is traversed;

[0128] Starting from the end point, according to the predecessor node information recorded by each node, the optimal patch path is constructed by gradually tracing back to the starting point.

[0129] Preferably, the placement force calculation module is used to calculate the placement force according to the device parameter information and the component information to obtain the optimal placement force, including:

[0130] The optimal placement force is calculated by the following formula:

[0131]

[0132] in, For optimal placement force, is the quality of the patch component, is the elastic modulus of the patch element, is the thickness of the circuit board, is the device acceleration, is the number of pins of the SMD component, , , , , is the proportionality coefficient.

[0133] Preferably, the patch mounting module is used to mount the patch component according to the optimal patch path and the optimal mounting force, including:

[0134] The patch equipment starts from the origin and installs each patch coordinate according to the optimal placement force along the optimal patch path.

[0135] It should be noted that the intelligent control system for PCB board patch processing provided in an embodiment of the present invention is used to execute all the process steps of the intelligent control method for PCB board patch processing in the above embodiment. The working principles and beneficial effects of the two correspond one to one, and thus will not be repeated here.

[0136] The embodiment of the present invention further provides an electronic device. The electronic device includes: a processor, a memory, and a computer program stored in the memory and executable on the processor, such as a data acquisition program. When the processor executes the computer program, the steps in the above-mentioned intelligent control method embodiments for PCB board patch processing are implemented, such as Figure 1 Alternatively, when the processor executes the computer program, the functions of the modules / units in the above-mentioned device embodiments are realized, such as the data acquisition module.

[0137] Exemplarily, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, which are used to describe the execution process of the computer program in the electronic device.

[0138] The electronic device may be a computing device such as a desktop computer, a notebook, a PDA, and a smart tablet. The electronic device may include, but is not limited to, a processor and a memory. Those skilled in the art will appreciate that the above components are merely examples of electronic devices and do not constitute a limitation on the electronic device. The electronic device may include more or fewer components than the above components, or may combine certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0139] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the electronic device, and uses various interfaces and lines to connect various parts of the entire electronic device.

[0140] The memory can be used to store the computer program and / or module, and the processor realizes various functions of the electronic device by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0141] Wherein, if the module / unit integrated in the electronic device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0142] It should be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the accompanying drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art may understand and implement it without paying any creative effort.

[0143] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. An intelligent control method for PCB board patch processing, characterized in that: include: Get circuit board layout information, component information and device parameter information; Perform digital coding according to the circuit board layout information to obtain a coding layout diagram; A weighted adjacency matrix is ​​obtained by performing weight calculation according to the coding layout diagram and the component information, including: The elements of the weighted adjacency matrix are calculated using the following formula: in, is the element in the i-th row and j-th column of the weighted adjacency matrix, is the time required for the displacement process from the i-th patch coordinate to the j-th patch coordinate, is the startup time required to move the i-th patch coordinate to the j-th patch coordinate, is the penalty coefficient, is a nozzle replacement indicator function for moving the i-th patch coordinate to the j-th patch coordinate, where i and j are the numbers of the patch coordinates; Among them, the elements of the main diagonal of the weight adjacency matrix are all set to 0; Performing path planning according to the weighted adjacency matrix to obtain an optimal patch path; Calculating the placement force according to the device parameter information and the component information to obtain an optimal placement force includes: The optimal placement force is calculated by the following formula: in, For optimal placement force, is the quality of the patch component, is the elastic modulus of the patch element, is the thickness of the circuit board, is the device acceleration, is the number of pins of the SMD component, , , , , is the proportionality coefficient; The patch component is mounted according to the optimal patch path and the optimal mounting force.

2. The intelligent control method for PCB board patch processing according to claim 1 is characterized in that: The step of performing digital coding according to the circuit board layout information to obtain a coding layout diagram includes: Determine the lower left corner of the circuit board as the coordinate origin; Dividing the circuit board into grids according to a preset grid size; Calculate the patch coordinates of each patch according to the circuit board layout information, wherein the abscissa of the patch coordinates is the column number of the grid, and the ordinate of the patch coordinates is the row number of the grid; Assign a unique integer code to each patch coordinate to obtain a coding layout map.

3. The intelligent control method for PCB board patch processing according to claim 1 is characterized in that: The performing path planning according to the weighted adjacency matrix to obtain an optimal patch path includes: Initialize a distance table and set the distance from all nodes to the starting point to the preset upper limit; Create an access list to record the access status of the node; Select the node with the shortest known distance from the unvisited nodes as the current node; For all unvisited neighbor nodes of the current node, calculate the current distance from the current node to all the neighbor nodes; When the current distance is less than the original distance in the distance table, the current distance is used as the original distance, and the current node is recorded as a predecessor node; When all the neighboring nodes of the current node are processed, updating the access status of the current node to visited; Continue to select the next unvisited node as the current node until the entire visit list is traversed; Starting from the end point, according to the predecessor node information recorded by each node, the optimal patch path is constructed by gradually tracing back to the starting point.

4. The intelligent control method for PCB board patch processing according to claim 1 is characterized in that: The step of installing the patch component according to the optimal patch path and the optimal placement force includes: The patch equipment starts from the origin and installs each patch coordinate according to the optimal placement force along the optimal patch path.

5. The intelligent control method for PCB board patch processing according to claim 1 is characterized in that: The circuit board layout information includes: circuit board thickness, circuit board image, precise coordinates of components on the circuit board and the outline of the components.

6. An intelligent control system for PCB board patch processing, used to implement the intelligent control method for PCB board patch processing according to any one of claims 1 to 5, characterized in that: include: A data acquisition module is used to obtain circuit board layout information, component information and device parameter information; A digital encoding module, used for performing digital encoding according to the circuit board layout information to obtain a coding layout diagram; A weight calculation module, used to perform weight calculation according to the coding layout diagram and the component information to obtain a weight adjacency matrix; A path planning module, used to perform path planning according to the weighted adjacency matrix to obtain an optimal patch path; A mounting force calculation module, used to calculate the mounting force according to the device parameter information and the component information to obtain an optimal mounting force; The patch mounting module is used to mount the patch component according to the optimal patch path and the optimal mounting force.

7. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the intelligent control method for PCB board patch processing as described in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the intelligent control method for PCB board patch processing as described in any one of claims 1 to 5.

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