Semiconductor memory device

Abstract

One embodiment provides a three-dimensional semiconductor memory device capable of reducing cell size. According to one embodiment, a semiconductor memory device includes: a stacked structure including a plurality of first layers and a plurality of second layers alternately stacked in a first direction; and first and second bit lines extending in a first direction within the stacked structure. The plurality of first layers includes: a plurality of word lines extending in a second direction; a plurality of first semiconductor layers extending in the second direction along the plurality of word lines and connected to the first bit lines; a plurality of second semiconductor layers extending in a second direction along the plurality of word lines, adjacent to the plurality of first semiconductor layers in the second direction, and connected to the second bit lines; a plurality of first portions of a plurality of first capacitors connected to the plurality of first semiconductor layers; and a plurality of first portions of a plurality of second capacitors connected to the plurality of second semiconductor layers.

Description

[0001] Related Applications

[0002] This application is based on Japanese Patent Application No. 2023-150300 (filing date: September 15, 2023) and claims priority thereto. This application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Art

[0004] A semiconductor memory device is proposed in which a DRAM (dynamic random access memory) having a three-dimensional structure is integrated on a semiconductor substrate. Summary of the invention

[0005] One embodiment provides a three-dimensional semiconductor memory device capable of reducing a cell size.

[0006] A semiconductor memory device according to an embodiment comprises: a stacked structure, comprising a plurality of first layers and a plurality of second layers alternately stacked along a first direction; a first bit line extending along the first direction within the stacked structure; and a second bit line extending along the first direction within the stacked structure, wherein the plurality of first layers: a plurality of word lines extending along a second direction intersecting the first direction; a plurality of first semiconductor layers extending in the second direction along the plurality of word lines and connected to the first bit lines; a plurality of second semiconductor layers extending in the second direction along the plurality of word lines, being adjacent to the plurality of first semiconductor layers in the second direction and connected to the second bit lines; a plurality of first gate insulating layers arranged between the plurality of word lines and the plurality of first semiconductor layers; a plurality of second gate insulating layers arranged between the plurality of word lines and the plurality of second semiconductor layers; a plurality of first portions of a plurality of first capacitors connected to the plurality of first semiconductor layers; and a plurality of first portions of a plurality of second capacitors connected to the plurality of second semiconductor layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a perspective view schematically showing the structure of a semiconductor memory device according to an embodiment.

[0008] Figure 2 It is a cross-sectional view schematically showing the structure of a semiconductor memory device according to an embodiment.

[0009] Figure 3 It is a cross-sectional view schematically showing the structure of a semiconductor memory device according to an embodiment.

[0010] Figure 4It is a perspective view schematically showing a part of the structure of a semiconductor memory device according to an embodiment.

[0011] Figure 5A It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0012] Figure 5B It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0013] Figure 5C It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0014] Figure 5D It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0015] Figure 5E It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0016] Fig. 5F It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0017] Figure 5G It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0018] Figure 5H It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0019] Fig.5I It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment.

[0020] Figure 5J It is a perspective view schematically showing a part of the method for manufacturing a semiconductor memory device according to the embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments will be described with reference to the drawings.

[0022] The semiconductor memory device of this embodiment is a DRAM having a three-dimensional structure, and has a structure in which a plurality of memory cells are three-dimensionally integrated in a direction perpendicular to and in a direction parallel to a main surface of a semiconductor substrate.

[0023] Figure 1 FIG. 1 is a perspective view schematically showing the structure of a semiconductor storage device according to an embodiment. Figure 1In the figure, in order to facilitate the understanding of the internal structure, a part on the front side of the structure divided into four parts is illustrated with the upper side part deleted, but in fact, there is also an upper side part like the other three parts.

[0024] Figure 2 It is a cross-sectional view perpendicular to the Z direction and schematically shows the structure of the semiconductor memory device according to the embodiment. Figure 3 is a cross-sectional view parallel to the Z direction schematically showing the structure of the semiconductor storage device according to the embodiment, corresponding to the cross-sectional view along the Z direction. Figure 2 The cross section of line A-A.

[0025] exist Figure 1 , Figure 2 as well as Figure 3 In the embodiment, four stacked memory cell structures (hereinafter, for convenience, sometimes referred to as stacked memory cell blocks) having four memory cells stacked in the Z direction are arranged parallel to the XY plane (a plane perpendicular to the Z direction). Figure 1 , Figure 2 as well as Figure 3 In FIG. 4 , four stacked memory cell blocks and 16 memory cells are shown. In fact, the memory cells are arranged along the X direction and the Y direction, respectively. Figure 1 , Figure 2 as well as Figure 3 Multiple unit structures of four stacked memory cell blocks are shown.

[0026] Figure 4 It indicates schematically Figure 1 , Figure 2 as well as Figure 3 A perspective view of a portion of the structure shown. Figure 4 In order to facilitate understanding of the structure, the portion mainly formed of insulating material is deleted for representation.

[0027] In addition, in each figure, the X direction, the Y direction, and the Z direction are directions intersecting each other. Specifically, the X direction, the Y direction, and the Z direction are orthogonal to each other.

[0028] like Figure 1 to Figure 4 As shown, a stacked structure 200 including a plurality of first layers L1 and a plurality of second layers L2 alternately stacked in the Z direction is provided on a semiconductor substrate (silicon substrate) 100 .

[0029] The plurality of first layers L1 respectively include a word line 11 extending in the Y direction, a semiconductor layer 12 extending in the Y direction along the word line 11, a gate insulating layer 13 provided between the word line 11 and the semiconductor layer 12, and a first portion 30a of the capacitor 30. That is, the stacked plurality of first layers L1 include a plurality of stacked word lines 11, a plurality of stacked semiconductor layers 12, a plurality of stacked gate insulating layers 13, and a plurality of stacked first portions 30a of the plurality of capacitors 30.

[0030] A MOS transistor for DRAM is formed by a word line 11 provided in a first layer L1 in a stacked memory cell block, a semiconductor layer 12, and a gate insulating layer 13. That is, the word line 11 functions as a gate electrode, and a channel is formed in the semiconductor layer 12. The word line 11 is formed of a metal material such as tungsten (W), the semiconductor layer 12 is formed of silicon, and the gate insulating layer 13 is formed of silicon oxide.

[0031] The plurality of capacitors 30 stacked in the Z direction are respectively connected to the corresponding semiconductor layers 12 and function as capacitors for DRAM.

[0032] When viewed from the Z direction, the patterns of the multiple word lines 11 stacked in each stacked memory cell block are consistent with each other, the patterns of the multiple semiconductor layers 12 stacked in each stacked memory cell block are consistent with each other, and the patterns of the multiple gate insulating layers 13 stacked in each stacked memory cell block are consistent with each other. In addition, when viewed from the Z direction, the patterns of the multiple first portions 30a stacked in each stacked memory cell block are consistent with each other.

[0033] In addition, when viewed from the Z direction, the pattern of the stacked multiple word lines 11 extends in the Y direction on the same straight line across the multiple stacked memory cell blocks arranged in the Y direction, and the pattern of the stacked multiple semiconductor layers (the stacked multiple first semiconductor layers) 12 adjacent to each other in the Y direction and the pattern of the stacked multiple semiconductor layers (the stacked multiple second semiconductor layers) 12 extend in the Y direction along the same straight line along the pattern of the stacked multiple word lines 11 extending in the Y direction. Therefore, the pattern of the stacked multiple semiconductor layers (the stacked multiple first semiconductor layers) 12 adjacent to each other in the Y direction and the pattern of the stacked multiple semiconductor layers (the stacked multiple second semiconductor layers) 12 are arranged on the same straight line extending in the Y direction. That is, the pattern of the multiple stacked semiconductor layers 12 included in the multiple stacked memory cell blocks arranged in the Y direction is arranged on the same straight line extending in the Y direction.

[0034] The stacked plurality of second layers L2 respectively include the insulating layer 21 and a portion of the second portion 30b of the capacitor 30. That is, the stacked plurality of second layers L2 include the stacked plurality of insulating layers 21 and a portion of the stacked plurality of second portions 30b of the capacitor 30. The plurality of insulating layers 21 respectively include a portion provided between the word lines 11 adjacent to each other in the Z direction and a portion provided between the semiconductor layers 12 adjacent to each other in the Z direction. The insulating layer 21 is formed of silicon oxide.

[0035] When viewed from the Z direction, the patterns of the stacked insulating layers 21 in each stacked memory cell block coincide with each other, and the patterns of the stacked second portions 30 b of the capacitors 30 in each stacked memory cell block coincide with each other.

[0036] Each capacitor 30 includes a capacitor electrode 31, a capacitor electrode 32, and a capacitor dielectric layer 33 provided between the capacitor electrode 31 and the capacitor electrode 32. The capacitor electrode 31 and the capacitor electrode 32 are formed of a metal material such as tungsten (W), and the capacitor dielectric layer 33 is formed of hafnium oxide (HfO x ) etc. Each capacitor electrode 31 is connected to the corresponding semiconductor layer 12. Each capacitor electrode 32 is connected to a common electrode 34 described later.

[0037] As described above, each capacitor 30 includes a first portion 30a and a second portion 30b. The first portion 30a is provided on the first layer L1 and includes a capacitor electrode 31, a capacitor electrode 32a, and a capacitor dielectric layer 33a. The second portion 30b includes a capacitor electrode 31, a capacitor electrode 32b, and a capacitor dielectric layer 33b. That is, the second portion 30b includes a portion provided on the first layer L1 (capacitor electrode 31) and a portion provided on the second layer L2 (capacitor electrode 32b, capacitor dielectric layer 33b).

[0038] A common electrode 34 extending in the Y direction and the Z direction is provided in the stacked structure 200. The common electrode 34 is provided between stacked memory cell blocks adjacent to each other in the X direction. A plurality of capacitor electrodes 32 (capacitor electrodes 32a and capacitor electrodes 32b) stacked in the Z direction are connected to the common electrode 34. The common electrode 34 is formed of a metal material such as tungsten (W).

[0039] In addition, a plurality of bit lines 41 extending in the Z direction and a plurality of body contacts 42 extending in the Z direction are provided in the stacked structure 200. The plurality of bit lines 41 are provided separately from each other, and the plurality of body contacts 42 are also provided separately from each other. In each stacked memory cell block, one bit line 41 and one body contact 42 are provided separately from each other. Each bit line 41 and each body contact 42 have a cylindrical shape.

[0040] In each stacked memory cell block, bit line 41 is connected (contacted) to the stacked semiconductor layers 12, and body contact 42 is connected (contacted) to the stacked semiconductor layers 12. Bit line 41 functions as a bit line for DRAM, and body contact 42 is given a predetermined potential.

[0041] The plurality of bit lines 41 and the plurality of body contacts 42 are formed of the same conductive material (or may not necessarily be formed of the same conductive material). Specifically, the bit lines 41 and the body contacts 42 are formed of a metal material such as tungsten (W).

[0042] In addition, an insulating portion 51 extending in the Z direction is provided in the stacked structure 200. The insulating portion 51 includes an insulating portion 51a and an insulating portion 51b which are provided integrally. The insulating portion 51a extends in the X direction and the Z direction in the stacked structure 200, and is provided between the stacked plurality of semiconductor layers (the stacked plurality of first semiconductor layers) 12 and the stacked plurality of semiconductor layers (the stacked plurality of second semiconductor layers) 12 which are adjacent to each other in the Y direction. The insulating portion 51b extends in the Y direction and the Z direction in the stacked structure 200, and is adjacent to the stacked plurality of semiconductor layers 12 in the X direction. When viewed from the Z direction, the pattern of the bit line 41 and the pattern of the body contact 42 are provided between the pattern of the stacked plurality of semiconductor layers 12 and the pattern of the insulating portion 51b.

[0043] In addition, an insulating portion 52 extending in the Y direction and the Z direction is provided in the stacked structure 200. The insulating portion 52 is adjacent to the stacked word lines 11, provided along the stacked word lines 11, and provided between stacked memory cell blocks adjacent to each other in the X direction.

[0044] The insulating portion 51 (the insulating portion 51 a and the insulating portion 51 b ) and the insulating portion 52 described above are formed of silicon oxide.

[0045] An upper insulating layer 53 is provided on the stacked structure 200, the bit lines 41, the body contacts 42, the insulating portions 51, and the insulating portions 52 (the upper insulating layer 53 may not be provided). The upper insulating layer 53 is formed of silicon nitride.

[0046] As described above, the semiconductor memory device of this embodiment includes word lines 11 and semiconductor layers 12 provided along the word lines 11 in each of a plurality of first layers L1 stacked in the Z direction. With this configuration, the cell size of the memory cell can be reduced as described below in this embodiment.

[0047] In this embodiment, the word line 11 and the semiconductor layer 12 are both provided in the first layer L1, so that the vertical spacing of the memory cells stacked in the vertical direction (Z direction) can be reduced, and the vertical height can be reduced. If the word line and the semiconductor layer are provided in different layers, a layer for the word line and a layer for the semiconductor layer are required, so the vertical height becomes higher. In this embodiment, the word line 11 and the semiconductor layer 12 are provided in a common layer (first layer L1), so the vertical dimension can be reduced.

[0048] In addition, in this embodiment, a semiconductor layer 12 is provided along the word line 11, so that the horizontal spacing of the memory cells arranged in the horizontal direction (the direction parallel to the XY plane) can be reduced, and the horizontal area can be reduced. Assuming that the semiconductor layer is not provided along the word line, the extension direction of the word line is different from the extension direction of the semiconductor layer, the gate electrode portion of the word line must be parallel to the semiconductor layer, and the gate electrode portion needs to be branched from the word line body. In this embodiment, a semiconductor layer 12 is provided along the word line 11, and the word line 11 and the semiconductor layer 12 extend in the same direction, so the horizontal dimension can be reduced.

[0049] Next, refer to Figure 5A to Figure 5J A method for manufacturing a semiconductor memory device according to this embodiment is described. Figure 5A to Figure 5J In the stereogram shown, Figure 1 Similarly, in the stereoscopic view shown, one of the parts on the front side of the structure divided into four parts is shown with the upper layer side portion deleted, but in fact, the upper layer side portion also exists like the other three parts.

[0050] First, if Figure 5A As shown, a stacked structure 200a is formed on a semiconductor substrate (silicon substrate) 100. The stacked structure 200a has a structure in which a plurality of semiconductor layers 12 and a plurality of sacrificial layers 22 are alternately stacked along the Z direction. Silicon (Si) is used in the semiconductor layer 12, and silicon germanium (SiGe) is used in the sacrificial layer 22. Both the semiconductor layer (Si layer) 12 and the sacrificial layer (SiGe layer) 22 have a single crystal structure. Next, a silicon nitride layer is formed on the stacked structure 200a as an upper insulating layer 53a.

[0051] Next, if Figure 5B As shown in FIG. 1 , a groove reaching the semiconductor substrate 100 is formed in the upper insulating layer 53a and the stacked structure 200a, and the groove is filled with an insulating material (silicon oxide). Thus, an insulating portion 51p is formed.

[0052] Next, if Figure 5C As shown, a portion of the upper insulating layer 53 a and a portion of the stacked structure 200 a are removed to form a groove for the insulating portion 52 .

[0053] Next, if Figure 5D As shown in FIG. 1 , the sacrificial layer (SiGe layer) 22 is replaced by the insulating layer (silicon oxide layer) 21. Specifically, by Figure 5C The plurality of sacrificial layers (SiGe layers) 22 are etched through the grooves formed in the process to form a plurality of spaces, and the plurality of spaces are filled with silicon oxide to form an insulating layer (silicon oxide layer) 21. Thus, a stacked structure 200b in which a plurality of semiconductor layers 12 and a plurality of insulating layers 21 are alternately stacked along the Z direction can be obtained.

[0054] Next, if Figure 5E As shown, a portion of each of the plurality of semiconductor layers (Si layers) 12 is removed to form a plurality of spaces 12s1.

[0055] Next, if Fig. 5F As shown in Figure 5E The plurality of spaces 12s1 formed in the process of oxidizing the plurality of semiconductor layers (Si layers) 12, thereby forming a plurality of gate insulating layers (silicon oxide layers) 13. After the gate insulating layers 13 are formed, the plurality of spaces 12s1 are filled with a metal material such as tungsten (W), thereby forming a plurality of word lines 11. Furthermore, the plurality of spaces 12s1 are filled with an insulating material such as silicon oxide. Figure 5C The groove formed in the process of forming the insulating portion 52 is formed. In this way, the stacked structure 200c is obtained.

[0056] Next, if Figure 5G As shown, a hole 41 h for the bit line 41 and a hole 42 h for the body contact 42 are formed so that the surface of the semiconductor substrate 100 is exposed.

[0057] Next, if Figure 5H As shown, the surface region of the semiconductor substrate 100 at the bottom of the hole 41h and the surface region of the semiconductor substrate 100 at the bottom of the hole 42h are doped with impurity elements, respectively. Furthermore, the hole 41h and the hole 42h are filled with a metal material such as tungsten (W), thereby forming the bit line 41 and the body contact 42.

[0058] Next, if Fig.5I As shown, Figure 5H A silicon nitride layer is formed on the structure obtained in the process to obtain an upper insulating layer 53. Furthermore, a groove 34t for the common electrode 34 is formed in the upper insulating layer 53, the stacked structure 200c and the insulating portion 51p, so that the surface of the semiconductor substrate 100 is exposed.

[0059] Next, if Figure 5J As shown, a portion of each of the plurality of semiconductor layers 12 is etched through the groove 34t to form a plurality of spaces 12s2.

[0060] Afterwards, if Figure 1, Figure 2 as well as Figure 3 As shown, multiple capacitors 30 and common electrodes 34 are formed in multiple spaces 12s2 and grooves 34t. Specifically, first, multiple capacitor electrodes 31 are formed in multiple spaces 12s2. Then, multiple insulating layers 21 are etched to form multiple spaces. At this time, the insulating portion 51p is also etched to form a groove. Moreover, capacitor dielectric layers 33 and capacitor electrodes 32 are formed in the multiple spaces and grooves obtained in this way. When the capacitor electrode 32 is formed, the common electrode 34 is formed in the groove 34t.

[0061] As described above, a Figure 1 , Figure 2 , Figure 3 as well as Figure 4 A semiconductor memory device having a structure as shown.

[0062] The above-described manufacturing method can reliably form a semiconductor memory device including a plurality of memory cells having a reduced cell size.

[0063] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor storage device, characterized in that: have: A stacked structure comprising a plurality of first layers and a plurality of second layers alternately stacked along a first direction; a first bit line extending in the first direction within the stacked structure; and a second bit line extending in the stacked structure along the first direction, The plurality of first layers include: a plurality of word lines extending along a second direction intersecting the first direction; a plurality of first semiconductor layers extending along the plurality of word lines in the second direction and connected to the first bit lines; a plurality of second semiconductor layers extending along the plurality of word lines in the second direction, adjacent to the plurality of first semiconductor layers in the second direction, and connected to the second bit lines; A plurality of first gate insulating layers, disposed between the plurality of word lines and the plurality of first semiconductor layers; A plurality of second gate insulating layers, disposed between the plurality of word lines and the plurality of second semiconductor layers; a plurality of first portions of a plurality of first capacitors connected to the plurality of first semiconductor layers; as well as A plurality of first portions of a plurality of second capacitors are connected to the plurality of second semiconductor layers.

2. The semiconductor memory device according to claim 1, wherein: When viewed from the first direction, patterns of the plurality of word lines are consistent with each other.

3. The semiconductor memory device according to claim 1, wherein: When viewed from the first direction, patterns of the plurality of first semiconductor layers are consistent with each other, and patterns of the plurality of second semiconductor layers are consistent with each other.

4. The semiconductor memory device according to claim 1, wherein: When viewed from the first direction, the patterns of the plurality of first semiconductor layers and the patterns of the plurality of second semiconductor layers are arranged on the same straight line extending along the second direction.

5. The semiconductor memory device according to claim 1, wherein: Also available: A first body contact extending along the first direction in the stacked structure and connected to the plurality of first semiconductor layers; and The second body contact extends along the first direction in the stacked structure and is connected to the plurality of second semiconductor layers.

6. The semiconductor memory device according to claim 5, wherein: The first bit line, the second bit line, the first body contact, and the second body contact are formed of a same conductive material.

7. The semiconductor memory device according to claim 1, wherein: The plurality of second layers include a plurality of insulating layers, The plurality of insulating layers respectively include a portion provided between the word lines adjacent to each other in the first direction, a portion provided between the first semiconductor layers adjacent to each other in the first direction, and a portion provided between the second semiconductor layers adjacent to each other in the first direction.

8. The semiconductor memory device according to claim 1, wherein: The plurality of first capacitors further include a plurality of second portions, wherein the plurality of second portions of the plurality of first capacitors include portions disposed in the plurality of second layers, The plurality of second capacitors further include a plurality of second portions, and the plurality of second portions of the plurality of second capacitors include portions disposed in the plurality of second layers.

9. The semiconductor memory device according to claim 1, wherein: Each of the plurality of first capacitors and each of the plurality of second capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric layer provided between the first capacitor electrode and the second capacitor electrode.

10. The semiconductor memory device according to claim 9, wherein: The first capacitor electrode of each of the plurality of first capacitors is connected to the corresponding first semiconductor layer. A first capacitor electrode of each of the plurality of second capacitors is connected to the corresponding second semiconductor layer.

11. The semiconductor memory device according to claim 9, wherein: A common electrode is further provided, the common electrode extending in the first direction and the second direction in the stacked structure, connected to the second capacitor electrodes of the plurality of first capacitors, and connected to the second capacitor electrodes of the plurality of second capacitors.

12. The semiconductor memory device according to claim 1, wherein: A first insulating portion is further provided, the first insulating portion extending along the first direction in the stacked structure and provided between the plurality of first semiconductor layers and the plurality of second semiconductor layers.

13. The semiconductor memory device according to claim 12, wherein: A second insulating portion is further provided, the second insulating portion extending along the first direction in the stacked structure and adjacent to the plurality of first semiconductor layers in a third direction intersecting the first direction and the second direction.

14. The semiconductor memory device according to claim 13, wherein: The first insulating portion and the second insulating portion are integrally provided.

15. The semiconductor memory device according to claim 13, wherein: The pattern of the first bit line is disposed between the patterns of the plurality of first semiconductor layers and the pattern of the second insulating portion when viewed from the first direction.

16. The semiconductor memory device according to claim 13, wherein: A third insulating portion is further provided, the third insulating portion extending along the first direction in the stacked structure and arranged along the plurality of word lines.

Images