Group III-N devices including source contacts connected to substrate through trenches

Abstract

The invention relates to a group III-N device including a source contact connected to a substrate through a trench. In one example, a semiconductor device (100) includes a semiconductor substrate (102) including a source region (105A), a gate region (105B), a drain region (105D), and a drain access region (105C), with a heterojunction structure (106) disposed over the semiconductor substrate (102). The heterojunction structure (106) includes a buffer layer (104) over the semiconductor substrate (102) and a barrier layer (110) over the buffer layer (104). A gate stack (112) is disposed over the barrier layer (110) in the gate region (105B). A source contact (122A) in the source region (105A) extends into the semiconductor substrate (102), the source contact including a first contact (124A) with a 2DEG (108) in the heterojunction structure (106) and a second contact (124B) with the semiconductor substrate (102).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This non-provisional application claims priority based on U.S. Provisional Application No. 63 / 582,982, filed on September 15, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The disclosed embodiments relate generally to the field of III-N semiconductor devices and their fabrication. Background Art

[0004] Group III nitride materials (also referred to as III-N materials) have a unique combination of physical and electrical properties that are found to be beneficial for modern microelectronics and optoelectronics. These properties include wide bandgap, high saturation drift rate, high breakdown voltage, high thermal conductivity, strong chemical and thermal stability, etc. Due to these characteristics, III-N materials are viewed as promising materials for fabricating high-power, high-frequency transistor structures capable of operating at high temperatures and in adverse environments. Although III-N devices and their fabrication continue to advance at a rapid pace, several drawbacks remain, requiring further innovations as described below. Summary of the invention

[0005] A simplified overview is presented below to provide a basic understanding of some examples of the present disclosure. The present summary is not an extensive overview of the examples, and is neither intended to identify the key or important elements of the examples nor to describe their scope. In fact, the main purpose of the present summary is to present some concepts of the present disclosure in a simplified form as a preface to the more detailed description presented in the following additional subsequent sections.

[0006] Examples of the present disclosure are directed to III-N semiconductor devices having source contacts extending into a substrate by means of a deep trench structure. In one example, a semiconductor device includes a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region between the drain region and the gate region, wherein a heterojunction structure is disposed above the semiconductor substrate. The heterojunction structure includes a buffer layer above the semiconductor substrate and a barrier layer above the buffer layer. A gate stack is disposed above the barrier layer in the gate region. A source contact in the source region extends into the semiconductor substrate, wherein the source contact includes a first contact to a 2DEG in the heterojunction structure and a second contact to the semiconductor substrate.

[0007] In one example, a method of manufacturing a semiconductor device is disclosed. The method includes, among other things: forming a heterojunction structure over a semiconductor substrate, the semiconductor substrate including a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region, the heterojunction structure including a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer; forming a gate stack in the gate region over the barrier layer; and forming a source contact in the source region, the source contact extending into the semiconductor substrate, wherein the source contact includes a first contact to a 2DEG in the heterojunction structure and a second contact to the semiconductor substrate. In some arrangements, the source contact may be formed before forming a gate electrode coupled to the gate stack. In some arrangements, the gate electrode may be formed before forming the source contact (and in some examples, the drain contact).

[0008] In one example, a semiconductor device is disclosed that includes, among other things: a first III-N unit cell formed over a first region of a semiconductor substrate, the first III-N unit cell including a first source contact in a source region of the first region, wherein the first source contact is connected to the semiconductor substrate via a trench extending into the semiconductor substrate; and a second III-N unit cell formed over a second region of the semiconductor substrate, the second III-N unit cell including a second source contact in a source region of the second region, wherein the first III-N unit cell and the second III-N unit cell are coupled together via a common gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the various figures of the accompanying drawings, embodiments of the present disclosure are shown by way of example and not by way of limitation. Different references to "an" or "one" embodiment in the present disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is also possible that this feature, structure, or characteristic is combined with other embodiments, whether or not explicitly described.

[0010] To illustrate one or more exemplary embodiments of the present disclosure, the accompanying drawings are incorporated into and form a part of the specification. Various advantages and features of the present disclosure are described in the following detailed description in conjunction with the appended claims and with reference to the accompanying drawings, in which:

[0011] Figures 1A-1K depicts cross-sectional views of a semiconductor device including a GaN device at various stages of a process flow according to a first example of the present disclosure;

[0012] Figures 2A-2H depicts cross-sectional views of a semiconductor device including a GaN device at various stages of a process flow according to a second example of the present disclosure;

[0013] Figures 3A-3J depicts cross-sectional views of a semiconductor device including a GaN device at various stages of a process flow according to a third example of the present disclosure;

[0014] Figures 4A-4I depicts cross-sectional views of a semiconductor device including a GaN device at various stages of a process flow according to a fourth example of the present disclosure;

[0015] Figure 5 and 6 depicts a layout of an example semiconductor device including a GaN unit cell according to some examples of the present disclosure;

[0016] Fig. 7A and 7B depicts a layout of an example semiconductor device including a plurality of GaN unit cells according to some examples of the present disclosure; and

[0017] Figures 8A-8D is a flow chart of a method of manufacturing a semiconductor device according to some examples of the present disclosure. DETAILED DESCRIPTION

[0018] Examples of the present disclosure are described with reference to the accompanying drawings, in which similar reference numerals are generally used to refer to similar elements. The figures are not drawn to scale, and only the figures are provided to illustrate the examples. Many specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, some examples may be practiced without such specific details. In other instances, well-known subsystems, components, structures, and techniques have not yet been shown in detail to avoid confusing the understanding of the examples. Therefore, examples of the present disclosure may be practiced without such specific components.

[0019] In addition, in the following specific embodiments, claims or both, terms such as "coupling" and "connection" and their derivatives can be used. It should be understood that these terms are not necessarily intended to be synonyms for each other. "Coupling" can be used to indicate that two or more elements (which may or may not be in direct physical or electrical contact with each other) cooperate or interact with each other. "Connection" can be used to indicate the establishment of communication (that is, communication relationship) between two or more elements coupled to each other. In addition, in one or more examples set forth herein, in general, if an element can be programmed to perform or otherwise structurally arranged to perform a certain function, an element, assembly or module can be configured to perform the function.

[0020] Without limitation, examples of the present disclosure will be described below in the context of improving performance characteristics of semiconductor devices based on Group III-nitride materials (also referred to as III-N materials), such as gallium nitride (GaN) devices.

[0021] GaN devices (e.g., GaN transistors) offer certain performance advantages over silicon, including lower on-state resistance (e.g., drain-source resistance or RDSON), lower switching losses, and improved breakdown voltage, among others. GaN transistors include a heteroepitaxial structure (e.g., a heterojunction structure) having a junction between materials of different bandgaps (e.g., aluminum gallium nitride (AlGaN) and gallium nitride) to provide a 2-dimensional electron gas (2DEG) formed within the AlGaN / GaN heteroepitaxial structure for device operation (e.g., forming a channel of a GaN device). The 2-dimensional electron gas (2DEG) may be referred to as a 2DEG channel. Depletion mode (DMODE) GaN transistors are typically on, while enhancement mode (EMODE) GaN transistors are typically off. In some examples, an EMODE GaN transistor includes a gate stack having a p-type doped gallium nitride (p-GaN) layer that depletes the 2DEG under the gate at zero or negative gate bias. Applying a positive gate voltage enhances the 2DEG under the gate and turns on the EMODE GaN device to allow current to flow between the source and drain.

[0022] In some examples, GaN devices may be formed with one or more GaN layers over a suitable semiconductor substrate (e.g., including a silicon substrate). In this approach and for proper operation, one or more electrical contacts from higher layers in the device to the semiconductor substrate are required. For example, such contacts permit a constant bias voltage to be maintained in the substrate and enable the GaN device to handle higher currents. However, integrating suitable contacts relative to the substrate while achieving the desired circuit density has been challenging.

[0023] Substrate contact connections (which may be referred to as substrate connections or substrate contacts) are particularly important for GaN power devices. In some examples, substrate connections may be achieved through a through-GaN via process in a dedicated non-active area of ​​the die, which may result in a reduction in the die area of ​​the active device area. In order to mitigate the die area loss due to substrate connections, in example embodiments, the number of through-GaN vias may be limited. However, reducing the number of substrate connections and / or distributing substrate connections outside the active area may have a negative impact on the specific on-resistance (Rsp) performance of the GaN device, especially in architectures that include several unit cells (e.g., about hundreds or thousands of unit cells). As the Rsp value increases, the charging / discharging of the parasitic capacitance may also increase and may become non-uniform, resulting in a decrease in the switching performance of the GaN device.

[0024] The examples of the present disclosure recognize the foregoing challenges and provide an integrated substrate contact solution in which the source contact and the substrate contact are integrated in a deep trench structure formed in the source region of the semiconductor device. In some arrangements, a metallization process is provided that connects the 2DEG of the device to a doped well (e.g., N-well or P-well) in the substrate (e.g., in the case of a discrete device) or the substrate of an IC device. Since a dedicated non-active area for a through-hole substrate connection, which may be distributed and / or shared between several unit cells in some examples, is not required, the source-substrate resistance of each individual unit cell may be made more uniform, thereby improving the switching performance of the device. Since each unit cell has its own substrate connection, the substrate bias effect may also become more uniform. In addition, since the separated nature of the thermal resistance path of the GaN device helps to bypass the high thermal impedance paths and / or locations of the baseline GaN device, the thermal performance may also be improved. Although the examples herein may provide various structures, materials, and processes that may produce these and other beneficial effects in various device modes, no specific results are required unless explicitly stated in a specific technical solution.

[0025] Turning to the schema, Figures 1A-1K Depicted are cross-sectional views of a semiconductor device 100 including a GaN device 101 at various stages of a process flow according to a first example of the present disclosure. By way of illustration, the GaN device 101 may be fabricated as an EMODE device, where for purposes herein, a substrate-connected source contact may be disposed in a deep trench formed in a source region of the GaN device. In a similar manner, Figures 2A-2H, 3A-3J and 4A-4I respectively depict semiconductor devices 200, 300 and 400 at various stages of a process flow according to additional and / or alternative examples of the present disclosure, wherein a substrate-connected source contact may be disposed in a deep trench formed in a source region. As will be described in detail below, according to an embodiment, the manufacture of a substrate-connected source contact may be integrated into a GaN process flow at different stages. Typically, a substrate-connected source contact, also referred to in some examples as a substrate-tied source contact or a deep trench source contact, may be manufactured before the formation of a gate electrode of a GaN device or after the formation of a gate electrode of a GaN device. An example process in which a deep trench source (DTS) contact (e.g., a source contact extending into a substrate in a source region) is formed before forming a gate electrode may be referred to as a "gate-last" process. Similarly, an example process in which a DTS contact is formed after forming a gate electrode may be referred to as a "gate-first" process. Regardless of the stage of integration relative to the formation of the DTS contact, the representative examples herein can be configured to provide an integrated source contact structure comprising a first contact coupled to the 2DEG of the device (e.g., a first portion of a deep trench source contact) and a second contact coupled to the substrate (e.g., a second portion of the deep trench source contact), which can be scaled to a variety of device architectures, as will be described below.

[0026] Specifically refer to Figures 1A-1K , an example “gate-last” process of the present disclosure is described in detail below. Figure 1A An early intermediate stage of semiconductor device 100 is depicted formed on a portion of semiconductor substrate 102, which may be provided as a silicon wafer, a silicon-on-sapphire wafer, or a silicon carbide wafer, and / or provided as a semiconductor substrate including a core optimized for coefficient of thermal expansion (CTE) matching, etc. A buffer layer 104 including one or more layers of III-N semiconductor material is formed on substrate 102. In some examples where substrate 102 is implemented as a silicon wafer or a sapphire wafer, buffer layer 104 may include a nucleation layer having a stoichiometry including aluminum to match the lattice constant of substrate 102. In some example versions, buffer layer 104 may further include a reduced aluminum content aluminum gallium nitride (AlGaN) layer / sublayer, including an unintentionally doped (UID) GaN sublayer in some arrangements. For purposes of example herein, individual layers / sublayers of a buffer layer (e.g., buffer layer 104) are not specifically shown in the drawings of the present disclosure.

[0027] According to an embodiment, the buffer layer 104 may have a thickness of about 1 micron (μm) to several microns (e.g., 3.5 μm to 7.0 μm), which may be formed by a suitable epitaxial process (e.g., a metal organic vapor phase epitaxy (MOVPE) process) using several operations to form various layers and / or sublayers. In some arrangements, the example buffer layer 104 may include a stack of multiple layers / sublayers of suitable materials and compositions (e.g., GaN, AlGaN) mentioned above, wherein the layers / sublayers may have variable thicknesses depending on the technology and device application. In some arrangements, the buffer layer 104 may include an AlGaN-based transition layer, an epitaxial layer having a strained layer superlattice (SLS) structure, and the like.

[0028] Depending on the size design of the GaN device 101, the buffer layer 104 can be formed to overlap with a region of the substrate 102, wherein different regions, such as the source region 105A, the gate region 105B, the drain region 105D, and the drain access region 105C between the gate region 105B and the drain region 105D, can be arranged relative to the GaN device 101. The channel layer can be arranged as a part of the buffer layer 104, for example, the buffer layer 104 is close to the top portion of the barrier layer 110. Although the channel layer can mainly include GaN material, in some embodiments, optional trace amounts of other Group III elements, such as aluminum or indium, can be present.

[0029] A barrier layer 110 comprising a III-N semiconductor material is formed over the buffer layer 104. In an example arrangement, the barrier layer 110 may have a thickness in a range of about 1 nanometer (nm) to about 60 nm, and may include aluminum and nitrogen. In some versions of this example, the barrier layer 110 may include gallium at a lower atomic percentage than aluminum. In some versions, the barrier layer 110 may also include indium. In some examples, the barrier layer 110 includes an AlGaN layer.

[0030] The barrier layer 110 above the buffer layer 104 may operate as part of the heterojunction structure 106 to facilitate the formation of the 2DEG 108 near the interface between the barrier layer 110 and the buffer layer 104. In some examples, the stoichiometry and thickness of the barrier layer 110 may be configured to provide a suitable free carrier density of the 2DEG (e.g., 3×10 12 cm -2 to 2×10 13 cm -2 ) to facilitate device operation.

[0031] For the purpose of achieving EMODE functionality, a p-doped III-N (p-III-N, p-GaN) layer 114 (e.g., one or more layers including III-N material) is formed over the barrier layer 110, such as Figure 1AThe formation of the p-GaN layer 114 causes the 2DEG to be reduced, for example, absent in some cases. In a version of this example, the p-doped III-N layer 114 may include a GaN layer doped with magnesium (Mg) or other p-type dopants. In some examples, the p-doped GaN layer 114 may include about 1x10 20 atoms / cm 3 The p-GaN layer 114 may have a peak p-dopant concentration of 100 nm and may have a thickness of about 50 nm to 200 nm. In some additional and / or alternative arrangements, an additional layer such as an AlGaN cap layer (eg, not p-doped; not shown) may be disposed over the p-GaN layer 114.

[0032] Figure 1B A stage is depicted after patterning the p-GaN layer 114 using a gate stack mask and appropriate photolithography and etching processes to form a portion of the gate stack 112, which in some embodiments may include additional layers. As a result of patterning the p-GaN layer 114 (e.g., removing portions of the p-GaN layer 114 outside the gate region 105B), a 2DEG 108 may be established in the channel layer outside the gate region 105B. In the example version herein, the source region 105A (where a source electrode or source contact including a DTS will be formed) and the drain region 105D (where a drain electrode or drain contact will be formed) are asymmetrically disposed relative to the gate region 105B, but this is not required. For example, due to an access region (e.g., drain access region 105C) disposed between the gate region 105B and the drain region 105D, the lateral distance between the gate region 105B and the drain region 105D may be greater than the lateral distance between the gate region 105B and the source region 105A. In some additional and / or alternative arrangements, a source access region may also be disposed between the source region 105A and the gate region 105B in a similar manner while still having source / drain region asymmetry relative to the gate region 105B.

[0033] Figure 1C A stage is depicted in which a dielectric layer 116 is formed over the gate stack 112. In some examples, the dielectric layer 116 may have a thickness of approximately 50 nm to 100 nm and may include silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), aluminum oxide (AlO), etc., deposited in a CVD process.

[0034] Figure 1DDepicted is a stage in which a contact aperture or opening 118 having a suitable form factor and size (e.g., including a rectangular shape, a square shape, etc.) is formed in the drain region 105D of the device 101. The aperture 118 may be formed by etching or removing material from the dielectric layer 116 and the barrier layer 110 over the buffer layer 104, for example, using a contact mask and a patterned etching process including wet etching and / or dry etching, thereby exposing the buffer layer 104 in the drain region 105D.

[0035] Figure 1E A stage is depicted in which a trench 120 having a suitable form factor and size (e.g., including a rectangular shape, a square shape, etc.) is formed in a source region 105A of a device 101, the trench extending to a suitable depth in a substrate 102 according to an embodiment. In some examples, the trench 120 may be formed by a high aspect ratio etching (HARE) process. In some examples, the trench 120 may have a depth 125 from a top surface of the barrier layer 110 to a bottom 121 of the trench 120 extending into the semiconductor substrate 102. In some examples, the trench 120 may have a width 123 that is a fraction of the depth 125. In some examples, the depth 125 may be in a range of about 0.1 μm to about 10 μm. According to an embodiment, the trench 120 may have an aspect ratio in which the depth 125 is greater than the width 123 by a factor of at least three.

[0036] In an example embodiment, the trench 120 may be formed using an inductively coupled plasma (ICP) based deep reactive ion etching (DRIE) etching process, but is not limited thereto. Figure 1E The formation of a single trench (e.g., trench 120) is shown in the cross-sectional view of FIG, but some additional and / or alternative examples may have multiple trenches (e.g., with corresponding sizes and form factors) formed in the source region 105A extending into the substrate 102. In addition, according to the embodiment, DRIE processes with different etch rates, chemistries, etc. may be implemented for different layers / sublayers of the buffer layer stack 104. In yet another arrangement, in addition to the trench 120, the source region 105A of the GaN device 101 may also include one or more source contact openings ( Figure 1E ), wherein the source contact opening only extends to the buffer layer 104 for facilitating the formation of a source contact that is not connected to the semiconductor substrate 102.

[0037] Figure 1FThe stage of forming the DTS contact or electrode 122A and the drain contact or electrode 122B using a suitable metallization process is depicted. According to an embodiment, the DTS contact 122A and the drain contact 122B may include one or more metals, such as titanium, nickel, tungsten, platinum, iridium, aluminum, gold, etc., and / or may include other conductive materials, such as carbon nanotubes or graphene. The DTS contact 122A may include a first contact 124A, which is configured to contact the 2DEG 108 of the heterojunction structure 106 (e.g., an ohmic contact), and a second contact 124B is made at or near the bottom 121 of the trench 120, which is configured to contact the semiconductor substrate 102 (e.g., an ohmic contact). Although DTS contact 122A is depicted as being completely filled with one or more metals, in some examples, DTS contact 122A may include one or more seams (e.g., voids, cavities), depending on the aspect ratio of trench 120 and the characteristics of the metal deposition step. By way of example, such seams may extend to the top of DTS contact 122A. In other examples, such seams may be enclosed (e.g., sealed) within DTS contact 122A.

[0038] Figure 1G Depicted is a stage in which a dielectric layer 130 of suitable thickness and composition is formed over the GaN device 101. In this illustrated version, the dielectric layer 130 is operable to mask and protect the DTS contact 122A and the drain contact 122B from subsequent processing (eg, gate electrode formation).

[0039] Figure 1H Depicted is a stage where a gate electrode lithography and etching process is performed to form an aperture 132 exposing the p-GaN layer 114 of the gate stack 112 . Fig. 1I A stage is depicted at which a gate electrode (or contact) 122C is formed using a suitable metallization process. Similar to the formation of the DTS contact 122A and the drain contact 122B, the gate electrode 122C may include metals such as titanium, nickel, tungsten, platinum, iridium, aluminum, and / or other conductive materials such as carbon nanotubes or graphene.

[0040] exist Figure 1J, a cross-sectional view of a more fully formed semiconductor device 100 including a GaN device 101 is shown. As depicted, a dielectric layer 140 (e.g., operable as an inter-level dielectric (ILD) and / or pre-metal dielectric (PMD) insulator) is formed over the GaN device 101. In some embodiments, the dielectric layer 140 may include multiple layers of different compositions, such as SiN, SiO, etc., with a total thickness ranging from about 0.5 μm to about 5 μm. The contact lithography and etching processes may be configured to pattern contact openings in the dielectric layer 140 over the source region 105A, the gate region 105B (not shown), and the drain region 105D. A source terminal or contact 144A is formed extending through the dielectric layer 140 for electrical contact with the DTS electrode 122A in the source region 105A. In a similar manner, a drain terminal or contact 144B is formed through dielectric layer 140 for electrical contact with drain electrode 122B. Although a gate terminal is also formed for contact with gate electrode 122C, in Figure 1J 144A and drain terminal 144B, as provided herein for purposes of illustration. According to an embodiment, source terminal 144A and drain terminal 144B may include various metals and / or other conductive materials, which may be similar to the composition of DTS electrode 122A, drain electrode 122B, and gate electrode 122C, but this is not required.

[0041] Although DTS contact 122A is Figure 1F 105A, depending on the aspect ratio of the trench 120 and the characteristics of the metal deposition step that forms the DTS contact 122A, as previously mentioned. In general, the presence or absence of a trench cavity may depend on the device design, such as the trench aspect ratio, the metal thickness, and / or the thickness of the GaN epitaxial stack that needs to be etched through, etc. In some arrangements, the cavity in the DTS contact, if present, may be filled with one or more dielectric materials in a subsequent stage, which may be removed in a back-end metallization process for forming corresponding terminals in the source, drain, and gate regions as described above. Thus, the cavity in the DTS contact, if present, may be at least partially filled with one or more dielectric materials, one or more metals, or a combination thereof.

[0042] In some additional and / or alternative arrangements, various portions of a DTS contact (e.g., DTS contact 122A) may be fabricated using different metals, such as a first metal for forming a first contact 124A to the 2DEG 108 and a second metal for forming a second contact 124B to the semiconductor substrate 102, such as Figure 1K . In such an arrangement, separate masks may be used to form the bottom and top portions of the DTS contact 122A, where different metals may be deposited for contact formation, such as platinum may be deposited for contact with the semiconductor substrate 102 and tungsten may be deposited for contact with the 2DEG 108 of the GaN device 101. In some representative versions of this example, a first metal may be deposited in the trench, which may be patterned using a first mask and a metal etching process for forming a substrate contact (e.g., a portion 150B including the second contact 124B). In some arrangements, the size of the first metal mask may be appropriately designed relative to the trench size design. A second metal may be deposited in the partially filled trench for forming a contact with respect to the 2DEG 108 (e.g., a portion 150A including the first contact 124A), including a capping layer for facilitating fabrication of a DTS electrode over the heterojunction structure 106. The second metal may be patterned using a second mask and a metal etching process, thereby forming a complete DTS contact structure in the source region of the GaN device 101. As will be explained below, similar bimetallic DTS contact structures may be provided in other examples of the present disclosure.

[0043] Figures 2A-2H Depicted are cross-sectional views of a semiconductor device 200 including a GaN device 201 at various stages of another "gate last" process flow according to another example of the present disclosure. In general, Figures 2A-2H The stages shown in Figures 1A-1K The corresponding stages shown in are substantially similar or identical. Figures 1A-1K The description set out here is largely applicable in relevant parts to Figures 2A-2H The various corresponding structures and features shown in the cross-sectional view will not be repeated in detail here except for what will be mentioned below.

[0044] Similar to Figures 1A-1C , the intermediate level of the semiconductor device 200 includes a semiconductor substrate 202, wherein a source region 205A, a gate region 205B, a drain region 205D, and a drain access region 205C between the gate region 205B and the drain region 205D may be disposed relative to the GaN device 201. A gate stack 212 including a p-GaN layer 214 is formed over a heterojunction structure 206 disposed over the substrate 202. As previously described, the heterojunction structure 206 includes a barrier layer 210 over a buffer layer 204, the barrier layer supporting a 2DEG 208 in the buffer layer 204 proximate to an interface between the barrier layer 210 and the buffer layer 204. Figure 2C, a dielectric layer 216 is formed over the barrier layer 210 and the gate stack 212. In this exemplary version, the dielectric layer 216 is operable to protect the p-GaN gate 214 during subsequent process stages of DTS and drain contact formation.

[0045] although Figure 1E The trench formation stage in involves fabricating a trench having a uniform vertical profile (e.g., a straight profile), such as trench 120, but the example GaN device 201 includes a "stepped" trench, where the trench profile may include a shallow upper portion that is wider than a deeper lower portion, thereby forming a ledge or edge in the trench profile. In some versions of this example, a first portion (e.g., an upper portion) of the trench may be provided for facilitating a wider source contact (e.g., a larger perimeter) configured to contact the 2DEG 208 at a shallow ledge (e.g., having a larger contact margin), while a second portion (e.g., a lower portion) may be provided for facilitating a deeper, narrower substrate contact configured to contact the substrate 202.

[0046] Figure 2D Depicted is a stage in which respective contact apertures or openings are formed in the source region 205A and the drain region 205B for facilitating the formation of the shallow wide portion of the stepped trench in the source region. As shown, a first contact aperture 218A is formed in the source region 205A and a second contact aperture 218B is formed in the drain region 205D, similar to Figure 1D . Although the two contact apertures 218A and 218B can be formed in a single contact lithography and etching process, this is not a requirement for the purposes of some examples of the present disclosure. In some examples, the first contact aperture 218A can extend at least partially into the buffer layer 204, for example to further facilitate electrical connection to the 2DEG 208.

[0047] Figure 2E The stage of forming a trench 220 in the source region 205A is depicted, the trench being narrower than the first contact opening 218A and extending to a suitable depth in the semiconductor substrate 202. In some examples, for Figure 2D The etching process for forming the first contact opening 218A in the stage shown in FIG. 2 may remove the barrier layer 210, thereby exposing the buffer layer 204 of the heterojunction structure 206, but this is not a necessary requirement. Regardless of whether the barrier layer 210 is completely removed when forming the first contact opening 218A, the ledge 227 is formed close to the 2DEG 208. In addition, similar to Figure 1E, the stepped profile groove 220 may have an overall depth 225 from the top surface of the barrier layer 210 to the bottom 221 of the groove 220, wherein the depth 225 of the groove 220 may be greater than the width 223 by a factor of at least three. Figure 2E A single-step trench 220 is shown in FIG. 2 , but additional and / or alternative arrangements may include forming a multi-step trench (eg, a trench having multiple ledges) in the source region 205A using appropriate masking / etching processes.

[0048] Figure 2F Describes something like Figure 1F 205B, where a DTS contact or electrode 222A and a drain contact or electrode 222B are formed in the source region 205A and the drain region 205B, respectively. Due to the flange 227 adjacent to the 2DEG 208, the top surface of the DTS contact 222A may have a different surface shape than the top surface of the drain contact 222B, but this is not a necessary requirement. In addition, in some examples, where multiple flanges are formed in the trench profile, one or more flanges may be disposed adjacent to the 2DEG 208. Similar to the DTS contact 122A, the DTS contact 222A includes a first contact 224A configured to contact the 2DEG 208 and a second contact 224B configured to contact the semiconductor substrate 202.

[0049] Figure 2G Describes something like Figure 1G , wherein a suitable dielectric layer 230 is formed over the DTS contact 222A, the drain contact 222B and the gate stack 212. Thereafter, a gate contact etch phase and a gate metallization phase may be similar to Figure 1H and 1I The stage depicted in FIG. 1 is followed by the formation of a gate contact or electrode. Figure 2H , a cross-sectional view of a more fully formed semiconductor device 200 including a GaN device 201 is shown, the more fully formed semiconductor device being similar to Figure 1J , in particular, except that the first contact 224A to the 2DEG 208 has a wider profile than the second contact 224B to the semiconductor substrate 202. Figure 1J , the GaN device 201 may have a source terminal 244A, a drain terminal 244B, and a gate terminal (not shown) formed through the ILD / PMD layer 240 to facilitate electrical contact with the DTS electrode 222A, the drain electrode 222B, and the gate electrode 222C, respectively.

[0050] Figures 3A-3JDepicted are cross-sectional views of a semiconductor device 300 including a GaN device 301 at various stages of a “gate-first” process flow for integrating a DTS contact according to an example of the present disclosure. Figures 2A-2H As shown in the stage Figures 3A-3J The stages shown in Figures 1A-1K The corresponding stages shown in are substantially similar or identical. Figures 1A-1K and / or Figures 2A-2H The description set out here also applies in relevant part to Figures 3A-3J The various corresponding structures and features shown in the cross-sectional view will not be repeated in detail here except for what will be mentioned below.

[0051] Similar to Figures 1A-1C and / or Figures 2A-2C , the intermediate level of the semiconductor device 300 includes a semiconductor substrate 302, wherein a source region 305A, a gate region 305B, a drain region 305D, and a drain access region 305C between the gate region 305B and the drain region 305D may be disposed relative to the GaN device 301. A gate stack 312 including a p-GaN layer 314 is formed over a heterojunction structure 306 disposed over the substrate 302. As previously described, the heterojunction structure 306 includes a barrier layer 310 over a buffer layer 304, the barrier layer supporting a 2DEG 308 in the buffer layer 304 proximate to an interface between the barrier layer 310 and the buffer layer 304. Figure 3C In the stage shown in , a dielectric layer 316 is formed over the barrier layer 310 and the gate stack 312 .

[0052] Prior to forming the DTS and drain contact structures described above, an example “gate first” flow includes first forming a gate electrode in the gate region 305B, which is facilitated by forming a gate contact aperture 332 in the gate stack 312, as shown in FIG. Figure 3D In this version of the example, you can execute something like Figure 1H , a gate contact photolithography and etching process is performed at the stage shown in FIG. 3 to form an opening 332 that exposes the p-GaN layer 314 of the gate stack 312 . Figure 3E A stage is depicted at which a suitable conductive layer 399 is formed over the device region. In this example version, conductive layer 399 may comprise a metal layer formed by sputtering.

[0053] Figure 3F Depicted is a stage where the gate electrode 322C is patterned from the gate metal layer 399 based on suitable gate lithography techniques and etching processes. Figure 3GDepicted is a stage where a dielectric layer 330 is first deposited over the device region and thereafter a drain contact opening 318 is formed in the drain region 305D, similar to the dielectric deposition and drain contact etch process stages described above. In this exemplary version, the dielectric layer 330 is operable to mask the gate electrode 322C during subsequent process stages of DTS and drain contact formation.

[0054] Figure 3H and 3I The trench formation stage and the DTS and drain contact formation stages are depicted separately. Figure 1E 1, a trench 320 having a suitable size and form factor is formed in the source region 305A, the trench extending to a suitable depth in the semiconductor substrate 302, such as Figure 3H In some additional and / or alternative arrangements, a shallow wider etch may be performed followed by a deep trench process to form a stepped trench in the source region 305A, similar to Figure 2D and 2E In addition, the trench 320 may have a depth 325 greater than the width 323 by at least three times, as previously described, wherein the bottom 321 of the trench 320 extends into the semiconductor substrate 302. Fig. 3I , a DTS contact or electrode 322A and a drain contact or electrode 322B are formed in trench 320 and drain contact opening 318, respectively, similar to Figure 1F As previously described, the DTS contact 322A includes a first contact 324A configured to contact the 2DEG 308 and a second contact 324B configured to contact the semiconductor substrate 302 .

[0055] exist Figure 3J , a cross-sectional view of a more fully formed semiconductor device 300 including a GaN device 301 is shown, the more fully formed semiconductor device being similar to Figure 1J The semiconductor device 100 shown in FIG. Figure 1J , the GaN device 301 may have a source terminal 344A, a drain terminal 344B, and a gate terminal (not shown) formed through the ILD / PMD layer 340 to facilitate electrical contact with the DTS electrode 322A, the drain electrode 322B, and the gate electrode 322C, respectively.

[0056] Figures 4A-4I Depicted are cross-sectional views of a semiconductor device 400 including a GaN device 401 at various stages of another example "gate-first" process flow for integrating a DTS contact according to the present disclosure. Figures 3A-3JCompared to the stage described in , in which the p-GaN layer 314 is patterned independently of and before forming the gate electrode (eg, in a non-self-aligned gate formation scheme), Figures 4A-4I The example process described in shows a self-aligned gate formation scheme in which a p-GaN layer can be patterned and etched together with a gate metal layer. In addition to the aforementioned changes, Figures 4A-4I The stages are roughly similar to those described above. Figures 3A-3J The corresponding stages shown in , which are similar to those previously described Figures 1A-1K Therefore, the above is relative to Figures 1A-1K and / or Figures 3A-3J The description set out here also applies in relevant part to Figures 4A-4I The various corresponding structures and features shown in the cross-sectional view will not be repeated in detail here except for what will be mentioned below.

[0057] Similar to Figure 1A , 2A and the stages shown in 3A, Figure 4A 4 includes a semiconductor substrate 402 in which a source region 405A, a gate region 405B, a drain region 405D, and a drain access region 405C between the gate region 405B and the drain region 405D may be disposed relative to a GaN device 401. Similar to the examples described above, a heterojunction structure 406 includes a barrier layer 410 over a buffer layer 404 that supports a 2DEG 408 in the barrier layer 410 proximate to an interface between the barrier layer 410 and the buffer layer 404. A p-GaN layer 414 is formed over the heterojunction structure 306, which is disposed over the semiconductor substrate 402.

[0058] Figure 4B Depicts a stage in which a gate metal layer 499 is formed (eg, sputtered) over the p-GaN layer 414, similar to Figure 3E Thereafter, the gate metal layer 499 may be etched to form a gate electrode 422C in the gate region 405B, as shown in FIG. Figure 4C In this example version, the same mask used to pattern the gate metal layer 499 can be used to etch the p-GaN layer 414 to form the gate, thereby forming a gate stack 412 in the gate region 405B above the barrier layer 410. In some arrangements, sidewall spacers (not shown) may be provided on each side of the gate electrode 422C before etching the p-GaN layer 414. Figure 4D In the example arrangement shown in , where the sidewall spacers have been removed, the p-GaN gate 414 may be patterned to be wider than the gate electrode 422C.

[0059] Figure 4E A dielectric deposition phase is depicted in which a dielectric layer 416 of suitable thickness and composition is formed over the device region. Figure 4F Depicted is a stage in which a contact aperture or opening 418 is formed in the drain region 405D, similar to Figure 1D The stages described in .

[0060] Figure 4G and 4H The trench formation stage and the DTS and drain contact formation stages are depicted separately. Figure 1E 1, a trench 420 having a suitable size and form factor is formed in the source region 405A, the trench extending to a suitable depth in the semiconductor substrate 402, such as Figure 4G In addition, the trench 420 may have a depth 425 greater than the width 423 by at least three times, as previously described, wherein the bottom 421 of the trench 420 extends into the semiconductor substrate 402. Figure 4H , DTS contacts or electrodes 422A and drain contacts or electrodes 422B are formed in trench 420 and drain contact opening 418, respectively, similar to Figure 1F In this exemplary version, the DTS contact 422A thus includes a first contact 424A configured to contact the 2DEG 408 and a second contact 424B configured to contact the semiconductor substrate 402 .

[0061] exist Fig. 4I , a cross-sectional view of a more fully formed semiconductor device 400 including a GaN device 401 is shown, the more fully formed semiconductor device being similar to Figure 1J The semiconductor device 100 shown in FIG. Figure 1J , the GaN device 401 may have a source terminal 444A, a drain terminal 444B, and a gate terminal (not shown) formed through the ILD / PMD layer 440 to facilitate electrical contact with the DTS electrode 422A, the drain electrode 422B, and the gate electrode 422C, respectively.

[0062] Figure 5A layout of a semiconductor device 500 according to some examples of the present disclosure is depicted, wherein a GaN unit cell 501 includes a region 502 (e.g., an active region, a device region, etc.) including a single DTS contact structure. The region 502 may be defined by an isolation boundary 503 formed by any suitable isolation process. The region 502 includes a source region 505A, a gate region 505B, a drain region 505D, and a drain access region 505C disposed between the gate region 505B and the drain region 505D. A single DTS contact 504A having a rectangular shape is disposed in the source region 505A, wherein the DTS contact 504A extends into the substrate below the active region 502 (e.g., along a Z axis orthogonal to the XY layout plane). A drain contact 504B and a gate contact 504C are disposed in the drain region 505B and the gate region 505B, respectively.

[0063] Figure 6 A layout of a semiconductor device 600 according to some examples of the present disclosure is depicted, wherein a GaN unit cell 601 includes a region 602 including multiple DTS contact structures in a hybrid source architecture. For purposes herein, in some examples, a hybrid source architecture may refer to a unit cell having at least one DTS contact in addition to a source contact that is not tied to a substrate (e.g., a non-DTS source contact including an independent source contact extending to a buffer layer (e.g., buffer layer 104, 204, 304, 404) above the substrate of the device). In some additional and / or alternative examples, a hybrid source architecture may refer to a semiconductor device including a plurality of unit cells, wherein at least one unit cell may include an independent source contact (e.g., a non-DTS source contact) in any combination with one or more DTS contacts on a per-cell basis, as will be described below.

[0064] Continue to refer Figure 6 , the region 602 of the GaN unit cell 601 may be surrounded by an isolation boundary 603, which may be similar to Figure 5 605A. The region 602 includes a source region 605A, a gate region 605B, a drain region 605D, and a drain access region 605C disposed between the gate region 605B and the drain region 605D. By way of illustration, two DTS contacts 604A-1, 604A-2 having a square shape are disposed in the source region 605A, wherein the DTS contacts 604A-1, 604A-2 each extend into the substrate below the region 602 by means of a corresponding trench. The drain contact 604B and the gate contact 604C are disposed in the drain region 605B and the gate region 605B, respectively. In addition to the DTS contacts 604A-1, 604A-2, the source region 605A also includes an independent source contact 626 (e.g., a non-DTS source contact).

[0065] Fig. 7A and 7B The layout of a semiconductor device including a plurality of unit cells according to some examples of the present disclosure is depicted. Fig. 7A , an example semiconductor device 700A includes two GaN unit cells 701A, 701B, each of which includes a respective region 702A, 702B separated by an isolation boundary 703A, 703B, similar to the GaN unit cells 501 and 601 described above. A single DTS contact 704A, 706A is disposed in a respective source region of the GaN unit cells 701A, 701B, the single DTS contact extending into the semiconductor substrate, similar to the DTS contact 504A of the GaN unit cell 501 described above. Likewise, drain contacts 704B, 706B are disposed in respective drain regions of the GaN unit cells 701A, 701B, the drain contacts being typically coupled via a shared gate contact structure 708.

[0066] Figure 7B A semiconductor device 700B including a plurality of unit cells based on a hybrid source architecture is depicted, wherein one of the unit cells may include an independent source contact that is not tied to the substrate. As shown, the semiconductor device 700B includes two GaN unit cells 751A, 751B, each of which includes a respective region 752A, 752B separated by an isolation boundary 753A, 753B, similar to Fig. 7A A single DTS contact 754A and a single independent source contact 758 are provided in the respective source regions of the GaN unit cells 751A, 751B. In addition, drain contacts 754B, 756B are provided in the respective drain regions of the GaN unit cells 751A, 751B, and the drain contacts are typically coupled via a shared gate contact structure 758, similar to Fig. 7A The semiconductor device 700A shown in FIG.

[0067] Figures 8A-8D is a flow chart of a method of fabricating a semiconductor device including a GaN device with a deep trench source according to some examples of the present disclosure, wherein different steps, actions, functions and / or blocks may be combined or otherwise rearranged in various combinations. Fig. 8A The method 800A shown in FIG. 8 may begin by forming a heterojunction structure over a semiconductor substrate that includes a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region (block 802). Figure 1A-4AAs described in the process stages shown in FIG. 8 , the heterojunction structure includes a buffer layer over a semiconductor substrate and a barrier layer over the buffer layer. At block 804, a gate stack including a p-doped III-N layer may be formed in a gate region over the barrier layer. At block 806, a source contact (e.g., a DTS contact or a substrate-connected contact) is formed in a source region, the source contact extending into the semiconductor substrate and including a first contact to a 2DEG in the heterojunction structure and a second contact to the semiconductor substrate, as previously described with respect to FIG. Figure 1E-1F ; 2E-2F; 3H-3I and 4G-4H illustrate the process stages shown.

[0068] In some arrangements, a contact opening may be formed in the drain region of the semiconductor substrate prior to forming the gate electrode, as set forth in block 820 of method 800B, which involves Figure 1D and 2D After forming the contact opening in the drain region, a trench may be formed in the source region, wherein the trench extends into the semiconductor substrate, as described at block 822, which involves Figure 1E and 2E Thereafter, the trenches and drain contact openings may be filled with metal to form source contacts (e.g., DTS contacts) in the source region and drain contacts in the drain region, as described at block 824, which involves Figure 1F and 2F Some aspects of the process stages shown in .

[0069] In some arrangements, before forming the gate electrode, a first contact opening and a second contact opening may be formed in the source region and the drain region, respectively, as set forth at block 830 of method 800C, which involves Figure 2D At block 832, a trench narrower than the first contact opening may be formed in the source region, wherein the trench extends from the contact opening of the source region and into the semiconductor substrate, which involves Figure 2E . As previously described, the upper portion of the trench may include or form a ledge leading to a first contact aperture, wherein the ledge is adjacent to a 2DEG of a heterojunction structure formed above the semiconductor substrate. At block 834, the first contact aperture and the trench may be filled with metal to form a first contact and a second contact of a source contact (e.g., a DTS contact). At block 836, the second contact aperture may be filled with metal to form a drain contact. In some examples, the foregoing blocks 834 and 836 may involve Figure 2F Some aspects of the process stages shown in .

[0070] In some arrangements, a gate electrode may be formed over the heterojunction structure prior to fabricating the source and drain contacts, wherein the gate electrode may be patterned using a self-aligned process or a non-self-aligned process, as set forth at block 840 of method 800D. In this example version, the actions set forth at block 840 may involve Figure 3D-3F and Figures 4B-4D , where sidewall spacers may be used in the self-aligned process described previously. At block 842, a contact opening may be formed in the drain region. Thereafter, a trench extending into the semiconductor substrate may be formed in the source region (block 844). Subsequently, the trench and contact opening may be filled with metal to form a source contact (e.g., a DTS contact) and a drain contact in the source and drain regions, respectively, as described at block 846. In some examples, the actions described at blocks 842-844 may involve the steps described above. Figure 3G-3I and Figure 4F-4H The process stages shown in .

[0071] Although various examples of the present disclosure have been described above, the examples have been presented by way of example only and not limitation. For example, although in the foregoing examples a DTS contact is shown in an EMODE GaN transistor, such a DTS contact may be included in a DMODE GaN transistor (e.g., a DMODE GaN transistor that does not have a p-GaN layer in its gate stack). In addition, in additional and / or alternative examples, a self-aligned gate formation process (e.g., similar to the above referenced example) may be used to form a gate electrode. Figures 4A-4I The described arrangement) can be combined with the gate-last process described above (for example, in Figures 1A-1J and Figures 2A-2H The invention is implemented in an arrangement of (e.g., DTS contacts) such as forming source contacts (e.g., DTS contacts) and drain contacts in the source and drain regions through the p-GaN layer, respectively, and then removing the p-GaN layer during a self-aligned gate formation process using a gate metal mask that patterns the gate metal layer and the p-GaN layer. Numerous changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of the present disclosure. Therefore, the breadth and scope of the present disclosure should not be limited by any of the examples described above. Indeed, the scope of the present disclosure should be defined in accordance with the appended claims and their equivalents.

[0072] For example, in the present disclosure and the following claims, unless otherwise stated and / or specified to the contrary, any one or more of the layers described herein may be formed in any number of suitable ways, such as using spin coating techniques, sputtering techniques (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD), etc. As another example, the silicon nitride may be silicon-rich silicon nitride or oxygen-rich silicon nitride. The silicon nitride may contain some oxygen, but not so much that the dielectric constant of the material is significantly different from that of high-purity silicon nitride.

[0073] In addition, in at least some additional or alternative embodiments, the function / action described in the frame may not occur in the order shown in the flow chart. For example, depending on the functionality / action involved, the two frames of continuous display can actually be substantially performed simultaneously or the frames can sometimes be performed in reverse order. In addition, the functionality of a given frame of a flow chart and / or block diagram can be divided into a plurality of frames, and / or the functionality of two or more frames of a flow chart and / or block diagram can be at least partially integrated. In addition, some frames in the flow chart can be optionally omitted. In addition, although some diagrams include arrows on the communication path to show the main direction of communication, it should be understood that communication can occur in the direction opposite to the arrows depicted. Finally, other frames can be added / inserted between the frames shown.

[0074] The order or sequence of actions, steps, functions, components or boxes shown in any of the flowcharts and / or block diagrams depicted in the drawings of the present disclosure may be modified, altered, replaced, customized or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of a particular action, step, function, component or box. In addition, the actions, steps, functions, components or boxes shown in a particular flowchart may be intermixed or otherwise arranged or rearranged with the actions, steps, functions, components or boxes shown in another flowchart to achieve additional changes, modifications and configurations relative to one or more processes for the purpose of practicing the teachings of the present disclosure. Similarly, although various examples have been set forth herein, not all features of a particular example are necessarily limited thereto and / or are therefore required.

[0075] At least some portions of the foregoing descriptions may include specific directional terms, such as "upper," "lower," "top," "bottom," "left," "right," "front," "back," "vertical," "horizontal," and the like, which may be used with reference to the orientation of some of the figures described or their illustrative elements. Since the components of some examples may be positioned in several different orientations, the directional terms are used for illustrative purposes and are by no means restrictive. Similarly, references to features referred to as "first," "second," and the like do not indicate any particular order, importance, and the like, and such references may be interchangeable, depending on context, implementation, and the like. In addition, terms such as "above," "below," "below," and the like, relative to the spatial orientation of two components, do not necessarily mean that one component is immediately adjacent to or directly above another component, or that one component is immediately adjacent to or directly below or below another component. In addition, unless specifically noted otherwise, the features and / or components of the examples described herein may be combined with one another.

[0076] Although various embodiments have been shown and described in detail, the claims are not limited to any specific embodiment or example. The above specific embodiments should not be considered to imply that any specific component, element, step, action, or function is basic so that it must be included in the scope of the claims. In the case of narrating or describing phrases such as "at least one of A and B" or phrases of similar meaning, such phrases should be understood to mean "only A, only B, or both A and B". Unless explicitly stated, references to singular elements are not intended to mean "one and only one", but "one or more". In a similar manner, depending on the context, phrases such as "a plurality" or "multiple" may mean "one or more" or "at least one". All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference, and are intended to be covered by the following claims.

Claims

1. A semiconductor device comprising: A semiconductor substrate comprising a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; a heterojunction structure over the semiconductor substrate, the heterojunction structure comprising a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer; a gate stack located in the gate region over the barrier layer; as well as A source contact extends into the semiconductor substrate in the source region and includes a first contact to a 2DEG in the heterojunction structure and a second contact to the semiconductor substrate.

2. The semiconductor device of claim 1, wherein the source contact is disposed in a trench, the trench having an aspect ratio wherein the depth of the trench is greater than the width by a factor of at least three. 3 . The semiconductor device of claim 1 , wherein the source contact is a first source contact, and wherein the source region further comprises a second source contact extending into the buffer layer. 4 . The semiconductor device according to claim 1 , wherein the first contact of the source contact comprises a first metal, and the second contact of the source contact comprises a second metal different from the first metal. 5 . The semiconductor device of claim 1 , wherein the first contact of the source contact includes a first portion connected to the 2DEG, and the second contact of the source contact includes a second portion narrower than the first portion, the second portion connected to the semiconductor substrate. 6 . The semiconductor device of claim 1 , wherein the gate stack comprises a p-doped III-N layer over the barrier layer. 7 . The semiconductor device of claim 6 , further comprising a gate electrode aligned with the p-doped III-N layer of the gate stack.

8. A method comprising: Forming a heterojunction structure on a semiconductor substrate, the semiconductor substrate comprising a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region, the heterojunction structure comprising a buffer layer on the semiconductor substrate and a barrier layer on the buffer layer; forming a gate stack in the gate region over the barrier layer; as well as A source contact is formed in the source region, the source contact extending into the semiconductor substrate and including a first contact to a 2DEG in the heterojunction structure and a second contact to the semiconductor substrate. 9 . The method of claim 8 , wherein the source contact is formed before forming a gate electrode coupled to the gate stack.

10. The method according to claim 9, further comprising: forming a contact aperture in the drain region; After forming the contact opening in the drain region, forming a trench in the source region, the trench extending into the semiconductor substrate; as well as The source contact is formed in the trench and a drain contact is formed in the contact opening.

11. The method of claim 9, further comprising forming a first contact opening in the source region and forming a second contact opening in the drain region. 12 . The method of claim 11 , further comprising forming a trench in the source region that is narrower than the first contact opening, the trench extending into the semiconductor substrate.

13. The method of claim 12, further comprising filling the first contact opening and the trench with metal to form the first and second contacts of the source contact.

14. The method of claim 11, further comprising filling the second contact opening in the drain region with metal to form a drain contact.

15. The method of claim 8, wherein the source contact is formed after forming a gate electrode coupled to the gate stack. 16 . The method of claim 15 , wherein the gate stack comprises a p-doped III-N layer, and wherein the gate electrode is patterned during patterning of the p-doped III-N layer.

17. The method according to claim 15, further comprising: forming a contact aperture in the drain region; After forming the contact opening in the drain region, forming a trench in the source region, the trench extending into the semiconductor substrate; as well as The source contact is formed in the trench and a drain contact is formed in the contact opening.

18. A semiconductor device comprising: a first III-N unit cell formed over a first region of a semiconductor substrate, the first III-N unit cell comprising a first source contact in a source region of the first region, wherein the first source contact is connected to the semiconductor substrate via a trench extending into the semiconductor substrate; as well as A second III-N unit cell is formed over a second region of the semiconductor substrate, the second III-N unit cell comprising a second source contact in a source region of the second region, wherein the first III-N unit cell and the second III-N unit cell are coupled together via a common gate. 19 . The semiconductor device of claim 18 , wherein the second source contact is connected to the semiconductor substrate through another trench extending into the semiconductor substrate.

20. The semiconductor device of claim 18, wherein the second source contact extends to a III-N buffer layer over the semiconductor substrate.

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