Semiconductor Device and Preparation Method

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof, belonging to the field of semiconductor technology. In this semiconductor device, since the width of the first sidewall becomes smaller and the width of the second sidewall becomes larger in the first direction, it is possible to make the first doping region in the substrate near the first sidewall larger in width compared to the existing one while keeping the conductive channel length of the semiconductor device unchanged. At this time, even if there is an overlap between the third doping region and the second doping region, it will not affect the doping concentration of the first doping region and will not cause a reduction in the on-resistance, resulting in better breakdown voltage performance of the device. In addition, simultaneously setting the third doping region and the first doping region in the substrate in the first opening region can also save the area of the device and improve the working efficiency of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in semiconductor devices is widely used due to its high input impedance, low power consumption and fast response capability.

[0003] Existing MOSFETs include SWITCH MOS and LDMOS. In the actual process of preparing the source and drain of SWITCH MOS and LDMOS, the photoresist is prone to standing waves or side-eating, which causes the different doping regions to overlap after the photoresist is developed, thereby affecting the doping concentration of the source and drain regions, and directly affecting the performance of the device. Although certain improvements can be made through the photolithography process, the process tolerance is still insufficient when the device is actually mass-produced, which will still cause the on-resistance of the device to be too low, causing the device to leak current or turn on too quickly, reducing the device's voltage resistance, etc.

[0004] Based on this, how to increase the on-resistance of the device while ensuring that the conductive channel of the existing semiconductor device remains unchanged has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] Based on this, it is necessary to provide a semiconductor device and a preparation method to address the problem that the on-resistance of the device is too low due to the overlap of doped regions, which affects the withstand voltage performance of the semiconductor device.

[0006] In order to achieve the above object, on the one hand, the present invention provides a semiconductor device, the semiconductor device comprising:

[0007] substrate;

[0008] At least two gate structures, at least two of the gate structures are located on one side of the substrate and are sequentially spaced apart along a first direction, an opening area is provided between the gate structures, the opening area includes a first opening area and a second opening area, the first opening area and the second opening area are alternately arranged in the first direction, and the first direction is parallel to the plane where the substrate is located;

[0009] A first sidewall spacer and a second sidewall spacer are respectively located on both sides of the gate structure, and the first sidewall spacer is located in the first opening area, and the second sidewall spacer is located in the second opening area; in the first direction, a width of a positive projection of the first sidewall spacer on the substrate is smaller than a width of a positive projection of the second sidewall spacer on the substrate;

[0010] Furthermore, the substrate includes a first doped region, a second doped region and a third doped region, the first doped region and the second doped region have a first conductivity type, and the third doped region has a second conductivity type; the first doped region is located in the first opening region, and is located on a side of the first side wall away from the gate structure; the second doped region is located in the second opening region, and is located on a side of the second side wall away from the gate structure; the third doped region is located in the first opening region, and is located between the two first doped regions in the first opening region.

[0011] In one embodiment, the first spacer includes a first spacer layer, and the second spacer includes a first spacer layer and a second spacer layer.

[0012] In one embodiment, the first spacer layer includes a first sub-layer and a second sub-layer;

[0013] In the first sidewall, the first sublayer and the second sublayer are stacked;

[0014] In the second spacer, the second spacer layer is located between the first sub-layer and the second sub-layer.

[0015] In one embodiment, the first spacer and the second spacer both include a third spacer layer, and the third spacer layer is located between the first sub-layer and the gate structure.

[0016] In one embodiment, the semiconductor device further includes:

[0017] a shielding layer, wherein the shielding layer covers the second sidewall, a portion of the surface of the gate structure close to the second sidewall, and a portion of the surface of the second doping region close to the second sidewall;

[0018] A metal silicide layer, located on the surface of the gate structure exposed by the shielding layer, the surface of the second doping region exposed by the shielding layer, the surface of the first doping region, and the surface of the third doping region;

[0019] A plurality of contact structures, wherein the plurality of contact structures are respectively in contact with the metal silicide layer on the surface of the gate structure exposed by the shielding layer, the metal silicide layer on the surface of the first doping region, the metal silicide layer on the surface of the second doping region, and the metal silicide layer on the surface of the third doping region.

[0020] In one embodiment, the semiconductor device further includes:

[0021] A metal silicide layer, located on a surface of the gate structure, a surface of the first doping region, a surface of the second doping region, and a surface of the third doping region;

[0022] A plurality of contact structures, wherein the plurality of contact structures are respectively in contact with the metal silicide layer located on the surface of the gate structure, the metal silicide layer on the surface of the first doping region, the metal silicide layer on the surface of the second doping region, and the metal silicide layer on the surface of the third doping region.

[0023] On the other hand, the present invention also provides a method for preparing a semiconductor device, the method comprising:

[0024] providing a substrate;

[0025] At least two gate structures are formed on one side of the substrate and are arranged in sequence and spaced apart from each other; an opening area is provided between the gate structures, the opening area includes a first opening area and a second opening area, the first opening area and the second opening area are alternately arranged in the first direction, and the first direction is parallel to the plane where the substrate is located;

[0026] A first sidewall spacer and a second sidewall spacer are formed on both sides of the gate structure, respectively, the first sidewall spacer is located in the first opening area, and the second sidewall spacer is located in the second opening area; in the first direction, the width of the first sidewall spacer projection on the substrate is smaller than the width of the second sidewall spacer projection on the substrate;

[0027] In the first opening region, a region of the substrate on a side of the first sidewall away from the gate structure is doped with a first type, and in the second opening region, a region of the substrate on a side of the second sidewall away from the gate structure is doped with a first type to form a first doping region and a second doping region, wherein the first doping region is located in the first opening region and the second doping region is located in the second opening region; the first doping region and the second doping region have a first conductivity type;

[0028] In the first opening region, the substrate between the two first doping regions is doped with a second type of conductive material to form a third doping region; the third doping region has a second conductivity type.

[0029] In one embodiment, the first sidewall spacer and the second sidewall spacer are respectively formed on both sides of the gate structure, the first sidewall spacer is located in the first opening area, and the second sidewall spacer is located in the second opening area, including:

[0030] sequentially forming a first material layer and a second material layer covering the substrate and the gate structure;

[0031] Partially etching the second material layer to form a spacer intermediate layer on both sides of the gate structure;

[0032] Using a photolithography process to remove the sidewall intermediate layer in the first opening area;

[0033] forming a third material layer covering the spacer intermediate layer and the first material layer in the second opening area;

[0034] The third material layer and the first material layer are partially etched to form the first sidewall spacer on one side of the gate structure and the second sidewall spacer on one side of the gate structure, wherein the first sidewall spacer is located in the first opening area and the second sidewall spacer is located in the second opening area.

[0035] In one embodiment, in the first opening region, a region of the substrate on a side of the first sidewall away from the gate structure is doped with a first type, and in the second opening region, a region of the substrate on a side of the second sidewall away from the gate structure is doped with a first type to form a first doping region and a second doping region, wherein the first doping region is located in the first opening region and the second doping region is located in the second opening region, comprising:

[0036] Forming a first photoresist in a middle area of ​​the first sidewall in the first opening area away from the gate structure;

[0037] The first photoresist, the gate structure, the first sidewall and the second sidewall are used as an injection barrier layer, and in the first opening region, a region of the substrate on a side of the first sidewall away from the gate structure is doped with a first type, and in the second opening region, a region of the substrate on a side of the second sidewall away from the gate structure is doped with a first type, so as to form a first doping region and a second doping region, wherein the first doping region is located in the first opening region and the second doping region is located in the second opening region;

[0038] The first photoresist is removed.

[0039] In one embodiment, in the first opening region, performing second-type doping on the substrate between two first doping regions to form a third doping region includes:

[0040] Forming a second photoresist in other regions except a middle region of the first sidewall 04 away from the gate structure 02;

[0041] Using the second photoresist as an injection barrier layer, in the first opening region, performing second-type doping on the substrate between the two first doping regions to form a third doping region;

[0042] The second photoresist is removed.

[0043] Compared with the prior art, the above technical solution has the following unexpected technical effects:

[0044] In the semiconductor device, the substrate includes at least two gate structures arranged in sequence and spaced in a first direction, and there is an opening area between the gate structures, the opening area includes a first opening area and a second opening area, and the first opening area and the second opening area are alternately arranged, and the first direction is parallel to the plane where the substrate is located. The substrate includes a first doping area, a second doping area and a third doping area, wherein the first doping area is located in the first opening area and is located on the side of the first sidewall away from the gate structure, the second doping area is located in the second opening area and is located on the side of the second sidewall away from the gate structure, the third doping area is located in the first opening area and is located between the two first doping areas in the first opening area, the first doping area and the second doping area have a first conductivity type, and the third doping area has a second conductivity type. A first sidewall and a second sidewall are respectively arranged on both sides of the gate structure, wherein the first sidewall is in the first opening area, and the second sidewall is in the second opening area, and in the first direction, the width of the positive projection of the first sidewall on the substrate is smaller than the width of the positive projection of the second sidewall on the substrate.

[0045] Since the width of the first sidewall in the first direction is reduced and the width of the second sidewall is increased, the first doped region in the substrate close to the first sidewall can be increased relative to the existing width when the conductive channel length of the semiconductor device remains unchanged. At this time, even if the third doped region overlaps with the second doped region, it will not affect the doping concentration of the first doped region, and will not cause a decrease in the on-resistance, so that the device has better withstand voltage performance. In addition, setting the third doped region and the first doped region in the substrate in the first opening region at the same time can also save the area of ​​the device and improve the working efficiency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 It is a schematic diagram of a part of the structure of an existing LDMOS device;

[0048] Figure 2It is a partial structural schematic diagram of an existing SWITCH MOS device;

[0049] Figure 3 A schematic diagram of a partial structure of a semiconductor device provided in an embodiment of the present application;

[0050] Figure 4 A partial structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0051] Figure 5 A partial structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0052] Figure 6 A partial structural schematic diagram of an LDMOS device provided in an embodiment of the present application;

[0053] Figure 7 A partial structural diagram of a SWITCH MOS device provided in an embodiment of the present application;

[0054] Figure 8 A schematic diagram of a semiconductor device manufacturing process provided in an embodiment of the present application;

[0055] Figure 9-Figure 14 A schematic diagram of a portion of a structure obtained in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0056] Fig.15 A schematic diagram of another part of the structure obtained in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0057] Fig.16 A schematic diagram of another part of a structure obtained in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0058] Fig.17 A schematic structural diagram of a structure obtained in a method for preparing an LDMOS device provided in an embodiment of the present application;

[0059] Fig.18 A schematic structural diagram of a structure obtained in a method for preparing a SWITCH MOS device provided in an embodiment of the present application.

[0060] Explanation of the reference numerals: 01-substrate; 02-gate structure; 03-opening area; 03a-first opening area; 03b-second opening area; 04-first side wall; 05-second side wall; 06-first doped area; 07-second doped area; 08-third doped area; 10-shielding layer; 11-metal silicide layer; 12-contact structure; 13-first material layer; 14-second material layer; 15-fourth material layer; 16-side wall intermediate layer; 17-first photoresist; 18-third material layer; 19-first photoresist; 20-second photoresist; 21-etching stop layer; 22-interlayer dielectric layer; x-first side wall layer; y-second side wall layer; v-first sublayer; u-second sublayer; z-third side wall layer. DETAILED DESCRIPTION

[0061] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0063] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0064] Based on the content in the background technology, in the actual process of SWITCH MOS devices and LDMOS devices, due to the influence of the underlying polysilicon pattern, the layout between the source region or drain region and the body region may be staggered. In this case, the photoresist is very likely to have problems such as standing waves or side eating, and the doped regions will overlap during development.

[0065] For example, refer to Figure 1 , Figure 1It is a partial structural schematic diagram of an existing LDMOS device; a first P-type body region 011a is provided in a first substrate 011, and the first P-type body region 011a has an n+ doping region 011b and a p+ doping region 011c. A conductive gate 011e located on a self-aligned shielding layer 011d is also provided in the LDMOS device, and the conductive gate 011e is prepared by depositing SA-poly, so that the LDMOS device has better voltage resistance. Wherein, a is the width of the left side wall of the gate, b is the width of the right side wall of the gate, and a is equal to b; c is the width of the conductive channel; d is the width of the n+ doping region 011b; and e is the width of the p+ doping region 011c. When n+ doping and p+ doping are performed in the first P-type body region 011a, it is very easy for the n+ doping region 011b to overlap with the p+ doping region 011c during photoresist development, that is, the p+ doping diffuses, resulting in a situation where the n+ doping region 011b becomes smaller. Overlapping of doped regions may result in degradation of the performance of LDMOS devices.

[0066] refer to Figure 2 , Figure 2 It is a partial structural diagram of an existing SWITCH MOS device; a second P-type body region 012a is provided in the second substrate 012, and the second P-type body region 012a has an n+ doping region 012b and a p+ doping region 012c. Wherein, f is the width of the left side wall of the gate, g is the width of the right side wall of the gate, and f is equal to g; h is the width of the conductive channel; i is the width of the n+ doping region 012b; j is the width of the p+ doping region 012c. When n+ doping and p+ doping are performed in the second P-type body region 012a, it is very easy for the n+ doping region 012b to overlap with the p+ doping region 012c during photoresist development, that is, the p+ doping diffuses, resulting in the reduction of the n+ doping region 011b. The overlapping of doping regions will lead to the reduction of the performance of the SWITCH MOS device.

[0067] In this case, the photolithography process can be used, such as forming a top anti-reflective coating to reduce the light reflected inside the photoresist, thereby reducing the standing wave effect of the photoresist; or adjusting the energy and focus during the photolithography process to improve the photoresist development problem. However, the process tolerance is still insufficient in actual mass production, resulting in the on-resistance of the device being too low, causing leakage current in the device or causing the device to turn on too quickly, reducing the device's voltage resistance.

[0068] Based on this, the present invention provides a semiconductor device and a preparation method, wherein the semiconductor device includes at least two gate structures arranged in sequence in a first direction on the substrate, and there is an opening area between the gate structures, the opening area includes a first opening area and a second opening area, and the first opening area and the second opening area are alternately arranged, and the first direction is parallel to the plane where the substrate is located. The substrate includes a first doping area, a second doping area and a third doping area, wherein the first doping area is located in the first opening area and is located on the side of the first sidewall away from the gate structure, the second doping area is located in the second opening area and is located on the side of the second sidewall away from the gate structure, the third doping area is located in the first opening area and is located between the two first doping areas in the first opening area, the first doping area and the second doping area have a first conductivity type, and the third doping area has a second conductivity type. A first sidewall and a second sidewall are respectively arranged on both sides of the gate structure, wherein the first sidewall is in the first opening area, and the second sidewall is in the second opening area, and in the first direction, the width of the positive projection of the first sidewall on the substrate is smaller than the width of the positive projection of the second sidewall on the substrate.

[0069] Since the width of the first sidewall in the first direction is reduced and the width of the second sidewall is increased, the first doping region in the substrate close to the first sidewall can be increased relative to the existing width when the conductive channel length of the semiconductor device remains unchanged. When the third doping region is formed, even if the third doping region overlaps with the second doping region, it will not affect the doping concentration of the first doping region, and will not cause a decrease in the on-resistance, so that the device has better withstand voltage performance. In addition, setting the third doping region and the first type doping region in the substrate of the first opening region at the same time can also save the area of ​​the device and improve the working efficiency of the device.

[0070] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0071] refer to Figure 3 , Figure 3 A partial structural schematic diagram of a semiconductor device provided in an embodiment of the present application; the semiconductor device comprises:

[0072] Substrate 01.

[0073] At least two gate structures 02 are located on one side of the substrate 01 and are arranged in sequence along the first direction M. There is an opening area 03 between the gate structures 02. The opening area 03 includes a first opening area 03a and a second opening area 03b. The first opening area 03a and the second opening area 03b are alternately arranged in the first direction M. The first direction M is parallel to the plane where the substrate 01 is located.

[0074] The first side wall 04 and the second side wall 05 are respectively located on both sides of the gate structure 02, and the first side wall 04 is located in the first opening area 03a, and the second side wall 05 is located in the second opening area 03b; in the first direction M, the width of the orthographic projection of the first side wall 04 on the substrate 01 is smaller than the width of the orthographic projection of the second side wall 05 on the substrate 01.

[0075] Furthermore, the substrate 01 includes a first doping region 06, a second doping region 07 and a third doping region 08, the first doping region 06 and the second doping region 07 have a first conductivity type, and the third doping region 08 has a second conductivity type; the first doping region 06 is located in the first opening region 03a, and is located on a side of the first side wall 04 away from the gate structure 02; the second doping region 07 is located in the second opening region 03b, and is located on a side of the second side wall 05 away from the gate structure 02; the third doping region 08 is located in the first opening region 03a, and is located between the two first doping regions 06 in the first opening region 03a.

[0076] Specifically, the substrate 01 may be a silicon substrate, which is not specifically limited. A gate oxide layer 02a is also provided between the gate structure 02 and the substrate 01, and the material of the gate oxide layer 02a may be a silicon oxide material.

[0077] An opening region 03 is provided between the gate structures 02, and the opening region 03 includes a first opening region 03a and a second opening region 03b alternately arranged in a first direction M. The gate structure 02 is provided with a first sidewall 04 and a second sidewall 05, wherein the first sidewall 04 is located in the first opening region 03a, and the second sidewall 05 is located in the second opening region 03b. A first doping region 06 of a first conductivity type is provided in the substrate 01 on a side of the first sidewall 04 of the first opening region 03a away from the gate structure 02, and a third doping region 08 of a second conductivity type is also provided in the substrate 01 between the first doping regions 06.

[0078] In the substrate 01 on the side of the second sidewall 05 of the second opening region 03b away from the gate structure 02, a second doping region 07 of the first conductivity type is provided. It should be noted that the first conductivity type may be N-type or P-type, and the second conductivity type may be N-type or P-type, but the first conductivity type and the second conductivity type are different. In other words, the first doping region 06 may be heavily N-type doped or P-type doped, the second doping region 07 may be heavily N-type doped or P-type doped, and the third doping region 08 may be heavily N-type doped or P-type doped, but the doping type of the first doping region 06 and the second doping region 07 may be the same, and the doping type of the third doping region 08 is different from that of the first doping region 06.

[0079] In the first direction M, the width of the orthographic projection of the first sidewall 04 on the substrate 01 is B, the width of the orthographic projection of the second sidewall 05 on the substrate 01 is A, the length of the conductive channel is C, the width of the first doping region 06 is D, and the width of the third doping region 08 is E. In this embodiment, in the first direction M, the width of the orthographic projection of the first sidewall 04 on the substrate 01 is smaller than the width of the orthographic projection of the second sidewall 05 on the substrate 01, that is, B<A. In order to ensure that the width C of the conductive channel in this embodiment is the same as that of Figure 1 The length c of the existing conductive channel shown is the same as or Figure 2 The length h of the existing conductive channel shown in FIG. 1 is the same, and the reduced width of the first sidewall 04 can be supplemented by the width of the second sidewall 05. At this time, since the width of the first sidewall 04 is reduced, the area of ​​the substrate 01 exposed by the first opening area 03a becomes larger, so the width D of the first doped area 06 can be made larger than that of the first doped area 06. Figure 1 The width d of the conventional N+ doped region shown is greater than Figure 2 The width i of the existing N+ doping region is shown. At this time, the width E of the third doping region 08 is Figure 1 The width e of the existing P+ doped region is the same as or equal to Figure 2 The width j of the existing P+ doping region shown is the same. Even if there is a partial overlap between the third doping region 08 and the first doping region 06 during photoresist development, it will not affect the doping concentration in the first doping region 06, and will not reduce the on-resistance, thereby ensuring the voltage resistance performance of the device.

[0080] Optional, reference Figure 4 , Figure 4 A partial structural diagram of another semiconductor device provided in an embodiment of the present application; the first sidewall spacer 04 includes a first sidewall spacer layer x, and the second sidewall spacer 05 includes the first sidewall spacer layer x and the second sidewall spacer layer y.

[0081] Specifically, the first side wall 04 has one less second side wall layer y than the second side wall 05. When the width C of the conductive channel in the first direction M remains unchanged, the present embodiment can make the area in the first opening area 3a except the first side wall 04, that is, the width of the exposed substrate 01 wider. When forming the first doping area 06, the width D of the first doping area 06 can be set wider than the existing one, thereby avoiding the problem of reduced device performance due to overlapping of doping areas.

[0082] Optional, reference Figure 5 , Figure 5 A partial structural diagram of another semiconductor device provided in an embodiment of the present application; the first spacer layer x includes a first sub-layer v and a second sub-layer u.

[0083] In the first sidewall 04 , the first sub-layer v and the second sub-layer u are stacked.

[0084] In the second spacer 05 , the second spacer layer y is located between the first sub-layer v and the second sub-layer u.

[0085] Specifically, the material of the first sublayer v is the same as that of the second sublayer u, which may be a silicon nitride material. In the second sidewall 05, the material of the second sidewall layer y may be a silicon oxide material, which is not specifically limited. During preparation, the second sidewall layer y in the second sidewall 05 may be arranged between the first sublayer v and the second sublayer u according to different preparation processes. It should be noted that this embodiment is only for illustrative purposes, and during preparation, it is only necessary to make the width B of the orthographic projection of the first sidewall 04 on the substrate 01 smaller than the width A of the second sidewall 05.

[0086] Optional, such as Figure 5 As shown, both the first spacer 04 and the second spacer 05 include a third spacer layer z, and the third spacer layer z is located between the first sub-layer v and the gate structure 02 .

[0087] Specifically, the first sidewall spacer 04 further includes a third sidewall spacer layer z located between the gate structure 02 and the first sublayer v, and the second sidewall spacer 05 also includes a third sidewall spacer layer z located between the gate structure 02 and the first sublayer v. In this embodiment, the material of the third sidewall spacer layer z can be a silicon oxide material. It should be noted that the first sidewall spacer 04 and the second sidewall spacer 05 are provided with multiple layers, which can better achieve the same width C of the conductive channel as the existing one, and ensuring the width of the conductive channel can ensure the performance of the device.

[0088] Optional, reference Figure 6 , Figure 6 A partial structural diagram of an LDMOS device provided in an embodiment of the present application; the semiconductor device further includes:

[0089] The shielding layer 10 covers the second sidewall spacer 05 , a portion of the surface of the gate structure 02 close to the second sidewall spacer 05 , and a portion of the surface of the second doping region 07 close to the second sidewall spacer 05 .

[0090] The metal silicide layer 11 is located on the surface of the gate structure 02 exposed by the shielding layer 10 , the surface of the second doping region 07 exposed by the shielding layer 10 , the surface of the first doping region 06 , and the surface of the third doping region 08 exposed by the shielding layer 10 .

[0091] Multiple contact structures 12, the multiple contact structures 12 are respectively in contact with the metal silicide layer 11 on the surface of the gate structure 02 exposed by the shielding layer 10, the metal silicide layer 11 on the surface of the first doping region 06, the metal silicide layer 11 on the surface of the second doping region 07 and the metal silicide layer 11 on the surface of the third doping region 08.

[0092] Specifically, in this embodiment, the semiconductor device can be an LDMOS device, in which a shielding layer 10 is also included. The shielding layer 10 is a self-aligned shielding layer. The shielding layer 10 is provided so that the subsequent metal silicide layer 11 can be provided at a desired position. The metal silicide layer 11 is located on the surface of the gate structure 02 exposed by the shielding layer 10, the surface of the second doping region 07 exposed by the shielding layer 10, the surface of the first doping region 06, and the surface of the third doping region 08. The metal silicide layer 11 can be conductive. When forming multiple contact structures 12, in one embodiment, multiple contact structures 12 are formed by etching first and then depositing. At this time, in order to ensure that etching does not affect the structure of the lower layer, an etching stop layer 21 can be formed first to ensure that etching stops. The etching stop layer 21 is described in the preparation method and will not be repeated here. Multiple contact structures 12 are respectively in contact with the metal silicide layer 11 on the surface of the gate structure 02 exposed by the shielding layer 10, the metal silicide layer 11 on the surface of the first doped region 06, the metal silicide layer 11 on the surface of the second doped region 07, and the metal silicide layer 11 on the surface of the third doped region 08, so as to realize the electrical connection between the internal and external circuits of the LDMOS device.

[0093] In this embodiment, since the distance between the doped ions in the first doped region 06 and the conductive channel becomes closer, the turn-on voltage required by the LDMOS device is relatively reduced, so it is no longer necessary to set Figure 1 The conductive gate shown in the figure omits the deposition of SA-poly and the yellow light and etching of this layer in this embodiment, so that the back side of the wafer will not easily cause occasional tailing problems in the edge area of ​​the wafer due to the SA-poly layer and unnecessary processes, thereby increasing the reliability of the LDMOS device and reducing economic losses.

[0094] Optional, reference Figure 7 , Figure 7 A partial structural diagram of a SWITCH MOS device provided in an embodiment of the present application; the semiconductor device further includes:

[0095] The metal silicide layer 11 is located on the surface of the gate structure 02 , the surface of the first doping region 06 , the surface of the second doping region 07 , and the surface of the third doping region 08 .

[0096] Multiple contact structures 12, the multiple contact structures 12 are in contact with the metal silicide layer 11 located on the surface of the gate structure 02, the metal silicide layer 11 on the surface of the first doping region 06, the metal silicide layer 11 on the surface of the second doping region 07 and the metal silicide layer 11 on the surface of the third doping region 08 respectively.

[0097] Specifically, in the present embodiment, the semiconductor device may be a SWITCH MOS device, wherein the metal silicide layer 11 is located on the surface of the gate structure 02, the surface of the first doping region 06, the surface of the second doping region 07, and the surface of the third doping region 08, and the metal silicide layer 11 is conductive. When forming a plurality of contact structures 12, in one embodiment, a plurality of contact structures 12 are formed by etching first and then depositing. At this time, in order to ensure that the etching does not affect the structure of the lower layer, an etching stop layer 21 may be formed first to ensure that the etching stops. The etching stop layer 21 is described in the preparation method and will not be described in detail here. The plurality of contact structures 12 are in contact with the metal silicide layer 11 located on the surface of the gate structure 02, the metal silicide layer 11 on the surface of the first doping region 06, the metal silicide layer 11 on the surface of the second doping region 07, and the metal silicide layer 11 on the surface of the third doping region 08, respectively, so as to realize the electrical connection between the internal and external circuits of the SWITCH MOS device.

[0098] Based on the above semiconductor device, the present application also provides a method for preparing a semiconductor device, which is used to prepare the above semiconductor device. Figure 3 As shown, and reference Figure 8 , Figure 8 A schematic diagram of a manufacturing process of a semiconductor device provided in an embodiment of the present application; the manufacturing method comprises:

[0099] S101: providing a substrate 01.

[0100] S102 : forming at least two gate structures 02 spaced apart from each other in sequence on one side of the substrate 01 .

[0101] There is an opening area 03 between the gate structures 02 , and the opening area 03 includes a first opening area 03 a and a second opening area 03 b . The first opening area 03 a and the second opening area 03 b are alternately arranged in a first direction M, and the first direction M is parallel to the plane where the substrate 01 is located.

[0102] S103 : forming a first spacer 04 and a second spacer 05 on two sides of the gate structure 02 respectively.

[0103] The first sidewall 04 is located in the first opening area 03 a , and the second sidewall 05 is located in the second opening area 03 b . In the first direction M, the orthographic projection width of the first sidewall 04 on the substrate 01 is smaller than the orthographic projection width of the second sidewall 05 on the substrate 01 .

[0104] S104: In the first opening region 03a, a region of the substrate 01 on a side of the first sidewall 04 away from the gate structure 02 is subjected to first-type doping, and in the second opening region 03b, a region of the substrate 01 on a side of the second sidewall 05 away from the gate structure 02 is subjected to first-type doping to form a first doping region 06 and a second doping region 07.

[0105] The first doping region 06 is located in the first opening region 03 a , and the second doping region 07 is located in the second opening region 03 b ; the first doping region 06 and the second doping region 07 have the first conductivity type.

[0106] S105 : performing second type doping on the substrate 01 between the two first doping regions 06 in the first opening region 03 a to form a third doping region 08 .

[0107] The third doping region 08 has the second conductivity type.

[0108] Specifically, in the semiconductor device prepared by the preparation method, in the first direction M, the width of the orthographic projection of the first sidewall 04 on the substrate 01 is B, the width of the orthographic projection of the second sidewall 05 on the substrate 01 is A, the length of the conductive channel is C, the width of the first doping region 06 is D, and the width of the third doping region 08 is E. In this embodiment, in the first direction M, the width of the orthographic projection of the first sidewall 04 on the substrate 01 is smaller than the width of the orthographic projection of the second sidewall 05 on the substrate 01, that is, B<A. In order to ensure that the width C of the conductive channel in this embodiment is the same as that in the embodiment Figure 1 The length c of the existing conductive channel shown is the same as or Figure 2 The length h of the existing conductive channel shown in FIG. 1 is the same, and the reduced width of the first sidewall 04 can be supplemented by the width of the second sidewall 05. At this time, since the width of the first sidewall 04 is reduced, the area of ​​the substrate 01 exposed by the first opening area 03a becomes larger, so the width D of the first doped area 06 can be made larger than that of the first doped area 06. Figure 1 The width d of the conventional N+ doped region shown is greater than Figure 2 The width i of the existing N+ doping region is shown. At this time, the width E of the third doping region 08 is Figure 1 The width e of the existing P+ doped region is the same as or equal to Figure 2 The width j of the existing P+ doping region shown is the same. Even if there is a partial overlap between the third doping region 08 and the first doping region 06 during photoresist development, it will not affect the doping concentration in the first doping region 06, and will not reduce the on-resistance, thereby ensuring the voltage resistance performance of the device.

[0109] Optional, reference Figure 9-14 , Figure 9-Figure 14A schematic diagram of a partial structure of a structure obtained in a method for preparing a semiconductor device provided in an embodiment of the present application; a first sidewall 04 and a second sidewall 05 are formed on both sides of a gate structure 02, the first sidewall 04 is located in a first opening area 03a, and the second sidewall 05 is located in a second opening area 03b, including:

[0110] S201 : sequentially forming a first material layer 13 and a second material layer 14 covering the substrate 01 and the gate structure 02 .

[0111] In this step, if Fig. 9 As shown, when setting the gate structure 02 on the substrate 01, a gate oxide layer is first formed on the substrate 01, and then after the gate structure 02 is formed, a polysilicon re-oxidation process is performed to improve the performance of the material. For example, a fourth material layer 15 with a thickness of 100 angstroms can be deposited on the surface of the gate structure 02 and the substrate 01; the fourth material layer 15 can be a silicon oxide material layer.

[0112] Then, a first material layer 13 and a second material layer 14 are sequentially formed on one side of the fourth material layer 15. For example, forming the first material layer 13 includes depositing a 200 angstrom silicon nitride material layer; forming the second material layer 14 includes depositing a 400 angstrom TEOSSiO 2 Material layer.

[0113] S202 : Partially etching the second material layer 14 to form spacer intermediate layers 16 on both sides of the gate structure 02 .

[0114] In this step, if Fig.10 As shown, the first material layer 13 is used as a stop layer, and the second material layer 14 is uniformly dry-etched to form a spacer intermediate layer 16 on both sides of the gate structure 02 .

[0115] S203: removing the spacer intermediate layer 16 in the first opening area 03a by using a photolithography process.

[0116] In this step, if Fig.11 As shown, a patterned first photoresist 17 is first formed, and then the sidewall intermediate layer 16 in the first opening area 03a is removed by wet etching using a photolithography process. Fig.12 As shown, wet cleaning is performed to remove the patterned first photoresist 17 for subsequent preparation.

[0117] S204 : forming a third material layer 18 covering the spacer intermediate layer 16 and the first material layer 13 in the second opening region 03 b .

[0118] In this step, if Fig.13As shown, a third material layer 18 is formed to cover the spacer intermediate layer 16 in the second opening area 03b and the first material layer 13. For example, a 800 angstrom silicon nitride material layer is deposited on the side of the spacer intermediate layer 16 and the first material layer 13 in the second opening area 03b away from the substrate 01. The material of the first material layer 13 can also be silicon nitride material, so it can be combined with the third material layer 18, and the combined thickness does not exceed 1000 angstroms.

[0119] S205: Partially etching the third material layer 18 and the first material layer 13 to form a first sidewall spacer 04 on one side of the gate structure 02 and a second sidewall spacer 05 on one side of the gate structure 02. The first sidewall spacer 04 is located in the first opening area 03a, and the second sidewall spacer 05 is located in the second opening area 03b.

[0120] In this step, if Fig.14 As shown, the third material layer 18 and the first material layer 13 are dry-etched. At this time, the third material layer 18, the first material layer 13 and the fourth material layer 15 on the upper surface of the gate structure 02 are all etched away, and the fourth material layer 15 on the lower side of the gate structure 02, the first sidewall 04 and the second sidewall 05 is also etched away. The first sidewall 04 forms a stacked structure of a third sidewall layer z, a first sublayer v and a second sublayer u in the first direction M; the second sidewall 05 forms a stacked structure of a third sidewall layer z, a first sublayer v, a second sidewall layer y and a second sublayer u in the first direction M. Among them, the third sidewall layer z is obtained by etching the fourth material layer 15, the first sublayer v is obtained by etching the first material layer 13, the second sidewall layer y is obtained by etching the second material layer 14, and the second sublayer u is obtained by etching the third material layer 18.

[0121] In this embodiment, in the first direction M, the width of the orthographic projection of the first sidewall 04 on the substrate 01 is smaller than the width of the orthographic projection of the second sidewall 05 on the substrate 01, which provides a preparation basis for the doping width of the subsequent doping region. Since the orthographic projection width of the first sidewall 04 on the substrate 01 is reduced, it is obvious that the doping region on one side of the first sidewall 04 is close to the conductive channel, which reduces the on-voltage required by the device, which is equivalent to increasing the on-resistance, reducing the leakage current, and making the on-off control better.

[0122] Optional, reference Fig.15 , Fig.15Another partial structural schematic diagram of a structure obtained in a method for preparing a semiconductor device provided in an embodiment of the present application; in another embodiment of the present application, in the first opening region 03a, a region of the substrate 01 on a side of the first sidewall 04 away from the gate structure 02 is subjected to first-type doping, and in the second opening region 03b, a region of the substrate 01 on a side of the second sidewall 05 away from the gate structure 02 is subjected to first-type doping to form a first doping region 06 and a second doping region 07, wherein the first doping region 06 is located in the first opening region 03a, and the second doping region 07 is located in the second opening region 03b, including:

[0123] S301 : forming a first photoresist 19 in a middle region of the first sidewall spacer 04 away from the gate structure 02 in the first opening region 03 a .

[0124] In this step, if Fig.15 As shown, in the middle area of ​​the first sidewall 04 away from the gate structure 02 in the first opening area 03 a , a first photoresist 19 is formed, and the first photoresist 19 blocks the area that does not need to be doped with the first type.

[0125] S302: Using the first photoresist 19, the gate structure 02, the first side wall 04 and the second side wall 05 as an injection barrier layer, in the first opening area 03a, a region of the substrate 01 on the side of the first side wall 04 away from the gate structure 02 is subjected to first-type doping, and in the second opening area 03b, a region of the substrate 01 on the side of the second side wall 05 away from the gate structure 02 is subjected to first-type doping to form a first doping region 06 and a second doping region 07, wherein the first doping region 06 is located in the first opening area 03a, and the second doping region 07 is located in the second opening area 03b.

[0126] In this step, if Fig.15 As shown, the doping of the first doping region 06 and the second doping region 07 are both first-type doping, so they can be doped at the same time to form the first doping region 06 and the second doping region 07 of the first conductivity type. The first-type doping can be N-type heavy doping or P-type medium doping, which is not specifically limited and is set according to specific needs. It should be noted that the first doping region 06 is located in the substrate 01 of the first opening region 03a, and the second doping region 07 is located in the substrate 01 of the second opening region 03b.

[0127] S303: removing the first photoresist 19.

[0128] After the first doping region 06 and the second doping region 07 are formed, the first photoresist 19 is removed.

[0129] In this embodiment, since the width of the orthographic projection of the first side wall 04 on the substrate 01 becomes smaller, the area exposed by the substrate 01 in the first opening area 03a becomes larger. When doping is performed, the width of the orthographic projection of the first doping area 06 is larger than the existing one. Therefore, even if the subsequent doping overlaps with it, it will not affect the doping concentration of the first doping area 06.

[0130] Optional, reference Fig.16 , Fig.16 A schematic diagram of another part of the structure obtained in a method for preparing a semiconductor device provided in an embodiment of the present application; in another embodiment of the present application, in the first opening region 03a, the substrate 01 between the two first doping regions 06 is subjected to second type doping to form a third doping region 08, including:

[0131] S401 : forming a second photoresist 20 in other regions except the middle region of the first spacer 04 away from the gate structure 02 .

[0132] S402 : using the second photoresist 20 as an injection barrier layer, in the first opening region 03 a , performing second type doping on the substrate 01 between the two first doping regions 06 to form a third doping region 08 .

[0133] S403 : removing the second photoresist 20 .

[0134] In this embodiment, if Fig.16 As shown, a second photoresist 20 is formed in other regions except the middle region of the first sidewall 04 away from the gate structure 02, and the second photoresist 20 covers the second doping region 07, the second sidewall 05, the gate structure 02, the first sidewall 04 and the first doping region 06. The second type of doping can be N-type heavy doping or P-type heavy doping, but the second type of doping is different from the first type of doping. After forming the third doping region 08, the second photoresist 20 is removed.

[0135] At this time, a sandwich structure of the first doping region 06 / the third doping region 07 / the first doping region 06 is formed in the substrate 01 in the first opening region 03a. Designing the third doping region 08 and the first doping region 06 together can save the area of ​​the semiconductor device.

[0136] In this embodiment, in the first direction M, the width of the orthographic projection of the first side wall 04 on the substrate 01 becomes smaller, and the width of the orthographic projection of the second side wall 05 on the substrate 01 becomes larger, while the area of ​​the semiconductor device and the conductive channel remain unchanged, so that the photoresist is less disturbed by the side wall during development, the profile of the photoresist is better, and serious cross-diffusion problems will not occur in the doped area.

[0137] refer to Fig.17 , Fig.17A schematic diagram of a structure obtained in a method for preparing an LDMOS device provided in an embodiment of the present application; when the semiconductor device is an LDMOS device, after forming the first doping region 06, the second doping region 07 and the third doping region 08, a shielding layer 10, a metal silicide layer 11 and a contact structure 12 are continuously formed. For example, after forming the doping region, a shielding layer 10 is formed on the second sidewall 05, a partial surface of the gate structure 02 close to the second sidewall 05 and a partial surface of the second doping region 07 close to the second sidewall 05 by photolithography, and the shielding layer 10 is a self-aligned shielding layer used to shield the area that does not need to be metallized, and then the surface of the gate structure 02 exposed by the shielding layer 10, the surface of the second doping region 07 exposed by the shielding layer 10, the surface of the first doping region 06 and the surface of the third doping region 08 are continuously metallized to form a metal silicide layer 11. Then, an etch stop layer 21 is formed on one side of the metal silicide layer 11 , the shielding layer 10 and the first sidewall spacer 04 , and then an interlayer dielectric layer 22 is formed on the upper side of the etch stop layer 21 . Then, the interlayer dielectric layer 22 and the etch stop layer 21 are etched to form a plurality of contact holes, which respectively expose the metal silicide layer 11 on the surface of the gate structure 02 exposed by the shielding layer 10, the metal silicide layer 11 on the surface of the first doping region 06, the metal silicide layer 11 on the surface of the second doping region 07, and the metal silicide layer 11 on the surface of the third doping region 08. Then, contact structures 12 are formed in the contact holes, and the plurality of contact structures 12 are respectively in contact with the metal silicide layer 11 on the surface of the gate structure 02 exposed by the shielding layer 10, the metal silicide layer 11 on the surface of the first doping region 06, the metal silicide layer 11 on the surface of the second doping region 07, and the metal silicide layer 11 on the surface of the third doping region 08, so as to realize the electrical connection between the internal and external circuits of the LDMOS device, and then all the processes of the back-end process can be formed.

[0138] In this embodiment, the SA-poly layer is not formed, a deposition and etching process can be omitted, and SA-poly is no longer formed on the back of the wafer, so that the occasional tailing effect problem at the edge of the wafer will not occur, reducing economic losses and improving device reliability.

[0139] refer to Fig.18 , Fig.18A schematic diagram of a structure obtained in a method for preparing a SWITCH MOS device provided in an embodiment of the present application; when the semiconductor device is a SWITCH MOS device, after forming the first doping region 06, the second doping region 07 and the third doping region 08, a metal silicide layer 11 and a contact structure 12 are continuously formed. For example, after forming the doping region, the surface of the gate structure 02, the surface of the first doping region 06, the surface of the second doping region 07 and the surface of the third doping region 08 are metallized to form a metal silicide layer 11. Then, an etch stop layer 21 is formed on the metal silicide layer 11, the first sidewall 04 and the second sidewall 05, and an interlayer dielectric layer 22 is continuously formed on one side of the etch stop layer 21. Then, the interlayer dielectric layer 22 and the etch stop layer 21 are etched to form a plurality of contact holes, wherein the contact holes expose the metal silicide layer 11 on the surface of the gate structure 02, the metal silicide layer 11 on the surface of the first doping region 06, the metal silicide layer 11 on the surface of the second doping region 07, and the metal silicide layer 11 on the surface of the third doping region 08. Then, contact structures 12 are formed in the contact holes, wherein the plurality of contact structures 12 are in contact with the metal silicide layer 11 on the surface of the gate structure 02, the metal silicide layer 11 on the surface of the first doping region 06, the metal silicide layer 11 on the surface of the second doping region 07, and the metal silicide layer 11 on the surface of the third doping region 08, respectively, so as to realize the electrical connection between the internal and external circuits of the SWITCH MOS device, and then all the processes of the back-end process can be formed.

[0140] In the embodiment of the present application, since the width of the orthographic projection of the first sidewall 04 on the substrate 01 is reduced, the etching window of the shielding layer 10 and the contact structure 12 is larger, and the process is healthier. In the entire process, the actual operation process difficulty is reduced, the development progress is accelerated, and the development cost is saved.

[0141] In the description of this specification, the description with reference to the terms "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0142] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; At least two gate structures, at least two of the gate structures are located on one side of the substrate and are sequentially spaced apart along a first direction, an opening area is provided between the gate structures, the opening area includes a first opening area and a second opening area, the first opening area and the second opening area are alternately arranged in the first direction, and the first direction is parallel to the plane where the substrate is located; A first sidewall spacer and a second sidewall spacer are respectively located on both sides of the gate structure, and the first sidewall spacer is located in the first opening area, and the second sidewall spacer is located in the second opening area; in the first direction, the width of the first sidewall spacer on the substrate is smaller than the width of the second sidewall spacer on the substrate; the first sidewall spacer includes a first sidewall spacer layer, and the second sidewall spacer includes a first sidewall spacer layer and a second sidewall spacer layer; The first sidewall layer includes a first sublayer and a second sublayer; In the first sidewall, the first sublayer and the second sublayer are stacked; In the second spacer, the second spacer layer is located between the first sub-layer and the second sub-layer; Furthermore, the substrate includes a first doped region, a second doped region and a third doped region, the first doped region and the second doped region have a first conductivity type, and the third doped region has a second conductivity type; the first doped region is located in the first opening region, and is located on a side of the first side wall away from the gate structure; the second doped region is located in the second opening region, and is located on a side of the second side wall away from the gate structure; the third doped region is located in the first opening region, and is located between the two first doped regions in the first opening region.

2. The semiconductor device according to claim 1, wherein: The first spacer and the second spacer both include a third spacer layer, and the third spacer layer is located between the first sub-layer and the gate structure.

3. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a shielding layer, wherein the shielding layer covers the second sidewall, a portion of the surface of the gate structure close to the second sidewall, and a portion of the surface of the second doping region close to the second sidewall; A metal silicide layer, located on the surface of the gate structure exposed by the shielding layer, the surface of the second doping region exposed by the shielding layer, the surface of the first doping region, and the surface of the third doping region; A plurality of contact structures, wherein the plurality of contact structures are respectively in contact with the metal silicide layer on the surface of the gate structure exposed by the shielding layer, the metal silicide layer on the surface of the first doping region, the metal silicide layer on the surface of the second doping region, and the metal silicide layer on the surface of the third doping region.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A metal silicide layer, located on a surface of the gate structure, a surface of the first doping region, a surface of the second doping region, and a surface of the third doping region; A plurality of contact structures, wherein the plurality of contact structures are respectively in contact with the metal silicide layer located on the surface of the gate structure, the metal silicide layer on the surface of the first doping region, the metal silicide layer on the surface of the second doping region, and the metal silicide layer on the surface of the third doping region.

5. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: providing a substrate; At least two gate structures are formed on one side of the substrate and are arranged in sequence and spaced apart from each other; an opening area is provided between the gate structures, and the opening area includes a first opening area and a second opening area, and the first opening area and the second opening area are alternately arranged in a first direction, and the first direction is parallel to the plane where the substrate is located; A first sidewall spacer and a second sidewall spacer are formed on both sides of the gate structure, respectively, the first sidewall spacer is located in the first opening area, and the second sidewall spacer is located in the second opening area; in the first direction, the width of the first sidewall spacer on the substrate is smaller than the width of the second sidewall spacer on the substrate; the first sidewall spacer includes a first sidewall spacer layer, and the second sidewall spacer includes a first sidewall spacer layer and a second sidewall spacer layer; The first sidewall layer includes a first sublayer and a second sublayer; In the first sidewall, the first sublayer and the second sublayer are stacked; In the second spacer, the second spacer layer is located between the first sub-layer and the second sub-layer; In the first opening region, a region of the substrate on a side of the first sidewall away from the gate structure is doped with a first type, and in the second opening region, a region of the substrate on a side of the second sidewall away from the gate structure is doped with a first type to form a first doping region and a second doping region, wherein the first doping region is located in the first opening region and the second doping region is located in the second opening region; the first doping region and the second doping region have a first conductivity type; In the first opening region, the substrate between the two first doping regions is doped with a second type of conductive material to form a third doping region; the third doping region has a second conductivity type.

6. The preparation method according to claim 5, characterized in that: The first sidewall spacer and the second sidewall spacer are respectively formed on both sides of the gate structure, the first sidewall spacer is located in the first opening area, and the second sidewall spacer is located in the second opening area, including: sequentially forming a first material layer and a second material layer covering the substrate and the gate structure; Partially etching the second material layer to form a spacer intermediate layer on both sides of the gate structure; Using a photolithography process to remove the sidewall intermediate layer in the first opening area; forming a third material layer covering the spacer intermediate layer and the first material layer in the second opening area; The third material layer and the first material layer are partially etched to form the first sidewall spacer on one side of the gate structure and the second sidewall spacer on one side of the gate structure, wherein the first sidewall spacer is located in the first opening area and the second sidewall spacer is located in the second opening area.

7. The preparation method according to claim 5, characterized in that: In the first opening region, a region of the substrate on a side of the first sidewall away from the gate structure is doped with a first type, and in the second opening region, a region of the substrate on a side of the second sidewall away from the gate structure is doped with a first type to form a first doping region and a second doping region, wherein the first doping region is located in the first opening region and the second doping region is located in the second opening region, comprising: Forming a first photoresist in a middle area of ​​the first sidewall in the first opening area away from the gate structure; The first photoresist, the gate structure, the first sidewall and the second sidewall are used as an injection barrier layer, and in the first opening region, a region of the substrate on a side of the first sidewall away from the gate structure is doped with a first type, and in the second opening region, a region of the substrate on a side of the second sidewall away from the gate structure is doped with a first type, so as to form a first doping region and a second doping region, wherein the first doping region is located in the first opening region and the second doping region is located in the second opening region; The first photoresist is removed.

8. The preparation method according to claim 5, characterized in that: The step of performing second-type doping on the substrate between the two first doping regions in the first opening region to form a third doping region comprises: forming a second photoresist in other regions except a middle region of a side of the first sidewall spacer away from the gate structure; Using the second photoresist as an injection barrier layer, in the first opening region, performing second-type doping on the substrate between the two first doping regions to form a third doping region; The second photoresist is removed.

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