Field effect transistor

Abstract

The embodiment of the invention provides a field effect transistor. The field effect transistor comprises a substrate; the drift region is formed on the substrate; the first doped region is formed in the drift region and is positioned at the upper part of the drift region; the well regions are formed in the first doped region, and every two adjacent well regions are separated from each other; the second doped region is formed on the first doped region; the third doped region is formed in the second doped region and located on the upper portion of the second doped region, and the doping concentration of the third doped region is larger than that of the second doped region; the gate dielectric layer and the polysilicon gate are sequentially formed on the third doped region; the additional layer is laid on the surface of the insulating dielectric layer, one end of the additional layer is electrically connected with the polysilicon gate, and the other end is electrically connected with the third doped region. According to the field effect transistor provided by the embodiment of the invention, when the gate source bias voltage is 0 and the field effect transistor works at high temperature, the additional layer leads out redundant carriers in the third doped region to the gate electrode, so that the transistor can be normally turned off.

Description

Technical Field

[0001] The present application relates to semiconductor technology, and in particular to a field effect transistor. Background Art

[0002] The vertical capacitively coupled gate-controlled junction field effect transistor is a new type of semiconductor device, in which an epitaxial layer, source, gate and drain are formed in sequence on a silicon carbide substrate. Among them, the top gate is floating. When the gate-source bias voltage Vgs=0V, a positive bias is applied to the drain source. When the device is in a high-temperature blocking state, the carrier concentration in the gate increases by 1 to 5 times, but these carriers have no discharge path, resulting in an increase in the potential difference of the gate, which is equivalent to applying a positive bias of less than 1V to the gate, making the device unable to turn off. When the device is used as a freewheeling diode, the gate source is short-circuited at high temperatures, and the blocking voltage of the device is too low. In addition, as the proportion of the conduction time increases, the potential of the gate decreases, causing the device's Ids to turn off as the conduction time increases. Summary of the invention

[0003] In order to solve one of the above technical defects, a field effect transistor is provided in an embodiment of the present application.

[0004] According to a first aspect of an embodiment of the present application, there is provided a field effect transistor, comprising:

[0005] substrate;

[0006] A drift region is formed on the substrate, the drift region being of a first doping type;

[0007] A first doped region formed in the drift region and located at an upper portion of the drift region, the first doped region being of a first doping type;

[0008] A well region is formed in the first doping region, two adjacent parts of the well region are spaced apart, and the well region is of a second doping type;

[0009] A second doping region is formed on the first doping region, the second doping region being of a second doping type;

[0010] a third doping region formed in the second doping region and located on the upper part of the second doping region, the doping concentration of the third doping region being greater than the doping concentration of the second doping region, and the third doping region being of the second doping type;

[0011] forming a gate dielectric layer on the third doped region;

[0012] A polysilicon gate formed on the gate dielectric layer;

[0013] an additional layer, one end of which is electrically connected to the polysilicon gate and the other end of which is electrically connected to the third doped region;

[0014] A source region is formed on both sides of the third doping region, and the source region and the third doping region are separated by the second doping region.

[0015] According to a second aspect of an embodiment of the present application, there is provided a field effect transistor, comprising:

[0016] A basic device; a first doping region, a second doping region and a third doping region are formed on the basic device and are arranged in sequence from bottom to top; a gate dielectric layer and a polysilicon gate are formed in sequence on the third doping region;

[0017] The additional layer has one end electrically connected to the polysilicon gate and the other end electrically connected to the third doped region.

[0018] The technical solution provided by the embodiment of the present application is as follows: a drift region is formed on the substrate, and the drift region is of a first doping type; a first doping region, a second doping region and a third doping region are provided in the drift region and located on the upper part of the drift region; the first doping region is of the first doping type; the second doping region and the third doping region are of the second doping type; the second doping region is located on the first doping region, and the third doping region is formed in the second doping region and located on the upper part of the second doping region; the doping concentration of the third doping region is greater than the doping concentration of the second doping region; a well region is provided in the first doping region, and two adjacent parts of the well region are spaced apart, and the well region is of the second doping type; a gate dielectric layer is formed on the third doping region, and a polysilicon gate is formed on the gate dielectric layer; one end of the additional layer is electrically connected to the polysilicon gate, and the other end is electrically connected to the third doping region; a source region is formed on both sides of the third doping region, and the source region and the third doping region are separated by the second doping region. When the gate-source bias voltage Vgs=0V and the transistor works at a high temperature, the additional layer guides the excess carriers in the third doping region to the gate electrode, so that the transistor can be normally turned off. In addition, when the transistor is used as a freewheeling diode of the main circuit, the gate and source are short-circuited under high temperature conditions, and the blocking voltage of the transistor and the main circuit are the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 A schematic diagram of the structure of a field effect transistor provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of an equivalent circuit of a field effect transistor provided in an embodiment of the present application;

[0022] Figure 3 A top view of a field effect transistor provided in an embodiment of the present application;

[0023] Figure 4 for Figure 3 Middle AA section view;

[0024] Figure 5 for Figure 3 Middle BB section view;

[0025] Figure 6 for Figure 3 Middle CC section view;

[0026] Figure 7 A top view of another field effect transistor provided in an embodiment of the present application;

[0027] Figure 8 This is a data curve chart obtained by testing the field effect transistor provided in the embodiment of the present application.

[0028] Reference numerals:

[0029] 1-substrate; 2-drift region; 3-well region; 6-first doping region; 800-second doping region; 8-third doping region; 9-gate dielectric layer; 10-polysilicon gate; 11-additional layer; 12-source electrode. DETAILED DESCRIPTION

[0030] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0031] like Figure 1 As shown, this embodiment provides a field effect transistor, including: a substrate 1 and a drift region 2. The substrate 1 may be a silicon substrate, a silicon carbide substrate, or other material substrates capable of manufacturing transistors. The drift region 2 is formed on the upper surface of the substrate 1, and the doping type of the drift region 2 is a first doping type.

[0032] Ions are injected into the drift region 2 and a first doping region 6, a well region 3, a second doping region 800 and a third doping region 8 are formed on the upper part thereof. The second doping region 800 is located above the first doping region 6, and the third doping region 8 is located in the second doping region 800 and located on the upper part of the second doping region 800. The first doping region 6 is of the first doping type, and the second doping region 800 and the third doping region 8 are both of the second doping type. The doping concentration of the third doping region 8 is greater than the doping concentration of the second doping region 800, that is, the second doping region 800 is lightly doped, and the third doping region 8 is heavily doped.

[0033] A well region 3 is formed in the first doping region 6, and two adjacent parts of the well region 3 are spaced apart, with the spaced part being located below the middle of the third doping region 8. The well region 3 is of the second doping type.

[0034] A gate dielectric layer 9 is formed on the upper surface of the third doping region 8 , and a polysilicon gate 10 is formed on the upper surface of the gate dielectric layer 9 .

[0035] Source regions are further provided on both sides of the third doping region 8, and the source region is separated from the third doping region 8 by a second doping region 800. A source electrode 12 is further provided above the source region, and the source electrode 12 is electrically connected to the source region.

[0036] An additional layer 11 is also provided, one end of the additional layer 11 is electrically connected to the polysilicon gate 10, and the other end is electrically connected to the third doped region 8. The additional layer 11 can be provided at any position on the surface of the insulating dielectric layer, as long as the polysilicon gate 10 is electrically connected to the third doped region 8. The laying area or shape of the additional layer 11 can also be in various ways.

[0037] On the wafer surface, the cross-sectional views of some areas are as follows: Figure 4 , Figure 5 and Figure 6 As shown in FIG. 1 , there are also some areas with only substrate 1 and drift region 2. Figure 4 The cross-sectional area, the insulating dielectric layer can be Figure 4 The gate dielectric layer 9 is laid on the surface of the third dielectric layer 800 .

[0038] Alternatively, the insulating dielectric layer is made of an insulating material different from that of the gate dielectric layer 9 and is laid on the surface of the third dielectric layer 800 .

[0039] Alternatively, in some regions, there are only the substrate 1 and the drift region 2 , and an insulating layer is laid on the upper surface of the drift region 2 as an insulating dielectric layer.

[0040] In summary, the insulating dielectric layer is at least one of the gate dielectric layer 9, the insulating layer formed on the drift region 2, and the insulating layer formed on the third doped region. Insulating dielectric layers are laid in different regions of the wafer in the above manner, and the additional layer 11 is formed on the upper surface of the insulating dielectric layer, which is insulated from the region below the insulating dielectric layer.

[0041] The additional layer 11 is electrically connected between the polysilicon gate 10 and the third doped region 8, which is equivalent to being connected in parallel with the polysilicon gate 10, and plays the role of a parallel resistor.

[0042] (1) When the gate-source bias voltage Vgs≥threshold voltage (Vth=2V), the potential of the third doping region 8 is about 1V, and the transistor provided in this embodiment is normally turned on.

[0043] (2) When the gate-source bias voltage Vgs≥15V, the potential of the third doping region 8 is about 2.5V, and the transistor provided in this embodiment is normally turned on.

[0044] (3) When the gate-source bias voltage Vgs≤0V and the transistor operates at room temperature, the PN junction formed by the third doping region 8 and the first doping region 6 is zero biased, and the transistor provided in this embodiment is normally turned off.

[0045] (4) When the gate-source bias voltage Vgs=0V and the transistor operates at a high temperature, the additional layer 11 conducts the excess carriers in the third doping region 8 to the gate electrode, and the transistor provided in this embodiment is normally turned off.

[0046] (5) When the gate-source bias voltage Vgs is less than 0 V and the transistor operates at high temperature, the additional layer 11 conducts the excess carriers in the third doping region 8, and the PN junction formed by the third doping region 8 and the first doping region 6 is reverse biased, and the transistor provided in this embodiment is normally turned off.

[0047] The technical solution provided by this embodiment is that a drift region is formed on the substrate, and the drift region is of a first doping type; a first doping region, a second doping region and a third doping region are arranged in the drift region and located on the upper part of the drift region; the first doping region is of the first doping type; the second doping region and the third doping region are of the second doping type; the second doping region is located on the first doping region, and the third doping region is formed in the second doping region and located on the upper part of the second doping region; the doping concentration of the second doping region is less than the doping concentration of the first doping region, and the doping concentration of the third doping region is greater than the doping concentration of the second doping region; in the first doping region A well region is provided, two adjacent parts of the well region are separated, and the well region is of the second doping type; a gate dielectric layer is formed on the third doping region, and a polysilicon gate is formed on the gate dielectric layer; an additional layer is formed on the gate dielectric layer, one end of the additional layer is electrically connected to the polysilicon gate, and the other end is electrically connected to the third doping region; a source region is formed on both sides of the third doping region, and the source region and the third doping region are separated by the second doping region. When the gate-source bias voltage Vgs=0V and the transistor works at a high temperature, the additional layer guides the excess carriers in the third doping region to the gate electrode, so that the transistor can be turned off normally. In addition, when the transistor is used as a freewheeling diode of the main tube, the gate source is short-circuited under high temperature conditions, and the blocking voltage of the transistor and the main tube is the same.

[0048] Further, such as Figure 2 As shown, in the technical solution provided by the above content, the equivalent diode 200 is a PN junction diode formed by the first doping region 6, the second doping region 800 and the third doping region 8 in the transistor; the equivalent capacitor 201 is a MOS capacitor formed by the third doping region 8, the gate dielectric layer 9 and the polysilicon gate 10; the equivalent capacitor 202 is a PN junction capacitor formed by the first doping region 6, the second doping region 800 and the third doping region 8. The equivalent capacitor 201 and the equivalent capacitor 202 are connected in series.

[0049] In the traditional scheme, according to the relationship between capacitive reactance and frequency, Xc=1 / 2πfc, where Xc is capacitive reactance, f is frequency, and c is capacitance value, the total reactance of the transient network of equivalent capacitor 201 and equivalent capacitor 202 is Xc=Xc201+Xc202, the current of the network is I=Vgs / Xc, and the voltage drops of equivalent capacitor 201 and equivalent capacitor 202 are Vc201=I*Xc201 and Vc202=I*Xc202 respectively. As the proportion of conduction time increases, the voltage division of equivalent capacitor 201 is larger, that is, the voltage division of equivalent capacitor 202 is smaller, and the potential of the top gate decreases, causing Ids to be turned off as the conduction time increases.

[0050] The potential expression in the second doping region 800 or the third doping region 8 is: Wherein, e is the electron charge, Na is the doping concentration, εs is the semiconductor dielectric constant, and xp is the position where the electric field E=0. It can be seen that as Na decreases, φ(x) decreases. According to the above formula, the carriers in the third doping region 8 are discharged through the additional layer 11 connected in parallel with the polysilicon gate 10, which reduces the carrier concentration in the third doping region 8, thereby preventing the potential of the third doping region 8 from being raised at high temperature.

[0051] In the present application, the additional layer 11 is added, which is equivalent to connecting a resistor in parallel to the polysilicon gate 10 to play a voltage divider role, and can increase the voltage divider of the equivalent capacitor 202. The diode leakage current formed by the third doping region 8 and the first doping region 6 is (1e-9~1e-3)A, and the product of the parallel resistance formed by the additional layer 11 and the current is about 1V. The JFET's own threshold voltage is about 1V, which can keep the threshold voltage of the transistor greater than 2V, thereby slowing down the decay of the transistor's full-on current Ids over time.

[0052] On the basis of the above technical solution, this embodiment provides an implementation method: the source region includes: a first source region 7 and a second source region 4, the second source region 4 is located outside the first source region 7, and the depth of the second source region 4 is greater than the depth of the first source region 7; the first source region 7 is of the first doping type, and the second source region 4 is of the second doping type. The source electrode 12 is formed above the source region and is electrically connected to the first source region 7 and the second source region 4, respectively. In addition, a drain electrode 13 is provided on the lower surface of the substrate 1 away from the drift region 2.

[0053] Furthermore, a buffer layer 100 is formed between the substrate 1 and the drift region 2 to reduce defects in the drift region 2, thereby improving the reliability of the transistor.

[0054] The first doping type and the second doping type can be set according to the type of transistor, for example: the first doping type is N-type, and the second doping type is P-type. Specifically, in the above scheme, the drift region 2 is N-type, the well region 3 is P-type, the second source region 4 is P-type, the first doping region 6 is N-type, the first source region 7 is N-type, the second doping region 800 is lightly doped P-type, and the third doping region 8 is heavily doped P-type.

[0055] The resistance value of the resistor formed is adjusted by adjusting factors such as the length, width, and material of the additional layer 11 . For example, the resistance value of the resistor formed by the additional layer 11 is (1e3-1e9) ohms.

[0056] Based on the above technical solution, this embodiment also provides a specific implementation method:

[0057] The arrangement of the polysilicon gate 10 is as follows Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, it is divided into a first part of the polysilicon gate 10a, a second part of the polysilicon gate 10b and a third part of the polysilicon gate 10c. Taking the figure as an example, the first part of the polysilicon gate 10a includes three polysilicon gates 10; the second part of the polysilicon gate 10b includes three polysilicon gates 10, and the third part of the polysilicon gate 10c includes one polysilicon gate 10. Among them, the first part of the polysilicon gate 10a is located on one side of the transistor, and the second part of the polysilicon gate 10b is located on the other side of the transistor. The first part of the polysilicon gate 10a and the second part of the polysilicon gate 10b are arranged at intervals, and both extend along the first direction. One end of the first part of the polysilicon gate 10a and the second part of the polysilicon gate 10b is flush, and the length of the second part of the polysilicon gate 10b is less than the length of the first part of the polysilicon gate 10a. Figure 3 As an example, the upper ends of the first polysilicon gate 10a and the second polysilicon gate 10b are flush with each other, the first polysilicon gate 10a is longer and located on the right, and the second polysilicon gate 10b is shorter and located on the left. The first direction is Figure 3 A gate dielectric layer 9 and a third doped region 8 are provided below each polysilicon gate 10 .

[0058] The third portion of the polysilicon gate 10c and the second portion of the polysilicon gate 10b are located on the same side of the transistor, that is, the third portion of the polysilicon gate 10c and the second portion of the polysilicon gate 10b are both located on Figure 3 The third portion of the polysilicon gate 10c is located on the left side of the second portion of the polysilicon gate 10b, and the third portion of the polysilicon gate 10c is located below the second portion of the polysilicon gate 10b. The additional layer 11 is laid in the area between the third portion of the polysilicon gate 10c and the second portion of the polysilicon gate 10b.

[0059] In the above scheme, the length of each polysilicon gate 10 in the first part of the polysilicon gate 10a can be 0.5mm-10mm, and the width can be 0.5μm-1.5μm. The length of each polysilicon gate 10 in the second part of the polysilicon gate 10b can be 0.5mm-5mm, and the width can be 0.5μm-1.5μm. The length of the third part of the polysilicon gate 10c can be 0.2mm-2mm, and the width can be 0.2mm-2mm. The above "length" refers to the length along Figure 3 The width refers to the vertical dimension. Figure 3 The size in the left-right direction.

[0060] In one embodiment, the additional layer 11 includes a first connecting segment 111, a second connecting segment 112 and a bending segment, wherein the bending segment is located between the first connecting segment 111 and the second connecting segment 112. The first connecting segment 111 and the second connecting segment 112 both extend along the first direction, the first connecting segment 111 is connected to the third doping region 8 below the second portion of the polysilicon gate 10b, and the second connecting segment 112 is connected to the third portion of the polysilicon 11c. The bending segments may be arranged in a serpentine shape, a spiral shape, or the like.

[0061] A specific method is: the bending section includes: a first bending section 113, a second bending section 114, a third bending section 115, a fourth bending section 116 and a fifth bending section 117 arranged in sequence, the first bending section 113 is connected to the first connecting section 111, and the fifth bending section 117 is connected to the second connecting section 112. The second bending section 114 and the fourth bending section 116 extend along the first direction, and the first bending section 113, the third bending section 115 and the fifth bending section 117 extend along the second direction. The second direction forms a certain angle with the first direction, Figure 3 The second direction is perpendicular to the first direction, that is, the first bending section 113, the third bending section 115 and the fifth bending section 117 are along Figure 3 Extends in left and right directions.

[0062] Specifically, the first bending section 113 extends from the connection point with the first connecting section 111 along the second direction toward the first portion of the polysilicon gate 10a to exceed the third portion of the polysilicon 10c.

[0063] The second bending section 114 extends from the junction with the first bending section 113 along the first direction toward the third portion of the polysilicon gate 10c to the area between the third portion of the polysilicon gate 10c and the first portion of the polysilicon gate 10a.

[0064] The third bending section 115 extends from the junction with the second bending section 114 along the second direction toward the third portion of the polysilicon gate 10 c.

[0065] The fourth bending section 116 extends from the junction with the third bending section 115 toward the second portion of the polysilicon gate 10b to the area between the second portion of the polysilicon gate 10b and the third portion of the polysilicon 10c.

[0066] The fifth bending section 117 extends from the connection with the fourth bending section 116 along the second direction toward a direction away from the first portion of the polysilicon gate 10 a until it is connected to the second connecting section 112 .

[0067] The resistance value of the resistor formed by the additional layer 11 is adjusted by adjusting the width and length of each bending section. In the above scheme, the first part of the polysilicon gate 10a includes three polysilicon gates 10, and the second part of the polysilicon gate 10b includes three polysilicon gates 10. The third part of the polysilicon gate 10c includes a polysilicon gate 10, and its length and width are greater than the polysilicon gates in the first part and the second part.

[0068] One implementation manner is: the lengths of the first connecting segment 111, the second connecting segment 112, the first bending segment 113, the second bending segment 114, the third bending segment 115, the fourth bending segment 116, the fifth bending segment 117, the sixth bending segment 118, and the seventh bending segment 119 are 0.5μm to 50μm, and the widths are 0.5μm to 50μm.

[0069] This embodiment also provides a structural layout solution. Figure 7 As shown, Figure 7 The first part of the polysilicon gate 10a, the second part of the polysilicon gate 10b and the third part of the polysilicon gate 10c are also included. Taking the figure as an example, the first part of the polysilicon gate 10a includes three polysilicon gates 10; the second part of the polysilicon gate 10b includes two polysilicon gates 10, and the third part of the polysilicon gate 10c includes one polysilicon gate 10. The first part of the polysilicon gate 10a is located on one side of the transistor, and the second part of the polysilicon gate 10b is located in the middle of the transistor; the first part of the polysilicon gate 10a and the second part of the polysilicon gate 10b are arranged at intervals, and both extend along the first direction, and the first direction is Figure 7 Specifically, the first portion of the polysilicon gate 10a is located Figure 7 The second polysilicon gate 10b and the third polysilicon gate 10c are located on the right side of Figure 7 The middle part of.

[0070] One end of the first polysilicon gate 10a and the second polysilicon gate 10b are flush with each other. Figure 7The tops of the first part of the polysilicon gate 10a and the second part of the polysilicon gate 10b are flush, and the length of the second part of the polysilicon gate 10b is less than the length of the first part of the polysilicon gate 10a, so that the third part of the polysilicon gate 10c is set in the space below the first part of the polysilicon gate 10a, that is, the third part of the polysilicon gate 10c is also located in the middle of the transistor.

[0071] In the above scheme, the length of each polysilicon gate 10 in the first part of the polysilicon gate 10a can be 0.5mm-10mm, and the width can be 0.5μm-1.5μm. The length of each polysilicon gate 10 in the second part of the polysilicon gate 10b can be 0.5mm-5mm, and the width can be 0.5μm-1.5μm. The length of the third part of the polysilicon gate 10c can be 0.2mm-2mm, and the width can be 0.2mm-2mm. The above "length" refers to the length along Figure 3 The width refers to the vertical dimension. Figure 3 The size in the left-right direction.

[0072] A gate dielectric layer 9 and a third doping layer 8 are disposed below the first portion of the polysilicon gate 10a and the second portion of the polysilicon gate 10b.

[0073] The additional layer 11 is laid on the side of the third polysilicon gate 10c and the second polysilicon gate 10b away from the first polysilicon gate 10a, that is, the additional layer 11 is laid on Figure 7 to the left of the transistor.

[0074] In one embodiment, the additional layer 11 includes a first connecting segment 111, a second connecting segment 112 and a bending segment, wherein the bending segment is located between the first connecting segment 111 and the second connecting segment 112. The first connecting segment 111 and the second connecting segment 112 both extend along the second direction. The first connecting segment 111 is connected to the third doped region 8 below the second portion of the polysilicon gate 10b; the second connecting segment 112 is connected to the third portion of the polysilicon 10c.

[0075] A specific implementation is: the bending segment includes: a first bending segment 113, a second bending segment 114, a third bending segment 115, a fourth bending segment 116, a fifth bending segment 117, a sixth bending segment 118, and a seventh bending segment 119 arranged in sequence, the first bending segment 113 is connected to the first connecting segment 111, and the seventh bending segment 119 is connected to the second connecting segment 112. The first bending segment 113, the third bending segment 115, the fifth bending segment 117, and the seventh bending segment 119 all extend along the first direction, and the second bending segment 114, the fourth bending segment 116, and the sixth bending segment 118 extend along the second direction.

[0076] The second direction is at a certain angle to the first direction. Figure 7The second direction is perpendicular to the first direction, that is, the second bending segment 114, the fourth bending segment 116 and the sixth bending segment 118 are along Figure 7 Extends in left and right directions.

[0077] Specifically, the first bending section 113 extends from the connection point with the first connecting section 111 along the first direction toward a direction away from the third portion of the polysilicon gate 10 c until reaching the edge of the transistor.

[0078] The second bending section 114 extends from the junction with the first bending section 113 along the second direction away from the second portion of the polysilicon gate 10 b until reaching the edge of the transistor.

[0079] The third bending section 115 extends from the junction with the second bending section 114 along the first direction toward the third portion of the polysilicon gate 10 c.

[0080] The fourth bending section 116 extends from the junction with the third bending section 115 along the second direction toward the second portion of the polysilicon gate 10 b.

[0081] The fifth bending section 117 extends from the junction with the fourth bending section 116 along the first direction toward the third portion of the polysilicon gate 10 c.

[0082] The sixth bending section 118 extends from the junction with the fifth bending section 117 along the second direction toward a direction away from the third portion of the polysilicon gate 10 c until reaching the edge of the transistor.

[0083] The seventh bending section 119 extends from a connection point with the sixth bending section 118 along the first direction to connect with the second connecting section 112 .

[0084] In the above solution, the fourth bending segment 116 , the fifth bending segment 117 , the sixth bending segment 118 , and the seventh bending segment 119 form a curved shape similar to a square wave.

[0085] Or as shown in FIG7, it also includes: an eighth bending segment 120, a ninth bending segment 121, a tenth bending segment 122 and an eleventh bending segment 123. The eighth bending segment 120 extends from the connection with the seventh bending segment 119 along the second direction toward the third portion of the polysilicon gate 10c. The ninth bending segment 121 extends from the connection with the eighth bending segment 120 along the first direction, the tenth bending segment 122 extends from the connection with the ninth bending segment 121 along the second direction toward the direction away from the third portion of the polysilicon gate 10c, and the eleventh bending segment 123 extends from the connection with the tenth bending segment 122 along the first direction to connect with the second connecting segment 112.

[0086] In the above solution, the fourth bending section 116, the fifth bending section 117, the sixth bending section 118, and the seventh bending section 119 form a square wave-like curved shape, and the eighth bending section 120, the ninth bending section 121, the tenth bending section 122, and the eleventh bending section 123 form another square wave-like curved shape. By analogy, when the space is large enough, there can be more square wave-like curved sections.

[0087] The first connecting segment 111, the second connecting segment 112, the first bending segment 113, the second bending segment 114, the third bending segment 115, the fourth bending segment 116, the fifth bending segment 117, the sixth bending segment 118, the seventh bending segment 119, the eighth bending segment 120, the ninth bending segment 121, the tenth bending segment 122 and the eleventh bending segment 123 have a length of 0.5μm to 50μm and a width of 0.5μm to 50μm.

[0088] Figure 3 and Figure 7 This is only an example, and the additional layer 11 may also have other layout forms.

[0089] Based on the above technical solution, this embodiment further provides a field effect transistor, including: a basic device and an additional layer. The basic device is formed with a first doping region, a second doping region and a third doping region arranged in sequence from bottom to top; a gate dielectric layer and a polysilicon gate are formed in sequence on the third doping region. The specific implementation of the above basic device can refer to the above content and Figures 1 to 7 .

[0090] Specifically, the basic device includes: a substrate 1 and a drift region 2. The substrate 1 may be a silicon substrate, a silicon carbide substrate or a substrate of other materials. The drift region 2 is formed on the upper surface of the substrate 1, and the doping type of the drift region 2 is a first doping type.

[0091] Ions are injected into the drift region 2 and a first doping region 6, a well region 3, a second doping region 800 and a third doping region 8 are formed on the upper part thereof. The second doping region 800 is located above the first doping region 6, and the third doping region 8 is located in the second doping region 800 and located on the upper part of the second doping region 800. The first doping region 6 is of the first doping type, and the second doping region 800 and the third doping region 8 are both of the second doping type. The doping concentration of the second doping region 800 is less than the doping concentration of the first doping region 6, that is, the second doping region 800 is lightly doped. The doping concentration of the third doping region 8 is greater than the doping concentration of the second doping region 800, that is, the third doping region 8 is heavily doped.

[0092] A well region 3 is formed in the first doping region 6, and two adjacent parts of the well region 3 are spaced apart, and the spaced part is located below the middle of the third doping region 8. The well region 3 is of the second doping type. A gate dielectric layer 9 is formed on the upper surface of the third doping region 8, and a polysilicon gate 10 is formed on the upper surface of the gate dielectric layer 9. Source regions are also provided on both sides of the third doping region 8, and the source region is separated from the third doping region 8 by a second doping region 800. A source electrode 12 is also provided above the source region, and the source electrode 12 is electrically connected to the source region.

[0093] The additional layer 11 is laid on the surface of the insulating dielectric layer, one end of the additional layer 11 is electrically connected to the polysilicon gate 10, and the other end is electrically connected to the third doping region 8; the additional layer 11 is arranged in a long strip shape and bent. The additional layer 11 is electrically connected between the polysilicon gate 10 and the third doping region 8, which is equivalent to being connected in parallel with the polysilicon gate 10, and plays the role of a parallel resistor.

[0094] The additional layer 11 can be disposed at any position on the surface of the insulating dielectric layer as long as the polysilicon gate 10 is electrically connected to the third doped region 8. The additional layer 11 can be laid in a variety of areas or shapes.

[0095] On the wafer surface, the cross-sectional views of some areas are as follows: Figure 4 , Figure 5 and Figure 6 As shown in FIG. 1 , there are also some areas with only substrate 1 and drift region 2. Figure 4 The cross-sectional area, the insulating dielectric layer can be Figure 4 The gate dielectric layer 9 is laid on the surface of the third dielectric layer 800 .

[0096] Alternatively, the insulating dielectric layer is made of an insulating material different from that of the gate dielectric layer 9 and is laid on the surface of the third dielectric layer 800 .

[0097] Alternatively, in some regions, there are only the substrate 1 and the drift region 2 , and an insulating layer is laid on the upper surface of the drift region 2 as an insulating dielectric layer.

[0098] In summary, the insulating dielectric layer is at least one of the gate dielectric layer 9, the insulating layer formed on the drift region 2, and the insulating layer formed on the third doped region. Insulating dielectric layers are laid in different regions of the wafer in the above manner, and the additional layer 11 is formed on the upper surface of the insulating dielectric layer, which is insulated from the region below the insulating dielectric layer.

[0099] (1) When the gate-source bias voltage Vgs≥threshold voltage (Vth=2V), the potential of the third doping region 8 is about 1V, and the transistor provided in this embodiment is normally turned on.

[0100] (2) When the gate-source bias voltage Vgs≥15V, the potential of the third doping region 8 is about 2.5V, and the transistor provided in this embodiment is normally turned on.

[0101] (3) When the gate-source bias voltage Vgs≤0V and the transistor operates at room temperature, the PN junction formed by the third doping region 8 and the first doping region 6 is zero biased, and the transistor provided in this embodiment is normally turned off.

[0102] (4) When the gate-source bias voltage Vgs=0V and the transistor operates at a high temperature, the additional layer 11 conducts the excess carriers in the third doping region 8 to the gate electrode, and the transistor provided in this embodiment is normally turned off.

[0103] (5) When the gate-source bias voltage Vgs is less than 0 V and the transistor operates at high temperature, the additional layer 11 conducts the excess carriers in the third doping region 8, and the PN junction formed by the third doping region 8 and the first doping region 6 is reverse biased, and the transistor provided in this embodiment is normally turned off.

[0104] In the above technical solution, the basic device is formed with a first doping region, a second doping region and a third doping region arranged in sequence from bottom to top; a gate dielectric layer and a polysilicon gate are formed in sequence on the third doping region; an additional layer is laid on the surface of the gate dielectric layer; one end of the additional layer is electrically connected to the polysilicon gate, and the other end is electrically connected to the third doping region; the additional layer is arranged in a long strip shape. When the gate-source bias voltage Vgs=0V and the transistor works at high temperature, the additional layer conducts the excess carriers in the third doping region to the gate electrode, so that the transistor can be turned off normally. In addition, when the transistor is used as a freewheeling diode of the main tube, the gate source is short-circuited under high temperature conditions, and the blocking voltage of the transistor is the same as that of the main tube.

[0105] Furthermore, this solution makes the voltage division of the equivalent capacitor 201 larger as the proportion of the conduction time of the transistor increases, that is, the voltage division of the equivalent capacitor 202 is smaller, and the potential of the top gate decreases, resulting in the Ids being turned off as the conduction time increases. In addition, the carriers in the third doping region 8 are discharged through the additional layer 11 connected in parallel with the polysilicon gate 10, which reduces the carrier concentration in the third doping region 8, thereby preventing the potential of the third doping region 8 from being raised at high temperature.

[0106] Further, the source region includes: a first source region 7 and a second source region 4, the second source region 4 is located outside the first source region 7, and the depth of the second source region 4 is greater than the depth of the first source region 7; the first source region 7 is of the first doping type, and the second source region 4 is of the second doping type. The source electrode 12 is formed above the source region and is electrically connected to the first source region 7 and the second source region 4, respectively. In addition, a drain electrode 13 is provided on the lower surface of the substrate 1 away from the drift region 2. Further, a buffer layer 100 is also used, formed between the substrate 1 and the drift region 2, which can reduce the defects of the drift region 2, thereby improving the reliability of the transistor.

[0107] The first doping type and the second doping type can be set according to the type of transistor, for example: the first doping type is N-type, and the second doping type is P-type. Specifically, in the above scheme, the drift region 2 is N-type, the well region 3 is P-type, the second source region 4 is P-type, the first doping region 6 is N-type, the first source region 7 is N-type, the second doping region 800 is lightly doped P-type, and the third doping region 8 is heavily doped P-type.

[0108] On the basis of the above technical solution, this embodiment also provides an arrangement of the polysilicon gate 10 and the additional layer 11, such as Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, it is divided into a first part of the polysilicon gate 10a, a second part of the polysilicon gate 10b and a third part of the polysilicon gate 10c. Among them, the first part of the polysilicon gate 10a is located on one side of the transistor, and the second part of the polysilicon gate 10b is located on the other side of the transistor. The first part of the polysilicon gate 10a and the second part of the polysilicon gate 10b are arranged at intervals and both extend along the first direction. One end of the first part of the polysilicon gate 10a and the second part of the polysilicon gate 10b is flush, and the length of the second part of the polysilicon gate 10b is less than the length of the first part of the polysilicon gate 10a. Figure 3 As an example, the upper ends of the first polysilicon gate 10a and the second polysilicon gate 10b are flush with each other, the first polysilicon gate 10a is shorter and located on the left, and the second polysilicon gate 10b is longer and located on the right. The first direction is Figure 3 A gate dielectric layer 9 and a third doped region 8 are provided below each polysilicon gate 10 .

[0109] The third portion of the polysilicon gate 10c and the second portion of the polysilicon gate 10b are located on the same side of the transistor, that is, the third portion of the polysilicon gate 10c and the second portion of the polysilicon gate 10b are both located on Figure 3 The third portion of the polysilicon gate 10c is located on the left side of the second portion of the polysilicon gate 10b, and the third portion of the polysilicon gate 10c is located below the second portion of the polysilicon gate 10b. The additional layer 11 is laid in the area between the third portion of the polysilicon gate 10c and the second portion of the polysilicon gate 10b.

[0110] In one embodiment, the additional layer 11 includes a first connecting segment 111, a second connecting segment 112 and a bending segment, wherein the bending segment is located between the first connecting segment 111 and the second connecting segment 112. The first connecting segment 111 and the second connecting segment 112 both extend along the first direction, the first connecting segment 111 is connected to the third doping region 8 below the second portion of the polysilicon gate 10b, and the second connecting segment 112 is connected to the third portion of the polysilicon 11c. The bending segments may be arranged in a serpentine shape, a spiral shape, or the like.

[0111] A specific method is: the bending section includes: a first bending section 113, a second bending section 114, a third bending section 115, a fourth bending section 116 and a fifth bending section 117 arranged in sequence, the first bending section 113 is connected to the first connecting section 111, and the fifth bending section 117 is connected to the second connecting section 112. The second bending section 114 and the fourth bending section 116 extend along the first direction, and the first bending section 113, the third bending section 115 and the fifth bending section 117 extend along the second direction. The second direction forms a certain angle with the first direction, Figure 3 The second direction is perpendicular to the first direction, that is, the first bending section 113, the third bending section 115 and the fifth bending section 117 are along Figure 3 Extends in left and right directions.

[0112] Specifically, the first bending section 113 extends from the connection point with the first connecting section 111 along the second direction toward the first portion of the polysilicon gate 10a to exceed the third portion of the polysilicon 10c.

[0113] The second bending section 114 extends from the junction with the first bending section 113 along the first direction toward the third portion of the polysilicon gate 10c to the area between the third portion of the polysilicon gate 10c and the first portion of the polysilicon gate 10a.

[0114] The third bending section 115 extends from the junction with the second bending section 114 along the second direction toward the third portion of the polysilicon gate 10 c.

[0115] The fourth bending section 116 extends from the junction with the third bending section 115 toward the second portion of the polysilicon gate 10b to the area between the second portion of the polysilicon gate 10b and the third portion of the polysilicon 10c.

[0116] The fifth bending section 117 extends from the connection with the fourth bending section 116 along the second direction toward a direction away from the first portion of the polysilicon gate 10 a until it is connected to the second connecting section 112 .

[0117] The resistance value of the resistor formed by the additional layer 11 is adjusted by adjusting the width and length of each bending section. In the above scheme, the first part of the polysilicon gate 10a includes three polysilicon gates 10, and the second part of the polysilicon gate 10b includes three polysilicon gates 10. The third part of the polysilicon gate 10c includes a polysilicon gate 10, and its length and width are greater than the polysilicon gates in the first part and the second part.

[0118] This embodiment also provides a structural layout solution. Figure 7 As shown, Figure 7The transistor also includes a first polysilicon gate 10a, a second polysilicon gate 10b and a third polysilicon gate 10c. The first polysilicon gate 10a is located on one side of the transistor, and the second polysilicon gate 10b is located in the middle of the transistor; the first polysilicon gate 10a and the second polysilicon gate 10b are arranged at intervals and both extend along a first direction, and the first direction is Figure 7 The first part of the polysilicon gate 10a and the second part of the polysilicon gate 10b are flush with each other. Figure 7 The tops of the first part of the polysilicon gate 10a and the second part of the polysilicon gate 10b are flush, and the length of the second part of the polysilicon gate 10b is less than the length of the first part of the polysilicon gate 10a, so that the third part of the polysilicon gate 10c is set in the space below the first part of the polysilicon gate 10a, that is, the third part of the polysilicon gate 10c is also located in the middle of the transistor.

[0119] A gate dielectric layer 9 and a third doping layer 8 are disposed below the first portion of the polysilicon gate 10a and the second portion of the polysilicon gate 10b.

[0120] The additional layer 11 is laid on the side of the third polysilicon gate 10c and the second polysilicon gate 10b away from the first polysilicon gate 10a, that is, the additional layer 11 is laid on Figure 7 to the left of the transistor.

[0121] In one embodiment, the additional layer 11 includes a first connecting segment 111, a second connecting segment 112 and a bending segment, wherein the bending segment is located between the first connecting segment 111 and the second connecting segment 112. The first connecting segment 111 and the second connecting segment 112 both extend along the second direction. The first connecting segment 111 is connected to the third doped region 8 below the second portion of the polysilicon gate 10b; the second connecting segment 112 is connected to the third portion of the polysilicon 10c.

[0122] A specific implementation is: the bending segment includes: a first bending segment 113, a second bending segment 114, a third bending segment 115, a fourth bending segment 116, a fifth bending segment 117, a sixth bending segment 118, and a seventh bending segment 119 arranged in sequence, the first bending segment 113 is connected to the first connecting segment 111, and the seventh bending segment 119 is connected to the second connecting segment 112. The first bending segment 113, the third bending segment 115, the fifth bending segment 117, and the seventh bending segment 119 all extend along the first direction, and the second bending segment 114, the fourth bending segment 116, and the sixth bending segment 118 extend along the second direction.

[0123] The second direction is at a certain angle to the first direction. Figure 7 The second direction is perpendicular to the first direction, that is, the second bending segment 114, the fourth bending segment 116 and the sixth bending segment 118 are along Figure 7 Extends in left and right directions.

[0124] Specifically, the first bending section 113 extends from the connection point with the first connecting section 111 along the first direction toward a direction away from the third portion of the polysilicon gate 10 c until reaching the edge of the transistor.

[0125] The second bending section 114 extends from the junction with the first bending section 113 along the second direction away from the second portion of the polysilicon gate 10 b until reaching the edge of the transistor.

[0126] The third bending section 115 extends from the junction with the second bending section 114 along the first direction toward the third portion of the polysilicon gate 10 c.

[0127] The fourth bending section 116 extends from the junction with the third bending section 115 along the second direction toward the second portion of the polysilicon gate 10 b.

[0128] The fifth bending section 117 extends from the junction with the fourth bending section 116 along the first direction toward the third portion of the polysilicon gate 10 c.

[0129] The sixth bending section 118 extends from the junction with the fifth bending section 117 along the second direction toward a direction away from the third portion of the polysilicon gate 10 c until reaching the edge of the transistor.

[0130] The seventh bending section 119 extends from a connection point with the sixth bending section 118 along the first direction to connect with the second connecting section 112 .

[0131] In the above solution, the fourth bending segment 116 , the fifth bending segment 117 , the sixth bending segment 118 , and the seventh bending segment 119 form a curved shape similar to a square wave.

[0132] Or as shown in FIG7, it also includes: an eighth bending segment 120, a ninth bending segment 121, a tenth bending segment 122 and an eleventh bending segment 123. The eighth bending segment 120 extends from the connection with the seventh bending segment 119 along the second direction toward the third portion of the polysilicon gate 10c. The ninth bending segment 121 extends from the connection with the eighth bending segment 120 along the first direction, the tenth bending segment 122 extends from the connection with the ninth bending segment 121 along the second direction toward the direction away from the third portion of the polysilicon gate 10c, and the eleventh bending segment 123 extends from the connection with the tenth bending segment 122 along the first direction to connect with the second connecting segment 112.

[0133] In the above solution, the fourth bending section 116, the fifth bending section 117, the sixth bending section 118, and the seventh bending section 119 form a square wave-like curved shape, and the eighth bending section 120, the ninth bending section 121, the tenth bending section 122, and the eleventh bending section 123 form another square wave-like curved shape. By analogy, when the space is large enough, there can be more square wave-like curved sections.

[0134] Figure 3 and Figure 7 This is only an example, and the additional layer 11 may also have other layout forms.

[0135] Based on the above technical solution, this embodiment also provides a method for manufacturing a field effect transistor. Figures 1 to 7 The structure of the transistor shown in FIG. 1 , the manufacturing method includes:

[0136] Step 1: forming a drift region, a first doping region, a second doping region and a third doping region in sequence on a substrate.

[0137] Specifically, the drift region 2, the first doping region 6, the second doping region 800 and the third doping region 8 are sequentially formed on the upper surface of the substrate 1. The first doping region 6 is of the first doping type, and the second doping region 800 and the third doping region 8 are of the second doping type.

[0138] Before forming the second doping region 800 , a well region 3 is further formed in the first doping region 6 .

[0139] After forming the second doping region 800 , a first source region 7 and a second source region 4 are formed on both sides. The second source region 4 is located outside the first source region 7 , and the depth of the second source region 4 is greater than that of the first source region 7 .

[0140] Step 2: forming a gate dielectric layer on the third doped region.

[0141] Step three: forming a polysilicon gate on the gate dielectric layer.

[0142] Specifically, a gate dielectric layer 9 is formed on the upper surface of the third doping region 8 , and then a polysilicon gate 10 is formed on the upper surface of the gate dielectric layer 9 .

[0143] Step 4: forming an additional layer on the field effect transistor, wherein one end of the additional layer is electrically connected to the polysilicon gate, and the other end of the additional layer is electrically connected to the third doped region.

[0144] The position of the additional layer can be flexibly adjusted for different positions of the field effect transistor, for example, an insulating dielectric layer is provided, the insulating dielectric layer being at least one of a gate dielectric layer, an insulating layer formed on the drift region, and an insulating layer formed on the third doping region.

[0145] An additional layer 11 is formed on the insulating dielectric layer. The additional layer 11 is laid on the surface of the insulating dielectric layer. One end of the additional layer 11 is electrically connected to the polysilicon gate 10, and the other end is electrically connected to the third doped region 8. The laying method of the additional layer 11 can refer to Figure 3 or Figure 7 , as well as the above.

[0146] On the wafer surface, the cross-sectional views of some areas are as follows: Figure 4 , Figure 5 and Figure 6 As shown in FIG. 1 , there are also some areas with only substrate 1 and drift region 2. Figure 4 The cross-sectional area, the insulating dielectric layer can be Figure 4 The gate dielectric layer 9 is laid on the surface of the third dielectric layer 800 .

[0147] Alternatively, the insulating dielectric layer is made of an insulating material different from that of the gate dielectric layer 9 and is laid on the surface of the third dielectric layer 800 .

[0148] Alternatively, in some regions, there are only the substrate 1 and the drift region 2 , and an insulating layer is laid on the upper surface of the drift region 2 as an insulating dielectric layer.

[0149] In summary, the insulating dielectric layer is at least one of the gate dielectric layer 9, the insulating layer formed on the drift region 2, and the insulating layer formed on the third doped region. Insulating dielectric layers are laid in different regions of the wafer in the above manner, and the additional layer 11 is formed on the upper surface of the insulating dielectric layer, which is insulated from the region below the insulating dielectric layer.

[0150] Then, a source electrode 12 is formed on the upper surface of the source region, and a drain electrode 13 is formed on the lower surface of the substrate 1 .

[0151] The above manufacturing method sequentially forms a drift region, a first doping region, a second doping region and a third doping region on the substrate; the first doping region is of the first doping type, and the second doping region and the third doping region are of the second doping type; a gate dielectric layer is formed on the third doping region; a polysilicon gate is formed on the gate dielectric layer; an additional layer is formed on the gate dielectric layer, and the additional layer is laid on the surface of the gate dielectric layer; one end of the additional layer is electrically connected to the polysilicon gate, and the other end is electrically connected to the third doping region. When the gate-source bias voltage Vgs=0V and the transistor is operated at a high temperature, the additional layer guides the excess carriers in the third doping region to the gate electrode, so that the transistor can be turned off normally. In addition, when the transistor is used as a freewheeling diode of the main tube, the gate source is short-circuited under high temperature conditions, and the blocking voltage of the transistor and the main tube is the same. In addition, the carriers in the third doping region 8 are discharged through the additional layer 11 connected in parallel with the polysilicon gate 10, which reduces the carrier concentration in the third doping region 8, thereby preventing the potential of the third doping region 8 from increasing at high temperatures and slowing down the decay of the transistor full-on current Ids over time.

[0152] like Figure 8 As shown, the Vgs of the transistor of the present application is substantially the same as the Vgs of the conventional transistor, maintaining a relatively high voltage drop. The Ids in the conventional solution decreases relatively quickly, while the Ids of the transistor of the present application decays relatively slowly. It can be seen that the transistor obtained by the technical solution provided in this embodiment has relatively good performance.

[0153] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0154] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0155] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0156] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0157] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A field effect transistor, comprising: substrate; A drift region is formed on the substrate, the drift region being of a first doping type; A first doped region formed in the drift region and located at an upper portion of the drift region, the first doped region being of a first doping type; A well region is formed in the first doping region, two adjacent parts of the well region are spaced apart, and the well region is of a second doping type; A second doping region is formed on the first doping region, the second doping region being of a second doping type; a third doping region formed in the second doping region and located on the upper part of the second doping region, the doping concentration of the third doping region being greater than the doping concentration of the second doping region, and the third doping region being of the second doping type; a gate dielectric layer formed on the third doped region; A polysilicon gate formed on the gate dielectric layer; The additional layer has one end electrically connected to the polysilicon gate and the other end electrically connected to the third doping region; source regions are formed on both sides of the third doping region, and the source region and the third doping region are separated by the second doping region.

2. According to the field effect transistor according to claim 1, the additional layer is laid on the surface of the insulating dielectric layer; the insulating dielectric layer is at least one of a gate dielectric layer, an insulating layer formed on the drift region, and an insulating layer formed on the third doping region.

3. The field effect transistor according to claim 1, wherein the source region comprises: a first source region and a second source region, the second source region being located outside the first source region, and the depth of the second source region being greater than the depth of the first source region; The first source region is of a first doping type, and the second source region is of a second doping type.

4. The field effect transistor according to claim 1, further comprising: A buffer layer is formed between the substrate and the drift region. The field effect transistor according to claim 2 , wherein the first doping type is N-type and the second doping type is P-type.

6. A field effect transistor comprising: Basic devices; The basic device is formed with a first doping region, a second doping region and a third doping region arranged in sequence from bottom to top; A gate dielectric layer and a polysilicon gate are sequentially formed on the third doped region; The additional layer has one end electrically connected to the polysilicon gate and the other end electrically connected to the third doped region.

7. According to the field effect transistor of claim 6, the additional layer is laid on the surface of the insulating dielectric layer; the additional layer is arranged in a long strip shape and bent; the insulating dielectric layer is at least one of a gate dielectric layer, an insulating layer formed on the drift region, and an insulating layer formed on the third doping region.

8. The field effect transistor according to claim 7, wherein the first portion of the polysilicon gate is located on one side of the transistor, and the second portion of the polysilicon gate is located on the other side of the transistor; the first portion of the polysilicon gate and the second portion of the polysilicon gate are spaced apart and both extend along the first direction, one end of the first portion of the polysilicon gate and the second portion of the polysilicon gate are flush, and the length of the second portion of the polysilicon gate is less than the length of the first portion of the polysilicon gate; The third portion of the polysilicon gate and the second portion of the polysilicon gate are located on the same side of the transistor; the additional layer is laid between the third portion of the polysilicon gate and the second portion of the polysilicon gate.

9. The field effect transistor of claim 8, the additional layer comprising: A first connecting section, a second connecting section and a bending section, wherein the bending section is located between the first connecting section and the second connecting section; The first connecting section and the second connecting section both extend along the first direction. The first connecting section is connected to the third doping region under the second portion of the polysilicon gate; the second connecting section is connected to the third portion of the polysilicon.

10. The field effect transistor according to claim 7, wherein the first portion of the polysilicon gate is located at one side of the transistor, and the second portion of the polysilicon gate is located in the middle of the transistor; the first portion of the polysilicon gate and the second portion of the polysilicon gate are spaced apart and both extend along the first direction, one end of the first portion of the polysilicon gate and the second portion of the polysilicon gate are flush, and the length of the second portion of the polysilicon gate is less than the length of the first portion of the polysilicon gate; The third part of the polysilicon gate is located in the middle of the transistor; the additional layer is laid on the side of the third part of the polysilicon gate and the second part of the polysilicon gate away from the first part of the polysilicon gate.

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