A bcd process device and method of fabrication

Abstract

This invention belongs to the field of BCD technology and discrete devices, and relates to a BCD process device and its fabrication method, comprising: an N+ substrate and an epitaxial layer N... EPI‑1 and epitaxial layer N EPI‑2 N EPI‑1 and N EPI‑2 The connection point has a PBL area, N EPI‑2 A DP is located on the right side of the PBL area. WELL District; N EPI‑2 DP WELL The left side of the region has an LDMOS N DRIFT District and P WELL‑1 District; N EPI‑2 DP WELL The right side of the region is equipped with the SGT deep trench and P of the SGT-VDMOS. WELL‑2 District; N DRIFT The area is divided into N+ areas; P WELL‑1 The area is divided into N+ area and P+ area; DP WELL The area is divided into P+ area, P WELL‑2 The area is divided into N+ area and P+ area; P WELL‑1 Districts and DPs WELL A gate is provided above the region, P WELL‑2 A metal layer is provided above the region; this invention integrates SGT-VDMOS and VDMOS simultaneously in the same process, and achieves this by fabricating the PBL region and DP region. WELL The SGT-VDMOS and LDMOS are isolated by a partition, so that the integrated BCD process device has the advantages of LDMOS device, which has its gate, source and drain located on the chip surface and is easy to integrate, and the advantages of SGT-VDMOS device, which has high voltage, low resistance and high current.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of BCD process and discrete devices, and relates to a BCD process device and a preparation method. BACKGROUND

[0002] In recent years, power integrated technology has developed rapidly, and the design of power integrated circuits represented by smart power integrated circuits (SPIC) has made great progress.

[0003] In the field of high-voltage SPIC, BCD process is generally used for manufacturing and processing. Due to the limitations of the performance of BCD process devices, including small current, low voltage resistance, and large on-resistance, the development of higher voltage, faster speed, and lower resistance SPIC puts forward higher requirements for devices.

[0004] The power tube of the traditional BCD process is made of a lateral diffused metal oxide semiconductor (LDMOS). Since the LDMOS device itself is a lateral device, the current flows in the lateral direction, and due to the limitation of silicon material itself, the relationship between the resistance and the voltage of the device cannot break the silicon limit. With the continuous expansion of power integrated circuits to higher voltage and larger current application fields, the current and voltage of the traditional LDMOS device are greatly limited, which cannot meet the urgent needs of increasing high-voltage and large-current.

[0005] The double-gate structure of the split gate transistor-vertical diffused metal oxide semiconductor (SGT-VDMOS) device in high-voltage power integrated circuits can adjust the electric field in the drift region of the device, greatly reduce the on-resistance of the device, and can be widely used in various power integrated circuits, and has many advantages. Therefore, the research on the integration of SGT-VDMOS and LDMOS process is of great significance to high-voltage power integrated circuits.

[0006] However, VDMOS has a large difference in process from LDMOS, which is a lateral device. How to integrate SGT-VDMOS devices and VDMOS devices in the same set of processes is a key problem and a difficult problem in power integration. SUMMARY

[0007] To solve the above-mentioned problems in the prior art, the application adopts a BCD process device, which comprises an N+ substrate, an epitaxial layer N EPI-1 and an epitaxial layer N EPI-1 above the epitaxial layer NEPI-2 ;

[0008] Epitaxial layer N EPI-1 and epitaxial layer N EPI-2 A PBL region is located at the left connection point; epitaxial layer N EPI-2 A DP is located on the right side of the PBL area. WELL Region; Epitaxial layer N EPI-2 DP WELL The left side of the region has an LDMOS N DRIFT District and P WELL-1 Region; Epitaxial layer N EPI-2 DP WELL The right side of the region has an SGT deep trench and a P-type SGT-VDMOS. WELL-2 district;

[0009] N DRIFT The region contains N+ regions, P WELL-1 The region is divided into N+ region and P+ region, DP WELL The area includes a P+ area, P WELL-2 The area is divided into N+ and P+ regions from top to bottom; P WELL-1 Districts and DPs WELL The gate of a BCD process device is located above the region, P WELL-2 A metal layer is provided above the area;

[0010] In this context, the N+ substrate serves as the drain of the BCD process device, and the N... DRIFT The N+ region in the region is the source of the BCD process device, N DRIFT P represents the drift region. WELL-1 Indicates the first P-well, P WELL-2 Indicates the second P-well, DP WELL PBL represents a deep P-well, SGT represents a split-gate field-effect transistor, and N+ and P+ represent highly doped N-type and P-type regions, respectively.

[0011] P WELL-1 District and DP WELL There is an STI zone between the zones, and an STI zone is located to the right of the first N+ zone; where STI is shallow trench isolation.

[0012] The metal layer consists of an isolation region and a metal region arranged sequentially from bottom to top; the isolation region and P WELL-2 The N+ region of the zone has a through-hole, and the metal region is connected to the P region through the through-hole. WELL-2 The N+ and P+ regions of the area are connected.

[0013] There are multiple SGT deep grooves, and each SGT deep groove contains a POLY region, a GPOLY region, and an SGPOLY region; P WELL-2The region is set in the area between the deep trenches of the SGT; where POLY, GPOLY and SGPOLY represent polysilicon, gate polysilicon and split gate polysilicon, respectively.

[0014] On the other hand, a method for fabricating a BCD device includes:

[0015] S1. Obtain an N+ substrate and grow an epitaxial layer N on the N+ substrate. EPI-1 ;

[0016] S2, in the epitaxial layer N EPI-1 PBL is injected into the left region to form the PBL area;

[0017] S3, in the epitaxial layer N EPI-1 N epitaxial layer grown on top EPI-2 ;

[0018] S4, in the epitaxial layer N EPI-2 P-type dopant is injected into the middle to form DP. WELL District, in DP WELL Etching a deep SGT trench on the right side of the area;

[0019] S5. Fabricate the SGT gate in the SGT deep trench to form the POLY region, GPOLY region and SGPOLY region;

[0020] S6, in the epitaxial layer N EPI-2 N-type dopant and P-type dopant are implanted into DP respectively. WELL N is formed on the left side of the area DRIFT District and P WELL-1 District, in DP WELL P forms on the right side of the area WELL-2 district;

[0021] S7, in N DRIFT District, P WELL District, P WELL-1 District and P WELL-2 N-type and P-type dopants are injected into the region to form N+ and P+ regions;

[0022] S8, in N DRIFT District and P WELL The gate is grown above the region, in P WELL-2 A metal layer grows on top of the area.

[0023] Before step S7, in N DRIFT Within the area and in P WELL-1 The STI region is etched and grown on the right side of the area.

[0024] Beneficial effects:

[0025] VDMOS devices have a vertical structure, while LDMOS devices have a horizontal structure, making direct integration difficult. Therefore, this invention integrates SGT-VDMOS and LDMOS simultaneously in the same process, and achieves this by fabricating the PBL region and DP region. WELL The SGT-VDMOS and LDMOS are isolated by a partition, so that the integrated BCD process device has the advantages of LDMOS device, which has its gate, source and drain located on the chip surface and is easy to integrate, and the advantages of SGT-VDMOS device, which has high voltage, low resistance and high current. Attached Figure Description

[0026] Figure 1 A structural diagram of a BCD process device integrating SGT-VDMOS and LDMOS provided in an embodiment of the present invention;

[0027] Figure 2 This is a flowchart illustrating a method for fabricating a BCD process device integrating SGT-VDMOS and LDMOS, as provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] like Figure 1 As shown, this embodiment employs a BCD process device, including: an N+ substrate and an epitaxial layer N2 located above the N+ substrate. EPI-1 and located in epitaxial layer N EPI-1 The upper epitaxial layer N EPI-2 ;

[0030] Epitaxial layer N EPI-1 and epitaxial layer N EPI-2 A PBL region is located at the left connection point; epitaxial layer N EPI-2 A DP is located on the right side of the PBL area. WELL Region; Epitaxial layer N EPI-2 DP WELL The left side of the region has an LDMOS N DRIFT District and P WELL-1 Region; Epitaxial layer N EPI-2 DP WELL The right side of the region has an SGT deep trench and a P-type SGT-VDMOS. WELL-2 district;

[0031] In this context, the N+ substrate serves as the drain of the BCD process device, and the N... DRIFTIndicates the drift region; P WELL-1 Indicates the first P-well, P WELL-2 This indicates the second P-well, used to isolate different areas and prevent current leakage; PBL indicates a buried phosphorus layer, DP... WELL It indicates a deep P-well, used to isolate SGT-VDMOS and LDMOS; SGT stands for Split Gate Transistor, used to improve the breakdown voltage and reduce the on-resistance of the device.

[0032] N DRIFT The region includes a first N+ region, which serves as the source of the BCD process device; P WELL-1 The region is divided into three sections from left to right: the second N+ section, the first P+ section, and the third N+ section; DP WELL The area contains a second P+ area, P WELL-2 The area is divided into a fourth N+ area and a fifth P+ area from top to bottom; P WELL-1 Districts and DPs WELL Above the region is the gate of the BCD process device, used to control the flow of current. WELL-2 A metal layer is provided above the area to form electrode contacts and wiring;

[0033] The metal layer has an isolation region and a metal region (MET) arranged sequentially from bottom to top; the isolation region and the fourth N+ region are provided with through holes, and the metal region is connected to the fourth N+ region and the fifth P+ region through the through holes.

[0034] P WELL-1 District and DP WELL There is an STI zone between the zones, and an STI zone is located to the right of the first N+ zone; where STI stands for shallow trench isolation, used to isolate different zones.

[0035] There are four SGT deep trenches, which are arranged sequentially from left to right in the epitaxial layer N. EPI-2 DP in WELL On the right side of the zone, an isolation zone is provided within the SGT deep trench; among them, the leftmost SGT deep trench contains a POLY zone, and the remaining SGT deep trenches contain GPOLY and SGPOLY zones from top to bottom; P WELL-2 The region is set in the area between the deep trenches of the SGT; where POLY, GPOLY and SGPOLY represent polysilicon, gate polysilicon and split gate polysilicon, respectively.

[0036] In one embodiment, a method for fabricating the above-mentioned BCD process device integrating SGT-VDMOS and LDMOS is provided, comprising:

[0037] S1. Obtain an N+ substrate and grow an epitaxial layer N on the N+ substrate. EPI-1 ;

[0038] S2, in the epitaxial layer N EPI-1 PBL is injected into the left region to form the PBL area;

[0039] S3, in the epitaxial layer N EPI-1 N epitaxial layer grown on top EPI-2 ;

[0040] S4, in the epitaxial layer N EPI-2 P-type dopant is injected into the middle to form DP. WELL District, in DP WELL Etching a deep SGT trench on the right side of the area;

[0041] S5. Fabricate the SGT gate in the SGT deep trench to form the POLY region, GPOLY region and SGPOLY region;

[0042] S6, in the epitaxial layer N EPI-2 N-type dopant and P-type dopant are implanted into DP respectively. WELL N is formed on the left side of the area DRIFT District and P WELL-1 District, in DP WELL P forms on the right side of the area WELL-2 District; in N DRIFT Within the area and in P WELL-1 The STI region is etched and grown on the right side of the area, respectively;

[0043] S7, in N DRIFT District, P WELL District, P WELL-1 District and P WELL-2 N-type and P-type dopants are injected into the region to form N+ and P+ regions;

[0044] S8, in N DRIFT District and P WELL The gate is grown above the region, in P WELL-2 A metal layer grows on top of the area.

[0045] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A BCD process device, characterized in that, include: N+ substrate, epitaxial layer N above N+ substrate EPI-1 and located in epitaxial layer N EPI-1 The upper epitaxial layer N EPI-2 ; Epitaxial layer N EPI-1 and epitaxial layer N EPI-2 A PBL region is located at the left connection point; epitaxial layer N EPI-2 A DP is located on the right side of the PBL area. WELL Region; Epitaxial layer N EPI-2 DP WELL The left side of the region has an LDMOS N DRIFT District and P WELL-1 Region; Epitaxial layer N EPI-2 DP WELL The right side of the region is equipped with an SGT deep trench and a P-type SGT-VDMOS. WELL-2 district; N DRIFT The region contains N+ regions, P WELL-1 The region is divided into N+ region and P+ region, DP WELL The area includes a P+ area, P WELL-2 The area is divided into N+ and P+ regions from top to bottom; P WELL-1 Districts and DPs WELL The gate of a BCD process device is located above the region, P WELL-2 A metal layer is provided above the area; In this context, the N+ substrate serves as the drain of the BCD process device, and the N... DRIFT The N+ region in the region is the source of the BCD process device, N DRIFT P represents the drift region. WELL-1 Indicates the first P-well, P WELL-2 Indicates the second P-well, DP WELL PBL represents a deep P-well, SGT represents a split-gate field-effect transistor, N+ and P+ represent highly doped N-type and P-type regions, respectively, LDMOS is a lateral double-diffused metal-oxide-semiconductor, and VDMOS is a vertical double-diffused metal-oxide-semiconductor.

2. A BCD process device according to claim 1, characterized in that, P WELL-1 District and DP WELL There is an STI zone between the zones, and an STI zone is located to the right of the first N+ zone; where STI is shallow trench isolation.

3. A BCD process device according to claim 1, characterized in that, The metal layer consists of an isolation region and a metal region arranged sequentially from bottom to top; the isolation region and P WELL-2 The N+ region of the zone has a through-hole, and the metal region is connected to the P region through the through-hole. WELL-2 The N+ and P+ regions of the area are connected.

4. A BCD process device according to claim 1, characterized in that, There are multiple SGT deep grooves, and each SGT deep groove contains a POLY region, a GPOLY region, and an SGPOLY region; P WELL-2 The region is set in the area between the deep trenches of the SGT; where POLY, GPOLY and SGPOLY represent polysilicon, gate polysilicon and split gate polysilicon, respectively.

5. A method for fabricating a BCD process device as described in any one of claims 1 to 4, characterized in that, include: S1. Obtain an N+ substrate and grow an epitaxial layer N on the N+ substrate. EPI-1 ; S2, in the epitaxial layer N EPI-1 PBL is injected into the left region to form the PBL area; S3, in the epitaxial layer N EPI-1 N epitaxial layer grown on top EPI-2 ; S4, in the epitaxial layer N EPI-2 P-type dopant is injected into the middle to form DP. WELL District, in DP WELL Etching a deep SGT trench on the right side of the area; S5. Fabricate the SGT gate in the SGT deep trench to form the POLY region, GPOLY region and SGPOLY region; S6, in the epitaxial layer N EPI-2 N-type dopant and P-type dopant are implanted into DP respectively. WELL N is formed on the left side of the area DRIFT District and P WELL-1 District, in DP WELL P forms on the right side of the area WELL-2 district; S7, in N DRIFT District, P WELL District, P WELL-1 District and P WELL-2 N-type and P-type dopants are injected into the region to form N+ and P+ regions; S8, in N DRIFT District and P WELL The gate is grown above the region, in P WELL-2 A metal layer grows on top of the area.

6. The method for fabricating a BCD process device according to claim 5, characterized in that, Before step S7, in N DRIFT Within the area and in P WELL-1 The STI region is etched and grown on the right side of the area.

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