Semiconductor element and manufacturing method thereof
By independently forming a separate gate structure above the well region of the semiconductor element, the problem of tip protrusions or inclines at the junction of different thicknesses of the gate dielectric layer in the prior art is solved, and the stability of the gate height and the preset height are achieved.
Patent Information
- Application Number
- CN202311187909.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-14
- Publication Date
- 2025-03-18
AI Technical Summary
During the production process, existing semiconductor components are prone to produce tip protrusions or inclines at the junction of different thicknesses of the gate dielectric layer, resulting in loss of gate height.
Using a separate gate structure, the first and second separate gate structures are independently formed over two well regions separated from each other and electrically identical, consisting of the first and second gate dielectric layers, respectively, and ensuring that the thickness of these gate dielectric layers is different to avoid tip protrusions at the junction.
It effectively prevents the loss of gate height, ensures the preset height of gate electrodes, and reduces mutual interference between different manufacturing processes, avoiding the generation of tip protrusions or bevels.
Smart Images
Figure CN119653853A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a semiconductor element with a drain extended structure and a manufacturing method thereof. Background Art
[0002] Semiconductor devices with drain extension structures, such as N-type channel drain extended metal-oxide-semiconductor (nEDMOS) transistors, can make the output voltage of the drain terminal greater than the input voltage of the source terminal by increasing the drift region of the drain terminal and adjusting the thickness of the gate dielectric layer. They are usually used in potential conversion (levelshifter) circuits in display driving circuits, for example.
[0003] Since the gate dielectric thickness of a typical drain-extended metal-oxide-semiconductor transistor is not uniform, the portion close to the source terminal is thinner than the portion close to the drain terminal. Generally, more than two dielectric material patterning processes are used to form at least two sub-gate dielectric layers with different thicknesses on the substrate, and then the two are combined to form a gate dielectric layer with different thicknesses. Another approach is to first form a dielectric material layer on the substrate, and then use an etching process to reduce the thickness of a portion of the dielectric material layer close to the source terminal to form gate dielectric layers with different thicknesses.
[0004] However, no matter which manufacturing process is used, it is easy to produce a sharp protrusion or a slope at the intersection of different thicknesses of the gate dielectric layer, resulting in a gate height loss problem in the gate electrode subsequently formed on the gate dielectric layer.
[0005] Therefore, there is a need to provide an advanced semiconductor device and a method for manufacturing the same to solve the problems faced by the prior art. Summary of the invention
[0006] One embodiment of the present invention discloses a semiconductor device, comprising: a substrate, a first well region, a second well region, a first gate dielectric layer, a second gate dielectric layer, a first gate electrode, a second gate electrode, a source and a drain. The first well region is located in the substrate and has a first electrical property. The second well region is located in the substrate, separated from the first well region, and has a first electrical property. The first gate dielectric layer is located above the first well region and has a first thickness. The second gate dielectric layer is located above the second well region, separated from the first gate dielectric layer, and has a second thickness, wherein the first thickness is greater than the second thickness. The first gate electrode is located above the first gate dielectric layer. The second gate electrode is located above the second gate dielectric layer and separated from the first gate electrode. The drain is located in the first well region; and the source is located in the second well region.
[0007] Another embodiment of the present invention discloses a method for manufacturing a semiconductor device, the method comprising the following steps: first, forming a first well region with a first electrical property and a second well region with a first electrical property in a substrate, and separating the first well region and the second well region from each other. Then, forming a first gate dielectric layer with a first thickness above the first well region; forming a second gate dielectric layer with a second thickness above the second well region, wherein the first gate dielectric layer and the second gate dielectric layer are separated from each other, and the first thickness is greater than the second thickness. Next, forming a first gate electrode above the first gate dielectric layer; forming a second gate electrode above the second gate dielectric layer, and separating the second gate electrode from the first gate electrode from each other. Subsequently, forming a drain in the first well region; and forming a source in the second well region.
[0008] According to the above embodiments, the present invention provides a semiconductor device with a separated gate structure. The separated gate structure of the semiconductor device includes a first separated gate structure and a second separated gate structure, which are formed independently above two first well regions and second well regions that are separated from each other and have the same electrical properties. Since the first well region and the second well region are isolated by a part of the body region of the substrate, the problem of the second well region near the drain end overlapping with the second separated gate structure near the source end, which leads to a decrease in the drain current, can be prevented.
[0009] In addition, since the first gate dielectric layer and the second gate dielectric layer of the first separated gate structure and the second separated gate structure are respectively formed above the first well region and the second well region separated from each other, the manufacturing processes of the two will not interfere with each other, and therefore no sharp protrusions or inclined surfaces will be generated at the adjacent parts of the two. This can ensure that the first gate electrode and the second gate electrode subsequently formed on the first gate dielectric layer and the second gate dielectric layer have a preset height, and there will be no problem of gate height loss after planarization. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings:
[0011] Figures 1A to 1D A schematic cross-sectional view of a series of manufacturing process structures for manufacturing a semiconductor device according to an embodiment of the present invention;
[0012] FIG. 2A to FIG. 2D A schematic cross-sectional view of a series of manufacturing process structures for manufacturing a semiconductor device according to another embodiment of the present invention;
[0013] Figure 3 A structural cross-sectional view of another semiconductor device according to yet another embodiment of the present invention; and
[0014] Figure 4The figure is a cross-sectional view of the structure of another semiconductor device according to yet another embodiment of the present invention.
[0015] Explanation of symbols
[0016] 100:Semiconductor components
[0017] 101:Semiconductor substrate
[0018] 101A: Native Area
[0019] 102: first well region
[0020] 103: Second well region
[0021] 104: Lightly doped region
[0022] 105: Drain region
[0023] 106: Lightly doped region
[0024] 107: Source region
[0025] 108: Metal silicide layer
[0026] 109: Metal silicide layer
[0027] 110: Shallow Trench Isolation Structure
[0028] 111:Heavily doped area
[0029] 112: Gap wall
[0030] 115: Interlayer plug
[0031] 116: Interlayer plug
[0032] 117: Interposer plug
[0033] 118: Interlayer plug
[0034] 119: Interlayer dielectric layer
[0035] 120: first separation gate structure
[0036] 121: first gate dielectric layer
[0037] 121b: lower surface of the first gate dielectric layer
[0038] 122: first gate electrode
[0039] 124: Metal conductor layer
[0040] 124A: word line
[0041] 124B: bit line
[0042] 124C: Gate wire
[0043] 130: Second separation gate structure
[0044] 131: second gate dielectric layer
[0045] 131b: lower surface of the second gate dielectric layer
[0046] 132: second gate electrode
[0047] 200:Semiconductor components
[0048] 201:Semiconductor substrate
[0049] 201A: Native Area
[0050] 202: first well region
[0051] 203: Second well region
[0052] 204: Lightly doped region
[0053] 205: Drain region
[0054] 206: lightly doped region
[0055] 207: Source region
[0056] 208: Metal silicide layer
[0057] 209: Metal silicide layer
[0058] 211:Heavily doped area
[0059] 212: Gap wall
[0060] 215: Interposer plug
[0061] 216: Interposer plug
[0062] 217: Interposer plug
[0063] 218: Interposer plug
[0064] 219: Interlayer dielectric layer
[0065] 220: first separation gate structure
[0066] 221: first gate dielectric layer
[0067] 221t: upper surface of the first gate dielectric layer
[0068] 222: first gate electrode
[0069] 223: Work function layer
[0070] 224: Metal conductor layer
[0071] 224A: word line
[0072] 224B: bit line
[0073] 224C: Gate wire
[0074] 230: Second separation gate structure
[0075] 231: second gate dielectric layer
[0076] 231t: upper surface of the second gate dielectric layer
[0077] 232: second gate electrode
[0078] 300:Semiconductor components
[0079] 301: Native Area
[0080] 400:Semiconductor components
[0081] 408: Metal silicide layer
[0082] A1: Component area
[0083] A2: Component Area
[0084] A21: Part of the component area
[0085] A22: Partial component area
[0086] H12: Second thickness
[0087] H11: First thickness
[0088] H22: Second thickness
[0089] H21: First thickness
[0090] DNW: n-doped deep well region
[0091] K: Height difference
[0092] G: Distance DETAILED DESCRIPTION
[0093] The present invention provides a semiconductor device with a drain extension structure and a method for forming the same, which can improve the problem of gate electrode height loss caused by the semiconductor device manufacturing process. In order to make the above embodiments and other purposes, features and advantages of the present invention more clearly understandable, a plurality of embodiments are specifically cited below and described in detail with the accompanying drawings.
[0094] However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention may still be implemented using other features, components, methods and parameters. The preferred embodiments are only intended to illustrate the technical features of the present invention and are not intended to limit the claims of the present invention. A person of ordinary skill in the art will be able to make equal modifications and changes based on the description of the following specification without departing from the spirit of the present invention. In different embodiments and drawings, the same components will be represented by the same component symbols.
[0095] Please refer to Figures 1A to 1D , Figures 1A to 1D 1 is a schematic cross-sectional view of a series of manufacturing process structures for manufacturing a semiconductor device 100 according to an embodiment of the present invention. In some embodiments of the present invention, the semiconductor device 100 may be an N-type channel drain extended metal oxide semiconductor including a separated polysilicon gate structure. The method for manufacturing the semiconductor device 100 includes the following steps:
[0096] First, a semiconductor substrate 101 is provided, and a shallow trench isolation structure 110 is formed in the semiconductor substrate 101 to define a device area A1 (eg, Figure 1A In some embodiments of the present invention, the semiconductor substrate 101 may be a silicon substrate (e.g., a silicon wafer) doped with a second electrical property (N-type electrical property). In other embodiments of the present invention, the semiconductor substrate 101 may be a silicon substrate having an n-doped deep well region DNW with a second electrical property (N-type electrical property).
[0097] Next, at least one ion implantation process is used to form a first well region 102 and a second well region 103 having the same electrical property and separated from each other in the semiconductor substrate 101, and a lightly doped region 104 having a second electrical property (e.g., N-type electrical property) is formed in the first well region 102. For example, in this embodiment, the same ion implantation process can be used to simultaneously form the first well region 102 and the second well region 103 having a first electrical property (e.g., P-type electrical property) in the n-doped deep well region DNW (third well region) of the device region A1 of the semiconductor substrate 101; then another ion implantation process is used to form the lightly doped region 104 having a second electrical property (e.g., N-type electrical property) in the first well region 102 of the semiconductor substrate 101. The first well region 102 and the second well region 103 are isolated from each other by a native region 101A which is a part of the semiconductor substrate 101. And the doping concentration of the first well region 102 is less than the doping concentration of the second well region 103.
[0098] However, the steps of forming the first well region 102 and the second well region 103 are not limited thereto. For example, in other embodiments, the first well region 102 and the second well region can be formed respectively by using different ion doping processes. In addition, in some embodiments, another ion doping process can be used to form a heavily doped region 111 having a first electrical property (for example, a P-type electrical property) in the first well region 102 and the second well region 103, respectively. The doping concentration of the heavily doped region 111 is greater than the doping concentration of the first well region 102.
[0099] Then, a first gate dielectric layer 121 having a first thickness H11 is formed above the first well region 102; a second gate dielectric layer 131 having a second thickness H12 is formed above the second well region 103, and the first gate dielectric layer 121 and the second gate dielectric layer 131 are separated from each other, and the first thickness H11 is greater than the second thickness H12. Figure 1B As shown, in this embodiment, the lower surface 121 b of the first gate dielectric layer 121 and the lower surface 131 b of the second gate dielectric layer 131 are substantially flush with each other.
[0100] For example, in some embodiments of the present invention, a first gate dielectric layer 121 and a second gate dielectric layer 131 may be formed respectively above the first well region 102 and the second well region 103 by two different dielectric material deposition and patterning processes. The first gate dielectric layer 121 and the second gate dielectric layer 131 may be a single-layer or multi-layer structure.
[0101] The materials constituting the first gate dielectric layer 121 and the second gate dielectric layer 131 may be the same or different dielectric materials. And these dielectric materials may be selected from, for example, a group consisting of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN) or a high-k material (e.g., hafnium silicon, hafnium oxide, hafnium silicon oxide or hafnium silicon oxynitride) and any combination thereof.
[0102] Next, a first gate electrode 122 is formed on the first gate dielectric layer 121; a second gate electrode 132 is formed on the second gate dielectric layer 131, and the second gate electrode 132 is separated from the first gate electrode 122 (eg, Figure 1CIn some embodiments of the present invention, the formation of the first gate electrode 122 and the second gate electrode 132 includes the following steps: First, a polysilicon layer (not shown) is formed on the device region A1 of the semiconductor substrate 101. Then, the polysilicon layer is patterned, and only a portion of the polysilicon layer located above the first gate dielectric layer 121 and a portion of the polysilicon layer located above the second gate dielectric layer 131 remain, which serve as the first gate electrode 122 and the second gate electrode 132, respectively. The first gate dielectric layer 121 and the first gate electrode 122 stacked vertically constitute the first separation gate structure 120; the second gate dielectric layer 131 and the second gate electrode 132 stacked vertically constitute the second separation gate structure 130.
[0103] Then, a spacer 112 is formed on the sidewalls of the first gate electrode 122 and the second gate electrode 132. The first separation gate structure 120, the second separation gate structure 130 and the spacer 112 are used as masks to perform at least one ion implantation process to form a drain region 105 having a second electrical property (e.g., N-type electrical property) in the lightly doped region 104; and a lightly doped region 106 and a source region 107 having a second electrical property (e.g., N-type electrical property) are formed in the second well region 103. A metal silicide block (SAB) manufacturing process is used to form metal silicide layers 108 and 109 on the drain region 105 and the source region 106, respectively, to serve as contact ends of the drain region 105 and the source region 106, respectively.
[0104] In this example, if Figure 1C As shown, the contact end (metal silicide layer 108) of the drain region 105 is adjacent to the first gate dielectric layer 121 (or adjacent to a portion of the spacer 112 covering the first separation gate structure 120); the contact end (metal silicide layer 109) of the source region 106 is adjacent to the second gate dielectric layer 131 (or adjacent to another portion of the spacer 112 covering the second separation gate structure 130). The doping concentration of the lightly doped regions 104 and 106 having the second electrical property (e.g., N-type electrical property) is substantially greater than the doping concentration of the native region 101A of the semiconductor substrate 101. The material constituting the metal silicide layers 108 and 109 is, for example, cobalt silicide (CoSi2) or nickel silicide (NiSi).
[0105] Subsequently, a series of back-end-of-line (BEOL) processes are performed, such as a metal damascene process, to form an interlayer dielectric (ILDs) 119 covering the device region A1, and to form a metal interconnect structure (including dielectric plugs 115, 116, 117, and 118) in the interlayer dielectric 119, so that the drain region 105, the source region 106, the first gate electrode 122, and the second gate electrode 132 are electrically connected to different wires of the metal wire layer 124, such as the word line 124A, the bit line 124B, and the gate wire 124C, respectively, to form a structure such as Figure 1D A semiconductor device 100 is shown.
[0106] In this example, the first separated gate structure 120 and the second separated gate structure 130 can be connected in parallel to each other through the dielectric plugs 117 and 118 and the gate wire 124C, so that the first separated gate structure 120 and the second separated gate structure 130 have the same gate voltage; and by adjusting the different thicknesses of the first gate dielectric layer 121 and the second gate dielectric layer 131, the output voltage of the drain 105 is greater than the input voltage of the source 106.
[0107] In addition, by isolating the first well region 102 and the second well region 103 through the native region 101A of the semiconductor substrate 101, not only can the distance between the drain region 105 and the source region 106 be extended, further increasing the output voltage of the drain region 105, but also the first gate dielectric layer 121 and the second gate dielectric layer 131 formed respectively above the first well region 102 and the second well region 103 can be isolated from each other. Thus, the mutual interference between different manufacturing processes for preparing the first gate dielectric layer 121 and the second gate dielectric layer 131 with different thicknesses is reduced, and the generation of a sharp protrusion or a slope between the two is prevented, thereby solving the problem of gate height loss of the existing N-type channel drain extension metal-oxide-semiconductor transistor.
[0108] Please refer to FIG. 2A to FIG. 2D , FIG. 2A to FIG. 2D 2 is a schematic cross-sectional view of a series of manufacturing process structures for manufacturing a semiconductor device 200 according to another embodiment of the present invention. In some embodiments of the present invention, the semiconductor device 200 may be an N-type channel drain extended metal oxide semiconductor including a separated metal gate structure. The method for manufacturing the semiconductor device 200 includes the following steps:
[0109] First, a semiconductor substrate 201 is provided, and a shallow trench isolation structure 210 is formed in the semiconductor substrate 201 to define a device area A2 (such as Figure 2A In some embodiments of the present invention, the semiconductor substrate 201 may be a silicon substrate having an n-doped deep well region DNW with a second electrical property (N-type electrical property).
[0110] Next, at least one ion implantation process is used to form a first well region 202 and a second well region 203 having the same electrical property and separated from each other in the semiconductor substrate 201, and a lightly doped region 204 having a second electrical property (e.g., N-type electrical property) is formed in the first well region 202. For example, in this embodiment, the same ion implantation process can be used to simultaneously form the first well region 202 and the second well region 203 having a first electrical property (e.g., P-type electrical property) in the n-doped deep well region DNW (third well region) of the device region A2 of the semiconductor substrate 201; then another ion implantation process is used to form a lightly doped region 204 having a second electrical property (e.g., N-type electrical property) in the first well region 202 of the semiconductor substrate 201. The first well region 202 and the second well region 203 are isolated from each other by a portion of the native region 201A of the semiconductor substrate 201. And the doping concentration of the first well region 202 is less than the doping concentration of the second well region 203. In addition, another ion doping process may be used to form a heavily doped region 211 having a first electrical property (e.g., P-type electrical property) in the first well region 202 and the second well region 203. The doping concentration of the heavily doped region 211 is greater than the doping concentration of the first well region 202 (and the second well region 203).
[0111] Then, a portion of the semiconductor substrate 201 located in the device region A2 is removed by photolithography and etching processes, so that there is a height difference K between the etched portion of the device region A21 and the unetched portion of the device region A22. In this embodiment, the first well region 202 is included in the etched portion of the device region A21; the first well region 202 is included in the unetched portion of the device region A22.
[0112] Then, a first gate dielectric layer 221 having a first thickness H21 is formed above the first well region 202; a second gate dielectric layer 231 having a second thickness H22 is formed above the second well region 203, and the first gate dielectric layer 221 and the second gate dielectric layer 231 are separated from each other, and the first thickness H21 is greater than the second thickness H22. Figure 2B As shown, in this embodiment, the upper surface 221 t of the first gate dielectric layer 221 and the upper surface 231 t of the second gate dielectric layer 231 are substantially flush with each other.
[0113] Next, a replacement metal gate (RMG) process is used to form a first metal gate electrode 222 on the first gate dielectric layer 221; a second metal gate electrode 232 is formed on the second gate dielectric layer 231, and the second metal gate electrode 232 is separated from the first metal gate electrode 222 (as shown in 1C). In some embodiments of the present invention, the formation of the first metal gate electrode 222 and the second metal gate electrode 232 includes the following steps: first, a polysilicon layer (not shown) is formed on the device region A2 of the semiconductor substrate 201, and the polysilicon layer is patterned, leaving only a portion of the polysilicon layer located above the first gate dielectric layer 221 and a portion of the polysilicon layer located above the second gate dielectric layer 231, respectively serving as virtual gate electrodes (not shown).
[0114] Then, a spacer 212 is formed on the sidewall of the virtual gate electrode, and the virtual gate electrode is removed to expose the first gate dielectric layer 221 and the second gate dielectric layer 231. A multilayer structure (barrier layer) work function layer 223 is formed on the first gate dielectric layer 221 and the second gate dielectric layer 231, respectively, and then a first metal gate electrode 222 and a second metal gate electrode 232 are formed on the work function layer 223 to fill the remaining positions after the virtual gate electrode is removed. The first gate dielectric layer 221, a part of the work function layer 223 and the first gate electrode 222 stacked vertically constitute the first separation gate structure 220; the second gate dielectric layer 231, another part of the work function layer 223 and the second gate electrode 232 stacked vertically constitute the second separation gate structure 230.
[0115] Then, at least one ion implantation process is performed using the first separation gate structure 220, the second separation gate structure 230 and the spacer 212 as masks to form a drain region 205 having a second electrical property (e.g., N-type electrical property) in the lightly doped region 204; and a lightly doped region 206 and a source region 207 having a second electrical property (e.g., N-type electrical property) are formed in the second well region 203. A metal silicide barrier layer manufacturing process is used to form metal silicide layers 208 and 209 on the drain region 205 and the source region 206, respectively. Figure 2C As shown, the drain region 205 is adjacent to the first gate dielectric layer 221 (or adjacent to a portion of the spacer 212 covering the first separation gate structure 220); the source region 206 is adjacent to the second gate dielectric layer 131 (or adjacent to another portion of the spacer 212 covering the second separation gate structure 230). In this example, the doping concentration of the lightly doped regions 204 and 206 having the second electrical property (e.g., N-type electrical property) is substantially greater than the doping concentration of the native region 201A of the semiconductor substrate 101.
[0116] Subsequently, a series of back-end manufacturing processes are performed. Through the back-end manufacturing processes, for example, a metal damascene manufacturing process is performed to form an interlayer dielectric layer 219 covering the device area A2, and a metal interconnect structure (including dielectric plugs 215, 216, 217 and 218) is formed in the interlayer dielectric layer 219 to electrically connect the drain region 205, the source region 206, the first metal gate electrode 222 and the second metal gate electrode 232 to different wires of the metal wire layer 224, such as the word line 224A, the bit line 224B and the gate wire 224C, to form a structure as shown in FIG. Figure 2D A semiconductor device 200 is shown.
[0117] In this example, the first separated gate structure 220 and the second separated gate structure 230 can be connected in parallel to each other through the dielectric plugs 217 and 218 and the gate wire 224C, so that the first separated gate structure 220 and the second separated gate structure 230 have the same gate voltage; and by adjusting the different thicknesses of the first gate dielectric layer 221 and the second gate dielectric layer 231, the output voltage of the drain 205 is greater than the input voltage of the source 206.
[0118] In addition, by isolating the first well region 202 and the second well region 203 through the native region 201A of the semiconductor substrate 201, the first gate dielectric layer 221 and the second gate dielectric layer 231 formed above the first well region 202 and the second well region 203 can be isolated from each other. This can not only prevent the problem of the conventional element that the current of the drain 205 decreases due to the overlap of the first well region 202 adjacent to the drain region 205 and the second gate dielectric layer 231 adjacent to the source region 206, but also reduce the mutual interference between different manufacturing processes for preparing the first gate dielectric layer 221 and the second gate dielectric layer 231 with different thicknesses, prevent the generation of a sharp protrusion or a slope between the two, and thus solve the problem of gate height loss of the existing N-type channel drain extension type metal-oxide-semiconductor transistor.
[0119] Figure 3 FIG. 1 is a cross-sectional view of another semiconductor device 300 according to another embodiment of the present invention. Figure 2D The semiconductor device 200 is similar to the semiconductor device 300, except that the semiconductor device 300 further includes a lightly doped region 301 located in the native region 201A of the semiconductor substrate 201, wherein the lightly doped region 301 has a second electrical property (e.g., N-type electrical property) and has a doping concentration greater than the native region 201A (or the n-doped deep well region DNW). In this embodiment, the lightly doped region 301 is substantially equal to the doping concentration of the lightly doped regions 204 and 206. The on-resistance between the drain 205 and the source 206 of the semiconductor device 300 can be further reduced (or the drain current can be increased).
[0120] Figure 4 FIG. 4 is a cross-sectional view of another semiconductor device 400 according to another embodiment of the present invention. Figure 2D The semiconductor device 200 is similar to the semiconductor device 400, except that there is a distance G between the contact end (metal silicide layer 408) of the drain region 205 of the semiconductor device 400 and the first separation gate structure 220, which can effectively reduce the gate induced drain leakage (GIDL) problem caused by the higher electric field of the gate.
[0121] According to the above embodiments, the present invention provides a semiconductor device with a separated gate structure. The separated gate structure of the semiconductor device includes a first separated gate structure and a second separated gate structure, which are formed independently above two first well regions and second well regions that are separated from each other and have the same electrical properties. Since the first well region and the second well region are isolated by a part of the body region of the substrate, the problem of the second well region near the drain end overlapping with the second separated gate structure near the source end, which leads to a decrease in the drain current, can be prevented.
[0122] In addition, since the first gate dielectric layer and the second gate dielectric layer of the first separated gate structure and the second separated gate structure are respectively formed above the first well region and the second well region separated from each other, the manufacturing processes of the two will not interfere with each other, and therefore no sharp protrusions or inclined surfaces will be generated at the adjacent parts of the two. This can ensure that the first gate electrode and the second gate electrode subsequently formed on the first gate dielectric layer and the second gate dielectric layer have a preset height, and there will be no problem of gate height loss after planarization.
[0123] Although the present invention is disclosed in conjunction with the above preferred embodiments, they are not intended to limit the present invention. Any ordinary technician in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the definition of the attached claims.
Claims
1. A semiconductor component, comprising: Base material; A first well region is located in the substrate and has a first electrical property; A second well region is located in the substrate, separated from the first well region, and has the first electrical property; A first gate dielectric layer is located above the first well region and has a first thickness; A second gate dielectric layer, located above the second well region, separated from the first gate dielectric layer, and having a second thickness, wherein the first thickness is greater than the second thickness; a first gate electrode, located above the first gate dielectric layer; A second gate electrode is located above the second gate dielectric layer and is separated from the first gate electrode; A drain electrode is located in the first well region; as well as The source is located in the second well region. 2 . The semiconductor device as claimed in claim 1 , wherein the first well region has a doping concentration lower than that of the second well region. 3 . The semiconductor device as claimed in claim 1 , wherein the first well region and the second well region are isolated from each other by a native region of the substrate. 4 . The semiconductor device as claimed in claim 3 , wherein the first well region and the second well region are both located in a third well region of the substrate, and the native region is located in the third well region. 5 . The semiconductor device as claimed in claim 3 , wherein the third well region and the native region have the second electrical property, and the first well region has a doping concentration greater than that of the native region. 6 . The semiconductor device as claimed in claim 3 , further comprising a lightly doped region located in the native region, wherein the lightly doped region has the second electrical property and has a doping concentration greater than that of the native region. 7 . The semiconductor device as claimed in claim 1 , wherein the first gate dielectric layer and the second gate dielectric layer have substantially flush upper surfaces, and wherein the first gate electrode and the second gate electrode comprise metal. 8 . The semiconductor device as claimed in claim 1 , wherein the first gate dielectric layer and the second gate dielectric layer have substantially flush lower surfaces, and wherein the first gate electrode and the second gate electrode comprise polysilicon. 9 . The semiconductor device as claimed in claim 1 , wherein a contact end of the source is adjacent to the second gate dielectric layer, and a distance exists between a contact end of the drain and the first gate dielectric layer. 10 . The semiconductor device as claimed in claim 1 , further comprising a metal connection line located above the first gate electrode and the second gate electrode to electrically connect the two.
11. A method for manufacturing a semiconductor element, comprising: Forming a first well region having a first electrical property and a second well region having the first electrical property in a substrate, and separating the first well region and the second well region from each other; forming a first gate dielectric layer having a first thickness over the first well region; forming a second gate dielectric layer having a second thickness over the second well region, wherein the first gate dielectric layer and the second gate dielectric layer are separated from each other, and the first thickness is greater than the second thickness; forming a first gate electrode over the first gate dielectric layer; forming a second gate electrode on the second gate dielectric layer so that the second gate electrode is separated from the first gate electrode; forming a drain in the first well region; as well as A source is formed in the second well region.
12. The method for manufacturing a semiconductor element as described in claim 11, wherein before forming the first well region and the second well region, it also includes first forming a third well region with a second electrical property in the substrate, then forming the first well region and the second well region in the third well region, and isolating the first well region and the second well region from each other through a native region with the second electrical property. 13 . The method for manufacturing a semiconductor device as claimed in claim 12 , further comprising forming a lightly doped region having the second electrical property in the native region, wherein the lightly doped region has a doping concentration greater than that of the native region. 14 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein before forming the first gate dielectric layer, the method further comprises forming a lightly doped region having the second electrical property in the first well region. 15 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein before forming the first gate dielectric layer, the method further comprises etching away a portion of the semiconductor substrate so that a height difference exists between the etched portion of the semiconductor substrate and another portion of the semiconductor substrate that is not etched. 16 . The method for manufacturing a semiconductor device as claimed in claim 15 , wherein the formation of the first gate electrode comprises a replacement metal gate (RMG) manufacturing process. 17 . The method for manufacturing a semiconductor device as claimed in claim 11 , further comprising forming a metal connection line above the first gate electrode and the second gate electrode to electrically connect the two. 18 . The method for manufacturing a semiconductor device as claimed in claim 11 , further comprising forming a metal silicide layer on the drain electrode, such that a distance exists between the metal silicide layer and the first gate dielectric layer.