Preparation method of detection substrate, detection substrate and flat panel detector

Abstract

The invention provides a preparation method of a detection substrate, the detection substrate and a flat panel detector, and the method comprises the steps: forming a source and drain electrode layer and a doped semiconductor active layer on a substrate, and the source and drain electrode layer comprises a source electrode region and a drain electrode region; forming a semiconductor active layer, a gate insulating layer and a gate layer above the doped semiconductor active layer, the substrate and the first region of the source and drain layer; the first region is a partial source region or a partial drain region; forming a first insulating protection layer above the gate layer and the first region; forming a photoelectric conversion structure and a first conductive layer over the exposed first region; forming a first flat layer and forming a first via hole in the first flat layer; forming a second conductive layer communicated with the first conductive layer above the first conductive layer; and forming a second insulation protection layer and a second flat layer, and forming a second via hole in the second insulation protection layer and the second flat layer. According to the technical scheme provided by the invention, the preparation cost of the detection substrate can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method for preparing a detection substrate, a detection substrate and a flat panel detector. Background Art

[0002] Flat X-ray Panel Detector (FPXD) based on Thin Film Transistor (TFT) technology is a crucial component in digital imaging technology. It has been widely used in industry, medicine, aviation and other fields due to its advantages such as fast imaging speed, good spatial and density resolution, high signal-to-noise ratio and direct digital output.

[0003] Amorphous silicon a-Si flat panel detectors are indirect flat panel detectors. The scintillator layer converts X-rays into visible light, and then converts the visible light into electrical signals under the action of the photoelectric conversion structure. Finally, the electrical signals are read by thin film transistors and output to display the image.

[0004] When manufacturing a detection substrate for a flat panel detector, a common method currently is to use a 13-photomask process. This preparation method requires 13 photomasks (or called mask plates) in the entire process flow, which makes the preparation cost of the detection substrate relatively high. Summary of the invention

[0005] In view of this, embodiments of the present application provide a method for preparing a detection substrate, a detection substrate, and a flat panel detector, which are used to reduce the preparation cost of the detection substrate.

[0006] In order to achieve the above objectives, in a first aspect, an embodiment of the present application provides a method for preparing a detection substrate, comprising:

[0007] Depositing a first conductive material layer and a doped semiconductor material layer on the substrate in sequence, and forming a source-drain electrode layer and a doped semiconductor active layer by a first photomask process, wherein the source-drain electrode layer includes a source region and a drain region;

[0008] A semiconductor material layer, a first insulating material layer and a second conductive material layer are sequentially covered above the doped semiconductor active layer and the substrate, and a first region of the source and drain layer is exposed by a second photomask process to form a semiconductor active layer, a gate insulating layer and a gate layer; the first region is a partial source region or a partial drain region;

[0009] Depositing a second insulating material layer above the gate layer and the first region, exposing a portion of the first region through a third photomask process, to form a first insulating protection layer;

[0010] Depositing a photoelectric conversion material layer and a third conductive material layer above the first insulating protection layer and the exposed first region, and forming a photoelectric conversion structure and a first conductive layer above the exposed first region using a fourth photomask process;

[0011] forming a first planar layer above the first insulating protection layer and the first conductive layer, and etching the first planar layer above the first conductive layer through a fifth photomask process to form a first via hole;

[0012] forming a fourth conductive material layer at the first via hole and above the first planar layer, removing a portion of the fourth conductive material layer through a sixth photomask process, and forming a second conductive layer above the first conductive layer and connected to the first conductive layer;

[0013] A second insulating protection layer and a second planar layer are sequentially formed above the first planar layer and the second conductive layer, and a second via hole is formed on the second insulating protection layer and the second planar layer by a seventh photomask process.

[0014] In a possible implementation manner of the first aspect, the step of forming the source and drain electrode layers and the doped semiconductor active layer by using a first photomask process includes:

[0015] forming a first patterned photoresist layer on the doped semiconductor material layer;

[0016] Using the first patterned photoresist layer as a mask, the doped semiconductor material layer is dry-etched, and the first conductive material layer is wet-etched to form the source and drain electrode layer and the doped semiconductor active layer.

[0017] In a possible implementation manner of the first aspect, a projection range of the semiconductor active layer located between the source region and the drain region on the base substrate is located within a projection range of the gate layer on the base substrate.

[0018] In a possible implementation manner of the first aspect, exposing the first region of the source and drain layer by a second photomask process to form a semiconductor active layer, a gate insulating layer, and a gate layer includes:

[0019] forming a second patterned photoresist layer over the second conductive material layer;

[0020] Using the second patterned photoresist layer as a mask, wet-etching the second conductive material layer, dry-etching the first insulating material layer, and dry-etching the semiconductor material layer are performed to form the semiconductor active layer, the gate insulating layer, and the gate layer.

[0021] In a possible implementation of the first aspect, the photoelectric conversion structure is a PIN structure.

[0022] In a possible implementation manner of the first aspect, depositing a photoelectric conversion material layer and a third conductive material layer on the first insulating protection layer and the exposed first region includes:

[0023] Sequentially forming a P-type semiconductor material layer, a low-doped intrinsic semiconductor layer, and an N-type semiconductor material layer above the first insulating protection layer and the exposed first region;

[0024] A third conductive material layer is deposited above the N-type semiconductor material layer.

[0025] In a possible implementation of the first aspect, the first conductive material layer, the second conductive material layer, the third conductive material layer, and the fourth conductive material layer are all formed by a physical vapor deposition process.

[0026] The doped semiconductor material layer, the semiconductor material layer, the first insulating material layer, the second insulating material layer, the photoelectric conversion material layer, the first planarization layer, the second insulating protection layer and the second planarization layer are all formed by a chemical vapor deposition process.

[0027] In a possible implementation manner of the first aspect, the material of the first conductive layer includes one or more of indium tin oxide, fluorine-doped tin oxide, copper, aluminum and silver;

[0028] The material of the second conductive layer is indium tin oxide or fluorine-doped tin oxide.

[0029] In a second aspect, an embodiment of the present application provides a detection substrate, wherein the detection substrate is prepared based on the method described in the first aspect or any embodiment of the first aspect.

[0030] In a third aspect, an embodiment of the present application provides a flat panel detector, comprising the detection substrate described in the second aspect.

[0031] The embodiments of the present application provide a method for preparing a detection substrate, a detection substrate, and a flat-panel detector, wherein the method for preparing the detection substrate comprises: depositing a first conductive material layer and a doped semiconductor material layer on a base substrate in sequence, and using a first mask process to form a source-drain layer and a doped semiconductor active layer, wherein the source-drain layer comprises a source region and a drain region; sequentially covering a semiconductor material layer, a first insulating material layer, and a second conductive material layer above the doped semiconductor active layer and the base substrate, exposing a first region of the source-drain layer through a second mask process to form a semiconductor active layer, a gate insulating layer, and a gate layer; the first region is a portion of the source region or a portion of the drain region; depositing a second insulating material layer above the gate layer and the first region, exposing a portion of the first region through a third mask process to form a first insulating protective layer; protective layer; depositing a photoelectric conversion material layer and a third conductive material layer above the first insulating protective layer and the exposed first area, and using a fourth mask process to form a photoelectric conversion structure and a first conductive layer above the exposed first area; forming a first flat layer above the first insulating protective layer and the first conductive layer, and etching the first flat layer above the first conductive layer through a fifth mask process to form a first via hole; forming a fourth conductive material layer at the first via hole and above the first flat layer, removing part of the fourth conductive material layer through a sixth mask process, and forming a second conductive layer connected to the first conductive layer above the first conductive layer; forming a second insulating protective layer and a second flat layer in sequence above the first flat layer and the second conductive layer, and using a seventh mask process to form a second via hole on the second insulating protective layer and the second flat layer. Compared with the prior art that requires 13 mask processes to prepare the detection substrate, the technical solution provided by the present application can realize the preparation of the detection substrate with only seven mask processes, which can reduce the use of masks and thus reduce the preparation cost of the detection substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a method for preparing a detection substrate provided in an embodiment of the present application;

[0033] Figures 2A to 2M A schematic diagram of the preparation process of the detection substrate provided in an embodiment of the present application.

[0034] Description of reference numerals:

[0035] 101 - substrate; 102 - first conductive material layer; 1021 - source and drain layer; 103 - doped semiconductor material layer; 1031 - doped semiconductor active layer; 104 - first patterned photoresist layer;

[0036] 105-semiconductor material layer; 1051-semiconductor active layer; 106-first insulating material layer; 1061-gate insulating layer; 107-second conductive material layer; 1071-gate layer; 108-second patterned photoresist layer;

[0037] 109 - a second insulating material layer; 1091 - a first insulating protection layer; 110 - a third patterned photoresist layer;

[0038] 111-photoelectric conversion structure; 1111-P-type semiconductor material layer; 1112-low-doped intrinsic semiconductor layer; 1113-N-type semiconductor material layer; 112-third conductive material layer; 1121-first conductive layer; 113-fourth patterned photoresist layer;

[0039] 114-first planar layer; 1141-first via hole; 115-fifth patterned photoresist layer;

[0040] 116 - a fourth conductive material layer; 1161 - a second conductive layer; 117 - a sixth patterned photoresist layer; 118 - a second insulating protection layer; 119 - a second planarization layer. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0042] Figure 1 A schematic diagram of a method for preparing a detection substrate provided in an embodiment of the present application, Figures 2A to 2M Schematic diagram of the preparation process of the detection substrate provided in the embodiment of the present application. Figures 1 to 2M As shown, the method may include the following steps:

[0043] Step S110: depositing a first conductive material layer and a doped semiconductor material layer on the substrate in sequence, and forming a source-drain electrode layer and a doped semiconductor active layer by a first photomask process.

[0044] like Figure 2A As shown, when preparing the detection substrate, first, a base substrate 101 can be provided. The base substrate 101 can be a glass substrate, a plastic flexible substrate, a silicon substrate, etc. If the material of the base substrate 101 is a conductive material, in order to improve the reliability of the detection substrate, a layer of insulating material can be formed on the upper surface of the base substrate 101 to reduce the occurrence of short circuits. In some embodiments, the base substrate 101 can also be cleaned to improve the adhesion between the base substrate 101 and the subsequent film layer.

[0045] After providing the base substrate 101, a physical vapor deposition process or a sputtering process may be used to sequentially form a first conductive material layer 102 on the base substrate 101, and the film thickness may be 3000-6000 angstroms. The material of the first conductive material layer 102 may be one or more of copper, aluminum or molybdenum, etc., so that it may have good electrical conductivity and thermal conductivity. The first conductive material layer 102 may also be made of an alloy.

[0046] In some embodiments, the first conductive material layer 102 may also be a stacked structure. For example, the first conductive material layer 102 may be formed in two steps, including a first sub-conductive material layer and a second sub-conductive material layer stacked from bottom to top. The material of the first sub-conductive material layer may be molybdenum, and the material of the second sub-conductive material layer may be copper, so that the etching difficulty of the second sub-conductive material layer may be less than that of the first sub-conductive material layer, thereby reducing the occurrence of undercutting or hollowing after etching, and the subsequent occurrence of deposition line breaks.

[0047] After forming the first conductive material layer 102, a chemical vapor deposition process may be used to deposit a doped semiconductor material layer 103 on the first conductive material layer 102. The doped semiconductor material layer 103 may be made of phosphorus-doped amorphous silicon (a-Si), and the thickness of the film may be 300-700 angstroms.

[0048] A coating process can be used to coat photoresist on the doped semiconductor material layer 103, and the film thickness can be 4000-7000 angstroms. The photoresist can be a positive photoresist, that is, light is irradiated onto the photoresist through the gaps of the mask, and the exposed part undergoes a photochemical reaction and can be removed by the developer in the development stage, while the unexposed part maintains the original thickness and structure.

[0049] For ease of explanation, the present application embodiment uses a positive photoresist as an example for illustration. Of course, in some embodiments, the photoresist may also be a negative photoresist, that is, the exposed portion is retained and the unexposed portion can be removed in the development stage.

[0050] After coating the photoresist, the photoresist may be baked to reduce the solvent content of the photoresist layer, thereby improving the adhesion between the photoresist and the doped semiconductor material layer 103, so that the photoresist can better protect the doped semiconductor material layer 103 in the covered area.

[0051] In the embodiment of the present application, the mask can be a conventional mask with a full light-shielding area and a full light-transmitting area to reduce the manufacturing cost. The doped semiconductor material layer 103 and the first conductive material layer 102 are processed in sequence using a first mask process. Specifically, the photoresist is patterned using a first mask to form a first patterned photoresist layer 104, exposing the doped semiconductor material layer 103 in the target area, wherein the target area refers to the area to be etched, and the patterning process may include but is not limited to exposure, development, and drying.

[0052] See also Figure 2B , using the first patterned photoresist layer 104 as a mask, dry etching is performed on the doped semiconductor material layer 103, and wet etching is performed on the first conductive material layer 102, thereby forming a source-drain electrode layer 1021 and a doped semiconductor active layer 1031, wherein the source-drain electrode layer 1021 includes a source region and a drain region. Then, the first patterned photoresist layer 104 can be removed by soaking and washing with a photoresist removal liquid to reduce costs. In some embodiments, the first patterned photoresist layer 104 can also be removed by ashing treatment to increase the removal rate of the first patterned photoresist layer 104.

[0053] Step S120, sequentially covering the semiconductor material layer, the first insulating material layer and the second conductive material layer above the doped semiconductor active layer and the base substrate, exposing the first region of the source and drain layer through a second mask process, to form a semiconductor active layer, a gate insulating layer and a gate layer.

[0054] See also Figure 2C , a semiconductor material layer 105, a first insulating material layer 106, and a second conductive material layer 107 may be sequentially covered on the doped semiconductor active layer 1031 and the base substrate 101. The semiconductor material layer 105 and the first insulating material layer 106 may be formed by a chemical vapor deposition process, and the second conductive material layer 107 may be formed by a physical vapor deposition process or a sputtering process.

[0055] The material of the semiconductor material layer 105 can be amorphous silicon material, and the film thickness can be 1000-2000 angstroms. The material of the first insulating material layer 106 can be silicon nitride (Si3N4) or silicon dioxide (SiO2). Taking the material of the first insulating material layer 106 as Si3N4 as an example, the film thickness can be 2000-4000 angstroms. The second conductive material layer 107 can be one or more of copper, aluminum or molybdenum, and the film thickness can be 3000-6000 angstroms.

[0056] The second conductive material layer 107, the first insulating material layer 106 and the semiconductor material layer 105 can be processed in sequence by using a second photomask process. For example, a photoresist is coated on the second conductive material layer 107, and then the photoresist can be patterned by using a second mask to form a second patterned photoresist layer 108.

[0057] Using the second patterned photoresist layer 108 as a mask, the second conductive material layer 107 in the target area is wet etched, and the first insulating material layer 106, the semiconductor material layer 105 and the doped semiconductor active layer 1031 are dry etched to expose the first area of ​​the source and drain layer 1021, thereby forming a semiconductor active layer 1051, a gate insulating layer 1061 and a gate layer 1071. The first area is Figure 2D The region above the source-drain layer 1021 that is not covered by the doped semiconductor active layer 1031 may be a portion of the source region or a portion of the drain region. This application is described by taking the first region as a portion of the drain region as an example. Afterwards, the second patterned photoresist layer 108 may be removed. Figure 2D .

[0058] It should be noted that the projection range of the semiconductor active layer 1051 located between the source region and the drain region on the base substrate 101 is within the projection range of the gate layer 1071 on the base substrate 101, so that the gate layer 1071 can block external visible light from irradiating to the semiconductor active layer 1051, prevent the leakage current from increasing, and thereby improve the reliability of the detection substrate.

[0059] Step S130 , depositing a second insulating material layer above the gate layer and the first region, exposing a portion of the first region through a third photomask process, and forming a first insulating protection layer.

[0060] See also Figure 2E A second insulating material layer 109 may be formed on the gate layer 1071 and the exposed first region by chemical vapor deposition, and the material may be SiNx, and the film thickness may be 2000-4000 angstroms. A photoresist is coated on the second insulating material layer 109, and then a third mask plate may be used for patterning to form a third patterned photoresist layer 110.

[0061] The exposed second insulating material layer 109 is dry-etched using the third patterned photoresist layer 110 as a mask to expose a portion of the first region and form a first insulating protection layer 1091. The third patterned photoresist layer 110 may then be removed. Figure 2F .

[0062] Step S140 , depositing a photoelectric conversion material layer and a third conductive material layer above the first insulating protection layer and the exposed first region, and forming a photoelectric conversion structure and a first conductive layer above the exposed first region using a fourth photomask process.

[0063] The photoelectric conversion structure may be a PIN structure or a PN structure. By way of example, the following is an exemplary description taking the photoelectric conversion structure as a PIN structure as an example.

[0064] See also Figure 2G and Figure 2H When preparing the photoelectric conversion structure 111, a chemical vapor deposition process can be used to sequentially form a P-type semiconductor material layer 1111, a low-doped intrinsic semiconductor layer 1112, and an N-type semiconductor material layer 1113 on the first insulating protection layer 1091 and the exposed first region. The film thickness of the photoelectric conversion structure 111 can be 8000-12000 angstroms.

[0065] After forming the N-type semiconductor material layer 1113, a physical vapor deposition process can be used to form a third conductive material layer 112 on the N-type semiconductor material layer 1113. The material can be a transparent conductive material, such as indium tin oxide or fluorine-doped tin oxide, and of course, it can also be one of metal materials such as copper, aluminum and silver, and the film thickness can be 500-1000 angstroms. A photoresist is coated on the third conductive material layer 112, and patterning is performed through a fourth mask to form a fourth patterned photoresist layer 113.

[0066] Using the fourth patterned photoresist layer 113 as a mask, the third conductive material layer 112 is first wet-etched, and then the N-type semiconductor material layer 1113, the low-doped intrinsic semiconductor layer 1112, and the P-type semiconductor material layer 1111 are sequentially dry-etched, thereby forming a photoelectric conversion structure 111 and a first conductive layer 1121 above the exposed first region. The fourth patterned photoresist layer 113 can then be removed.

[0067] Step S150 , forming a first planar layer above the first insulating protection layer and the first conductive layer, and etching the first planar layer above the first conductive layer through a fifth photomask process to form a first via hole.

[0068] See also Fig.2I After forming the first conductive layer 1121, a first flat layer 114 may be formed on the first insulating protection layer 1091 and the first conductive layer 1121 to ensure that subsequent film layers can be fabricated on a flat surface. The film layer thickness may be 24,000-28,000 angstroms.

[0069] A photoresist is coated on the first planar layer 114 , the film thickness of which may be 4000-7000 angstroms, and patterned through a fifth mask to form a fifth patterned photoresist layer 115 , thereby exposing a portion of the first planar layer 114 above the first conductive layer 1121 .

[0070] Then, the exposed first planar layer 114 may be etched by dry etching to form a first via hole 1141, and then the fifth patterned photoresist layer 115 may be removed. Figure 2J .

[0071] Step S160, forming a fourth conductive material layer at the first via hole and above the first planar layer, removing a portion of the fourth conductive material layer through a sixth photomask process, and forming a second conductive layer above the first conductive layer and connected to the first conductive layer.

[0072] See also Figure 2K After forming the first via hole 1141, a physical vapor deposition process can be used to deposit a conductive material on the first via hole 1141 and the first flat layer 114 to form a fourth conductive material layer 116. The fourth conductive material layer 116 can be made of a transparent conductive material, such as indium tin oxide or fluorine-doped tin oxide, which can improve the light transmittance of the photoelectric conversion structure 111, thereby reducing light loss and further reducing the power consumption of the detection substrate. The film thickness of the fourth conductive material layer 116 can be 500-1000 angstroms. A photoresist is coated on the fourth conductive material layer 116, and then the photoresist can be patterned to form a sixth patterned photoresist layer 117.

[0073] The sixth patterned photoresist layer 117 is used as a mask, and a portion of the fourth conductive material layer 116 is removed by wet etching, and a second conductive layer 1161 is formed in a corresponding area above the first conductive layer 1121. The second conductive layer 1161 is connected to the first conductive layer 1121 through the first via 1141, and then the sixth patterned photoresist layer 117 is removed. Figure 2L .

[0074] Step S170 , forming a second insulating protection layer and a second planar layer in sequence on the first planar layer and the second conductive layer, and forming a second via hole on the second insulating protection layer and the second planar layer by using a seventh photomask process.

[0075] A second insulating protective layer 118 and a second flat layer 119 are sequentially deposited on the first flat layer 114 and the second conductive layer 1161 by a chemical vapor deposition process. The second insulating protective layer 118 may have a film thickness of 2000-4000 angstroms and may be made of SiNx. The second flat layer 119 may have a film thickness of 18000-24000 angstroms and may be made of the same material as the first flat layer 114.

[0076] A photoresist may be coated on the second flat layer 119, and the thickness of the film layer may refer to the above. The photoresist is patterned through the seventh mask to form a seventh patterned photoresist layer (not shown). The second flat layer 119 and the second insulating protective layer 118 are etched in sequence by dry etching, and a second via (not shown) may be formed in the second flat layer 119 and the second insulating protective layer 118. The second via may be an opening for the terminal area, and exposes the metal point for binding, so as to facilitate subsequent preparation, such as connecting a flexible circuit board. Afterwards, the seventh patterned photoresist layer is removed.

[0077] It can be understood that in the embodiments of the present application, the film thickness, deposition rate, deposition time, etching gas for dry etching and etching solution for wet etching of each film layer can be selected according to actual needs, and the embodiments of the present application do not impose any special restrictions on this.

[0078] The embodiment of the present application provides a method for preparing a detection substrate, comprising: depositing a first conductive material layer and a doped semiconductor material layer on a substrate in sequence, and using a first mask process to form a source-drain layer and a doped semiconductor active layer, wherein the source-drain layer includes a source region and a drain region; sequentially covering a semiconductor material layer, a first insulating material layer, and a second conductive material layer above the doped semiconductor active layer and the substrate, exposing a first region of the source-drain layer through a second mask process to form a semiconductor active layer, a gate insulating layer, and a gate layer; the first region is a portion of the source region or a portion of the drain region; depositing a second insulating material layer above the gate layer and the first region, exposing a portion of the first region through a third mask process to form a first insulating protective layer; between the first insulating protective layer and A photoelectric conversion material layer and a third conductive material layer are deposited above the exposed first area, and a photoelectric conversion structure and a first conductive layer are formed above the exposed first area by a fourth photomask process; a first flat layer is formed above the first insulating protection layer and the first conductive layer, and the first flat layer above the first conductive layer is etched by a fifth photomask process to form a first via hole; a fourth conductive material layer is formed at the first via hole and above the first flat layer, and a portion of the fourth conductive material layer is removed by a sixth photomask process to form a second conductive layer connected to the first conductive layer above the first conductive layer; a second insulating protection layer and a second flat layer are sequentially formed above the first flat layer and the second conductive layer, and a second via hole is formed on the second insulating protection layer and the second flat layer by a seventh photomask process.

[0079] Compared with the prior art, the technical solution provided in the present application can realize the preparation of the detection substrate with only seven photomask processes, which can not only reduce the use of masks, thereby reducing the preparation cost of the detection substrate, but also reduce the process complexity, thereby improving product yield.

[0080] Those skilled in the art will appreciate that the above embodiments are exemplary and are not intended to limit the present application. Where possible, the execution order of one or more of the above steps may be adjusted, or may be selectively combined to obtain one or more other embodiments. Those skilled in the art may select and combine any of the above steps as needed, and all those that do not depart from the essence of the present application fall within the scope of protection of the present application.

[0081] Based on the same inventive concept, as an implementation of the above method, the present application embodiment provides a detection substrate. Figure 2M As shown, the detection substrate may include:

[0082] A source-drain electrode layer and a doped semiconductor active layer are formed on the substrate, wherein the source-drain electrode layer includes a source region and a drain region;

[0083] A semiconductor active layer, a gate insulating layer, and a gate layer are formed on the doped semiconductor active layer;

[0084] A first insulating protection layer is formed on the gate layer and the first region, wherein the first region is a portion of the source region or a portion of the drain region;

[0085] forming a photoelectric conversion structure and a first conductive layer over the first region;

[0086] A first flat layer is formed above the first insulating protection layer and the first conductive layer, wherein the first flat layer is provided with a first via hole;

[0087] A second conductive layer is formed in a corresponding area above the first area, and the second conductive layer is connected to the first conductive layer through a first via hole;

[0088] A second insulating protection layer and a second planar layer are formed on the first planar layer and the second conductive layer, and second via holes are formed in the second insulating protection layer and the second planar layer.

[0089] It should be noted that the preparation method of the detection substrate corresponds to the aforementioned method embodiment. For ease of reading, the details of the aforementioned method embodiment will not be repeated here one by one.

[0090] Based on the same inventive concept, the embodiment of the present application further provides a flat panel detector. The flat panel detector includes the above-mentioned detection substrate.

[0091] The naming or numbering of the steps in this application does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The named or numbered process steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved.

[0092] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0093] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0094] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0095] In the description of this application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0096] Furthermore, in the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0097] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0098] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0099] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a detection substrate, characterized in that: include: Depositing a first conductive material layer and a doped semiconductor material layer on the substrate in sequence, and forming a source-drain electrode layer and a doped semiconductor active layer by a first photomask process, wherein the source-drain electrode layer includes a source region and a drain region; A semiconductor material layer, a first insulating material layer and a second conductive material layer are sequentially covered above the doped semiconductor active layer and the substrate, and a first region of the source and drain layer is exposed by a second photomask process to form a semiconductor active layer, a gate insulating layer and a gate layer; the first region is a partial source region or a partial drain region; Depositing a second insulating material layer above the gate layer and the first region, exposing a portion of the first region through a third photomask process, to form a first insulating protection layer; Depositing a photoelectric conversion material layer and a third conductive material layer above the first insulating protection layer and the exposed first region, and forming a photoelectric conversion structure and a first conductive layer above the exposed first region using a fourth photomask process; forming a first planar layer above the first insulating protection layer and the first conductive layer, and etching the first planar layer above the first conductive layer through a fifth photomask process to form a first via hole; forming a fourth conductive material layer at the first via hole and above the first planar layer, removing a portion of the fourth conductive material layer through a sixth photomask process, and forming a second conductive layer above the first conductive layer and connected to the first conductive layer; A second insulating protection layer and a second planar layer are sequentially formed above the first planar layer and the second conductive layer, and a second via hole is formed on the second insulating protection layer and the second planar layer by a seventh photomask process.

2. The method according to claim 1, characterized in that The method of forming the source and drain electrode layer and the doped semiconductor active layer by using the first photomask process includes: forming a first patterned photoresist layer on the doped semiconductor material layer; Using the first patterned photoresist layer as a mask, the doped semiconductor material layer is dry-etched, and the first conductive material layer is wet-etched to form the source and drain electrode layer and the doped semiconductor active layer.

3. The method according to claim 1, characterized in that The projection range of the semiconductor active layer located between the source region and the drain region on the base substrate is located within the projection range of the gate layer on the base substrate.

4. The method according to claim 1, characterized in that: The method of exposing the first region of the source and drain electrode layer by a second photomask process to form a semiconductor active layer, a gate insulating layer and a gate layer comprises: forming a second patterned photoresist layer over the second conductive material layer; Using the second patterned photoresist layer as a mask, wet-etching the second conductive material layer, dry-etching the first insulating material layer, and dry-etching the semiconductor material layer are performed to form the semiconductor active layer, the gate insulating layer, and the gate layer.

5. The method according to claim 1, characterized in that The photoelectric conversion structure is a PIN structure.

6. The method according to claim 5, characterized in that The step of depositing a photoelectric conversion material layer and a third conductive material layer on the first insulating protection layer and the exposed first region comprises: Sequentially forming a P-type semiconductor material layer, a low-doped intrinsic semiconductor layer, and an N-type semiconductor material layer above the first insulating protection layer and the exposed first region; A third conductive material layer is deposited above the N-type semiconductor material layer.

7. The method according to claim 1, characterized in that The first conductive material layer, the second conductive material layer, the third conductive material layer and the fourth conductive material layer are all formed by a physical vapor deposition process. The doped semiconductor material layer, the semiconductor material layer, the first insulating material layer, the second insulating material layer, the photoelectric conversion material layer, the first planarization layer, the second insulating protection layer and the second planarization layer are all formed by a chemical vapor deposition process.

8. The method according to any one of claims 1 to 7, characterized in that: The material of the first conductive layer includes one or more of indium tin oxide, fluorine-doped tin oxide, copper, aluminum and silver; The material of the second conductive layer is indium tin oxide or fluorine-doped tin oxide.

9. A detection substrate, characterized in that: The detection substrate is prepared based on the method according to any one of claims 1-8.

10. A flat panel detector, characterized in that: Comprising the detection substrate as claimed in claim 9.

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