Array substrate, manufacturing method thereof and display device

Abstract

The application is suitable for the technical field of display devices, and provides an array substrate, a manufacturing method thereof and a display device, wherein the manufacturing method of the array substrate comprises the following steps: forming a thin film transistor, a first insulating layer and a first conductive layer which are sequentially and layerwisely arranged on a substrate; and patterning the first conductive layer by using a half-tone mask plate, wherein the half-tone mask plate comprises a half-shading part, and the orthographic projection of the thin film transistor on the substrate is located in the orthographic projection of the half-shading part on the substrate. By patterning the first conductive layer by using the half-tone mask plate, the half-shading part of the half-tone mask plate is used to cover the surface at the position of the thin film transistor, the half-shading part of the half-tone mask plate can play a certain shading role on the thin film transistor, and meanwhile, the photoresist can be exposed. Compared with the manufacturing method in the related art, the application does not need to additionally set a shading layer for the thin film transistor, thereby saving the processing procedure and reducing the processing and manufacturing cost.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display devices, and particularly relates to an array substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0002] With the development of technology, electronic paper display devices have gradually integrated into people's daily life. Electronic paper display devices have the advantages of convenient reading, convenient carrying, resource saving, low energy consumption, fast transmission speed, and thus have broad development prospects.

[0003] The electronic paper display device at least includes an array substrate. In the related art, in the manufacturing process of the array substrate of the electronic paper display device, a light shielding layer needs to be separately provided for a thin film transistor in the array substrate to improve the stability thereof, and the manufacturing process is complex and the cost is high. SUMMARY

[0004] Therefore, the present application provides an array substrate, a manufacturing method thereof, and a display device to solve the problem that a light shielding layer needs to be separately provided for a thin film transistor in the array substrate to improve the stability thereof, and the manufacturing process is complex and the cost is high.

[0005] A first aspect of the present application provides a manufacturing method of an array substrate, comprising: forming a thin film transistor, a first insulating layer and a first conductive layer which are sequentially stacked on a substrate; and patterning the first conductive layer by using a half-tone mask plate, wherein the half-tone mask plate comprises a half-shading part, and a normal projection of the thin film transistor on the substrate is located within a normal projection of the half-shading part on the substrate.

[0006] In one embodiment, the patterning of the first conductive layer by using the half-tone mask plate specifically comprises: disposing a photoresist layer on the first conductive layer; exposing and developing the photoresist layer by using the half-tone mask plate; etching the first conductive layer; and removing the photoresist layer.

[0007] In one embodiment, the photoresist layer comprises a first photoresist layer and a second photoresist layer which are connected to each other, the normal projection of the thin film transistor on the substrate is located within a normal projection of the first photoresist layer on the substrate, and the removing of the photoresist layer specifically comprises: removing the first photoresist layer; performing surface treatment on the first conductive layer; and removing the second photoresist layer.

[0008] In one embodiment, in a direction perpendicular to the surface of the substrate, the thickness dimension of the first photoresist layer is smaller than the thickness dimension of the second photoresist layer.

[0009] In one embodiment, the surface treatment of the first conductive layer specifically comprises: bombarding the surface of the first conductive layer by using plasma.

[0010] In one embodiment, the plasma comprises hydrogen ions.

[0011] In one embodiment, the first conductive layer is made of a light-transmitting material.

[0012] In one embodiment, the material for making the first conductive layer comprises indium tin oxide.

[0013] The first aspect of the embodiments of the present application provides a manufacturing method of an array substrate. The first conductive layer is patterned by using a half-tone mask plate. The surface at the position where the thin film transistor is located is covered by using the half-shading part of the half-tone mask plate. The half-shading part of the half-tone mask plate can shade the thin film transistor to a certain extent, and can also expose the photoresist. Compared with the manufacturing method in the related art, the present application does not need to additionally set a shading layer for the thin film transistor, saves the processing procedure, and reduces the processing and manufacturing cost.

[0014] The second aspect of the embodiments of the present application provides an array substrate, which is manufactured by using the manufacturing method described above.

[0015] The array substrate provided by the second aspect of the embodiments of the present application is patterned by using a half-tone mask plate. The surface at the position where the thin film transistor is located is covered by using the half-shading part of the half-tone mask plate. The half-shading part of the half-tone mask plate can shade the thin film transistor to a certain extent, and can also expose the photoresist. Compared with the manufacturing method in the related art, the present application does not need to additionally set a shading layer for the thin film transistor, saves the processing procedure, and reduces the processing and manufacturing cost.

[0016] The third aspect of the embodiments of the present application provides a display device, which comprises the array substrate described in the second aspect.

[0017] It can be understood that the beneficial effects of the third aspect described above can be referred to the related descriptions of the first aspect and the second aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0019] Figure 1 is a flow chart of the manufacturing method of the array substrate provided by one embodiment of the present application;

[0020] Figure 2is a structural sectional view of an array substrate provided by one embodiment of the present application;

[0021] Figure 3 is a structural sectional view of an array substrate provided by another embodiment of the present application;

[0022] Figure 4 is a flow chart of a manufacturing method of an array substrate provided by another embodiment of the present application;

[0023] Figure 5 is a structural schematic diagram of an array substrate in a manufacturing process provided by one embodiment of the present application;

[0024] Figure 6 is a structural schematic diagram of an array substrate in a manufacturing process provided by another embodiment of the present application;

[0025] Figure 7 is a structural schematic diagram of an array substrate in a manufacturing process provided by yet another embodiment of the present application.

[0026] Reference Signs:

[0027] 100, array substrate;

[0028] 110, substrate;

[0029] 120, thin film transistor, 121, first metal layer, 122, second insulating layer, 123, active layer, 124, second metal layer;

[0030] 130, first insulating layer, 131, passivation layer, 132, planarization layer;

[0031] 140, first conductive layer;

[0032] 150, photoresist layer, 151, first resist layer, 152, second resist layer. DETAILED DESCRIPTION

[0033] In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular sequences of steps, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, and circuits are omitted so as not to obscure the description of the present application with unnecessary detail.

[0034] It should also be understood that the term "and / or" as used herein, refers to any one of the associated listed items, or a combination of any of the associated listed items, and all possible combinations thereof.

[0035] It is to be noted that when an element is referred to as being "fixed" or "set" on another element, it can be directly on the other element or indirectly on the other element with intervening elements. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or indirectly connected to the other element with intervening elements.

[0036] It is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, specify relative positions or orientations based on the orientations or positions shown in the drawings, and are used only for convenience in describing the present application and simplifying the description, and thus cannot be construed as indicating or implying that a device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as limiting the present application.

[0037] In addition, in the description of the present application and the appended claims, the terms "first", "second", "third", and the like are used only for the purpose of distinguishing between similar elements and cannot be construed as indicating or implying relative importance.

[0038] In the present application, the reference to "one embodiment" or "some embodiments" and the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrases "in one embodiment", "in some embodiments", "in other embodiments", "in additional embodiments", and the like, in various places in the specification are not necessarily all referring to the same embodiment, unless otherwise specifically noted. The term "comprising", "containing", "having" and the like, means "including but not limited to", unless otherwise specifically noted. "Multiple" means two or more.

[0039] Embodiment one

[0040] To at least partially solve the problems in the related art, please refer to Figures 1 to 3 The present application provides a manufacturing method of an array substrate 100, which comprises the following steps:

[0041] S102, forming a thin film transistor 120, a first insulating layer 130 and a first conductive layer 140 which are sequentially stacked on a substrate 110.

[0042] As Figure 2 and Figure 3As shown, the thin film transistor 120 is exemplarily composed of a first metal layer 121, a second insulating layer 122, an active layer 123 and a second metal layer 124 which are sequentially stacked on the substrate 110. The material of the substrate 110 can be selected according to different requirements of the array substrate 100. The substrate 110 can be a glass substrate made of transparent material, or a plastic substrate made of non-transparent material, etc. The first metal layer 121 includes gate lines, gate electrodes and common electrodes. The second metal layer 124 includes data lines, source electrodes and drain electrodes. The first metal layer 121 and the second metal layer 124 are insulated from each other by the second insulating layer 122. The active layer 123 is disposed on the second insulating layer 122. The active layer 123 can be formed by patterning a semiconductor layer and then implanting ions into the semiconductor layer to form an active layer 123 with ion doping, so as to improve the mobility of electrons or holes inside the active layer 123. The source electrode and the drain electrode in the second metal layer 124 are electrically connected to the active layer 123.

[0043] The first insulating layer 130 is used to insulate the thin film transistor 120 from the first conductive layer 140. The first insulating layer 130 can be a single layer structure made of a single insulating material, or a multi-layer stacked structure made of multiple different insulating materials. In the embodiment of the present application, the first insulating layer 130 includes a passivation layer 131 and a planarization layer 132 which are sequentially stacked on the second metal layer 124. The passivation layer 131 can include silicon nitride deposited by a suitable deposition technique, or an organic layer based on propylene glycol, etc. The planarization layer 132 can keep its surface substantially flat, so as to facilitate the subsequent manufacturing process without losing flatness, for example, facilitating the arrangement of the first conductive layer 140.

[0044] The first conductive layer 140 is used to form a pixel electrode. The first conductive layer 140 can be made of metal, alloy, metal oxide, etc.

[0045] In S104, the first conductive layer 140 is patterned by using a half-tone mask plate. The half-tone mask plate includes a half-shading portion. The orthographic projection of the thin film transistor 120 on the substrate 110 is located within the orthographic projection of the half-shading portion on the substrate 110.

[0046] Since the material of the active layer 123 in the thin film transistor 120 is generally photosensitive, during the manufacturing of the first conductive layer 140, external light can irradiate on the active layer 123, causing the active layer 123 to have electrical deviation, and then display unevenness, switching picture trailing and other adverse phenomena occur. Therefore, in the related art, a light shielding layer is generally provided for the thin film transistor 120 in the array substrate 100 to improve the stability, resulting in a complex manufacturing process and high cost. In the embodiments of the present application, however, the first conductive layer 140 is patterned by using a half-tone mask plate, and the half-tone mask plate includes a half-light shielding portion which can block part of the light so as to avoid the light irradiating on the active layer 123 in the thin film transistor 120, thereby avoiding affecting the stability of the active layer 123. The half-light shielding portion can also allow part of the light to pass through, thereby allowing the first conductive layer 140 to be patterned by using the part of the light. In some embodiments, the half-tone mask plate can also include a completely transparent portion which can completely transmit the light, or a non-transparent portion which can completely block the light, which can be set according to actual use requirements, and is not limited herein.

[0047] The manufacturing of the thin film transistor 120, the first insulating layer 130 and the first conductive layer 140 and the like can adopt a physical vapor deposition (PVD) process. The physical vapor deposition technology refers to a technology of vaporizing a material source (solid or liquid) on a surface into gaseous atoms or molecules, or partially ionizing into ions under vacuum conditions by using a physical method, and depositing a thin film with certain special functions on a substrate surface through a low-pressure gas (or plasma) process. The physical vapor deposition technology mainly includes three types: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition include vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. The physical vapor deposition technology process is simple, improves the environment, has no pollution, consumes less material, and forms a uniform and dense film with strong adhesion to the substrate.

[0048] The manufacturing of the thin film transistor 120, the first insulating layer 130 and the first conductive layer 140 and the like can also adopt a chemical vapor deposition (CVD) process. The chemical vapor deposition is a method of generating a thin film on a substrate surface by using one or more gas phase compounds or elements containing thin film elements through a chemical reaction.

[0049] The manufacturing method of the array substrate 100 in the embodiment of the present application performs patterning on the first conductive layer 140 by using a half-tone mask plate, and uses the half-shading part of the half-tone mask plate to cover the surface at the position of the thin film transistor 120. The half-shading part of the half-tone mask plate can shield light for the thin film transistor 120 to a certain extent, and can also expose the photoresist. Compared with the manufacturing method in the related art, the present application does not need to additionally set a light shielding layer for the thin film transistor 120, saves the processing procedure, and reduces the processing cost.

[0050] Embodiment Two

[0051] Please refer to Figure 4 The manufacturing method of the array substrate 100 in the embodiment includes the following steps:

[0052] S202, forming the thin film transistor 120, the first insulating layer 130 and the first conductive layer 140 which are sequentially and layerwisely arranged on the substrate 110.

[0053] S204, setting a photoresist layer 150 on the first conductive layer 140.

[0054] S206, exposing and developing the photoresist layer 150 by using a half-tone mask plate, the half-tone mask plate including a half-shading part, and the orthographic projection of the thin film transistor 120 on the substrate 110 being located within the orthographic projection of the half-shading part on the substrate 110.

[0055] S208, etching the first conductive layer 140.

[0056] That is, in the embodiment, the patterning of the first conductive layer 140 can be completed by setting the photoresist layer 150 on the first conductive layer 140 and exposing, developing and etching the photoresist layer 150 by using the half-tone mask plate.

[0057] S210, removing the first photoresist layer 151.

[0058] Please refer to Figure 4 and refer to Figures 5 to 7 In some embodiments, the photoresist layer 150 includes the first photoresist layer 151 and the second photoresist layer 152 which are connected to each other, the orthographic projection of the thin film transistor 120 on the substrate 110 is located within the orthographic projection of the first photoresist layer 151 on the substrate 110, and the step of removing the photoresist layer 150 specifically includes: removing the first photoresist layer 151; performing surface treatment on the first conductive layer 140; and removing the second photoresist layer 152.

[0059] After the photoresist layer 150 is set on the first conductive layer 140, the structure is as shown in Figure 5As shown in FIG. 1C, the photoresist layer 150 is exposed and developed by using a half-tone mask plate. The structure after exposure and development is as shown in FIG. 1D. Figure 6 As shown in FIG. 1D, because the half-tone mask plate includes regions with different light transmission properties, the photoresist layer 150 after exposure and development also forms regions with different thicknesses in the direction perpendicular to the surface of the substrate 110, i.e., the first photoresist layer 151 and the second photoresist layer 152 in this embodiment.

[0060] The structure after removal of the first photoresist layer 151 is as shown in FIG. 1E. Figure 7 As shown in FIG. 1E, the region on the first conductive layer 140 that was originally covered by the first photoresist layer 151, i.e., the region above the thin film transistor 120, can be subjected to surface treatment to reduce the light transmittance of this region on the first conductive layer 140, thereby further shielding external light from shining onto the active layer 123 and causing electrical shift of the active layer 123.

[0061] In some embodiments, the thickness of the first photoresist layer 151 is smaller than the thickness of the second photoresist layer 152 in the direction perpendicular to the surface of the substrate 110.

[0062] Because the half-tone mask plate includes a semi-shading portion and the orthographic projection of the thin film transistor 120 on the substrate 110 is within the orthographic projection of the semi-shading portion on the substrate 110, the photoresist layer 150 after exposure and development forms the first photoresist layer 151 and the second photoresist layer 152 with different thicknesses in the direction perpendicular to the surface of the substrate 110, where the thickness of the first photoresist layer 151 is smaller than the thickness of the second photoresist layer 152. In this embodiment, the specific thicknesses of the first photoresist layer 151 and the second photoresist layer 152 in the direction perpendicular to the surface of the substrate 110 are not limited, as long as the thickness of the first photoresist layer 151 is smaller than the thickness of the second photoresist layer 152.

[0063] S212, bombarding the surface of the first conductive layer 140 with plasma.

[0064] In order to reduce the light transmittance of the region on the first conductive layer 140 that was originally covered by the first photoresist layer 151, i.e., the region above the thin film transistor 120, thereby further shielding external light from shining onto the active layer 123 and causing electrical shift of the active layer 123, the region on the first conductive layer 140 can be subjected to surface treatment. In some embodiments, the surface treatment of the first conductive layer 140 specifically includes bombarding the surface of the first conductive layer 140 with plasma.

[0065] Plasma, also called electric plasma, is an ionized gas-like substance composed of positive and negative ions generated by atoms and atomic groups after partial electrons are deprived, a macroscopic electric neutral ionized gas with a scale larger than Debye length, whose movement is mainly governed by electromagnetic force and exhibits significant collective behavior. Plasma is a fourth state of matter different from solids, liquids and gases, which is composed of ions, electrons and un-ionized neutral particles, and is a neutral substance state as a whole. After the surface of the first conductive layer 140 is bombarded by plasma, the surface of the first conductive layer 140 can be made rougher, the light reflection and scattering ability of the surface of the first conductive layer 140 is increased, and thus the light transmittance of the first conductive layer 140 is reduced.

[0066] Further, on the basis of the above-mentioned embodiments, the plasma includes hydrogen ions. After the surface of the first conductive layer 140 is bombarded by the plasma including hydrogen ions, in addition to being able to make the surface of the first conductive layer 140 rougher and increase the light reflection and scattering ability of the surface of the first conductive layer 140, a reduction reaction with metal compounds in the first conductive layer 140 can also occur, forming metal elements on the surface of the first conductive layer 140. These metal elements can increase the reflectivity of light, thereby further reducing the light transmittance of the region on the first conductive layer 140.

[0067] S214, removing the second adhesive layer 152.

[0068] Similarly to Embodiment One, the manufacturing method of the array substrate 100 of the present embodiment uses a half-tone mask plate to pattern the first conductive layer 140, and uses the half-shading part of the half-tone mask plate to cover the surface at the position of the thin film transistor 120. The half-shading part of the half-tone mask plate can shield the light for the thin film transistor 120, and at the same time, the photoresist can be exposed. Compared with the manufacturing method in the related art, the present application does not need to additionally provide a light shielding layer for the thin film transistor 120, saves the processing procedure, and reduces the processing and manufacturing cost.

[0069] Embodiment Three

[0070] Please continue to refer to Figure 2 and Figure 3 The present embodiment provides an array substrate 100 manufactured by the above-mentioned manufacturing method. The array substrate 100 includes a substrate 110, a thin film transistor 120, a first insulating layer 130 and a first conductive layer 140 which are sequentially stacked. The thin film transistor 120 includes a first metal layer 121, a second insulating layer 122, an active layer 123 and a second metal layer 124 which are sequentially stacked on the substrate 110. The first insulating layer 130 includes a passivation layer 131 and a planarization layer 132 which are sequentially stacked on the second metal layer 124.

[0071] The array substrate 100 in the embodiment of the present application is manufactured by the manufacturing method in the embodiment one or the embodiment two, the first conductive layer 140 is patterned by using the half-tone mask plate, the surface at the position where the thin film transistor 120 is located is covered by using the half-shading part of the half-tone mask plate, the half-shading part of the half-tone mask plate can play a certain shading role on the thin film transistor 120, and at the same time, the photoresist can be exposed. Compared with the manufacturing method in the related art, the present application does not need to additionally set a shading layer for the thin film transistor 120, saves the processing procedure, and reduces the processing and manufacturing cost.

[0072] In some embodiments, optionally, the first conductive layer 140 is manufactured by using a light-transmitting material. The first conductive layer 140 is manufactured by using the light-transmitting material, so that the pixel electrode in the array substrate 100 has the light-transmitting property, the use performance and the application range of the array substrate 100 can be improved, and at the same time, since the first conductive layer 140 is patterned by using the half-tone mask plate, the surface at the position where the thin film transistor 120 is located is covered by using the half-shading part of the half-tone mask plate, the half-shading part of the half-tone mask plate can play a certain shading role on the thin film transistor 120, and there is no need to worry about the problem that the external light will irradiate on the active layer 123 in the manufacturing process of the first conductive layer 140, and the electrical property of the active layer 123 is offset.

[0073] On the basis of the above-mentioned embodiments, the manufacturing material of the first conductive layer 140 includes indium tin oxide. The indium tin oxide is a kind of substitution solid solution, is a transparent brown film or yellowish gray block, is mixed by 90% In2O3 and 10% SnO2, and mainly has the characteristics of simultaneously having the electrical conductivity and the optical transparency.

[0074] Embodiment four

[0075] The embodiment of the present application provides a display device, which comprises the array substrate 100 in the embodiment three.

[0076] The display device can further include a display panel applied in the display device to provide the function of displaying pictures, and the array substrate 100 is used to drive the display panel to display specific images. The display device can be any product or component with display function, including but not limited to mobile phones, tablets, notebooks, e-readers, wearable devices, remote controls, televisions, desktop computers, vehicle-mounted devices, etc. Since the display panel in the above embodiments is used, the first conductive layer 140 is patterned by using a half-tone mask plate, the surface at the position of the thin film transistor 120 is covered by the half-shading part of the half-tone mask plate, the half-shading part of the half-tone mask plate can play a certain shading role for the thin film transistor 120, and at the same time, the photoresist can be exposed. Compared with the manufacturing method in the related art, the present application does not need to additionally set a shading layer for the thin film transistor 120, saves the processing procedure, and reduces the processing and manufacturing cost.

[0077] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0078] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for fabricating an array substrate, characterized in that, The application relates to an array substrate manufacturing method. Forming a thin film transistor (120), a first insulating layer (130) and a first conductive layer (140) which are sequentially arranged on a substrate (110); Setting a photoresist layer (150) on the first conductive layer (140); Exposing and developing the photoresist layer (150) by using a half-tone mask plate, the half-tone mask plate comprising a half-shading part, the orthographic projection of the thin film transistor (120) on the substrate (110) is located in the orthographic projection of the half-shading part on the substrate (110), the photoresist layer (150) after exposure and development comprises a first photoresist layer (151) and a second photoresist layer (152) which are connected with each other, the thickness dimension of the first photoresist layer (151) is smaller than that of the second photoresist layer (152) in the direction perpendicular to the surface of the substrate (110), and the orthographic projection of the thin film transistor (120) on the substrate (110) is located in the orthographic projection of the first photoresist layer (151) on the substrate (110); Etching the first conductive layer (140); Removing the first photoresist layer (151); Surface processing the first conductive layer (140); Removing the second photoresist layer (152).

2. The method of manufacturing an array substrate according to claim 1, wherein The surface processing of the first conductive layer (140) specifically comprises: Plasma is used to bombard the surface of the first conductive layer (140).

3. The method of manufacturing an array substrate according to claim 2, wherein The plasma comprises hydrogen ions.

4. The method of manufacturing an array substrate according to any one of claims 1 to 3, wherein The first conductive layer (140) is made of a light-transmitting material.

5. The method of manufacturing an array substrate according to claim 4, wherein The material of the first conductive layer (140) comprises indium tin oxide.

6. An array substrate, characterized by, The array substrate is manufactured by using the manufacturing method as claimed in any one of claims 1 to 5.

7. A display device, characterized by comprising: The application relates to an array substrate manufacturing method. The array substrate (100) according to claim 6.

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