Tunnel Field-Effect Transistor, Preparation Method Thereof, and Photoelectric Detector

Abstract

The present invention provides a tunneling field effect transistor, a preparation method thereof, and a photodetector, which relate to the field of optoelectronic devices. The tunneling field effect transistor includes a substrate, and an insulating layer, a conductive layer, a dielectric layer, a heterojunction layer, and a packaging layer that are sequentially stacked on one side of the substrate; the heterojunction layer includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is stacked on the dielectric layer, at least a part of the second semiconductor layer is stacked on the first semiconductor layer, and the other part of the second semiconductor layer is stacked on the dielectric layer; the first semiconductor layer includes a tin disulfide layer, the second semiconductor layer includes a hafnium disulfide layer, and the packaging layer includes a hafnium oxide layer. The present invention uses plasma oxidation technology to perform packaging treatment on hafnium disulfide with ultra-high carrier characteristics, forming a hafnium oxide dielectric layer with a high dielectric constant, ensuring a high-quality interface, and then realizing the tunneling characteristics of the field effect transistor, laying a foundation for finally realizing low-power tunneling devices of high-performance nanomaterials in the future.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic devices, and particularly to a tunneling field effect transistor, a preparation method thereof, and a photodetector. Background Art

[0002] As the size of the core component transistor of integrated circuits continues to shrink to the nanometer level, problems such as short-channel effects have become increasingly obvious, posing a huge challenge to device performance. At the same time, the rapid development of modern information technology requires continuous improvement in device density on integrated circuits, which has led to a sharp increase in power consumption. In this context, the research and development of low-power devices is not only crucial for improving device performance and applications, but also of great significance for environmental protection and energy conservation. Therefore, the development of low-power technologies has become a key research direction in the field of integrated circuits.

[0003] On the path of pursuing low-power devices, researchers have continuously tried and explored new technical approaches. Tunneling field effect transistors show great potential as low-power devices. Different from traditional metal-oxide-semiconductor layer field effect transistors (MOSFETs), tunneling field effect transistors can break through the theoretical limit of the subthreshold swing of 60 mV / dec, which makes them promising to become a new type of device that can replace MOSFETs and lead the development of future low-power devices.

[0004] Although tunneling field effect transistor devices theoretically show the potential of extremely low subthreshold swings, in practice, interface effects have a profound impact on the devices, severely restricting the application of tunneling field effect transistors. Summary of the Invention

[0005] The main object of the present invention is to propose a tunneling field effect transistor, a preparation method thereof, and a photodetector, aiming to provide a tunneling field effect transistor with a high-quality packaging interface.

[0006] To achieve the above object, the present invention proposes a tunneling field effect transistor, including a substrate, and an insulating layer, a conductive layer, a dielectric layer, a heterojunction layer, and a packaging layer that are sequentially stacked on one side of the substrate;

[0007] The heterojunction layer includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a tin disulfide layer, the second semiconductor layer includes a hafnium disulfide layer, and the packaging layer includes a hafnium oxide layer.

[0008] In one embodiment, the hafnium oxide layer is obtained by oxidizing the hafnium disulfide layer.

[0009] In one embodiment, both the tin disulfide layer and the hafnium disulfide layer are disposed on the dielectric layer, and at least a part of the hafnium disulfide layer is stacked on the tin disulfide layer so that the tin disulfide layer and the hafnium disulfide layer are arranged in a cross manner.

[0010] In one embodiment, the thickness of the tin disulfide layer is 5 - 15 nm, and the thickness of the hafnium disulfide layer is 20 - 30 nm.

[0011] In one embodiment, the tunneling field effect transistor further includes a source electrode, a drain electrode, and a gate electrode. The source electrode is disposed on the first semiconductor layer, the drain electrode is disposed on the second semiconductor layer, and the gate electrode is disposed on the conductive layer.

[0012] In one embodiment, the materials of the source electrode, the drain electrode, and the gate electrode include a stacked titanium layer and a gold layer;

[0013] The thickness of the titanium layer is 4 - 6 nm, and the thickness of the gold layer is 45 - 55 nm.

[0014] In one embodiment, the substrate includes a silicon substrate, the insulating layer includes a silicon dioxide layer, the conductive layer includes a graphene layer, and the dielectric layer includes a hexagonal boron nitride layer;

[0015] The thickness of the silicon dioxide layer is 285 - 300 nm, the thickness of the graphene layer is 8 - 12 nm, and the thickness of the hexagonal boron nitride layer is 8 - 12 nm.

[0016] The present invention also provides a method for manufacturing a tunneling field effect transistor, including the following steps:

[0017] S10. Provide a substrate covered with an insulating layer;

[0018] S20. Set a conductive layer on the insulating layer;

[0019] S30. Set a dielectric layer on the conductive layer;

[0020] S40. Set a first semiconductor layer and a second semiconductor layer on the dielectric layer. The first semiconductor layer and the second semiconductor layer are partially stacked, and the other parts are both disposed on the dielectric layer to obtain a stacked body. The first semiconductor layer includes a tin disulfide layer, and the second semiconductor layer includes a hafnium disulfide layer;

[0021] S50. Perform plasma oxidation on the stacked body to oxidize the surface of the hafnium disulfide to obtain a hafnium oxide layer, and the hafnium oxide layer forms a packaging layer;

[0022] S60. Perform vacuum annealing, dispose the source electrode on the first semiconductor layer, dispose the drain electrode on the second semiconductor layer, and dispose the gate electrode on the conductive layer to obtain a tunneling field effect transistor.

[0023] In one embodiment, step S20 includes: after obtaining a graphene layer by a mechanical exfoliation method, transferring the graphene layer onto the substrate, and the graphene layer forms the conductive layer;

[0024] Step S30 includes: exfoliating a hexagonal boron nitride layer onto polydimethylsiloxane, and then transferring the hexagonal boron nitride layer onto the conductive layer by dry transfer, and the hexagonal boron nitride layer forms the dielectric layer;

[0025] Step S40 includes: disposing a first semiconductor layer on the dielectric layer, and disposing a second semiconductor layer on the first semiconductor layer and the dielectric layer;

[0026] In step S50, during the plasma oxidation treatment, the plasma power is 25 - 35 W, the oxygen flow rate is 3 - 6 sccm, the pressure is 450 - 500 mTorr, and the duration is 8 - 12 min;

[0027] In step S60, the temperature of the vacuum annealing is 100 - 150 °C, the heating-up time is 20 - 30 min, and the holding time is 30 - 60 min;

[0028] In step S60, the source electrode and the drain electrode are respectively disposed on the first semiconductor layer and the second semiconductor layer by evaporation.

[0029] The present invention also provides a photodetector, which includes the tunneling field effect transistor as described above, or a tunneling field effect transistor prepared according to the preparation method of the tunneling field effect transistor as described above.

[0030] The technical solution of the present invention is to prepare a low-power tunneling device with a cross-type semiconductor layer structure composed of tin disulfide / hafnium disulfide. In this structure, the natural hafnium oxide layer is obtained by plasma oxidation treatment of hafnium disulfide, which has a high dielectric constant and can be used as a dielectric layer to isolate the influence of water and oxygen on hafnium disulfide, and at the same time form an interface without impurities and defects, thereby improving the performance of the tunneling field effect transistor and increasing its current level and mobility. The high-quality interface between the top dielectric of the heterojunction layer and the channel material is crucial for a high-performance tunneling field effect transistor. The heterojunction layer ensures the fast switching and low power consumption requirements of the device; the present invention uses plasma oxidation technology to encapsulate hafnium disulfide with ultra-high carrier characteristics, forming a natural hafnium oxide dielectric layer with a high dielectric constant, ensuring a high-quality interface, greatly improving the tunneling performance of the two-dimensional tin disulfide / hafnium disulfide detector, and laying a foundation for ultimately realizing a low-power tunneling field effect transistor of high-performance nanomaterials in the future. Description of the Drawings

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other related drawings can be obtained based on these drawings.

[0032] Figure 1 Schematic diagram of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor provided in Embodiment 1 of the present invention;

[0033] Figure 2 Stacking diagram of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor provided in Embodiment 1 of the present invention;

[0034] Figure 3 Optical microscope image of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor provided in Embodiment 1 of the present invention;

[0035] Figure 4 Raman spectrum of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor in Embodiment 1 of the present invention;

[0036] Figure 5 Atomic force microscopy (AFM) image of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor in Embodiment 1 of the present invention;

[0037] Figure 6 Output curve of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling device in Embodiment 1 of the present invention ( I ds - V ds ) graph;

[0038] Figure 7 Time response graph of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling device in Embodiment 1 of the present invention at different wavelengths;

[0039] Figure 8 For the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide / hexagonal boron nitride device in Comparative Example 1 of the present invention I ds - V ds curve graph;

[0040] Figure 9 For the graphene / hexagonal boron nitride / tin disulfide / tin diselenide device in Comparative Example 2 of the present invention I ds -V ds Graphs;

[0041] Figure 10 The tin disulfide / hafnium disulfide device of Comparative Example 3 of the present invention I ds - V ds Graph.

[0042] Description of Figure Numbers:

[0043] 100. Tunneling field effect transistor; 1. substrate; 2. insulating layer; 3. conductive layer; 4. dielectric layer; 5. heterojunction layer; 51. first semiconductor layer; 52. second semiconductor layer; 6. source electrode; 7. drain electrode; 8. gate electrode; 9. packaging layer.

[0044] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0045] To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them.

[0046] It should be noted that, in the embodiments, those without specifying specific conditions are carried out according to conventional conditions or conditions recommended by the manufacturer. Those without specifying the manufacturer of reagents or instruments used are conventional products that can be purchased commercially. In addition, the technical schemes between the various embodiments can be combined with each other, but must be based on the ability of ordinary technicians in the field to achieve. When the combination of the technical schemes is mutually contradictory or cannot be achieved, it should be considered that the combination of such technical schemes does not exist, and is not within the scope of protection required by the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present invention.

[0047] Tunneling field-effect transistors show great potential as low-power devices. Unlike MOSFETs, tunneling field-effect transistors can break through the theoretical limit of subthreshold swing of 60 mV / dec, which makes them a promising new type of device that can replace MOSFET and lead the development of future low-power devices.

[0048] At present, although tunneling field-effect transistor devices show the potential of extremely low subthreshold swing in theory, in practice, interface effects have a profound impact on the devices, seriously restricting the application of tunneling field-effect transistors.

[0049] This goal can be effectively achieved by constructing heterojunctions with appropriate two-dimensional materials. Two-dimensional materials have the characteristics of smooth surfaces and few defects, which are beneficial to the efficient transport of carriers. In addition, there are no dangling bonds on the surface of two-dimensional materials, which helps to reduce the negative impact of lattice mismatch on device performance, making two-dimensional materials an ideal choice for fabricating novel tunneling field-effect transistors.

[0050] The energy band alignments of heterostructures formed by stacking two-dimensional materials are mainly divided into spanning type, staggered type, and broken type structures. In the spanning type structure, the minimum value of the conduction band and the maximum value of the valence band are both located within the same material, which confines the photo-generated electrons and holes within the same material and promotes their radiative recombination. In addition, there is a carrier transport barrier from the narrow-bandgap semiconductor layer to the wide-bandgap semiconductor layer, which is beneficial to achieving a low dark current, thus significantly improving the on-off ratio of the tunneling current.

[0051] In view of this, referring to Figure 1 , the present invention provides a tunneling field-effect transistor 100, which includes a substrate 1, and an insulating layer 2, a conductive layer 3, a dielectric layer 4, a heterojunction layer 5, and a packaging layer 9 stacked in sequence on one side of the substrate 1; the heterojunction layer 5 includes a first semiconductor layer 51 and a second semiconductor layer 52, the first semiconductor layer 51 includes a tin disulfide layer, the second semiconductor layer 52 includes a hafnium disulfide layer, and the packaging layer 9 includes a hafnium oxide layer.

[0052] It should be noted that the field-effect transistor prepared from hafnium disulfide has an ultra-high on-off ratio (exceeding 10 8 ), which is crucial for high-performance electronic devices.

[0053] The technical solution of the present invention is to fabricate a low-power tunneling device with a spanning type semiconductor layer structure composed of tin disulfide / hafnium disulfide. In this structure, the hafnium oxide layer has a high dielectric constant, which can be used as a dielectric layer to isolate the influence of water and oxygen on hafnium disulfide, and at the same time form an interface without impurities and defects, thereby improving the performance of the tunneling field-effect transistor 100; in addition, the high-quality interface between the top dielectric of the heterojunction layer 5 and the channel material is crucial for the high-performance tunneling field-effect transistor 100, and the heterojunction layer 5 ensures the low energy consumption requirement of the device. The present invention uses plasma oxidation technology to package hafnium disulfide with ultra-high carrier characteristics, forming a natural hafnium oxide dielectric layer with a high dielectric constant, ensuring a high-quality interface, greatly improving the tunneling performance of the tin disulfide / hafnium disulfide detector, and laying a foundation for ultimately realizing low-power tunneling devices of high-performance nanomaterials in the future.

[0054] In one embodiment, the hafnium oxide layer is obtained by oxidizing the hafnium disulfide layer.

[0055] The technical solution of the present invention synthesizes hafnium oxide, a natural dielectric layer, through an oxidation method to form a natural hafnium oxide dielectric layer with a high dielectric constant, ensuring a high-quality interface, thereby greatly reducing the influence of moisture and oxygen in the surrounding environment on it.

[0056] In one embodiment, the tin disulfide layer and the hafnium disulfide layer are both disposed on the dielectric layer 4, and at least a part of the hafnium disulfide layer is stacked on the tin disulfide layer, so that the tin disulfide layer and the hafnium disulfide layer are arranged in a cross manner.

[0057] The technical solution of the present invention forms a heterojunction layer 5 by arranging the tin disulfide layer and the hafnium disulfide layer in a cross manner. At the same time, by disposing the tin disulfide layer and the hafnium disulfide layer on the dielectric layer 4, the carrier distribution states in the tin disulfide layer and the hafnium disulfide layer can be respectively adjusted through the dielectric layer 4, thereby precisely controlling the tunneling probability, and further realizing obtaining devices with different properties in the same heterojunction.

[0058] In one embodiment, the thickness of the tin disulfide layer is 5 - 15 nm, and the thickness of the hafnium disulfide layer is 20 - 30 nm.

[0059] In one embodiment, the tunneling field effect transistor 100 further includes a source electrode 6, a drain electrode 7, and a gate electrode 8. The source electrode 6 is disposed on the first semiconductor layer 51, the drain electrode 7 is disposed on the second semiconductor layer 52, and the gate electrode 8 is disposed on the conductive layer 3.

[0060] The technical solution of the present invention can effectively control the electron tunneling process by disposing the source electrode 6 on the first semiconductor layer 51 and the drain electrode 7 on the second semiconductor layer 52; by disposing the gate electrode 8 on the conductive layer 3, the tunneling barrier can be more effectively controlled, improving the regulation ability of the carrier tunneling process, thereby enhancing the overall controllability and stability of the device.

[0061] In one embodiment, the materials of the source electrode 6, the drain electrode 7, and the gate electrode 8 include a stacked titanium layer and a gold layer;

[0062] The thickness of the titanium layer is 4 - 6 nm, and the thickness of the gold layer is 45 - 55 nm.

[0063] The technical solution of the present invention selects titanium and gold as electrode materials. Among them, the titanium layer is used to improve the contact quality between the electrode and the semiconductor layer due to its good adhesion; the gold layer has excellent electrical conductivity and chemical stability, which helps to reduce the contact resistance and improve the electrical conductivity of the electrode; the combined electrode of titanium and gold helps to optimize the carrier transmission path and reduce the loss during the carrier transmission process; both titanium and gold have good thermal stability and can maintain stable performance within a wide temperature range, which helps to broaden the operating temperature range of the tunneling field effect transistor 100; by using a titanium layer with a thickness of 4 - 6 nm, sufficient adhesion is ensured while avoiding the increase in additional resistance caused by excessive thickness; by using a gold layer with a thickness of 45 - 55 nm, good electrical conductivity can be ensured while maintaining a low contact resistance; by precisely controlling the thickness of the titanium and gold layers, not only the high performance of the device is ensured, but also the cost can be effectively reduced.

[0064] In one embodiment, referring to Figures 1 to 3 , the substrate 1 includes a silicon substrate, the insulating layer 2 includes a silicon dioxide layer, the conductive layer 3 includes a graphene layer, and the dielectric layer 4 includes a hexagonal boron nitride layer;

[0065] The thickness of the silicon dioxide layer is 285 - 300 nm, the thickness of the graphene layer is 8 - 12 nm, and the thickness of the hexagonal boron nitride layer is 8 - 12 nm.

[0066] The technical solution of the present invention uses hexagonal boron nitride as the dielectric layer 4. By utilizing its high-quality insulating characteristics and excellent dielectric properties, it can effectively isolate the conductive layer 3 and the heterojunction layer 5, reduce unnecessary carrier recombination phenomena, and thus improve the photoelectric conversion efficiency; by using graphene as the conductive layer 3, by utilizing its extremely high electron mobility and good electrical conductivity, it helps to accelerate the carrier transmission process and reduce the energy loss during the transmission process, thereby improving the response speed of the tunneling field effect transistor 100; in addition, both hexagonal boron nitride and graphene have good stability and can withstand high mechanical stress, which helps to improve the reliability and durability of the tunneling field effect transistor 100. By using a hexagonal boron nitride layer with a thickness of 8 - 12 nm as a high-quality insulating layer 2, it can effectively isolate each layer, reduce unnecessary carrier recombination, and further improve the photoelectric conversion efficiency; by using a graphene layer, by utilizing its high electron mobility and good electrical conductivity, it helps to accelerate the carrier transmission process and reduce the energy loss during the transmission process, thereby improving the response speed of the tunneling field effect transistor 100.

[0067] It should be noted that the silicon substrate is a doped silicon substrate. Specifically, in some embodiments of the present invention, the silicon substrate is a p-type doped silicon substrate.

[0068] The present invention also provides a method for manufacturing a tunneling field effect transistor 100, which includes the following steps: S10. Provide a substrate 1 covered with an insulating layer 2; S20. Provide a conductive layer 3 on the insulating layer 2; S30. Provide a dielectric layer 4 on the conductive layer 3; S40. Provide a first semiconductor layer 51 and a second semiconductor layer 52 on the dielectric layer 4, where the first semiconductor layer 51 and the second semiconductor layer 52 are partially stacked, and the other parts are both provided on the dielectric layer 4 to obtain a stacked body. The first semiconductor layer 51 includes a tin disulfide layer, and the second semiconductor layer 52 includes a hafnium disulfide layer; S50. Perform plasma oxidation on the stacked body to oxidize the surface of hafnium disulfide to obtain a hafnium oxide layer, and the hafnium oxide layer forms a packaging layer 9; S60. Perform vacuum annealing, provide a source electrode 6 on the first semiconductor layer 51, provide a drain electrode 7 on the second semiconductor layer 52, and provide a gate electrode 8 on the conductive layer 3 to obtain the tunneling field effect transistor 100.

[0069] The technical solution of the present invention uses tin disulfide and hafnium disulfide as the materials of the first semiconductor layer 51 and the second semiconductor layer 52, and utilizes the special energy band structure and high mobility characteristics of these two materials to improve the performance of the tunneling field effect transistor 100; through plasma oxidation treatment, the surface of hafnium disulfide is oxidized to form a hafnium oxide layer as the packaging layer 9, forming a natural oxide layer, which will not cause a series of interface problems, and reduces the manufacturing steps, further reducing the risk of interface contamination. Thus, the characteristics of a forward rectifier, Esaki diode, and reverse rectifier are simultaneously realized in one structure; by stacking the first semiconductor layer 51 and the second semiconductor layer 52 in a partially stacked manner, it helps to optimize the tunneling path of charge carriers, further reducing the leakage current and improving the performance of the tunneling field effect transistor 100.

[0070] In addition, in some embodiments of the present invention, a graphene electrode is further added on the packaging layer 9, thus forming a dual-gate regulation, that is, a bottom-gate dielectric hexagonal boron nitride and a top-gate dielectric hafnium oxide, thereby further improving the carrier regulation ability.

[0071] In one embodiment, step S20 includes: after mechanically exfoliating a graphene layer, transferring the graphene layer onto the substrate 1, and the graphene layer forms the conductive layer 3; step S30 includes: exfoliating a hexagonal boron nitride layer onto polydimethylsiloxane, and transferring the hexagonal boron nitride layer onto the conductive layer 3 by dry transfer, and the hexagonal boron nitride layer forms the dielectric layer 4; step S40 includes: disposing a first semiconductor layer 51 on the dielectric layer 4, and disposing a second semiconductor layer 52 on the first semiconductor layer 51 and the dielectric layer 4; in step S50, during plasma oxidation treatment, the plasma power is 25 - 35 W, the oxygen flow rate is 3 - 6 sccm, the pressure is 450 - 500 mTorr, and the duration is 8 - 12 min; in step S60, the temperature of vacuum annealing is 100 - 150 °C, the heating-up time is 20 - 30 min, and the heat preservation time is 30 - 60 min; in step S60, the source electrode 6 and the drain electrode 7 are respectively disposed on the first semiconductor layer 51 and the second semiconductor layer 52 by evaporation coating.

[0072] The technical solution of the present invention exfoliates a graphene layer mechanically and transfers it onto the substrate 1 to form the conductive layer 3. The graphene layer has a high electron mobility and good electrical conductivity, which helps to accelerate the carrier transport process and reduce the energy loss during the transport process, thereby improving the response speed of the tunneling field effect transistor 100; exfoliating a hexagonal boron nitride layer onto polydimethylsiloxane and transferring it onto the graphene layer by dry transfer to form the dielectric layer 4 can provide good electrical insulation performance, reduce the radiative recombination of charge carriers, and help to improve the photoelectric conversion efficiency. Among them, the hexagonal boron nitride layer can effectively isolate each layer, reduce unnecessary carrier recombination, and further improve the photoelectric conversion efficiency; by disposing the first semiconductor layer 51 on the dielectric layer 4 and disposing the second semiconductor layer 52 on the first semiconductor layer 51 and the dielectric layer 4, the position and mutual relationship of the semiconductor layers can be precisely controlled, the carrier transport path can be optimized, and the energy loss during the carrier transport process can be reduced, thereby improving the response speed of the tunneling field effect transistor 100; by performing vacuum annealing in the temperature range of 100 to 150 °C, defects and impurities can be reduced, thereby enhancing the reliability and stability of the device. The reasonable heating-up time and heat preservation time also help to optimize the material properties; the hafnium oxide layer prepared by plasma oxidation treatment is used as the encapsulation layer 9. The precise control of the plasma power, oxygen flow rate, pressure, and duration helps to obtain a high-quality encapsulation layer 9. This encapsulation layer 9 can not only provide good electrical insulation performance but also enhance the thermal stability and chemical stability of the device.

[0073] The present invention also proposes a photodetector, which includes the tunneling field effect transistor 100 as described above, or a tunneling field effect transistor 100 prepared by the preparation method of the tunneling field effect transistor 100 as described above.

[0074] Since this photodetector adopts all the technical solutions of the above-mentioned all embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated one by one here.

[0075] The technical solutions of the present invention will be further described in detail below in conjunction with specific embodiments. It should be understood that the following embodiments are only used to explain the present invention and are not used to limit the present invention; in the embodiments, some thickness data are ranges rather than precise point values because the thicknesses of each layer formed during the preparation process fluctuate due to instrument errors, so the obtained thickness is a range rather than a point value.

[0076] Embodiment 1

[0077] This embodiment provides a tunneling field effect transistor, the structure of which is as Figure 1 shown, and its preparation method includes the following steps:

[0078] 1. Strip 8 - 12 nm of graphene on the SiO2 - Si substrate; strip 8 - 12 nm of hexagonal boron nitride onto polydimethylsiloxane; transfer the hexagonal boron nitride to the graphene through a transfer stage; transfer 5 - 15 nm of tin disulfide to the hexagonal boron nitride through a transfer stage; transfer 20 - 30 nm of hafnium disulfide to the tin disulfide layer through a transfer stage to form a heterojunction;

[0079] 2. Perform plasma oxidation treatment on the stacked graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide heterojunction, with a plasma power of 30 W, an oxygen flow rate of 5 sccm, a pressure of 470 mTorr, and a duration of 10 min to obtain a hafnium oxide layer;

[0080] 3. Place the oxidized heterojunction in a vacuum annealing furnace for annealing treatment, control the vacuum annealing temperature at 100 °C, the heating time at 30 mins, the holding time at 1 h, and cool it to room temperature with the furnace;

[0081] 4. Construct electrodes on the annealed graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide, first evaporate a titanium layer with a thickness of 5 nm, and then continue to evaporate a gold layer with a thickness range of 50 nm.

[0082] Comparative experiment and results

[0083] Comparative Example 1

[0084] This comparative example provides a hexagonal boron nitride encapsulation layer. The difference from Embodiment 1 is that a conventional hexagonal boron nitride encapsulation layer is used instead of a hafnium oxide layer in close contact with the heterojunction material to obtain a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide / hexagonal boron nitride heterojunction. The specific steps are as follows:

[0085] 1. Graphene with a thickness of 8 - 15 nm is exfoliated onto a p - type doped silicon substrate with a 285 - 300 nm thick silicon dioxide insulating layer on its surface by mechanical exfoliation. A 10 - 20 nm hexagonal boron nitride layer is exfoliated onto polydimethylsiloxane, and the hexagonal boron nitride is transferred onto part of the graphene by dry transfer. Subsequently, 10 - 20 nm tin disulfide is transferred onto the hexagonal boron nitride, and then 60 - 80 nm hafnium disulfide is transferred onto part of the tin disulfide and hexagonal boron nitride, stacking to form a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide heterojunction;

[0086] 2. The hexagonal boron nitride is transferred onto the hafnium disulfide by dry transfer to form a capping layer;

[0087] 3. Electrodes are fabricated on the annealed graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide heterojunction. First, a titanium layer with a thickness in the range of 5 nm is evaporated, and then a gold layer with a thickness in the range of 50 nm is continuously evaporated.

[0088] Comparative Example 2

[0089] This comparative example provides a heterojunction structure, which is different from that in Example 1 in that a graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction is used. The specific steps are as follows:

[0090] 1. Graphene with a thickness of 8 - 15 nm is exfoliated onto a p - type doped silicon substrate with a 285 - 300 nm thick silicon dioxide insulating layer on its surface by mechanical exfoliation. A 10 - 20 nm hexagonal boron nitride layer is exfoliated onto polydimethylsiloxane, and the hexagonal boron nitride is transferred onto part of the graphene by dry transfer. Subsequently, 10 - 20 nm tin disulfide is transferred onto the hexagonal boron nitride, and then 60 - 80 nm tin diselenide is transferred onto part of the tin disulfide and hexagonal boron nitride, stacking to form a graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction;

[0091] 2. The stacked graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction is placed in a vacuum annealing furnace for annealing treatment. The vacuum annealing temperature is controlled at 100 °C, the heating - up time is 30 mins, the holding time is 1 h, and it is cooled to room temperature with the furnace;

[0092] 3. Electrodes are fabricated on the annealed graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction. First, a titanium layer with a thickness in the range of 5 nm is evaporated, and then a gold layer with a thickness in the range of 50 nm is continuously evaporated.

[0093] Comparative Example 3

[0094] This comparative example provides a heterojunction structure, which is different from that in Example 1 in that a tin disulfide / hafnium disulfide heterojunction is used. The specific steps are as follows:

[0095] 1. Transfer 10 - 20 nm of hafnium disulfide to a part of tin disulfide by mechanical exfoliation and stack to form a tin disulfide / hafnium disulfide heterojunction;

[0096] 2. Construct electrodes on the annealed tin disulfide / hafnium disulfide heterojunction. First, evaporate a titanium layer with a thickness range of 5 nm, and then continue to evaporate a gold layer with a thickness range of 50 nm.

[0097] Performance testing

[0098] Use the tunneling field effect transistor provided in Example 1 to perform Raman spectroscopy characterization, AFM testing, and current - voltage (I - V) curve testing.

[0099] As Figure 4 shown, Raman spectroscopy characterization was performed on the tin disulfide / hafnium disulfide device. The abscissa represents the Raman shift (cm -1 ), and the ordinate represents the relative intensity (a.u.). The Raman peaks of tin disulfide and hafnium disulfide can be observed from the figure. Among them, A 1g (318 cm -1 ) is the Raman peak of tin disulfide, and E g (261 cm -1 ) and A 1g (340 cm -1 ) are the Raman peaks of hafnium disulfide; It can be seen from the above that the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide heterojunction can be successfully prepared by using the preparation method of the present invention.

[0100] As Figure 5 shown, AFM testing was performed on the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide device. The abscissa represents the distance (μm), and the ordinate represents the height (a.u.). The thickness of hafnium disulfide is about 30 nm, and the thickness of tin disulfide is about 6 nm.

[0101] As Figure 6 shown, the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide device was subjected to I ds - V ds curve testing. The abscissa represents the source - drain voltage ( V ds ), and the ordinate represents the source - drain current ( I ds), a forward rectifier is obtained when the gate voltage is 3 V, an Esaki diode is obtained when the gate voltage is 0.1 V, and a reverse rectifier is obtained when the gate voltage is -3 V. Thus, the integration of three characteristics including a forward rectifier, an Esaki diode, and a reverse rectifier is successfully achieved in the same heterojunction.

[0102] As Figure 7 shown, the optoelectronic properties of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide device were characterized, and its light response performance with time dependence was evaluated. Due to the light-induced band alignment regulation, the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide device exhibits broadband detection characteristics and reaches the maximum value at 455 nm.

[0103] The tunneling field effect transistors provided in Comparative Examples 1 to 3 were used for I-V curve testing.

[0104] As Figure 8 shown, in Comparative Example 1, a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide / hexagonal boron nitride heterojunction was used, with the bottom hexagonal boron nitride as the dielectric layer and the top hexagonal boron nitride as the encapsulation layer. A relatively high source-drain current can be achieved at a small voltage. However, compared with the I-V curve test results of Example 1, due to the relatively complex preparation and inevitable interface problems, it is impossible to obtain three different types of devices in the same heterojunction by regulating the gate voltage.

[0105] As Figure 9 shown, a graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction was used, with hexagonal boron nitride as the dielectric layer. A relatively high source-drain current can be achieved at a small voltage. However, compared with the I-V curve test results of Example 1, three different types of devices were not obtained in the same structure by regulating the gate voltage.

[0106] As Figure 10 shown, a tin disulfide / hafnium disulfide heterojunction was used. To obtain a source-drain current corresponding to that of Example 1, it is necessary to greatly increase the gate voltage. Therefore, compared with the I-V curve test results of Example 1, the gate voltage is high, the energy consumption is large, and the obtained device does not achieve different performances.

[0107] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural transformation made using the content of the specification of the present invention under the inventive concept of the present invention, or any direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A tunneling field effect transistor, characterized in that: It includes a substrate and an insulating layer, a conductive layer, a dielectric layer, a heterojunction layer and a packaging layer stacked in sequence on one side of the substrate; The heterojunction layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer includes a tin disulfide layer, the second semiconductor layer includes a hafnium disulfide layer, and the encapsulation layer includes a hafnium oxide layer; Wherein, the hafnium oxide layer is obtained by plasma oxidation of the hafnium disulfide layer.

2. The tunneling field effect transistor according to claim 1, characterized in that: The tin disulfide layer and the hafnium disulfide layer are both disposed on the dielectric layer, and the hafnium disulfide layer is at least partially stacked on the tin disulfide layer, so that the tin disulfide layer and the hafnium disulfide layer are cross-disposed.

3. The tunneling field effect transistor according to claim 1, characterized in that: The thickness of the tin disulfide layer is 5-15 nm, and the thickness of the hafnium disulfide layer is 20-30 nm.

4. The tunneling field effect transistor according to claim 1, characterized in that: The tunneling field effect transistor further includes a source electrode, a drain electrode and a gate electrode. The source electrode is arranged on the first semiconductor layer, the drain electrode is arranged on the second semiconductor layer, and the gate electrode is arranged on the conductive layer.

5. The tunneling field effect transistor according to claim 4, characterized in that: The materials of the source electrode, the drain electrode and the gate electrode include stacked titanium layers and gold layers; The thickness of the titanium layer is 4-6 nm, and the thickness of the gold layer is 45-55 nm.

6. The tunneling field effect transistor according to claim 1, characterized in that: The substrate comprises a silicon substrate, the insulating layer comprises a silicon dioxide layer, the conductive layer comprises a graphene layer, and the dielectric layer comprises a hexagonal boron nitride layer; The thickness of the silicon dioxide layer is 285-300 nm, the thickness of the graphene layer is 8-12 nm, and the thickness of the hexagonal boron nitride layer is 8-12 nm.

7. A method for preparing a tunneling field effect transistor, characterized in that: The following steps are involved: S10. Providing a substrate covered with an insulating layer; S20. Disposing a conductive layer on the insulating layer; S30. Disposing a dielectric layer on the conductive layer; S40. Disposing a first semiconductor layer and a second semiconductor layer on the dielectric layer, wherein the first semiconductor layer and the second semiconductor layer are partially stacked and the other parts are disposed on the dielectric layer to obtain a stacked body, wherein the first semiconductor layer includes a tin disulfide layer, and the second semiconductor layer includes a hafnium disulfide layer; S50. Plasma-oxidizing the stack to oxidize the surface of hafnium disulfide to obtain a hafnium oxide layer, wherein the hafnium oxide layer forms an encapsulation layer; S60. Perform vacuum annealing, set the source electrode on the first semiconductor layer, set the drain electrode on the second semiconductor layer, and set the gate electrode on the conductive layer to obtain a tunneling field effect transistor.

8. The method for preparing a tunneling field effect transistor according to claim 7, characterized in that: Step S20 comprises: after obtaining a graphene layer by a mechanical exfoliation method, transferring the graphene layer to the substrate, wherein the graphene layer forms the conductive layer; Step S30 includes: after peeling the hexagonal boron nitride layer to polydimethylsiloxane, transferring the hexagonal boron nitride layer to the conductive layer by dry transfer, wherein the hexagonal boron nitride layer forms the dielectric layer; Step S40 includes: disposing a first semiconductor layer on the dielectric layer, and disposing a second semiconductor layer on the first semiconductor layer and the dielectric layer; In step S50, during the plasma oxidation treatment, the plasma power is 25-35 W, the oxygen flow rate is 3-6 sccm, the pressure is 450-500 mTorr, and the duration is 8-12 min; In step S60, the vacuum annealing temperature is 100-150°C, the heating time is 20-30 min, and the holding time is 30-60 min; In step S60 , the source electrode and the drain electrode are disposed on the first semiconductor layer and the second semiconductor layer respectively by evaporation.

9. A photoelectric detector, characterized in that: The photodetector comprises a tunneling field effect transistor as claimed in any one of claims 1 to 6, or a tunneling field effect transistor prepared by the method for preparing a tunneling field effect transistor as claimed in claim 7 or 8.

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