Display device

Abstract

The display device of the present invention comprises: a base layer; a circuit layer disposed on the base layer and including 1-1 pixel circuits and 1-2 pixel circuits; and a light emitting element layer disposed on the circuit layer and including a first light emitting element and a second light emitting element, each of the first light emitting element and the second light emitting element including a first electrode, an emission layer, a second electrode, and a pixel defining film having a pixel opening defined therein, the pixel opening exposing a portion of the first electrode, wherein each of the 1-1 pixel circuit and the 1-2 pixel circuit comprises a driving transistor and a gate conductive layer, the driving transistor comprises a source electrode, a drain electrode, an active region and a gate electrode, and the gate conductive layer comprises a gate electrode. And a region where the first electrode of the first light emitting element overlaps the gate conductive layer of the 1-1 pixel circuit in plan view and a region where the first electrode of the second light emitting element overlaps the gate conductive layer of the 1-2 pixel circuit in plan view have the same surface area, thereby improving display quality.

Description

Technical Field

[0001] The present disclosure relates to a display device including an oxide transistor. Background Art

[0002] The display device includes pixels and driving circuits (e.g., scan driving circuits and data driving circuits) configured to control the pixels. Each pixel may include a display element and a pixel driving circuit configured to control the display element. The pixel driving circuit may include an organically connected transistor.

[0003] The scan driving circuit and / or the data driving circuit may be formed by the same process as the pixel. The scan driving circuit and / or the data driving circuit may include organically connected transistors. Summary of the invention

[0004] Technical issues

[0005] A display device having improved display quality is disclosed.

[0006] Technical Solution

[0007] An embodiment provides a display device, which may include: a substrate layer; a circuit layer, including a 1-1 pixel circuit and a 1-2 pixel circuit, the circuit layer being disposed on the substrate layer; and a light-emitting element layer, including a first light-emitting element and a second light-emitting element, each of the first light-emitting element and the second light-emitting element including a first electrode, an emission layer, a second electrode and a pixel defining film, the pixel defining film including a pixel opening exposing a portion of the first electrode. The light-emitting element layer may be disposed on the circuit layer. The 1-1 pixel circuit and the 1-2 pixel circuit may each include a driving transistor and a gate conductive layer, the driving transistor including a source electrode, a drain electrode, an active region and a gate electrode. The area of ​​the first electrode of the first light-emitting element overlapping the gate conductive layer of the 1-1 pixel circuit in a plan view may be equal to the area of ​​the first electrode of the second light-emitting element overlapping the gate conductive layer of the 1-2 pixel circuit in a plan view.

[0008] In an embodiment, the first electrode of the second light emitting element and the gate conductive layer may define the first electrode and the second electrode of the first capacitor, respectively, and the first electrode of the second light emitting element and the gate conductive layer may define the first electrode and the second electrode of the second capacitor, respectively.

[0009] In an embodiment, the capacitance of the first capacitor may be substantially equal to the capacitance of the second capacitor.

[0010] In an embodiment, in a plan view, a pixel opening of the first light emitting element may overlap with a lower side of the 1-1 pixel circuit. In a plan view, a pixel opening of the second light emitting element may overlap with an upper side of the 1-2 pixel circuit.

[0011] In an embodiment, the driving transistor may include an oxide semiconductor.

[0012] In an embodiment, the 1-1 pixel circuit may be arranged on the 1-2 pixel circuit in the first direction. The circuit layer may further include a 1-3 pixel circuit and a 1-4 pixel circuit, the 1-3 pixel circuit being adjacent to the 1-1 pixel circuit in a second direction intersecting the first direction, and the 1-4 pixel circuit being adjacent to the 1-2 pixel circuit in the second direction. The light-emitting element layer may include a third light-emitting element and a fourth light-emitting element, the third light-emitting element being arranged on the 1-3 pixel circuit, and the fourth light-emitting element being arranged on the 1-4 pixel circuit. The third light-emitting element and the fourth light-emitting element may each include a first electrode, an emission layer, a second electrode, and a pixel defining film, the pixel defining film including a pixel opening exposing a portion of the first electrode. The 1-3 pixel circuit and the 1-4 pixel circuit may each include a first portion, a second portion, and a third portion divided in the first direction. In a plan view, the first electrode of the third light-emitting element may overlap with the first portion to the third portion of the 1-3 pixel circuit. In a plan view, the first electrode of the fourth light-emitting element may overlap with the first portion to the third portion of the 1-4 pixel circuit. In a plan view, the pixel opening of the third light-emitting element may overlap with the second portion and the third portion of the 1-3 pixel circuit. In a plan view, a pixel opening of the fourth light emitting element may overlap with the first portion and the second portion of the 1-4 pixel circuit.

[0013] In an embodiment, the first light emitting element and the second light emitting element may emit a first light.

[0014] In an embodiment, the first light emitting element may be electrically connected to the 1-1 pixel circuit, and the second light emitting element may be electrically connected to the 1-2 pixel circuit.

[0015] In an embodiment, the light emitting element layer may further include a fifth light emitting element that emits a second light different from the first light and is adjacent to the first light emitting element. The first light emitting element may be connected to the fifth light emitting element.

[0016] In an embodiment, a display device may include: a substrate layer; a circuit layer including a 1-1 pixel circuit and a 1-2 pixel circuit adjacent to the 1-1 pixel circuit in a first direction, the circuit layer being disposed on the substrate layer; and a light-emitting element layer including a first light-emitting element disposed on the 1-1 pixel circuit and a second light-emitting element disposed on the 1-2 pixel circuit, the light-emitting element layer being disposed on the circuit layer. The first light-emitting element and the second light-emitting element may each include a first electrode, an emission layer, a second electrode, and a pixel defining film, the pixel defining film including a pixel opening exposing a portion of the first electrode. The 1-1 pixel circuit and the 1-2 pixel circuit may each include a first portion, a second portion, and a third portion divided in the first direction. In a plan view, the first electrode of the first light-emitting element may overlap with the first portion to the third portion of the 1-1 pixel circuit. In a plan view, the first electrode of the second light-emitting element may overlap with the first portion to the third portion of the 1-2 pixel circuit. In a plan view, the pixel opening of the first light-emitting element may overlap with the first portion and the second portion of the 1-1 pixel circuit. In a plan view, the pixel opening of the second light-emitting element may overlap with the second portion and the third portion of the 1-2 pixel circuit.

[0017] In an embodiment, in a plan view, a pixel opening of the first light emitting element may not overlap with a third portion of the 1-1 pixel circuit. In a plan view, a pixel opening of the second light emitting element may not overlap with a first portion of the 1-2 pixel circuit.

[0018] In an embodiment, the 1-1 pixel circuit and the 1-2 pixel circuit may both include a driving transistor and a gate conductive layer, the driving transistor including a source, a drain, an active region, and a gate. The area of ​​the first electrode of the first light-emitting element overlapping the gate conductive layer of the 1-1 pixel circuit in a plan view may be equal to the area of ​​the first electrode of the second light-emitting element overlapping the gate conductive layer of the 1-2 pixel circuit in a plan view.

[0019] In an embodiment, the driving transistor may be an oxide semiconductor.

[0020] In an embodiment, the 1-1 pixel circuit may be arranged on the 1-2 pixel circuit in the first direction. The circuit layer may further include a 1-3 pixel circuit and a 1-4 pixel circuit, the 1-3 pixel circuit being adjacent to the 1-1 pixel circuit in a second direction intersecting the first direction, and the 1-4 pixel circuit being adjacent to the 1-2 pixel circuit in the second direction. The light-emitting element layer may include a third light-emitting element and a fourth light-emitting element, the third light-emitting element being arranged on the 1-3 pixel circuit, and the fourth light-emitting element being arranged on the 1-4 pixel circuit. The third light-emitting element and the fourth light-emitting element may each include a first electrode, an emission layer, a second electrode, and a pixel defining film, the pixel defining film including a pixel opening exposing a portion of the first electrode. The 1-3 pixel circuit and the 1-4 pixel circuit may each include a first portion, a second portion, and a third portion divided in the first direction. In a plan view, the first electrode of the third light-emitting element may overlap with the first portion to the third portion of the 1-3 pixel circuit. In a plan view, the first electrode of the fourth light-emitting element may overlap with the first portion to the third portion of the 1-4 pixel circuit. In a plan view, the pixel opening of the third light-emitting element may overlap with the second portion and the third portion of the 1-3 pixel circuit. In a plan view, a pixel opening of the fourth light emitting element may overlap with the first portion and the second portion of the 1-4 pixel circuit.

[0021] In an embodiment, the first light emitting element and the second light emitting element may emit a first light.

[0022] In an embodiment, the first light emitting element may be electrically connected to the 1-1 pixel circuit, and the second light emitting element may be electrically connected to the 1-2 pixel circuit.

[0023] In an embodiment, the light emitting element layer may further include a fifth light emitting element that emits a second light different from the first light and is adjacent to the first light emitting element. The first light emitting element may be connected to the fifth light emitting element.

[0024] In an embodiment, a display device may include: a substrate layer; a first pixel circuit unit to a fourth pixel circuit unit, arranged in one direction; and a first light-emitting unit to a fourth light-emitting unit, arranged in the one direction, and respectively disposed on the first pixel circuit unit to the fourth pixel circuit unit. The first light-emitting unit to the fourth light-emitting unit may each include a 1-1 light-emitting element, a 1-2 light-emitting element, a 1-3 light-emitting element, and a 1-4 light-emitting element. The 1-1 light-emitting element to the 1-4 light-emitting element may each include a first electrode, an emission layer, a second electrode, and a pixel defining film, the pixel defining film including a pixel opening exposing a portion of the first electrode. The first pixel circuit unit to the fourth pixel circuit unit may each include a first pixel circuit, a second pixel circuit, and a third pixel circuit, the first pixel circuit is electrically connected to the 1-1 light-emitting element and the 1-2 light-emitting element, the second pixel circuit is electrically connected to the 1-2 light-emitting element, the third pixel circuit is electrically connected to the 1-3 light-emitting element, the first pixel circuit to the third pixel circuit each include a driving transistor and a gate conductive layer, the driving transistor includes a source, a drain, an active area, and a gate. The areas where the first electrodes of the 1-1 light emitting element and the 1-2 light emitting element overlap with the gate conductive layer of the first pixel circuit in a plan view may be equal in the first pixel circuit unit and the fourth pixel circuit unit.

[0025] In an embodiment, the pixel opening of the 1-1 light emitting element and the pixel opening of the 1-2 light emitting element may be respectively disposed at different positions in the first pixel circuit unit and the fourth pixel circuit unit.

[0026] In an embodiment, the 1-1 light emitting element and the 1-2 light emitting element may emit a first light, the 1-3 light emitting element may emit a second light different from the first light, and the 1-4 light emitting element may emit a third light different from the first light and the second light.

[0027] Beneficial Effects

[0028] The display device of the embodiment can improve display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic block diagram of a display device according to a disclosed embodiment;

[0030] Figure 2 is an equivalent circuit diagram of a pixel according to the disclosed embodiment;

[0031] Figure 3 Is used to drive Figure 2 Schematic waveform diagram of a driving signal of a pixel shown in ;

[0032] Figure 4 is a view schematically showing a display panel according to a disclosed embodiment;

[0033] Figure 5 is a schematic cross-sectional view of a display panel according to a disclosed embodiment;

[0034] Figure 6 is a schematic plan view of a display panel according to a disclosed embodiment;

[0035] Figure 7 is a schematic plan view of a pixel circuit according to a disclosed embodiment;

[0036] Figure 8 is a schematic plan view showing a portion of a pattern included in a pixel circuit according to a disclosed embodiment;

[0037] FIG. 9A is a schematic plan view showing components of a display panel according to a disclosed embodiment;

[0038] FIG. 9B is a schematic plan view showing components of a display panel according to a disclosed embodiment;

[0039] Fig.10 is a schematic plan view of a display panel according to a comparative example;

[0040] 11A and 11B are schematic plan views showing components of a display panel according to a comparative example; and

[0041] Fig.12 is a schematic plan view of a pixel according to a disclosed embodiment. DETAILED DESCRIPTION

[0042] The disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. However, the disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0043] In the specification, when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, this means that the element may be directly disposed on / directly connected to / directly coupled to the other element, or a third element may be disposed therebetween. In addition, the connection may be physical and / or electrical in nature.

[0044] In the description, "directly disposed" may indicate that no layer, film, region, plate, etc. is added between a portion of a layer, film, region, plate, etc. and other portions. For example, "directly disposed" may indicate that no additional member such as an adhesive member is disposed between two layers or two members. The same reference numerals denote the same elements.

[0045] In the accompanying drawings, in order to effectively describe the technical content, the thickness, ratio and size of the elements can be exaggerated. In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purpose of its meaning and interpretation. For example, "A and / or B" can be understood to mean any combination including "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction, and can be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one (kind / person) in ... " is intended to include the meaning of "at least one (kind / person) selected from the group of ... " for the purpose of its meaning and interpretation. For example, "at least one (kind / person) in A and B" can be understood to mean any combination including "A, B, or A and B".

[0046] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the disclosed teachings, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0047] Terms such as "below", "on the lower side", "above", or "on the upper side" may be used to describe the relationship of components shown in the drawings. The terms are used as relative concepts and are described with reference to directions indicated in the drawings. In the specification, "disposed on" may mean not only disposed on the top surface but also disposed on the bottom surface.

[0048] It should be understood that the terms “includes,” “comprising,” and “having” are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof in the disclosure, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0049] The term "superimposed" or "overlapping" means that a first object can be above or below or to the side of a second object, and vice versa. In addition, the term "superimposed" may include stacked, stacked, facing or facing, extending above, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0050] When an element is described as “not “overlaying” or “not overlapping” another element, this may include the elements being spaced apart, offset or biased from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0051] As used herein, "about" or "approximately" or "substantially" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0052] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the disclosure belongs. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0053] Figure 1 is a schematic block diagram of a display device DD according to a disclosed embodiment. The display device DD may include a timing controller TC, a scan drive circuit SDC, a data drive circuit DDC, and a display panel DP. In an embodiment, the display panel DP is described as a light-emitting display panel. The light-emitting display panel may include an organic light-emitting display panel or an inorganic light-emitting display panel.

[0054] The timing controller TC can receive an input image signal, convert the data format of the input image signal to meet the interface specification with the scan driving circuit SDC, and generate image data D-RGB. The timing controller TC outputs the image data D-RGB and various control signals DCS and SCS.

[0055] The scan driving circuit SDC may receive a scan control signal SCS from the timing controller TC. The scan control signal SCS may include a vertical start signal for starting the operation of the scan driving circuit SDC, a clock signal for determining the output timing of the signal, etc. The scan driving circuit SDC may generate a scan signal and sequentially output the signal to the corresponding scan signal lines SL11 to SL1n. The scan driving circuit SDC may generate a light emitting control signal in response to the scan control signal SCS and output the light emitting control signal to the corresponding light emitting signal lines EL1 to ELn.

[0056] although Figure 1 It is shown that a plurality of scan signals and a plurality of light emission control signals are output from one scan drive circuit SDC, but the disclosed embodiment is not limited thereto. In the disclosed embodiment, the display device DD may include a plurality of scan drive circuits. In the disclosed embodiment, a drive circuit that generates and outputs a plurality of scan signals and a drive circuit that generates and outputs a plurality of light emission control signals may be formed separately.

[0057] The data driving circuit DDC may receive a data control signal DCS and image data D-RGB from a timing controller TC. The data driving circuit DDC may convert the image data D-RGB into a data signal and output the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal may be an analog voltage corresponding to a grayscale value of the image data D-RGB.

[0058] The display panel DP may include a plurality of groups of scan lines. Figure 1 The first group of scan signal lines SL11 to SL1n is shown as an example. The display panel DP may include light emitting signal lines EL1 to ELn, data lines DL1 to DLm, first, second, third and fourth voltage lines VL1, VL2, VL3 and VL4, and pixels PX.

[0059] The first group of scan signal lines SL11 to SL1n may extend in the first direction DR1 and may be arranged in the second direction DR2. The data lines DL1 to DLm may cross (intersect) the first group of scan signal lines SL11 to SL1n.

[0060] The first voltage line VL1 may receive a first power voltage ELVSS. The second voltage line VL2 may receive a second power voltage ELVDD. The second power voltage ELVDD may have a higher level than the first power voltage ELVSS. The third voltage line VL3 may receive a reference voltage Vref (hereinafter, referred to as the first voltage). The fourth voltage line VL4 may receive an initialization voltage Vint (hereinafter, referred to as the second voltage). The first voltage Vref may have a lower level than the second power voltage ELVDD. The second voltage Vint may have a lower level than the second power voltage ELVDD. In an embodiment, the second voltage Vint may have a lower level than the first voltage Vref and the first power voltage ELVSS.

[0061] At least one of the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, and the fourth voltage line VL4 may include at least one of a line extending in the first direction DR1 and a line extending in the second direction DR2. Even if the voltage line extending in the first direction DR1 and the voltage line extending in the second direction DR2 are arranged Figure 4 Even when the plurality of insulating layers 10 to 40 shown in FIG. 4 are on different layers, they can be electrically connected to each other.

[0062] Referenced above Figure 1The display device DD according to the embodiment is described, but the display device DD according to the disclosed embodiment is not limited thereto. According to the configuration of the pixel driving circuit, a signal line may be further added or omitted. The electrical connection relationship between one pixel PX and the signal line may be changed.

[0063] The pixel PX may include a plurality of groups that generate light of different colors. For example, the pixel PX may include a red pixel that generates red light, a green pixel that generates green light, and a blue pixel that generates blue light. The light-emitting diodes of the red pixel, the light-emitting diodes of the green pixel, and the light-emitting diodes of the blue pixel may include emission layers of different materials.

[0064] The pixel driving circuit may include a transistor and at least one capacitor. At least one of the scan driving circuit SDC and the data driving circuit DDC may include a plurality of transistors formed by the same process as the pixel driving circuit.

[0065] The above-mentioned signal lines, pixels PX, scan driving circuits SDC, and data driving circuits DDC may be formed on the base substrate by a process including a photolithography process and an etching process.

[0066] Multiple insulating layers may be formed on the base substrate by multiple deposition processes and coating processes. The insulating layer may include an organic layer and / or an inorganic layer. Any of the insulating layers may include a plurality of insulating patterns. The insulating layers may overlap with the pixels PX. Contact holes may be formed in the insulating layer. The contact holes may be arranged according to a predetermined or selectable rule for each of the pixels PX.

[0067] Figure 2 is a pixel PX according to the disclosed embodiment ij Equivalent circuit diagram of . Figure 3 Is used to drive Figure 2 The pixel PX shown in ij Schematic waveform diagram of the driving signal.

[0068] Figure 2 The first group of scanning lines SL11 to SL1n (see Figure 1 ) and is connected to the data lines DL1 to DLm (see Figure 1 ) of the pixel PX of the j-th data line DLj ij As a typical example. Pixel PX ij It can be connected to the i-th scan line SL2i among the second group of scan lines and to the i-th scan line SL3i among the third group of scan lines.

[0069] In an embodiment, the pixel driving circuit may include a first transistor T1 to a fifth transistor T5, a storage capacitor Cst, a holding capacitor Chold, and a light emitting diode OLED. In an embodiment, the first transistor T1 to the fifth transistor T5 are described as N-type transistors. However, the disclosed embodiment is not limited thereto, and at least one of the first transistor T1 to the fifth transistor T5 may be a P-type transistor. In the disclosed embodiment, at least one of the first transistor T1 to the fifth transistor T5 may be omitted, or may be provided in the pixel PX. ij The method further includes an additional transistor.

[0070] In the embodiment, the first transistor T1 to the fifth transistor T5 are each shown to include two gates, but at least one transistor may include only one gate. The upper gates G2-1, G3-1, G4-1 and G5-1 of each of the second transistor T2 to the fifth transistor T5 and the lower gates G2-2, G3-2, G4-2, G5-2 are shown to be electrically connected to each other, but the disclosed embodiments are not limited thereto. The lower gates G2-2, G3-2, G4-2 and G5-2 of each of the second transistor T2 to the fifth transistor T5 may be floating electrodes.

[0071] In an embodiment, the first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. The node to which the gate G1-1 of the first transistor T1 is connected may be defined as a first node ND1, and the node to which the source S1 of the first transistor T1 is connected may be defined as a second node ND2.

[0072] The light emitting diode OLED may include a first electrode electrically connected to the first node ND1, a second electrode receiving the first power voltage ELVSS, and an emission layer disposed between the first electrode and the second electrode. A detailed description of the light emitting diode OLED will be described later.

[0073] The first transistor T1 may be electrically connected between a second voltage line VL2 receiving a second power voltage ELVDD and a second node ND2. The first transistor T1 may include a source S1 (hereinafter, referred to as a first source), a drain D1 (hereinafter, referred to as a first drain), a semiconductor region, and a gate G1-1 (hereinafter, referred to as an upper gate) electrically connected to the second node ND2. The first transistor T1 may also include a gate G1-2 (hereinafter, referred to as a lower gate) connected to the second node ND2.

[0074] The second transistor T2 may be electrically connected between the first data line DLj and the first node ND1. The second transistor T2 may include a source S2 connected to the first node ND1, a drain D2 connected to the first data line DLj, a semiconductor region, and a gate G2-1 (hereinafter referred to as the second upper gate) connected to the i-th scan line SL1i of the first group. The second transistor T2 may also include a gate G2-2 (hereinafter referred to as the second lower gate) electrically connected to the second upper gate G2-1. The third transistor T3 to the fifth transistor T5, which will be described later, may include upper gates G3-1, G4-1, and G5-1 corresponding to the second upper gate G2-1 and the second lower gate G2-2, and lower gates G3-2, G4-2, and G5-2.

[0075] The third transistor T3 may be electrically connected between the first node ND1 and a third voltage line VL3 receiving the first voltage Vref. The third transistor T3 may include a drain D3 (hereinafter, referred to as a third drain) connected to the first node ND1, a source S3 (hereinafter, referred to as a third source) connected to the third voltage line VL3, a semiconductor region, and a third upper gate G3-1 connected to the i-th scan line SL2i of the second group.

[0076] The fourth transistor T4 may be electrically connected between a fourth voltage line VL4 receiving the second voltage Vint and the second node ND2. The second transistor T4 may include a drain D4 (hereinafter, referred to as a fourth drain) connected to the second node ND2, a source S4 (hereinafter, referred to as a fourth source) connected to the fourth voltage line VL4, a semiconductor region, and a fourth upper gate G4-1 connected to the i-th scan line SL3i of the third group.

[0077] The fifth transistor T5 may be electrically connected between the second voltage line VL2 and the first drain D1 or the first source S1. In an embodiment, the fifth transistor T5 may include a source S5 (hereinafter, referred to as a fifth source) connected to the second voltage line VL2, a drain D5 (hereinafter, referred to as a fifth drain) connected to the first drain D1, a semiconductor region, and a fifth upper gate G5-1 connected to the i-th light emitting signal line ELi.

[0078] The storage capacitor Cst may be electrically connected between the first node ND1 and the second node ND2. The storage capacitor Cst may include a first electrode E1-1 connected to the first node ND1 and a second electrode E1-2 connected to the second node ND2.

[0079] The holding capacitor Chold may be electrically connected between the second voltage line VL2 and the second node ND2. The holding capacitor Chold may include a first electrode E2-1 connected to the second voltage line VL2 and a second electrode E2-2 connected to the second node ND2.

[0080] The gap capacitor Cga may be formed between the upper gate G1-1 of the first transistor T1 and the anode electrode of the light emitting diode OLED, and the gap capacitor Cga may be a parasitic capacitor. Regarding the gap capacitor Cga, the upper gate G1-1 of the first transistor T1 may be the first electrode E3-1, and the anode electrode of the light emitting diode OLED may be the second electrode E3-2. For example, the gap capacitor Cga may be electrically connected between the first node ND1 and the second node ND2. Therefore, the gap capacitor Cga may be connected in parallel to the storage capacitor Cst, and the capacitance of the gap capacitor Cga may be added to the capacitance of the storage capacitor Cst.

[0081] Will refer to Figure 2 and Figure 3 Let's describe the pixel PX in more detail. ij Operation of the display device DD (see Figure 1 ) can display an image for each frame period. The signal lines of each of the first group of scan lines, the second group of scan lines, the third group of scan lines, and the light emitting signal lines can be sequentially scanned during the frame period. Figure 3 A portion of a frame period is shown.

[0082] Reference Figure 3 , the signals Ei, GRi, GWi and GIi may all have a high level V-HIGH during a portion of the period, and have a low level V-LOW during a portion of the period. When the corresponding control signal has a high level V-HIGH, the above-mentioned N-type first transistor T1 to fifth transistor T5 may be turned on.

[0083] During the initialization period IP, the third transistor T3 and the fourth transistor T4 may be turned on. The first node ND1 may be initialized to the first voltage Vref. The second node ND2 may be initialized to the second voltage Vint. The storage capacitor Cst may be initialized to the difference between the first voltage Vref and the second voltage Vint. The holding capacitor Chold may be initialized to the difference between the second power voltage ELVDD and the second voltage Vint.

[0084] During the compensation period CP, the third transistor T3 and the fifth transistor T5 may be turned on. In the storage capacitor Cst, a voltage corresponding to the threshold voltage of the first transistor T1 may be compensated.

[0085] During the write period WP, ​​the second transistor T2 may be turned on. The second transistor T2 may output a voltage corresponding to the data signal DS. As a result, the voltage value corresponding to the data signal DS may be charged in the storage capacitor Cst. The data signal DS that compensates for the threshold voltage of the first transistor T1 may be charged in the storage capacitor Cst. The threshold voltage of the driving transistor may be adjusted for the pixel PX (see Figure 1 ) and regardless of the deviation of the threshold voltage of the driving transistor, Figure 2 and Figure 3 The pixel PX shown in ij A current having a magnitude proportional to the data signal DS may be supplied to the light emitting diode OLED.

[0086] Thereafter, during the light emission period, the fifth transistor T5 may be turned on. The first transistor T1 may provide a current corresponding to the voltage value stored in the storage capacitor Cst to the light emitting diode OLED. The light emitting diode OLED may emit light having brightness corresponding to the data signal DS.

[0087] In the disclosed embodiment, by setting the ij The values ​​of the generated gap capacitors Cga are controlled to be equal, and the values ​​of the capacitances formed between the first node ND1 and the second node ND2 (for example, the sum of the capacitances of the storage capacitor Cst and the gap capacitor Cga) can be controlled to be equal for each pixel. ij Display device DD (see Figure 1 ) can have improved display quality.

[0088] Figure 4 is a view schematically illustrating a display panel DP according to a disclosed embodiment.

[0089] Figure 4 A light emitting element layer DP-OLED and a circuit layer DP-CL included in the display panel DP are shown.

[0090] The light emitting element layer DP-OLED may include a light emitting element unit EDU. In an embodiment, the light emitting element unit EDU may include first to fourth light emitting element units EDU1, EDU2, EDU3, and EDU4 adjacent to each other. The light emitting element layer DP-OLED may include a structure in which the first to fourth light emitting element units EDU1, EDU2, EDU3, and EDU4 are repeatedly arranged on a plane.

[0091] In the first direction DR1 , the second light emitting device unit EDU2 may be disposed below the first light emitting device unit EDU1 , and the fourth light emitting device unit EDU4 may be disposed below the third light emitting device unit EDU3 .

[0092] In the second direction DR2 , the third light emitting element unit EDU3 may be disposed below the first light emitting element unit EDU1 , and the fourth light emitting element unit EDU4 may be disposed below the second light emitting element unit EDU2 .

[0093] The first to fourth light emitting element units EDU1, EDU2, EDU3 and EDU4 may each include first light emitting elements ED1-1, ED2-1, ED3-1 and ED4-1 that emit first light, second light emitting elements ED1-2, ED2-2, ED3-2 and ED4-2 that emit second light different from the first light, and third light emitting elements ED1-3, ED2-3, ED3-3 and ED4-3 that emit third light different from the first light and the second light. Figure 4 The first to third light emitting elements ED1-1, ED2-1, ED3-1, ED4-1, ED1-2, ED2-2, ED3-2, ED4-2, ED1-3, ED2-3, ED3-3, and ED4-3 are shown with respect to the light emitting areas.

[0094] In the first light emitting element unit EDU1 according to the embodiment, the first light emitting element ED1-1 may be in a form extending in the first direction DR1, and in the second direction DR2, the second light emitting element ED1-2 and the third light emitting element ED1-3 may be disposed on one side of the first light emitting element ED1-1. The same description may be applied to the second to fourth light emitting element units EDU2, EDU3, and EDU4.

[0095] In the first direction DR1, the first light emitting element ED1-1 of the first light emitting element unit EDU1 may face the first light emitting element ED2-1 of the second light emitting element unit EDU2, and the first light emitting element ED3-1 of the third light emitting element unit EDU3 may face the first light emitting element ED4-1 of the fourth light emitting element unit EDU4.

[0096] A distance LL1 between the first light emitting element ED1-1 of the first light emitting element unit EDU1 and the first light emitting element ED2-1 of the second light emitting element unit EDU2 may be smaller than a distance LL2 between the first light emitting element ED3-1 of the third light emitting element unit EDU3 and the first light emitting element ED4-1 of the fourth light emitting element unit EDU4. The display panel DP according to the disclosed embodiment may include a structure as described above to have greater visibility than a case where the first light emitting elements ED1-1, ED2-1, ED3-1, and ED4-1 are disposed at the same position for each of the first to fourth light emitting element units EDU1, EDU2, EDU3, and EDU4.

[0097] For each of the first to fourth light emitting element units EDU1, EDU2, EDU3, and EDU4, the second light emitting elements ED1-2, ED2-2, ED3-2, and ED4-2 and the third light emitting elements ED1-3, ED2-3, ED3-3, and ED4-3 may all be disposed at the same position. However, the disclosed embodiments are not limited thereto.

[0098] The circuit layer DP-CL may be disposed below the light emitting element layer DP-OLED. The circuit layer DP-CL may include a plurality of pixel circuit units PCU. The pixel circuit unit PCU may be connected to a corresponding one of the light emitting element units EDU to drive the connected light emitting element unit EDU. Figure 4 1 to 3 pixel transistors T_B, T_G, and T_R as components of the pixel circuit unit PCU are shown. The first pixel transistors T_B, T_G, and T_R may be electrically connected to the first light emitting element ED1-1, ED1-2, and ED1-3, respectively. The first pixel transistors T_B, T_G, and T_R may all be driving transistors. For example, in an embodiment, the first pixel transistors T_B, T_G, and T_R may all correspond to the above reference Figure 1 A first transistor T1 is described.

[0099] The first pixel transistor T_B and the first light emitting element ED1-1 connected thereto may constitute a pixel. The second pixel transistor T_G and the second light emitting element ED1-2 connected thereto may constitute a pixel. The third pixel transistor T_R and the third light emitting element ED1-3 connected thereto may constitute a pixel. However, the disclosed embodiments are not limited thereto, and the first light emitting element unit EDU1 and the pixel circuit unit PCU connected thereto may be defined as a pixel.

[0100] Figure 5 is a schematic cross-sectional view of a display panel DP according to a disclosed embodiment. Figure 5 Included above Figure 4 A partial cross-sectional view of the display panel DP of the first light emitting element ED1-1 (hereinafter, referred to as the first light emitting element) of the first light emitting element unit EDU1 and the first light emitting element ED2-1 (hereinafter, referred to as the second light emitting element) of the second light emitting element unit EDU2 described in FIG.

[0101] The two first transistors T1 may be disposed under the first light emitting element ED1-1 and the second light emitting element ED2-1. The first light emitting element ED1-1 and the second light emitting element ED2-1 may be each disposed to overlap the first transistor T1 in a plan view.

[0102] In an embodiment, the two first transistors T1 may be electrically connected to the first light emitting element ED1-1 and the second light emitting element ED2-1. The two first transistors T1 may both be reference Figure 4 For example, in different parts of the display panel DP, the sources S1 of the two first transistors T1 may be electrically connected to the anode electrodes AE (or first electrodes) of the first and second light emitting elements ED1-1 and ED2-1.

[0103] However, the disclosed embodiments are not limited thereto. For example, at least one of the two first transistors T1 may not be connected to the first light emitting element ED1-1 or the second light emitting element ED2-1, but may be connected to the second light emitting elements ED1-2 and ED2-2 or the third light emitting elements ED1-3 and ED2-3. For example, the first light emitting element ED1-1 may be connected to the second light emitting element ED1-2 and ED2-2 or the third light emitting element ED1-3 and ED2-3 in a plan view. Figure 4 In another embodiment, the first light emitting element ED1-1 may be connected to the second pixel transistor T_G of the second light emitting element ED1-2 disposed adjacent to the first light emitting element ED1-1 in a plan view. Figure 4 The third pixel transistor T_R of the third light emitting element ED1 - 3 disposed adjacent to the first light emitting element ED1 - 1 is overlapped.

[0104] As mentioned above, Figure 5 The first transistor T1 shown in FIG. 1 is not necessarily connected to the first light emitting element ED1 - 1 or the second light emitting element ED2 - 1 , and the following description may be applied in the case where the first transistor T1 overlaps the light emitting element ED1 - 1 .

[0105] Reference Figure 5, the display panel DP may include a base layer BS, a circuit layer DP-CL disposed on the base layer BS, a light emitting element layer DP-OLED, and a thin film encapsulation layer TFE. The display panel DP may also include a functional layer such as an anti-reflection layer or a refractive index control layer. The circuit layer DP-CL may include at least an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. Hereinafter, the insulating layer may include an organic layer and / or an inorganic layer.

[0106] The base layer BS may be a synthetic resin layer including a synthetic resin. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide resin layer, and the material is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. The base layer BS may include a glass substrate, a metal substrate, and / or an organic / inorganic composite material substrate.

[0107] At least one inorganic layer may be formed on the upper surface of the base layer BS. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed as a multilayer. The multilayer inorganic layer may constitute a barrier layer BRL and / or a buffer layer BFL, which will be described later. The barrier layer BRL and the buffer layer BFL may be selectively provided.

[0108] The barrier layer BRL can prevent foreign matter from being introduced from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. A plurality of these layers may be provided, and the silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0109] A conductive layer (hereinafter, referred to as a first conductive layer) may be disposed on the barrier layer BRL. The first conductive layer may include a plurality of conductive patterns. Figure 5 A partial pattern of the first conductive layer is shown. A lower gate G1-2 is shown as an example of a conductive pattern of the first conductive layer.

[0110] The buffer layer BFL may be disposed on the barrier layer BRL to cover the lower gate G1-2. The buffer layer BFL may increase the bonding force between the base layer BS and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0111] The semiconductor layer may be disposed on the buffer layer BFL. The semiconductor layer may include a plurality of semiconductor patterns. The semiconductor pattern may include a metal oxide. The metal oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide containing zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and oxides thereof. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), indium zinc oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO) and / or zinc tin oxide (ZTO).

[0112] The semiconductor pattern may include a plurality of regions divided according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduction region) may have a greater conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduction region). The reduction region may be basically used as the source / drain or signal line of the transistor. The non-reduction region may basically correspond to the semiconductor region (or channel) of the transistor. For example, a portion of the semiconductor pattern may be the semiconductor region of the transistor, another portion may be the source / drain of the transistor, and another portion may be the signal transmission region.

[0113] The source S1, the semiconductor region A1, and the drain D1 of the first transistor T1 may be formed of a semiconductor pattern. The source S1 and the drain D1 of the first transistor T1 may extend from the semiconductor region A1 in opposite directions.

[0114] The lower gate G1-2 may function as a light blocking pattern. The lower gate G1-2 may be disposed below the semiconductor region A1 of the first transistor T1 to block light from the outside from being incident on the first transistor T1. The light blocking pattern may prevent external light from changing the voltage-current characteristics of the first transistor T1.

[0115] The first insulating layer 10 may be disposed on the buffer layer BFL. In an embodiment, the first insulating layer 10 may not be completely formed on the display panel DP but may be only a specific conductive pattern, which will be described later. The first insulating layer 10 may include a plurality of insulating patterns. Figure 4 The first insulating pattern 10 - 1 and the second insulating pattern 10 - 2 are shown as an example.

[0116] The first insulating pattern 10 - 1 may overlap a lower gate G1 - 2 and an upper gate G1 - 1 which will be described later. The second insulating pattern 10 - 2 may overlap a first conductive pattern P1 (or a gate conductive layer) which will be described later.

[0117] A conductive layer (hereinafter, referred to as a second conductive layer) may be disposed on the first insulating layer 10. The second conductive layer may include a plurality of conductive patterns each overlapping the insulating patterns 10-1 and 10-2 of the first insulating layer 10. Figure 5 The upper gate G1-1 and the first conductive pattern P1 are shown as examples of the conductive pattern of the second conductive layer. The second conductive layer and the first insulating layer may be etched by the same process, and thus the conductive pattern of the second conductive layer and the insulating pattern of the first insulating layer may have substantially the same shape.

[0118] The first conductive pattern P1 may define Figure 2 . In the cross-sectional view, the first conductive pattern P1 is shown to be spaced apart from the upper gate G1-1 of the first transistor T1, but the first conductive pattern P1 may have a single body shape with the upper gate G1-1 of the first transistor T1. For example, a first portion of any one conductive pattern may correspond to the upper gate G1-1 of the first transistor T1, and a second portion may correspond to the first conductive pattern P1.

[0119] The second insulating layer 20 covering the upper gate G1-1 and the first conductive pattern P1 may be disposed on the buffer layer BFL. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure.

[0120] A conductive layer (hereinafter, referred to as a third conductive layer) may be disposed on the second insulating layer 20. The third conductive layer may include a plurality of conductive patterns. Figure 5 The second conductive pattern P2 is shown as an example of a conductive pattern of the third conductive layer.

[0121] The second conductive pattern P2 overlapping the first conductive pattern P1 may be disposed on the second insulating layer 20. The second conductive pattern P2 may define Figure 2 , and a second electrode E1 - 2 of the storage capacitor Cst and a second electrode E2 - 2 of the holding capacitor Chold are shown in FIG.

[0122] The third insulating layer 30 covering the second conductive pattern P2 may be disposed on the second insulating layer 20. In an embodiment, the third insulating layer 30 may be an organic layer and may have a single-layer structure, but is not particularly limited.

[0123] A conductive layer (hereinafter, referred to as a fourth conductive layer) may be disposed on the third insulating layer 30. The fourth conductive layer may include a plurality of conductive patterns. Figure 2 An opening P3-OP may be defined in the third conductive pattern P3.

[0124] The fourth conductive layer may further include a plurality of connection electrodes. Figure 4 The first connection electrode CNE1 and the second connection electrode CNE2 are shown as examples. The first connection electrode CNE1 may be connected to the first source S1 through a contact hole H1 passing through the second insulating layer 20 and the third insulating layer 30 , and the second connection electrode CNE2 may be connected to the second conductive pattern P2 through a contact hole H2 passing through the third insulating layer 30 .

[0125] The fourth insulating layer 40 covering the third conductive layer may be disposed on the third insulating layer 30. In an embodiment, the fourth insulating layer 40 may be an organic layer and may have a single-layer structure, but is not particularly limited.

[0126] A conductive layer (hereinafter, referred to as a fifth conductive layer) may be provided on the fourth insulating layer 40. The fifth conductive layer may include a plurality of conductive patterns. The fifth conductive layer may include a third connection electrode CNE3. The third connection electrode CNE3 may be connected to the second connection electrode CNE2 through a contact hole H3 passing through the fourth insulating layer 40.

[0127] The fifth insulating layer 50 covering the fourth conductive layer may be disposed on the fourth insulating layer 40. In the embodiment, the fifth insulating layer 50 may be an organic layer and may have a single-layer structure, but is not particularly limited.

[0128] Anode electrodes AE-1 and AE-2 of the light emitting diode OLED may be disposed on the fifth insulating layer 50. A pixel defining layer PDL may be disposed on the fifth insulating layer 50. The anode electrodes AE-1 and AE-2 may be connected to the third connection electrode CNE3 through a contact hole H4 passing through the fifth insulating layer 50.

[0129] In an embodiment, the first light emitting element ED1-1 and the second light emitting element ED2-1 may each include anode electrodes AE-1 and AE-2, a hole control layer HCL, an emission layer EML, an electron control layer ECL, and a cathode electrode CE (or second electrode).

[0130] The pixel defining film PDL may expose at least a portion of the anode electrodes AE-1 and AE-2 to define the light emitting regions PXA-1 and PXA-2. The non-light emitting region NPXA may surround the light emitting regions PXA-1 and PXA-2 in a plan view.

[0131] For example, the first pixel opening PDL-OP1 of the pixel defining film PDL may expose the first area AR1 of the anode electrode AE-1 of the first light emitting element ED1-1 to define the light emitting area PXA-1. The second pixel opening PDL-OP2 of the pixel defining film PDL may expose the second area AR2 of the anode electrode AE-2 of the second light emitting element ED2-1 to define the light emitting area PXA-2. The area of ​​the anode electrode AE-1 of the first light emitting element ED1-1 and the area of ​​the anode electrode AE-2 of the second light emitting element ED2-1 may be equal, and in one anode electrode AE-1 and AE-2, the first area AR1 and the second area AR2 may be different areas. For example, the first area AR1 may not overlap with the upper gate G1-1 of the first transistor T1 in a plan view, and the second area AR2 may overlap with the upper gate G1-1 of the first transistor T1 in a plan view.

[0132] The anode electrodes AE-1 and AE-2 of the light-emitting elements ED1-1 and ED1-2 may form the upper gate G1-1 of the first transistor T1 and the gap capacitor Cga disposed thereunder. Specifically, the anode electrode AE-1 of the first light-emitting element ED1-1 may form the upper gate G1-1 of the first transistor T1 and the first gap capacitor C1, and the anode electrode AE-2 of the second light-emitting element ED2-1 may form the upper gate G1-1 of the first transistor T1 and the second gap capacitor C2. The first gap capacitor C1 and the second gap capacitor C2 may both correspond to the above reference Figure 2 Described is the gap capacitor Cga.

[0133] In the disclosed embodiment, the overlapping area of ​​the anode electrode AE-1 and the upper gate G1-1 of the first light emitting element ED1-1 may be equal to the overlapping area of ​​the anode electrode AE-2 and the upper gate G1-1 of the second light emitting element ED2-1. Therefore, the size of the first gap capacitor C1 may be substantially equal to the size of the second gap capacitor C2, and the deviation of the gap capacitors C1 and C2 between the adjacent light emitting elements ED1-1 and ED2-1 may be substantially zero.

[0134] The hole control layer HCL may be disposed on the anode electrodes AE-1 and AE-2. The hole control layer HCL may be commonly disposed in the light emitting area PXA and the non-light emitting area NPXA. In an embodiment, the hole control layer HCL may include a hole transport layer and a hole injection layer.

[0135] The emission layer EML may be disposed on the hole control layer HCL. The emission layer EML may be disposed in regions corresponding to the pixel openings PDL-OP1 and PDL-OP2. The emission layer EML may be formed in each of the light emitting elements ED1-1 and ED1-2, respectively. In the embodiment, a patterned emission layer EML is shown as an example, but the emission layer EML may be commonly disposed in the light emitting elements ED1-1 and ED1-2. The commonly disposed emission layer EML may generate white light or blue light. The emission layer EML may have a multilayer structure.

[0136] The electron control layer ECL is disposed on the emission layer EML. In an embodiment, the electron control layer ECL may include an electron transport layer and an electron injection layer. The cathode electrode CE is disposed on the electron control layer ECL. The electron control layer ECL and the cathode electrode CE are commonly disposed in the light emitting elements ED1-1 and ED1-2.

[0137] The thin film encapsulation layer TFE may be disposed on the cathode electrode CE. The thin film encapsulation layer TFE may be commonly disposed on the light emitting elements ED1-1 and ED1-2. In an embodiment, the thin film encapsulation layer TFE may directly cover the cathode electrode CE. In the disclosed embodiment, a coating directly covering the cathode electrode CE may be further provided. The thin film encapsulation layer TFE may include at least an inorganic layer or an organic layer. In the disclosed embodiment, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer disposed therebetween. In the disclosed embodiment, the thin film encapsulation layer may include a plurality of inorganic layers and a plurality of organic layers alternately stacked on each other.

[0138] Figure 6 is a schematic plan view of a display panel DP according to a disclosed embodiment.

[0139] Figure 6 Shows Figure 4 Components of the display panel DP. Figure 6 The first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 and the first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4 are shown.

[0140] The first to fourth pixel circuit units PCU1, PCU2, PCU3 and PCU4 may be electrically connected to the above referenced Figure 4 Four light emitting element units EDU1, EDU2, EDU3 and EDU4 are described.

[0141] The first to fourth pixel circuit units PCU1, PCU2, PCU3 and PCU4 may each include a first pixel circuit PC1, a second pixel circuit PC2 and a third pixel circuit PC3. The first pixel circuit PC1, the second pixel circuit PC2 and the third pixel circuit PC3 may be used to drive the above reference Figure 4 For example, the first pixel circuit PC1, the second pixel circuit PC2 and the third pixel circuit PC3 may each include the circuits described above. Figure 4 The first pixel transistor to the third pixel transistor T_B, T_G and T_R described in the above description. The first pixel circuit PC1 included in the first pixel circuit unit PCU1 may be a 1-1 pixel circuit. The first pixel circuit PC1 included in the second pixel circuit unit PCU2 may be a 1-2 pixel circuit. The first pixel circuit PC1 included in the third pixel circuit unit PCU3 may be a 1-3 pixel circuit. The first pixel circuit PC1 included in the fourth pixel circuit unit PCU4 may be a 1-4 pixel circuit.

[0142] The first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4 may include those mentioned above with reference to Figure 4 The first light emitting elements ED1-1, ED2-1, ED3-1 and ED4-1 described above (see Figure 4 ) in each of them. Figure 6 The first to third light emitting regions PXA-B, PXA-G, and PXA-R are shown instead of the first to third light emitting elements ED1-1, ED1-2, and ED1-3. In an embodiment, the first light emitting region PXA-B may emit blue light, the second light emitting region PXA-G may emit green light, and the third light emitting region PXA-R may emit red light. However, the disclosed embodiments are not limited thereto.

[0143] The first to third light emitting regions PXA-B, PXA-G, and PXA-R may be defined by a pixel opening. For example, the first light emitting region PXA-B may be defined as a shape corresponding to the first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3, and PDL-OP4. The first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3, and PDL-OP4 may expose at least a portion of each of the first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4.

[0144] The same applies to the first anode electrode AE-1. Figure 5The description of the anode electrode AE-1 of the first light emitting element ED1-1 in FIG. The same can be applied to the second anode electrode AE-2. Figure 5 The same description can be applied to the first pixel opening PDL-OP1 and the second pixel opening PDL-OP2. Figure 5 Description of the first pixel opening PDL-OP1 and the second pixel opening PDL-OP2 in FIG.

[0145] The description of the second anode electrode AE-2 and the second pixel opening PDL-OP2 in the second pixel circuit unit PCU2 can be applied to the third anode electrode AE-3 and the third pixel opening PDL-OP3 in the third pixel circuit unit PCU3. The description of the first anode electrode AE-1 and the first pixel opening PDL-OP1 in the first pixel circuit unit PCU1 can be applied to the fourth anode electrode AE-4 and the fourth pixel opening PDL-OP4 in the fourth pixel circuit unit PCU4.

[0146] As mentioned above Figure 4 As described above, a pixel may include a light emitting element and a pixel circuit connected to the light emitting element. For example, a first pixel may include a first light emitting element ED1-1 including a first anode electrode AE-1 (see Figure 5 ) and connected to the first light emitting element ED1-1 (see Figure 5 ) of the first pixel circuit PC1. The second pixel may include a second light emitting element ED2-1 including a second anode electrode AE-2 (see Figure 5 ) and connected to the second light emitting element ED2-1 (see Figure 5 ) of the first pixel circuit PC1. The third pixel may include a second light emitting element ED2-1 including a third anode electrode AE-3 (see Figure 5 ) and connected to the second light emitting element ED2-1 (see Figure 5 )'s first pixel circuit PC1.

[0147] In the first pixel to the fourth pixel, the positions and areas of the first anode electrode to the fourth anode electrode AE-1, AE-2, AE-3 and AE-4 may be equal. Therefore, in the first pixel to the fourth pixel, the overlapping areas of the first anode electrode to the fourth anode electrode AE-1, AE-2, AE-3 and AE-4 and the first pixel circuit PC1 may be equal to each other.

[0148] In contrast, the areas of the first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3 and PDL-OP4 may be equal, but the positions of the first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3 and PDL-OP4 in the first to fourth pixels may be different from each other.

[0149] For example, in the first pixel, the first pixel opening PDL-OP1 may be adjacent to the lower end of the first pixel circuit PC1; in the second pixel, the second pixel opening PDL-OP2 may be adjacent to the upper end of the first pixel circuit PC1; in the third pixel, the third pixel opening PDL-OP3 may be adjacent to the upper end of the first pixel circuit PC1; in the fourth pixel, the fourth pixel opening PDL-OP4 may be adjacent to the lower end of the first pixel circuit PC1. Accordingly, the distance LL1 between the first pixel opening PDL-OP1 and the second pixel opening PDL-OP2 may be smaller than the distance LL2 between the third pixel opening PDL-OP3 and the fourth pixel opening PDL-OP4.

[0150] Therefore, the area where the specific components included in the first pixel circuit PC1 and the first pixel opening PDL-OP1 overlap in a plan view may be different from the area where the specific components included in the first pixel circuit PC1 and the second pixel opening PDL-OP2 overlap in a plan view. Figure 7 To Figure 9B.

[0151] Figure 7 is a schematic plan view of a pixel circuit PC1 according to a disclosed embodiment. Figure 8 is a schematic plan view showing a portion of a pattern included in the pixel circuit PC1 according to the disclosed embodiment. Figure 7 and Figure 8 It is enlarged and included in Figure 6 2 is a plan view of a first pixel circuit PC1 according to an embodiment among the first to fourth pixel circuit units PCU1 , PCU2 , PCU3 , and PCU4 shown in FIG.

[0152] Reference Figure 7 According to the embodiment, the first pixel circuit PC1 may include a plurality of conductive layers. For example, the first pixel circuit PC1 may include the above reference Figure 4 The first to fifth conductive layers are described. Figure 7 The first to fifth transistors T1 , T2 , T3 , T4 , and T5 , the data line DLj, the first voltage line VL1 , and the third voltage line VL3 are shown as examples.

[0153] Figure 8 Shown included in Figure 7The second conductive layer may include a plurality of conductive patterns, for example, the second conductive layer may include a first conductive pattern P1 and upper gates G1-1, G2-1, G3-1, G4-1 and G5-1 of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5.

[0154] The first conductive pattern P1 may have a single body shape with the upper gate G1 - 1 of the first transistor T1 .

[0155] The first pixel circuit PC1 according to the embodiment may include a first portion PT1, a second portion PT2, and a third portion PT3.

[0156] 9A and 9B are schematic plan views showing components of a display panel according to an embodiment of the disclosure. Figure 6 FIG9B is a plan view of an embodiment of a first pixel circuit PC1, a first anode electrode AE-1, and a first pixel opening PDL-OP1 of a first pixel circuit unit PCU1 shown in FIG9B. Figure 6 2 is a plan view of an embodiment of a first pixel circuit PC1, a second anode electrode AE-2, and a second pixel opening PDL-OP2 of a second pixel circuit unit PCU2 shown in FIG.

[0157] Refer to Figure 6 9A, the first anode electrode AE-1 and the first pixel opening PDL-OP1 according to the embodiment may overlap with the first pixel circuit PC1 in a plan view. Specifically, the first anode electrode AE-1 may be arranged to overlap with the first portion PT1, the second portion PT2, and the third portion PT3 of the first pixel circuit PC1. For example, the first anode electrode AE-1 may include a first electrode portion AE-PT1 overlapping with the first portion PT1, a second electrode portion AE-PT2 overlapping with the second portion PT2, and a third electrode portion AE-PT3 overlapping with the third portion PT3.

[0158] In contrast, the first pixel opening PDL-OP1 may be disposed to overlap the first portion PT1 and the second portion PT2 of the first pixel circuit PC1 , and not to overlap the third portion PT3 .

[0159] Refer to Figure 69B, the second anode electrode AE-2 and the second pixel opening PDL-OP2 according to the embodiment may overlap with the first pixel circuit PC1 in a plan view. Specifically, the second anode electrode AE-2 may be arranged to overlap with the first portion PT1, the second portion PT2, and the third portion PT3 of the first pixel circuit PC1. Conversely, the second pixel opening PDL-OP2 may be arranged to overlap with the second portion PT2 and the third portion PT3 of the first pixel circuit PC1, and not overlap with the first portion PT1.

[0160] 9A and 9B together, the first pixel opening PDL-OP1 and the second pixel opening PDL-OP2 may overlap different portions of the upper gate G1-1 of the first transistor T1. Therefore, the area where the first pixel opening PDL-OP1 and the upper gate G1-1 of the first transistor T1 overlap may be different from the area where the second pixel opening PDL-OP2 and the upper gate G1-1 of the first transistor T1 overlap.

[0161] However, the first anode electrode AE-1 and the second anode electrode AE-2 may be disposed at the same position in the first pixel circuit PC1, and therefore, the area where the first anode electrode AE-1 and the upper gate G1-1 of the first transistor T1 overlap may be equal to the area where the second anode electrode AE-2 and the upper gate G1-1 of the first transistor T1 overlap. Figure 5 The sizes of the first gap capacitor C1 and the second gap capacitor C2 described in the drawings may be equal.

[0162] The display panel DP according to the disclosed embodiment may be formed as described above with reference to Figure 6 The first pixel opening PDL-OP1 and the second pixel opening PDL-OP2 described above are similar to each other, but the area where the first anode electrode AE-1 overlaps with the upper gate G1-1 of the first transistor T1 and the area where the second anode electrode AE-2 overlaps with the upper gate G1-1 of the first transistor T1 may be equal, so that the gap capacitor Cga (see Figure 2 ) can be substantially the same in size. Therefore, even when a gap capacitor Cga (see Figure 2 ), the storage capacitor Cst between adjacent pixels (see Figure 2 ) can also be essentially zero.

[0163] Fig.10 11A and 11B are schematic plan views showing components of a display panel according to a comparative example.

[0164] exist Fig.10 In the comparison example, Figure 6Compared with the embodiment of the present invention, the sizes and arrangement positions of the first to fourth anode electrodes AE-1, AE-2, AE-3 and AE-4 are changed. Specifically, the first to fourth anode electrodes AE-1, AE-2, AE-3 and AE-4 may be in the form of surrounding each of the first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3 and PDL-OP4. Figure 6 Compared with the first anode electrodes AE-1, AE-2, AE-3 and AE-4 shown in the figure, the first anode electrode AE-1 and the third anode electrode AE-3 can be set at the lower end of the first pixel circuit PC1, and the second anode electrode AE-2 and the fourth anode electrode AE-4 can be set at the upper end of the first pixel circuit PC1.

[0165] Figure 11A is an enlarged Fig.10 FIG11B is a plan view of an embodiment of a first pixel circuit PC1, a first anode electrode AE-1, and a first pixel opening PDL-OP1 of a first pixel circuit unit PCU1 shown in FIG11B. Fig.10 2 is a plan view of an embodiment of a first pixel circuit PC1, a second anode electrode AE-2, and a second pixel opening PDL-OP2 of a second pixel circuit unit PCU2 shown in FIG.

[0166] Refer to Fig.10 11A, the first anode electrode AE-1 and the first pixel opening PDL-OP1 according to the embodiment may overlap with the first pixel circuit PC1 in a plan view. Specifically, the first anode electrode AE-1 and the first pixel opening PDL-OP1 may be both arranged to overlap with the first portion PT1 and the second portion PT2 of the first pixel circuit PC1, and not overlap with the third portion PT3.

[0167] Refer to Fig.10 11B, the second anode electrode AE-2 and the second pixel opening PDL-OP2 according to the embodiment may overlap with the first pixel circuit PC1 in a plan view. Specifically, the second anode electrode AE-2 and the second pixel opening PDL-OP2 may both be arranged to overlap with the second portion PT2 and the third portion PT3 of the first pixel circuit PC1, and not overlap with the first portion PT1.

[0168] Except for Fig.10 11A and 11B, the components other than those shown in FIG. 11A and FIG. 11B may also be applied Figure 1 To the above description in FIG. 9B .

[0169] 11A and 11B together, the first anode electrode AE-1 and the second anode electrode AE-2 may overlap different portions of the upper gate G1-1 of the first transistor T1. Therefore, the area where the first anode electrode AE-1 and the upper gate G1-1 of the first transistor T1 overlap may be different from the area where the second anode electrode AE-2 and the upper gate G1-1 of the first transistor T1 overlap. Figure 5 The sizes of the first gap capacitor C1 and the second gap capacitor C2 described in the embodiment of the present invention may be different. For example, display quality may be degraded due to the size difference of the gap capacitors between adjacent pixels.

[0170] The shapes of the light emitting regions PXA-B, PXA-G, and PXA-R according to the disclosed embodiment are not limited to Figure 6 The shapes shown in .

[0171] Fig.12 is a schematic plan view of a pixel according to a disclosed embodiment.

[0172] Reference Fig.12 , the display panel according to the embodiment may include first to fourth pixel rows PXL1, PXL2, PXL3, and PXL4 sequentially arranged in the first direction DR1. The first to fourth pixel rows PXL1, PXL2, PXL3, and PXL4 each include first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 sequentially arranged in the second direction DR2. The first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 may each include first to third pixel circuits PC1, PC2, and PC3.

[0173] On the first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 arranged in a row, the first to fourth light emitting element units electrically connected to the first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4, respectively, may be arranged along the second direction DR2. The first to fourth light emitting element units may each include a 1-1 light emitting element, a 1-2 light emitting element, a 1-3 light emitting element, and a 1-4 light emitting element.

[0174] exist Fig.12, the first to fourth light-emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R are shown to represent the 1-1 light-emitting element, the 1-2 light-emitting element, the 1-3 light-emitting element, and the 1-4 light-emitting element. The 1-1 light-emitting element and the 1-2 light-emitting element, both including the first light-emitting region PXA-Ba and the second light-emitting region PXA-Bb, may be driven by the first pixel circuit PC1. For example, the anode electrodes included in each of the 1-1 light-emitting element and the 1-2 light-emitting element may be electrically connected to each other or have a single body shape. Fig.12 An embodiment in which the first anode electrode AE-1 is commonly provided for the 1-1 light emitting element and the 1-2 light emitting element is shown. For example, the first light emitting region PXA-Ba and the second light emitting region PXA-Bb may overlap with the first anode electrode AE-1 in a plan view. The third light emitting element including the third light emitting region PXA-G may be driven by the second pixel circuit PC2. The fourth light emitting element including the fourth light emitting region PXA-R may be driven by the third pixel circuit PC3. In an embodiment, the first light emitting region PXA-Ba and the second light emitting region PXA-Bb may emit blue light, the third light emitting region PXA-G may emit green light, and the fourth light emitting region PXA-R may emit red light. However, the disclosed embodiments are not limited thereto.

[0175] Referring to the first pixel circuit unit PCU1 disposed in the first pixel row PXL1 and the first to fourth light emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R disposed on the first pixel circuit unit PCU1, the first anode electrode AE-1 may be disposed to overlap the first to third pixel circuits PC1, PC2, and PC3. 1a The pixel opening PDL-OPa may expose a portion of the first anode electrode AE-1 to define the first light emitting region PXA-Ba, and 1b The pixel opening PDL-OPb may expose another portion of the first anode electrode AE-1 to define the second light emitting region PXA-Bb. In an embodiment, the first light emitting region PXA-Ba and the second light emitting region PXA-Bb may be disposed adjacent to the right side of the first pixel circuit unit PCU1.

[0176] Referring to the fourth pixel circuit unit PCU4 disposed in the first pixel row PXL1 and the first to fourth light emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R disposed on the fourth pixel circuit unit PCU4, the fourth anode electrode AE-4 may be disposed to overlap with the first to third pixel circuits PC1, PC2, and PC3. The 1a pixel opening PDL-OPa may expose a portion of the fourth anode electrode AE-4 to define the first light emitting region PXA-Ba, and the 1b pixel opening PDL-OPb may expose another portion of the fourth anode electrode AE-4 to define the second light emitting region PXA-Bb. In an embodiment, the first light emitting region PXA-Ba and the second light emitting region PXA-Bb may be disposed adjacent to the left side of the fourth pixel circuit unit PCU4.

[0177] In the first pixel circuit unit PCU1 and the fourth pixel circuit unit PCU4 in the first pixel row PXL1, the position of the first anode electrode AE-1 and the position of the fourth anode electrode AE-4 may not be exactly the same. However, the first anode electrode AE-1 and the fourth anode electrode AE-4 may be arranged in the first pixel row PXL1 so that the first anode electrode AE-1 is aligned with the first conductive pattern P1 (see Figure 8 ) may be overlapped with the fourth anode electrode AE-4 and the first conductive pattern P1 (see Figure 8 )The area of ​​overlap.

[0178] Therefore, the gap capacitor Cga (see FIG. 1 ) between the first pixel circuit unit PCU1 and the fourth pixel circuit unit PCU4 in the first pixel row PXL1 is Figure 2 ) can be essentially zero.

[0179] The structure of the second pixel row PXL2 may be different from that of the first pixel row PXL1 .

[0180] Referring to the second pixel circuit unit PCU2 disposed in the second pixel row PXL2 and the first to fourth light emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R disposed on the second pixel circuit unit PCU2, the second anode electrode AE-2 may be disposed to overlap the first to third pixel circuits PC1, PC2, and PC3. In an embodiment, the first light emitting region PXA-Ba and the second light emitting region PXA-Bb may be disposed adjacent to the left side of the second pixel circuit unit PCU2.

[0181] Referring to the third pixel circuit unit PCU3 disposed in the second pixel row PXL2 and the first to fourth light emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R disposed on the third pixel circuit unit PCU3, the third anode electrode AE-3 may be disposed to overlap the first to third pixel circuits PC1, PC2, and PC3. In an embodiment, the first light emitting region PXA-Ba and the second light emitting region PXA-Bb may be disposed adjacent to the right side of the third pixel circuit unit PCU3.

[0182] In the second pixel circuit unit PCU2 and the third pixel circuit unit PCU3 in the second pixel row PXL2, the position of the second anode electrode AE-2 and the position of the third anode electrode AE-3 may not be exactly the same. However, the second anode electrode AE-2 and the third anode electrode AE-3 may be arranged in the second pixel row PXL2 so that the second anode electrode AE-2 is aligned with the first conductive pattern P1 (see Figure 8 ) may be overlapped with the third anode electrode AE-3 and the first conductive pattern P1 (see Figure 8 )The area of ​​overlap.

[0183] Therefore, the gap capacitor Cga (see FIG. 1 ) between the second pixel circuit unit PCU2 and the third pixel circuit unit PCU3 in the second pixel row PXL2. Figure 2 ) can be essentially zero.

[0184] The structure of the third pixel row PXL3 may be the same as that of the first pixel row PXL1. The structure of the fourth pixel row PXL4 may be the same as that of the second pixel row PXL2.

[0185] The display device according to the disclosed embodiment may include two adjacent pixels, each of which includes a light emitting element and a pixel circuit. In the two pixels, the portions of the anode electrode exposed by the pixel opening may be different from each other. However, the anode electrode included in the light emitting element may be arranged at the same position in the two pixels. Therefore, the size of the gap capacitor formed between the anode and the gate electrode included in the pixel circuit may be substantially equal in the two pixels. Therefore, the display device may have an improved display quality.

[0186] The display device according to the embodiment may have improved display quality.

[0187] Although the disclosure has been described with reference to the disclosed embodiments, it will be understood that the disclosure should not be limited to the embodiments but various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the disclosure.

[0188] Therefore, the disclosed technical scope is not intended to be limited to the contents set forth in the detailed description of the specification.

[0189] Industrial Applicability

[0190] The present invention, which provides a display device with improved display quality, has high industrial applicability.

Claims

1. A display device, comprising: Base layer; A circuit layer, including a 1-1 pixel circuit and a 1-2 pixel circuit, wherein the circuit layer is disposed on the substrate layer; as well as The light-emitting element layer includes a first light-emitting element and a second light-emitting element, wherein the first light-emitting element and the second light-emitting element each include: a first electrode; an emission layer; a second electrode; and a pixel defining film including a pixel opening exposing a portion of the first electrode, Wherein, the light emitting element layer is arranged on the circuit layer, The 1-1 pixel circuit and the 1-2 pixel circuit each include: a driving transistor including a source, a drain, an active region and a gate; and a gate conductive layer, and An area where the first electrode of the first light-emitting element overlaps with the gate conductive layer of the 1-1 pixel circuit in a plan view is equal to an area where the first electrode of the second light-emitting element overlaps with the gate conductive layer of the 1-2 pixel circuit in a plan view.

2. The display device according to claim 1, wherein: The first electrode of the first light emitting element and the gate conductive layer define a first electrode and a second electrode of a first capacitor, respectively, and The first electrode of the second light emitting element and the gate conductive layer define a first electrode and a second electrode of a second capacitor, respectively.

3. The display device according to claim 2, wherein: The capacitance of the first capacitor is substantially equal to the capacitance of the second capacitor.

4. The display device according to claim 1, wherein: In a plan view, the pixel opening of the first light emitting element overlaps the lower side of the 1-1 pixel circuit, and In a plan view, the pixel opening of the second light emitting element overlaps an upper side of the 1-2 pixel circuit.

5. The display device according to claim 1, wherein: The driving transistor includes an oxide semiconductor.

6. The display device according to claim 1, wherein: The 1-1 pixel circuit is arranged on the 1-2 pixel circuit in a first direction, The circuit layer further includes a 1-3 pixel circuit and a 1-4 pixel circuit, wherein the 1-3 pixel circuit is adjacent to the 1-1 pixel circuit in a second direction intersecting the first direction, and the 1-4 pixel circuit is adjacent to the 1-2 pixel circuit in the second direction, The light-emitting element layer includes a third light-emitting element and a fourth light-emitting element, wherein the third light-emitting element is arranged on the 1-3 pixel circuit, and the fourth light-emitting element is arranged on the 1-4 pixel circuit. The third light-emitting element and the fourth light-emitting element each include: a first electrode; an emission layer; a second electrode; and a pixel definition film including a pixel opening exposing a portion of the first electrode, The 1-3 pixel circuit and the 1-4 pixel circuit both include a first part, a second part, and a third part divided in the first direction, In a plan view, the first electrode of the third light emitting element overlaps the first portion to the third portion of the 1-3 pixel circuit, In a plan view, the first electrode of the fourth light-emitting element overlaps the first portion to the third portion of the 1-4 pixel circuit, In a plan view, the pixel opening of the third light emitting element overlaps the second portion and the third portion of the 1-3 pixel circuit, and In a plan view, the pixel opening of the fourth light emitting element overlaps the first portion and the second portion of the 1-4 pixel circuit.

7. The display device according to claim 1, wherein: The first light emitting element and the second light emitting element emit first light.

8. The display device according to claim 7, wherein: The first light emitting element is electrically connected to the 1-1 pixel circuit, and the second light emitting element is electrically connected to the 1-2 pixel circuit.

9. The display device according to claim 7, wherein: The light emitting element layer further includes a fifth light emitting element that emits a second light different from the first light and is adjacent to the first light emitting element, and The first light emitting element is connected to the fifth light emitting element.

10. A display device, comprising: Base layer; a circuit layer, comprising a 1-1 pixel circuit and a 1-2 pixel circuit adjacent to the 1-1 pixel circuit in a first direction, wherein the circuit layer is disposed on the substrate layer; as well as A light-emitting element layer, comprising a first light-emitting element arranged on the 1-1 pixel circuit and a second light-emitting element arranged on the 1-2 pixel circuit, wherein the light-emitting element layer is arranged on the circuit layer, wherein: The first light emitting element and the second light emitting element each include: a first electrode; an emission layer; a second electrode; and a pixel defining film including a pixel opening exposing a portion of the first electrode, The 1-1 pixel circuit and the 1-2 pixel circuit each include a first part, a second part, and a third part divided in the first direction, In a plan view, the first electrode of the first light emitting element overlaps the first portion to the third portion of the 1-1 pixel circuit, In a plan view, the first electrode of the second light emitting element overlaps the first portion to the third portion of the 1-2 pixel circuit, In a plan view, the pixel opening of the first light emitting element overlaps the first portion and the second portion of the 1-1 pixel circuit, and In a plan view, the pixel opening of the second light emitting element overlaps the second portion and the third portion of the 1-2 pixel circuit.

11. The display device according to claim 10, wherein: In a plan view, the pixel opening of the first light emitting element does not overlap the third portion of the 1-1 pixel circuit, and In a plan view, the pixel opening of the second light emitting element does not overlap the first portion of the 1-2 pixel circuit.

12. The display device according to claim 10, wherein: The 1-1 pixel circuit and the 1-2 pixel circuit each include a driving transistor and a gate conductive layer, the driving transistor includes a source, a drain, an active region and a gate, and An area where the first electrode of the first light-emitting element overlaps with the gate conductive layer of the 1-1 pixel circuit in a plan view is equal to an area where the first electrode of the second light-emitting element overlaps with the gate conductive layer of the 1-2 pixel circuit in a plan view.

13. The display device according to claim 12, wherein: The driving transistor is an oxide semiconductor.

14. The display device according to claim 10, wherein: The 1-1 pixel circuit is arranged on the 1-2 pixel circuit in the first direction; The circuit layer further includes a 1-3 pixel circuit and a 1-4 pixel circuit, wherein the 1-3 pixel circuit is adjacent to the 1-1 pixel circuit in a second direction intersecting the first direction, and the 1-4 pixel circuit is adjacent to the 1-2 pixel circuit in the second direction, The light-emitting element layer includes a third light-emitting element and a fourth light-emitting element, wherein the third light-emitting element is arranged on the 1-3 pixel circuit, and the fourth light-emitting element is arranged on the 1-4 pixel circuit. The third light-emitting element and the fourth light-emitting element each include a first electrode, an emission layer, a second electrode and a pixel definition film, wherein the pixel definition film includes a pixel opening exposing a portion of the first electrode, The 1-3 pixel circuit and the 1-4 pixel circuit both include a first part, a second part, and a third part divided in the first direction, In a plan view, the first electrode of the third light emitting element overlaps the first portion to the third portion of the 1-3 pixel circuit, In a plan view, the first electrode of the fourth light-emitting element overlaps the first portion to the third portion of the 1-4 pixel circuit, In a plan view, the pixel opening of the third light emitting element overlaps the second portion and the third portion of the 1-3 pixel circuit, and In a plan view, the pixel opening of the fourth light emitting element overlaps the first portion and the second portion of the 1-4 pixel circuit.

15. The display device according to claim 10, wherein: The first light emitting element and the second light emitting element emit first light.

16. The display device according to claim 15, wherein: The first light emitting element is electrically connected to the 1-1 pixel circuit, and the second light emitting element is electrically connected to the 1-2 pixel circuit.

17. The display device according to claim 15, wherein: The light emitting element layer further includes a fifth light emitting element that emits a second light different from the first light and is adjacent to the first light emitting element, and The first light emitting element is connected to the fifth light emitting element.

18. A display device, comprising: Base layer; The first pixel circuit unit to the fourth pixel circuit unit are arranged in one direction; as well as The first to fourth light emitting units are arranged in the one direction and are respectively disposed on the first to fourth pixel circuit units, Wherein, the first light-emitting unit to the fourth light-emitting unit each include: 1-1 light-emitting element; 1-2 light-emitting element; 1-3 light-emitting element; and 1-4 light-emitting element, Each of the light-emitting elements 1-1 to 1-4 includes: a first electrode; an emission layer; a second electrode; and a pixel defining film, including a pixel opening exposing a portion of the first electrode. The first pixel circuit unit to the fourth pixel circuit unit each include a first pixel circuit, a second pixel circuit and a third pixel circuit, the first pixel circuit is electrically connected to the 1-1 light emitting element and the 1-2 light emitting element, the second pixel circuit is electrically connected to the 1-2 light emitting element, the third pixel circuit is electrically connected to the 1-3 light emitting element, the first pixel circuit to the third pixel circuit each include a driving transistor and a gate conductive layer, the driving transistor includes a source, a drain, an active area and a gate, and An area in which the first electrode of the 1-1 light emitting element and the first electrode of the 1-2 light emitting element overlap with the gate conductive layer of the first pixel circuit in a plan view is equal in the first pixel circuit unit and the fourth pixel circuit unit.

19. The display device according to claim 18, wherein: The pixel opening of the 1-1 light emitting element and the pixel opening of the 1-2 light emitting element are respectively arranged at different positions in the first pixel circuit unit and the fourth pixel circuit unit.

20. The display device according to claim 18, wherein: The 1-1 light emitting element and the 1-2 light emitting element emit a first light, The 1-3 light emitting elements emit a second light different from the first light, and The 1-4 light emitting element emits a third light different from the first light and the second light.

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