Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are disclosed. The display device includes a substrate including a first-first display area, a second-first display area, and a first-second display area arranged in a first direction; a pixel circuit in the first-first display area and the first-second display area; a first driving circuit in the second-first display area and providing a first driving signal to the pixel circuit; a light emitting element in each of the first-first display area, the first-second display area, and the second-first display area; a first data output pad connected to a first pixel circuit in the first-first display area; a second data output pad connected to a second pixel circuit in the first-second display area and spaced apart from the first data output pad in the first direction; and a first control output pad connected to the first driving circuit and located between the first data output pad and the second data output pad in the first direction.

Description

Technical Field

[0001] The embodiments relate to a display device and an electronic device including the display device. More specifically, the embodiments relate to a display device having reduced unused space and an electronic device including the display device. Background Technology

[0002] Flat panel displays are replacing cathode ray tube (CRT) displays due to their lightweight and thin profile. Representative examples of such flat panel displays include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0003] Display devices include light-emitting elements and driving circuits for driving the light-emitting elements. The light-emitting elements emit light according to signals and / or voltages applied from the driving circuits, thereby generating an image. Research is underway regarding the connection between the light-emitting elements and the driving circuits to improve the reliability and display quality of display devices. Summary of the Invention

[0004] The embodiments provide a display device with reduced unused space and improved display quality.

[0005] The embodiments also provide an electronic device that includes the display device.

[0006] Further features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0007] The display device according to an embodiment includes a substrate, a pixel circuit, a first driving circuit, a light-emitting element, a first data output pad, a second data output pad, and a first control output pad. The substrate includes a display area and a peripheral area. The display area includes a first-first display area, a first-second display area spaced apart from the first-first display area in a first direction, and a second-first display area located between the first-first display area and the first-second display area in a first direction. The pixel circuit is disposed in the first-first display area and the first-second display area. The first driving circuit is disposed in the second-first display area and provides a first driving signal to the pixel circuit. The light-emitting element is disposed in each of the first-first display area, the first-second display area, and the second-first display area. The first data output pad is disposed in the peripheral area and electrically connected to the first pixel circuit disposed in the first-first display area. The second data output pad is disposed in the peripheral area, electrically connected to the second pixel circuit disposed in the first-second display area, and spaced apart from the first data output pad in a first direction. The first control output pad is disposed in the peripheral area, electrically connected to the first drive circuit, and located in the first direction between the first data output pad and the second data output pad.

[0008] In one embodiment, the first data output pad, the second data output pad, and the first control output pad can be arranged in a row in a first direction.

[0009] In an embodiment, the display device may further include a first data line, a second data line, a first data connection line, a second data connection line, and a first control connection line. The first data line may be disposed in a first-first display area and electrically connected to a first data output pad. The second data line may be disposed in a first-second display area and electrically connected to a second data output pad. The first data connection line connects the first data output pad and the first data line. The second data connection line connects the second data output pad and the second data line and may be spaced apart from the first data connection line in a first direction. The first control connection line connects the first control output pad and the first driving circuit and may be located between the first data connection line and the second data connection line in a first direction.

[0010] In an embodiment, the display device may further include: a first crack detection circuit disposed in a second direction intersecting the first direction between a first data output pad and a first-first display area; and a second crack detection circuit disposed in the second direction between a second data output pad and a first-second display area. The second crack detection circuit may be spaced apart from the first crack detection circuit in the first direction. A first control connection line may be located in the first direction between the first crack detection circuit and the second crack detection circuit.

[0011] In an embodiment, the display area may further include a first-third display area spaced apart from the first-second display area in a first direction, and a second-second display area located between the first-second display area and the first-third display area in the first direction. Pixel circuitry may be further disposed in the first-third display area. Light-emitting elements may be further disposed in the first-third display area and the second-second display area.

[0012] In an embodiment, the display device may further include a second driving circuit, a third data output pad, and a second control output pad. The second driving circuit may be disposed in the second-third display area and may provide a second driving signal to the pixel circuit. The third data output pad may be disposed in the peripheral area, electrically connected to a third pixel circuit disposed in the first-third display area, and may be spaced apart from the second data output pad in a first direction. The second control output pad may be disposed in the peripheral area, electrically connected to the second driving circuit, and may be located between the second data output pad and the third data output pad in the first direction.

[0013] In an embodiment, each of the first driving circuit and the second driving circuit may be a scanning driving circuit or a transmitting driving circuit.

[0014] In an embodiment, the pixel circuit may further include a third pixel circuit disposed in the first-first display area. The light-emitting element may include a first light-emitting element disposed in the second-first display area and electrically connected to the first pixel circuit, and a second light-emitting element disposed in the first-first display area and electrically connected to the third pixel circuit.

[0015] In an embodiment, the first pixel circuit may be located in the first direction between the second-first display area and the third pixel circuit.

[0016] In an embodiment, the display device may further include a bridging wire and a first shielding layer disposed between the bridging wire and the first driving circuit. The bridging wire may include a first end electrically connected to a first pixel circuit in the first display area and a second end electrically connected to a first light-emitting element in the second display area.

[0017] In this embodiment, a first shielding layer may define a first through-hole and a first dummy hole. A conductive pattern located in the same layer as the first shielding layer may be disposed inside the first through-hole. There is no conductive pattern inside the first dummy hole.

[0018] In an embodiment, the display device may further include drive signal lines disposed on a first shielding layer. The drive signal lines can transmit a first drive signal provided from a first drive circuit to a first pixel circuit and a third pixel circuit.

[0019] In this embodiment, the drive signal line may be located on the same layer as the bridge line.

[0020] In one embodiment, the display device may further include a second shielding layer disposed on the bridging wire.

[0021] In an embodiment, the display device may further include a common voltage line disposed in the display area and subjected to a common voltage. The common voltage line may be connected to a common electrode of the light-emitting element in the display area.

[0022] In an embodiment, the display device may further include: an organic encapsulation layer disposed on the light-emitting element; an input sensing layer disposed on the organic encapsulation layer and including a first sensing electrode and a second sensing electrode; and a first trace disposed below the light-emitting element and electrically connecting the first sensing electrode and the first sensing pad.

[0023] In an embodiment, the first trace may include: a first end portion connected to a first sensing pad in a peripheral region; a second end portion connected to a first sensing electrode in the peripheral region; and a connection portion connecting the first end portion and the second end portion and extending through the display area.

[0024] In one embodiment, the second end of the first trace may be connected to the first sensing electrode outside the organic encapsulation layer in a plan view.

[0025] In an embodiment, the display device may further include: a second trace, located in the same layer as the first trace, and electrically connecting the second sensing electrode and the second sensing pad.

[0026] An electronic device according to an embodiment includes a display device for displaying an image and a housing housing the display device. The display device includes a substrate, pixel circuitry, a first driving circuit, a light-emitting element, a first data output pad, a second data output pad, and a first control output pad. The substrate includes a display area and a peripheral area. The display area includes a first-first display area, a first-second display area spaced apart from the first-first display area in a first direction, and a second-first display area located between the first-first display area and the first-second display area in a first direction. Pixel circuitry is disposed in the first-first display area and the first-second display area. The first driving circuit is disposed in the second-first display area and provides a first driving signal to the pixel circuitry. Light-emitting element is disposed in each of the first-first display area, the first-second display area, and the second-first display area. The first data output pad is disposed in the peripheral area and electrically connected to the first pixel circuit disposed in the first-first display area. The second data output pad is disposed in the peripheral area, electrically connected to the second pixel circuit disposed in the first-second display area, and spaced apart from the first data output pad in a first direction. The first control output pad is disposed in the peripheral area, electrically connected to the first drive circuit, and located in the first direction between the first data output pad and the second data output pad.

[0027] According to the embodiments, the unused space of the display device can be reduced, and the display quality of the display device can be improved.

[0028] It will be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated into and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to illustrate the disclosure.

[0030] Figure 1This is a block diagram illustrating a display device according to an embodiment.

[0031] Figure 2 This is an equivalent circuit diagram of a pixel according to an embodiment.

[0032] Figure 3 This is a plan view of a display device according to an embodiment.

[0033] Figure 4 The illustration is based on an embodiment. Figure 3 A magnified plan view of region A.

[0034] Figure 5 The illustration is based on an embodiment. Figure 3 A magnified plan view of region A.

[0035] Figure 6 The illustration includes Figure 3 A cross-sectional view of an example display panel in a display device.

[0036] Figure 7 The illustration includes Figure 3 A plan view of an example of a common voltage line in a display device.

[0037] Figure 8 The illustration includes Figure 3 A plan view of another example of a common voltage line in a display device.

[0038] Figure 9 The illustration includes Figure 3 A cross-sectional view of an example of the connection portion of the common voltage line in a display device.

[0039] Figure 10 The illustration includes Figure 3 A cross-sectional view of another example of the connection portion of the common voltage line in a display device.

[0040] Figure 11 This is a plan view illustrating an example of traces included in a display panel according to an embodiment.

[0041] Figure 12 It is a diagram. Figure 11 A cross-sectional view of an example display panel.

[0042] Figure 13 This is a block diagram illustrating an electronic device according to an embodiment.

[0043] Figure 14 It is shown that Figure 13 The electronic device is implemented as an example view of a smartphone.

[0044] Figure 15 yes Figure 14An exploded perspective view of an electronic device. Detailed Implementation

[0045] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, which illustrate some exemplary embodiments. However, the inventive concept can be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0046] Various modifications and forms may be made in this disclosure, and specific embodiments will be illustrated in the accompanying drawings and described in detail in the text. However, this is not intended to limit this disclosure to the specific forms disclosed, and it will be understood that all variations, equivalents, or substitutions falling within the spirit and scope of this disclosure should be included.

[0047] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the inventive concept. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0048] It will be understood that when an element is referred to as “connected” or “coupled” to another element, the element may be directly connected or directly coupled to that other element, or there may be an intermediary element. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, there is no intermediary element. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between”, “adjacent” vs. “directly adjacent”, etc.).

[0049] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used in this specification indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0050] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another illustrated in the figures. It will be understood that, in addition to the orientations shown in the figures, the relative terms are also intended to cover different orientations of the device. For example, if a device in one of the figures is flipped, an element described as being “down” of the other elements will be oriented “up” of the other elements. Thus, depending on the specific orientation of the figure, the term “down” can cover both “down” and “up” orientations. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “under” the other elements will be oriented “above” the other elements. Thus, the terms “below” or “under” can cover both “up” and “down” orientations.

[0051] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms defined, for example, in common dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and not as an idealized or overly formal meaning, unless expressly defined herein.

[0052] In the following description, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0053] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0054] refer to Figure 1 According to an embodiment, the display device DD may include a display panel DP comprising pixels PX and a panel driver for driving the display panel DP based on input image data IDAT. In an embodiment, the panel driver may include a data driving circuit DDC, a scan driving circuit SDC, a transmit driving circuit EDC, and a drive controller CON. The data driving circuit DDC can provide data signals to the pixels PX. The scan driving circuit SDC can provide scan signals to the pixels PX. The transmit driving circuit EDC can provide transmit signals to the pixels PX. The drive controller CON can control the data driving circuit DDC, the scan driving circuit SDC, and the transmit driving circuit EDC.

[0055] The display panel DP may include a display area for displaying an image and a peripheral area surrounding the display area. The display panel DP may include scan lines SL, data lines DL, emission lines EML, and pixels PX. Pixels PX may be electrically connected to the scan lines SL, data lines DL, and emission lines EML. For example, the scan lines SL may each extend in a first direction DR1. The data lines DL may each extend in a second direction DR2 intersecting the first direction DR1. The emission lines EML may each extend in the first direction DR1.

[0056] The data driver circuit DDC can generate a data signal based on the output image data ODAT received from the drive controller CON and the data control signal DCTL, and can provide the data signal to the pixel PX through the data line DL. In an embodiment, the data control signal DCTL may include an output data enable signal, a level start signal, and a load signal, but the embodiment is not limited thereto. In an embodiment, the data driver circuit DDC and the drive controller CON can be implemented as a single integrated circuit, and this integrated circuit may be referred to as a timing controller embedded data driver (TED). In an embodiment, the data driver circuit DDC and the drive controller CON can be implemented as separate integrated circuits.

[0057] The scan drive circuit SDC can generate scan signals based on the scan control signal SCTL received from the drive controller CON, and can sequentially provide the scan signals to the pixels PX line by line through the scan lines SL. In an embodiment, the scan control signal SCTL may include a scan start signal and / or a scan clock signal, etc., but the embodiment is not limited to this. In an embodiment, the scan drive circuit SDC may be integrated or formed in the display panel DP.

[0058] The transmit drive circuit EDC can generate transmit signals based on the transmit control signal EMCTL received from the drive controller CON, and can sequentially provide the transmit signals to the pixels PX row by row through the transmit line EML. In an embodiment, the transmit control signal EMCTL may include a transmit start signal and / or a transmit clock signal, etc., but the embodiment is not limited to this. In an embodiment, the transmit drive circuit EDC may be integrated or formed in the display panel DP.

[0059] The drive controller CON can be generated from an external main processor (e.g., Figure 13The processor 910 receives input image data IDAT and input control signal CTL. In an embodiment, the input control signal CTL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and / or a master clock signal, etc., but the embodiment is not limited thereto. The drive controller CON can generate output image data ODAT, data control signal DCTL, scan control signal SCTL, and transmit control signal EMCTL based on the input image data IDAT and the input control signal CTL. In addition, the drive controller CON can control the data drive circuit DDC by providing the output image data ODAT and the data control signal DCTL to the data drive circuit DDC, control the scan drive circuit SDC by providing the scan control signal SCTL to the scan drive circuit SDC, and control the transmit drive circuit EDC by providing the transmit control signal EMCTL to the transmit drive circuit EDC.

[0060] Figure 2 This is an equivalent circuit diagram of a pixel according to an embodiment.

[0061] Each pixel PX may include a pixel circuit PC and a light-emitting element ED. Each pixel circuit PC may have a substantially identical structure. In the following description, a pixel PX connected to the m-th data line DLm and the i-th scan line SLi will be used. m and i are natural numbers greater than 0.

[0062] refer to Figure 2 The pixel circuit PC may include first to seventh pixel transistors T1, T2, T3, T4, T5, T6 and T7, as well as storage capacitor CST.

[0063] The first pixel transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3.

[0064] The second pixel transistor T2 may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the m-th data line DLm, and a second electrode connected to the second node N2.

[0065] The third pixel transistor T3 may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the first node N1, and a second electrode connected to the third node N3.

[0066] The fourth pixel transistor T4 may include a gate electrode connected to the (i-1)th scan line SLi-1, a first electrode to which an initialization signal VINT is applied, and a second electrode connected to the first node N1.

[0067] The fifth pixel transistor T5 may include a gate electrode connected to the i-th emitter line EMLi, a first electrode to which a driving voltage ELVDD is applied, and a second electrode connected to the second node N2. The driving voltage ELVDD may be a high power supply voltage.

[0068] The sixth pixel transistor T6 may include a gate electrode connected to the i-th emitter line EMLi, a first electrode connected to the third node N3, and a second electrode connected to the first electrode (e.g., the anode) of the light-emitting element ED.

[0069] The seventh pixel transistor T7 may include a gate electrode connected to the (i-1)th scan line SLi-1, a first electrode to which an initialization signal VINT is applied, and a second electrode connected to the first electrode of the light-emitting element ED.

[0070] The storage capacitor CST may include a first electrode to which a drive voltage ELVDD is applied and a second electrode connected to a first node N1.

[0071] The light-emitting element (ED) may include a first electrode and a second electrode (e.g., a cathode) to which a common voltage ELVSS is applied. The common voltage ELVSS may be a low supply voltage. The ED may emit light based on a drive current supplied from the pixel circuit PC. For example, the ED may include an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, or a micro light-emitting diode, etc.

[0072] exist Figure 2 In the illustration, the first to seventh pixel transistors T1, T2, T3, T4, T5, T6, and T7 are depicted as p-channel metal-oxide-semiconductor (PMOS) transistors, but the embodiment is not limited to this. For example, the third pixel transistor T3 and the fourth pixel transistor T4 may be n-channel metal-oxide-semiconductor (NMOS) transistors, and the other pixel transistors may be PMOS transistors. As another example, all of the first to seventh pixel transistors T1, T2, T3, T4, T5, T6, and T7 may be NMOS transistors.

[0073] in addition, Figure 2 The number of pixel transistors and capacitors shown in the illustration are merely examples and can be varied according to embodiments.

[0074] Figure 3 This is a plan view of a display device according to an embodiment.

[0075] refer to Figure 3 The display device DD may include a display panel DP and a driver chip DIC. In an embodiment, the display panel DP (or Figure 6The substrate (SUB) may include a display area DA and a peripheral area PA. The display area DA can display an image. For example, in a plan view, the display area DA may have a rectangular shape and the corners of the display area DA may each have a rounded curved shape, but the embodiments are not limited thereto.

[0076] The peripheral area PA may be located around the display area DA. In an embodiment, the peripheral area PA may include a first peripheral area PA1, a second peripheral area PA2, and a bending area BA. In a plan view, the first peripheral area PA1 may surround the outer edge of the display area DA. In a plan view, the second peripheral area PA2 may be disposed in a second direction DR2 relative to the display area DA and the first peripheral area PA1. In a plan view, the bending area BA may be located between the first peripheral area PA1 and the second peripheral area PA2. The bending area BA may be a portion of the display device DD that is bent therein. In a plan view, the second peripheral area PA2 may be spaced apart from the first peripheral area PA1 in the second direction DR2, wherein the bending area BA is located between the first peripheral area PA1 and the second peripheral area PA2.

[0077] In this embodiment, the driver chip DIC can be disposed on the display panel DP and in the second peripheral area PA2. For example, the driver chip DIC can be connected to the display panel DP via an anisotropic conductive film (ACF). In this embodiment, the driver chip DIC may include... Figure 1 The data drive circuit DDC and drive controller CON.

[0078] In an embodiment, the display panel DP may include pixels PX, driving circuit DC, input pad group IPG, output pad group OPG, and crack detection circuit CDC.

[0079] Pixel PX and driving circuit DC can be disposed in display area DA. In an embodiment, the driving circuit DC disposed in display area DA can each extend in the second direction DR2 and can be spaced apart from each other in the first direction DR1. Since the driving circuit DC is disposed in display area DA, the area of ​​peripheral area PA can be reduced, and the unused space of display device DD can be reduced.

[0080] The following text will focus on such aspects. Figure 3 The example shown illustrates an embodiment where the four drive circuits DC are spaced apart from each other in the first direction DR1 within the display area DA. However, this is an example, and the embodiment is not limited to this; the number of drive circuits DC in the display area DA can be varied to three or less, or five or more.

[0081] The display area DA may include a first display area and a second display area disposed on a first direction DR1. The first display area may be an area in which the driving circuit DC is not disposed, and the second display area may be an area in which the driving circuit DC is disposed. Each of the second display areas may be located between two adjacent first display areas that are adjacent to each other on the first direction DR1. The pixel circuit PC may be disposed in the first display area, but may not be disposed in the second display area. The light-emitting element ED may be disposed in both the first and second display areas. This will be described in detail later.

[0082] In an embodiment, the first display area may include a first-first display area DA1a, a first-second display area DA1b, a first-third display area DA1c, a first-fourth display area DA1d, and a first-fifth display area DA1e, spaced apart from each other in the first direction DR1. The second display area may include a second-first display area DA2a, a second-second display area DA2b, a second-third display area DA2c, and a second-fourth display area DA2d, spaced apart from each other in the first direction DR1. In a plan view, the first-second display area DA1b may be spaced apart from the first-first display area DA1a in the first direction DR1, and the second-first display area DA2a may be located between the first-first display area DA1a and the first-second display area DA1b in the first direction DR1. In a plan view, the first-third display area DA1c may be spaced apart from the first-second display area DA1b in the first direction DR1, and the second-second display area DA2b may be located between the first-second display area DA1b and the first-third display area DA1c in the first direction DR1. In the plan view, the first-fourth display area DA1d can be spaced apart from the first-third display area DA1c along the first direction DR1, and the second-third display area DA2c can be located between the first-third display area DA1c and the first-fourth display area DA1d along the first direction DR1. In the plan view, the first-fifth display area DA1e can be spaced apart from the first-fourth display area DA1d along the first direction DR1, and the second-fourth display area DA2d can be located between the first-fourth display area DA1d and the first-fifth display area DA1e along the first direction DR1.

[0083] The pixel circuit PC can be located in the first-first display area DA1a, the first-second display area DA1b, the first-third display area DA1c, the first-fourth display area DA1d, and the first-fifth display area DA1e. The pixel circuit PC may not be located in the second-first display area DA2a, the second-second display area DA2b, the second-third display area DA2c, and the second-fourth display area DA2d.

[0084] A first driving circuit DC1 can be located in the second-first display area DA2a and can provide a first driving signal to the pixel circuit PC. A second driving circuit DC2 can be located in the second-second display area DA2b and can provide a second driving signal to the pixel circuit PC. A third driving circuit DC3 can be located in the second-third display area DA2c and can provide a third driving signal to the pixel circuit PC. A fourth driving circuit DC4 can be located in the second-fourth display area DA2d and can provide a fourth driving signal to the pixel circuit PC. For example, each of the first to fourth driving signals can be a scan signal or a transmit signal.

[0085] In the plan view, each of the first to fourth driving circuits DC1, DC2, DC3, and DC4 may not overlap with the pixel circuit PC. In the plan view, each of the first to fourth driving circuits DC1, DC2, DC3, and DC4 may be arranged between the pixel circuits PC in the first direction DR1.

[0086] Each of the first to fourth drive circuits, DC1, DC2, DC3, and DC4, can be Figure 1 The scanning drive circuit SDC or the transmit drive circuit EDC is used, but the embodiments are not limited to these. For example, when the first drive circuit DC1 is Figure 1 When the scan drive circuit SDC is activated, the first drive signal can be a scan signal, and when the first drive circuit DC1 is... Figure 1 When the transmit drive circuit EDC is used, the first drive signal can be a transmit signal. In an embodiment, at least some of the first to fourth drive circuits DC1, DC2, DC3, and DC4 can be the same circuit. In an embodiment, the first to fourth drive circuits DC1, DC2, DC3, and DC4 can be different circuits.

[0087] The input pad group IPG, output pad group OPG, and crack detection circuit CDC can be located in the peripheral area PA. In an embodiment, the input pad group IPG, output pad group OPG, and crack detection circuit CDC can be located in the second peripheral area PA2. In a plan view, the input pad group IPG and output pad group OPG can overlap with the driver chip DIC.

[0088] The input pad group (IPG) can include input pads. These input pads can transmit signals from a circuit board input connected to the end of the display panel (DP) to the driver chip (DIC).

[0089] The output pad group (OPG) may include control output pads (CO) and data output pads (DO). The control output pads (CO) can receive control signals from the driver chip (DIC). For example, each of the control output pads (CO) can receive a scan control signal (SCTL) or a transmit control signal (EMCTL) from the drive controller (CON) included in the driver chip (DIC). Figure 1 Each of the control output pads (CO) can transmit a control signal to the corresponding one in the drive circuit (DC) via a control connection line.

[0090] Each of the data output pads (DO) can receive a data signal from the driver chip (DIC). For example, each of the data output pads (DO) can receive a data signal from the data drive circuit (DDC) included in the driver chip (DIC) (see...). Figure 1 Each of the data output pads (DO) can transmit data signals to the corresponding data line via a data connection cable.

[0091] In an embodiment, the control output pad CO can be configured to correspond to the drive circuit DC. In a plan view, the control output pad CO can be configured to correspond to the second-first display area DA2a, the second-second display area DA2b, the second-third display area DA2c, and the second-fourth display area DA2d in the second direction DR2, and the data output pad DO can be configured to correspond to the first-first display area DA1a, the first-second display area DA1b, the first-third display area DA1c, the first-fourth display area DA1d, and the first-fifth display area DA1e in the second direction DR2.

[0092] The first data output pad DO1 can be configured to correspond to the first-first display area DA1a. In an embodiment, in a plan view, the first data output pad DO1 can overlap with the first-first display area DA1a in the second direction DR2.

[0093] The first data output pad DO1 can be electrically connected to the first data line DL1 located in the first-first display area DA1a via the first data connection line DCL1. The first data line DL1 can be electrically connected to some of the pixel circuit PC located in the first-first display area DA1a. That is, the first data output pad DO1 can be electrically connected to some of the pixel circuit PC located in the first-first display area DA1a via the first data connection line DCL1 and the first data line DL1.

[0094] The second data output pad DO2 can be configured to correspond to the first-second display area DA1b. In an embodiment, in a plan view, the second data output pad DO2 can overlap with the first-second display area DA1b in the second direction DR2. In a plan view, the second data output pad DO2 can be spaced apart from the first data output pad DO1 in the first direction DR1.

[0095] The second data output pad DO2 can be electrically connected to the second data line DL2 disposed in the first-second display area DA1b via the second data connection line DCL2. The second data line DL2 can be electrically connected to some of the pixel circuit PCs disposed in the first-second display area DA1b. That is, the second data output pad DO2 can be electrically connected to some of the pixel circuit PCs disposed in the first-second display area DA1b via the second data connection line DCL2 and the second data line DL2. In the plan view, the second data line DL2 can be spaced apart from the first data line DL1 in the first direction DR1, and the second data connection line DCL2 can be spaced apart from the first data connection line DCL1 in the first direction DR1.

[0096] The first control output pad CO1 can be configured to correspond to the second-first display area DA2a. In an embodiment, in a plan view, the first control output pad CO1 can overlap with the second-first display area DA2a in the second direction DR2. In a plan view, the first control output pad CO1 can be located between the first data output pad DO1 and the second data output pad DO2 in the first direction DR1.

[0097] The first control output pad CO1 can be electrically connected to the first drive circuit DC1 disposed in the second-first display area DA2a via the first control connection line CCL1. In the plan view, the first control connection line CCL1 can be located between the first data connection line DCL1 and the second data connection line DCL2 in the first direction DR1.

[0098] The third data output pad DO3 can be configured to correspond to the first-third display area DA1c. In an embodiment, in a plan view, the third data output pad DO3 can overlap with the first-third display area DA1c in the second direction DR2. In a plan view, the third data output pad DO3 can be spaced apart from the second data output pad DO2 in the first direction DR1.

[0099] The third data output pad DO3 can be electrically connected to the third data line DL3 located in the first-third display area DA1c via the third data connection line DCL3. The third data line DL3 can be electrically connected to some of the pixel circuit PC located in the first-third display area DA1c. In other words, the third data output pad DO3 can be electrically connected to some of the pixel circuit PC located in the first-third display area DA1c via the third data connection line DCL3 and the third data line DL3. In the plan view, the third data line DL3 can be spaced apart from the second data line DL2 in the first direction DR1, and the third data connection line DCL3 can be spaced apart from the second data connection line DCL2 in the first direction DR1.

[0100] The second control output pad CO2 can be configured to correspond to the second-second display area DA2b. In an embodiment, in a plan view, the second control output pad CO2 can overlap with the second-second display area DA2b in the second direction DR2. In a plan view, the second control output pad CO2 can be located between the second data output pad DO2 and the third data output pad DO3 in the first direction DR1.

[0101] The second control output pad CO2 can be electrically connected to the second drive circuit DC2 located in the second-second display area DA2b via the second control connection line CCL2. In the plan view, the second control connection line CCL2 can be located between the second data connection line DCL2 and the third data connection line DCL3 in the first direction DR1.

[0102] The fourth data output pad DO4 can be configured to correspond to the first-fourth display area DA1d. In an embodiment, in a plan view, the fourth data output pad DO4 can overlap with the first-fourth display area DA1d in the second direction DR2. In a plan view, the fourth data output pad DO4 can be spaced apart from the third data output pad DO3 in the first direction DR1.

[0103] The fourth data output pad DO4 can be electrically connected to the fourth data line DL4 located in the first-fourth display area DA1d via the fourth data connection line DCL4. The fourth data line DL4 can be electrically connected to some of the pixel circuit PC located in the first-fourth display area DA1d. That is, the fourth data output pad DO4 can be electrically connected to some of the pixel circuit PC located in the first-fourth display area DA1d via the fourth data connection line DCL4 and the fourth data line DL4. In the plan view, the fourth data line DL4 can be spaced apart from the third data line DL3 in the first direction DR1, and the fourth data connection line DCL4 can be spaced apart from the third data connection line DCL3 in the first direction DR1.

[0104] The third control output pad CO3 can be configured to correspond to the second-third display area DA2c. In an embodiment, in a plan view, the third control output pad CO3 can overlap with the second-third display area DA2c in the second direction DR2. In a plan view, the third control output pad CO3 can be located between the third data output pad DO3 and the fourth data output pad DO4 in the first direction DR1.

[0105] The third control output pad CO3 can be electrically connected to the third drive circuit DC3 located in the second-third display area DA2c via the third control connection line CCL3. In the plan view, the third control connection line CCL3 can be located between the third data connection line DCL3 and the fourth data connection line DCL4 on the first direction DR1.

[0106] The fifth data output pad DO5 can be configured to correspond to the first-fifth display area DA1e. In an embodiment, in a plan view, the fifth data output pad DO5 can overlap with the first-fifth display area DA1e in the second direction DR2. In a plan view, the fifth data output pad DO5 can be spaced apart from the fourth data output pad DO4 in the first direction DR1.

[0107] The fifth data output pad DO5 can be electrically connected to the fifth data line DL5 located in the first-fifth display area DA1e via the fifth data connection line DCL5. The fifth data line DL5 can be electrically connected to some of the pixel circuit PC located in the first-fifth display area DA1e. That is, the fifth data output pad DO5 can be electrically connected to some of the pixel circuit PC located in the first-fifth display area DA1e via the fifth data connection line DCL5 and the fifth data line DL5. In the plan view, the fifth data line DL5 can be spaced apart from the fourth data line DL4 in the first direction DR1, and the fifth data connection line DCL5 can be spaced apart from the fourth data connection line DCL4 in the first direction DR1.

[0108] The fourth control output pad CO4 can be configured to correspond to the second-fourth display area DA2d. In an embodiment, in a plan view, the fourth control output pad CO4 can overlap with the second-fourth display area DA2d in the second direction DR2. In a plan view, the fourth control output pad CO4 can be located between the fourth data output pad DO4 and the fifth data output pad DO5 in the first direction DR1.

[0109] The fourth control output pad CO4 can be electrically connected to the fourth drive circuit DC4 located in the second-fourth display area DA2d via the fourth control connection line CCL4. In the plan view, the fourth control connection line CCL4 can be located between the fourth data connection line DCL4 and the fifth data connection line DCL5 on the first direction DR1.

[0110] In this embodiment, the first data output pad DO1, the first control output pad CO1, the second data output pad DO2, the second control output pad CO2, the third data output pad DO3, the third control output pad CO3, the fourth data output pad DO4, the fourth control output pad CO4, and the fifth data output pad DO5 can be arranged in a row on the first direction DR1.

[0111] The crack detection circuit CDC can be arranged adjacent to the output pad group OPG. In an embodiment, in a plan view, the crack detection circuit CDC can be arranged between the output pad group OPG and the display area DA. Each of the crack detection circuits CDC can be connected to a crack detection line to detect whether a crack exists in the display panel DP. In an embodiment, the display panel DP may include first to fifth crack detection circuits CDC1, CDC2, CDC3, CDC4, and CDC5 spaced apart from each other in the first direction DR1.

[0112] In an embodiment, in a plan view, the first crack detection circuit CDC1 can be disposed on the second direction DR2 between the first data output pad DO1 and the first-first display area DA1a. For example, the first crack detection circuit CDC1 can be electrically connected to the first data connection line DCL1.

[0113] In an embodiment, in a plan view, the second crack detection circuit CDC2 can be disposed on the second direction DR2 between the second data output pad DO2 and the first-second display area DA1b. For example, the second crack detection circuit CDC2 can be electrically connected to the second data connection line DCL2. In an embodiment, in a plan view, the first control connection line CCL1 can be located on the first direction DR1 between the first crack detection circuit CDC1 and the second crack detection circuit CDC2.

[0114] In an embodiment, in a plan view, the third crack detection circuit CDC3 can be disposed on the second direction DR2 between the third data output pad DO3 and the first-third display area DA1c. For example, the third crack detection circuit CDC3 can be electrically connected to the third data connection line DCL3. In an embodiment, in a plan view, the second control connection line CCL2 can be located on the first direction DR1 between the second crack detection circuit CDC2 and the third crack detection circuit CDC3.

[0115] In an embodiment, in a plan view, the fourth crack detection circuit CDC4 can be disposed on the second direction DR2 between the fourth data output pad DO4 and the first-fourth display area DA1d. For example, the fourth crack detection circuit CDC4 can be electrically connected to the fourth data connection line DCL4. In an embodiment, in a plan view, the third control connection line CCL3 can be located on the first direction DR1 between the third crack detection circuit CDC3 and the fourth crack detection circuit CDC4.

[0116] In an embodiment, in a plan view, the fifth crack detection circuit CDC5 can be disposed on the second direction DR2 between the fifth data output pad DO5 and the first-fifth display area DA1e. For example, the fifth crack detection circuit CDC5 can be electrically connected to the fifth data connection line DCL5. In an embodiment, in a plan view, the fourth control connection line CCL4 can be located on the first direction DR1 between the fourth crack detection circuit CDC4 and the fifth crack detection circuit CDC5.

[0117] Figure 4 and Figure 5 It is a diagram. Figure 3 A magnified plan view of region A.

[0118] In the following text, reference will be made to Figures 3 to 5 Describe the arrangement of pixel circuits (PC) and light-emitting elements (ED) in the first and second display areas. Figure 4 The diagram illustrates the pixel circuit PC and the first driving circuit DC1, and... Figure 5 The diagram shows the electrical connections respectively. Figure 4 The pixel circuit PC has a light-emitting element ED.

[0119] refer to Figures 3 to 5The first pixel circuit PU1 and the second pixel circuit PU2 can be disposed in the first-first display area DA1a, and the third pixel circuit PU3 and the fourth pixel circuit PU4 can be disposed in the first-second display area DA1b. The first pixel circuit PU1 may include a first red pixel circuit PC1a, a first green pixel circuit PC1b, and a first blue pixel circuit PC1c disposed on the first direction DR1. The second pixel circuit PU2 may include a second red pixel circuit PC2a, a second green pixel circuit PC2b, and a second blue pixel circuit PC2c disposed on the first direction DR1. The third pixel circuit PU3 may include a third red pixel circuit PC3a, a third green pixel circuit PC3b, and a third blue pixel circuit PC3c disposed on the first direction DR1. The fourth pixel circuit PU4 may include a fourth red pixel circuit PC4a, a fourth green pixel circuit PC4b, and a fourth blue pixel circuit PC4c disposed on the first direction DR1. The first driving circuit DC1 may be disposed in the second-first display area DA2a, and the pixel circuit PC may not be disposed in the second-first display area DA2a.

[0120] Each of the first unit pixel circuit PU1 and the third unit pixel circuit PU3 may be adjacent to the second-first display area DA2a (i.e., the first driving circuit DC1). For example, in a plan view, the first unit pixel circuit PU1 may be located between the second-first display area DA2a (i.e., the first driving circuit DC1) and the second unit pixel circuit PU2 in the first direction DR1. For example, in a plan view, the third unit pixel circuit PU3 may be located between the second-first display area DA2a (i.e., the first driving circuit DC1) and the fourth unit pixel circuit PU4 in the first direction DR1.

[0121] The light-emitting element ED can be disposed on the pixel circuit PC and the driving circuit DC. The first unit light-emitting element EU1, electrically connected to the first unit pixel circuit PU1, can be disposed in the second-first display area DA2a. The first unit light-emitting element EU1 may include a first red light-emitting element ED1a electrically connected to the first red pixel circuit PC1a, a first green light-emitting element ED1b electrically connected to the first green pixel circuit PC1b, and a first blue light-emitting element ED1c electrically connected to the first blue pixel circuit PC1c. Each of the first red light-emitting element ED1a, the first green light-emitting element ED1b, and the first blue light-emitting element ED1c may overlap with the first driving circuit DC1 in the plan view.

[0122] The second unit light-emitting element EU2, which is electrically connected to the second unit pixel circuit PU2, can be disposed in the first-first display area DA1a. The second unit light-emitting element EU2 may include a second red light-emitting element ED2a electrically connected to the second red pixel circuit PC2a, a second green light-emitting element ED2b electrically connected to the second green pixel circuit PC2b, and a second blue light-emitting element ED2c electrically connected to the second blue pixel circuit PC2c.

[0123] A third unit light-emitting element EU3, electrically connected to the third unit pixel circuit PU3, can be disposed in the second-first display area DA2a. The third unit light-emitting element EU3 may include a third red light-emitting element ED3a electrically connected to the third red pixel circuit PC3a, a third green light-emitting element ED3b electrically connected to the third green pixel circuit PC3b, and a third blue light-emitting element ED3c electrically connected to the third blue pixel circuit PC3c. Each of the third red light-emitting element ED3a, the third green light-emitting element ED3b, and the third blue light-emitting element ED3c may overlap with the first driving circuit DC1 in the plan view.

[0124] The fourth unit light-emitting element EU4, which is electrically connected to the fourth unit pixel circuit PU4, can be disposed in the first-second display area DA1b. The fourth unit light-emitting element EU4 may include a fourth red light-emitting element ED4a electrically connected to the fourth red pixel circuit PC4a, a fourth green light-emitting element ED4b electrically connected to the fourth green pixel circuit PC4b, and a fourth blue light-emitting element ED4c electrically connected to the fourth blue pixel circuit PC4c.

[0125] Figure 5 The illustration shows two unit light-emitting elements EU1 and EU3 arranged on the first direction DR1 in the second-first display area DA2a. However, this is an example, and the embodiment is not limited to this. Three or more unit light-emitting elements can be arranged on the first direction DR1 in the second-first display area DA2a. Furthermore, Figure 5 The illustration shows light-emitting elements included in each unit light-emitting element arranged in a strip shape; however, this is an example, and the embodiment is not limited thereto. Furthermore, the light-emitting elements included in each unit light-emitting element can be arranged in various ways, such as Pentile. ® Type or Diamond Pentile ® Various type settings for models, etc. Additionally, refer to the above. Figure 4 and Figure 5 The content described can be basically applied to the same purpose. Figure 3 Near the second-second display area DA2b, near the second-third display area DA2c, and near the second-fourth display area DA2d.

[0126] Figure 6The illustration includes Figure 3 A cross-sectional view of an example display panel in a display device.

[0127] refer to Figures 3 to 6 In this embodiment, the display panel DP may include a substrate SUB, a buffer layer BFL, a circuit layer CL, and a light-emitting element layer EDL. The circuit layer CL may include a driving circuit DC, a pixel circuit PC, an insulating layer, connecting electrodes, a first shielding layer SHL1, a driving signal line DSL, a bridging line BRL, and a second shielding layer SHL2. The light-emitting element layer EDL may include light-emitting elements ED and a pixel defining layer PDL. For convenience, Figure 6 The illustrations show some of the constructions included in the circuit layer CL and some of the constructions included in the light-emitting element layer EDL. For example, Figure 6 The diagram illustrates the first red pixel circuit PC1a and the second red pixel circuit PC2a located in the first-first display area DA1a within the pixel circuit PC, and the first driving circuit DC1 located in the second-first display area DA2a within the driving circuit DC. Additionally, Figure 6 The illustration shows a first red light-emitting element ED1a and a second red light-emitting element ED2a disposed in the second-first display area DA2a.

[0128] The substrate SUB can be an insulating substrate consisting of transparent or opaque materials or made of transparent or opaque materials.

[0129] A buffer layer (BFL) can be disposed on the substrate SUB. The buffer layer BFL prevents or reduces the penetration of impurities, oxygen, or moisture through the substrate SUB into the upper part of the substrate SUB. The buffer layer BFL can comprise inorganic materials such as silicon compounds or metal oxides. For example, the buffer layer BFL can comprise silicon oxide (SiO₂). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x Aluminum nitride (AlN) x ), tantalum oxide (TaO) x ), hafnium oxide (HfO) x Zirconia (ZrO) x ) or titanium dioxide (TiO) x These can be used individually or in combination with each other. The buffer layer BFL can have a single-layer structure or a multi-layer structure including multiple insulating layers. In embodiments, the buffer layer BFL can be omitted.

[0130] The first red pixel circuit PC1a and the second red pixel circuit PC2a can be disposed on the buffer layer BFL and in the first-first display area DA1a. The first red pixel circuit PC1a may include a first red pixel transistor TR1a, and the second red pixel circuit PC2a may include a second red pixel transistor TR2a.

[0131] A first driving circuit DC1 can be disposed on the buffer layer BFL and in the second-first display area DA2a. The first driving circuit DC1 may include a driving circuit transistor TR_D. In an embodiment, the driving circuit transistor TR_D can provide a driving signal to the gate electrode of each of the first red pixel transistor TR1a and the second red pixel transistor TR2a via a driving signal line DSL. For example, in... Figure 6 In the middle, each of the first red pixel transistor TR1a and the second red pixel transistor TR2a can be connected to Figure 2 The anode of the light-emitting element ED (e.g., Figure 6 The sixth pixel transistor T6 is the pixel electrode PE. In this case, the first driving circuit DC1 can be the one that provides the emission signal to the gate electrode of each of the first red pixel transistor TR1a and the second red pixel transistor TR2a. Figure 1 The transmitter drive circuit is EDC. However, this is just an example, and the embodiments are not limited to this, and the first drive circuit DC1 can be... Figure 1 The scanning drive circuit SDC.

[0132] Each of the first red pixel transistor TR1a, the second red pixel transistor TR2a, and the driving circuit transistor TR_D may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0133] The active layer ACT can be disposed on the buffer layer BFL. The active layer ACT can include oxide semiconductors, silicon semiconductors, or organic semiconductors. For example, the oxide semiconductor can include at least one oxide selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor can include amorphous silicon or polycrystalline silicon. The active layer ACT can include a source region, a drain region, and a channel region located between the source and drain regions. The source and drain regions can have higher conductivity than the channel region.

[0134] The first insulating layer IL1 can be disposed on the active layer ACT. The first insulating layer IL1 can cover the active layer ACT on the buffer layer BFL. For example, the first insulating layer IL1 can include an inorganic insulating material.

[0135] The gate electrode GE can be disposed on the first insulating layer IL1. The gate electrode GE can overlap with the channel region of the active layer ACT. The gate electrode GE can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive materials. For example, the gate electrode GE can include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum, alloys containing silver, alloys containing copper, alloys containing molybdenum, and aluminum nitride (AlN). x ), Tungsten nitride (WN) x Titanium nitride (TiN) x ), Chromium nitride (CrN) x ), Tantalum nitride (TaN) x ), SrRuO x ), zinc oxide (ZnO) x Indium tin oxide (ITO), tin oxide (SnO) x Indium oxide (InO) x Gallium oxide (GaO) x Gate electrodes (GE) can be single-layer structures or multilayer structures comprising multiple conductive layers.

[0136] The second insulating layer IL2 can be disposed on the gate electrode GE. The second insulating layer IL2 can cover the gate electrode GE on the first insulating layer IL1. For example, the second insulating layer IL2 may include an inorganic insulating material.

[0137] The source electrode SE and drain electrode DE can be disposed on the second insulating layer IL2. The source electrode SE and drain electrode DE can be connected to the source region and drain region of the active layer ACT, respectively. Each of the source electrode SE and drain electrode DE can include a conductive material. Each of the source electrode SE and drain electrode DE can have a single-layer structure or a multilayer structure including multiple conductive layers.

[0138] The third insulating layer IL3 can be disposed on the source electrode SE and the drain electrode DE. For example, the third insulating layer IL3 may include inorganic insulating materials and / or organic insulating materials.

[0139] The first to fifth connecting electrodes CNE1, CNE2, CNE3, CNE4, and CNE5, and the first shielding layer SHL1, may be disposed on the third insulating layer IL3. Each of the first to fifth connecting electrodes CNE1, CNE2, CNE3, CNE4, and CNE5, and the first shielding layer SHL1, may include a conductive material. Each of the first to fifth connecting electrodes CNE1, CNE2, CNE3, CNE4, and CNE5, and the first shielding layer SHL1, may have a single-layer structure or a multi-layer structure including multiple conductive layers.

[0140] The first connection electrode CNE1 can be electrically connected to the drive circuit transistor TR_D of the first drive circuit DC1. For example, the first connection electrode CNE1 can be connected to the source electrode SE of the drive circuit transistor TR_D through a contact hole penetrating the third insulating layer IL3.

[0141] The second connection electrode CNE2 and the third connection electrode CNE3 can be electrically connected to the first red pixel transistor TR1a of the first red pixel circuit PC1a. For example, the second connection electrode CNE2 can be connected to the gate electrode GE of the first red pixel transistor TR1a through a contact hole penetrating the second insulating layer IL2 and the third insulating layer IL3. For example, the third connection electrode CNE3 can be connected to the source electrode SE of the first red pixel transistor TR1a through a contact hole penetrating the third insulating layer IL3.

[0142] The fourth connection electrode CNE4 and the fifth connection electrode CNE5 can be electrically connected to the second red pixel transistor TR2a of the second red pixel circuit PC2a. For example, the fourth connection electrode CNE4 can be connected to the gate electrode GE of the second red pixel transistor TR2a through a contact hole penetrating the second insulating layer IL2 and the third insulating layer IL3. For example, the fifth connection electrode CNE5 can be connected to the source electrode SE of the second red pixel transistor TR2a through a contact hole penetrating the third insulating layer IL3.

[0143] The first shielding layer SHL1 can be disposed on the first driving circuit DC1. The first shielding layer SHL1 can be disposed between the first driving circuit DC1 and the bridge wire BRL. The first shielding layer SHL1 can also be disposed on the pixel circuit PC. Voltage can be applied to the first shielding layer SHL1, and the first shielding layer SHL1 can prevent or reduce signal noise and / or signal coupling above the first driving circuit DC1 and / or above the pixel circuit PC.

[0144] The first shielding layer SHL1 may define vias and dummy vias. Each of the vias and dummy vias may penetrate the first shielding layer SHL1 in the thickness direction. A conductive pattern formed of the same layer as the first shielding layer SHL1 may be disposed within each of the vias in the first shielding layer SHL1. For example, as... Figure 6 As shown, the first connecting electrode CNE1 can be disposed inside the first through hole TH1a in the first shielding layer SHL1, the second connecting electrode CNE2 and the third connecting electrode CNE3 can be disposed inside the second through hole TH1b in the first shielding layer SHL1, and the fourth connecting electrode CNE4 and the fifth connecting electrode CNE5 can be disposed inside the third through hole TH1c in the first shielding layer SHL1, but the embodiment is not limited to this.

[0145] Unlike vias, each of the dummy vias in the first shielding layer SHL1 may not have a conductive pattern formed by the same layer as the first shielding layer SHL1 inside. For example, as Figure 6 As shown, the first dummy hole DMH1 in the first shielding layer SHL1 has no conductive pattern inside, and the entire first dummy hole DMH1 can be filled with the fourth insulating layer IL4. Each of the dummy holes can serve as a channel for venting internal gases generated during the formation of the insulating layer. That is, each of the dummy holes can be a degassing channel.

[0146] In this embodiment, the first to fifth connecting electrodes CNE1, CNE2, CNE3, CNE4, and CNE5, as well as the first shielding layer SHL1, can be disposed in the same layer. For example, the first to fifth connecting electrodes CNE1, CNE2, CNE3, CNE4, and CNE5, as well as the first shielding layer SHL1, can comprise the same material and can be formed substantially simultaneously.

[0147] The fourth insulating layer IL4 may be disposed on the first to fifth connecting electrodes CNE1, CNE2, CNE3, CNE4 and CNE5 and the first shielding layer SHL1. For example, the fourth insulating layer IL4 may comprise an organic insulating material.

[0148] The drive signal line DSL, the bridging wire BRL, and the sixth connecting electrode CNE6 can be disposed on the fourth insulating layer IL4. Each of the drive signal line DSL, the bridging wire BRL, and the sixth connecting electrode CNE6 may include a conductive material. Each of the drive signal line DSL, the bridging wire BRL, and the sixth connecting electrode CNE6 may have a single-layer structure or a multi-layer structure including multiple conductive layers.

[0149] The drive signal line DSL can transmit drive signals (e.g., transmit signals or scan signals) provided from the first drive circuit DC1 to the pixel circuit PC.

[0150] Figure 6 The illustration shows that the drive signal line DSL comprises separate portions; however, the drive signal line DSL can be continuous and connected as a single unit. For example, the drive signal line DSL can be connected to each of the first connection electrode CNE1, the second connection electrode CNE2, and the fourth connection electrode CNE4 through a contact hole penetrating the fourth insulating layer IL4. Accordingly, the drive signal line DSL can transmit the drive signal provided from the first drive circuit DC1 to the gate electrode GE of the first red pixel transistor TR1a of the first red pixel circuit PC1a and the gate electrode GE of the second red pixel transistor TR2a of the second red pixel circuit PC2a.

[0151] The bridging wire BRL can be configured to electrically connect a first red pixel circuit PC1a disposed in a first-first display area DA1a and a first red light-emitting element ED1a disposed in a second-first display area DA2a. The bridging wire BRL may include a first end electrically connected to the first red pixel circuit PC1a in the first-first display area DA1a and a second end electrically connected to the first red light-emitting element ED1a in the second-first display area DA2a.

[0152] For example, the first end of the bridging wire BRL can be connected to the third connection electrode CNE3 through a contact hole penetrating the fourth insulating layer IL4. Accordingly, the first end of the bridging wire BRL can be electrically connected to the source electrode SE of the first red pixel transistor TR1a.

[0153] In an embodiment, such as Figure 6 As shown, the drive signal line DSL and the bridge line BRL can be located on the same layer. In an embodiment, the drive signal line DSL and the bridge line BRL can be located on different layers.

[0154] The sixth connecting electrode CNE6 can be connected to the fifth connecting electrode CNE5 through a contact hole that penetrates the fourth insulating layer IL4.

[0155] The fifth insulating layer IL5 can be disposed on the drive signal line DSL, the bridge wire BRL, and the sixth connection electrode CNE6. For example, the fifth insulating layer IL5 may include an organic insulating material.

[0156] The seventh connecting electrode CNE7, the eighth connecting electrode CNE8, and the second shielding layer SHL2 can be disposed on the fifth insulating layer IL5. Each of the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, and the second shielding layer SHL2 may include a conductive material. Each of the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, and the second shielding layer SHL2 may have a single-layer structure or a multilayer structure including multiple conductive layers.

[0157] The seventh connecting electrode CNE7 can be connected to the sixth connecting electrode CNE6 through a contact hole that penetrates the fifth insulating layer IL5.

[0158] The eighth connecting electrode CNE8 can be connected to the second end of the bridge wire BRL through a contact hole that penetrates the fifth insulating layer IL5.

[0159] The second shielding layer SHL2 can be disposed on the bridging line BRL. The second shielding layer SHL2 can also be disposed on the drive signal line DSL. The second shielding layer SHL2 can be disposed between the drive signal line DSL and the pixel electrode PE of the light-emitting element ED. Voltage can be applied to the second shielding layer SHL2, and the second shielding layer SHL2 can prevent or reduce signal noise and / or signal coupling above the bridging line BRL, above the drive signal line DSL, and / or below the pixel electrode PE.

[0160] The second shielding layer SHL2 can define vias and dummy vias. Each of the vias and dummy vias can penetrate the second shielding layer SHL2 in the thickness direction. A conductive pattern formed of the same layer as the second shielding layer SHL2 can be formed inside each of the vias in the second shielding layer SHL2. For example, as... Figure 6 As shown, the seventh connecting electrode CNE7 can be disposed inside the fourth through hole TH2a in the second shielding layer SHL2, and the eighth connecting electrode CNE8 can be disposed inside the fifth through hole TH2b in the second shielding layer SHL2, but the embodiment is not limited to this.

[0161] Unlike through-holes, each of the dummy holes in the second shielding layer SHL2 may not have a conductive pattern formed by the same layer as the second shielding layer SHL2 inside. For example, as Figure 6 As shown, the second dummy via DMH2 in the second shielding layer SHL2 has no conductive pattern inside, and the entire second dummy via DMH2 can be filled with the sixth insulating layer IL6. Each of the dummy vias can serve as a channel for venting internal gases generated during the formation of the insulating layer. That is, each of the dummy vias can be a degassing channel.

[0162] In this embodiment, the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, and the second shielding layer SHL2 can be disposed in the same layer. For example, the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, and the second shielding layer SHL2 can comprise the same material and can be formed substantially simultaneously.

[0163] The sixth insulating layer IL6 can be disposed on the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, and the second shielding layer SHL2. For example, the sixth insulating layer IL6 may include an organic insulating material.

[0164] The first red light-emitting element ED1a and the second red light-emitting element ED2a can be disposed on the sixth insulating layer IL6. Each of the first red light-emitting element ED1a and the second red light-emitting element ED2a may include a pixel electrode PE, a first functional layer FL, an emitting layer EL, a second functional layer FU, and a common electrode CE.

[0165] The pixel electrode PE can be disposed on the sixth insulating layer IL6. The pixel electrode PE can include a conductive material. The pixel electrode PE can have a single-layer structure or a multilayer structure including multiple conductive layers. For example, the pixel electrode PE can be an anode.

[0166] The pixel electrode PE of the first red light-emitting element ED1a disposed in the second-first display area DA2a can be connected to the eighth connection electrode CNE8 through a contact hole penetrating the sixth insulating layer IL6. Accordingly, the pixel electrode PE of the first red light-emitting element ED1a disposed in the second-first display area DA2a can be electrically connected to the source electrode SE of the first red pixel transistor TR1a disposed in the first-first display area DA1a through the eighth connection electrode CNE8, the bridging wire BRL, and the third connection electrode CNE3.

[0167] The pixel electrode PE of the second red light-emitting element ED2a disposed in the first-first display area DA1a can be connected to the seventh connection electrode CNE7 through a contact hole penetrating the sixth insulating layer IL6. Accordingly, the pixel electrode PE of the second red light-emitting element ED2a disposed in the first-first display area DA1a can be electrically connected to the source electrode SE of the second red pixel transistor TR2a disposed in the first-first display area DA1a through the seventh connection electrode CNE7, the sixth connection electrode CNE6, and the fifth connection electrode CNE5.

[0168] A pixel defining layer (PDL) may be disposed on a pixel electrode (PE). The PDL may cover the peripheral portion of the pixel electrode (PE) and may define a pixel opening that exposes the central portion of the pixel electrode (PE). The emission region may be defined by the pixel opening. For example, the PDL may include an organic insulating material. In embodiments, the PDL may further include an inorganic or organic material, which includes (or contains) a light-shielding material having a black color.

[0169] The first functional layer FL can be disposed on the pixel electrode PE. For example, the first functional layer FL may include a hole transport layer and / or a hole injection layer.

[0170] In this embodiment, the emitting layer EL may be disposed on the first functional layer FL. The emitting layer EL may include a light-emitting material. For example, the emitting layer EL may include an organic light-emitting material.

[0171] In the embodiments, the organic light-emitting material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. Examples of low-molecular-weight organic compounds may include copper phthalocyanine, N,N'-diphenylbenzidine, or tri-(8-hydroxyquinoline)aluminum, etc. Examples of high-molecular-weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, poly(phenylenevinylene), or polyfluorene, etc. These materials may be used alone or in combination.

[0172] The second functional layer FU can be disposed on the emitter layer EL. For example, the second functional layer FU may include an electron transport layer and / or an electron injection layer.

[0173] The common electrode CE can be disposed on the second functional layer FU. In an embodiment, the common electrode CE can be disposed integrally in the display area DA. That is, the common electrode CE of the first red light-emitting element ED1a and the common electrode CE of the second red light-emitting element ED2a can be connected as one unit. For example, the common electrode CE can be a cathode.

[0174] As mentioned above, reference has been made. Figure 6 An example of the cross-sectional structure of a display panel DP is described, but this is an example and the embodiments are not limited thereto, and the number of conductive layers and insulating layers included in the circuit layer CL and the arrangement of the structures can be varied.

[0175] According to an embodiment, the driving circuit DC can be disposed in the second display area of ​​the display area DA. Since the light-emitting element ED is also disposed in the second display area where the driving circuit DC is disposed, the size of the area in the display device DD where no image is displayed can be reduced. In other words, the unused space of the display device DD can be reduced.

[0176] Furthermore, since the drive circuits DC are spaced apart from each other in the first direction DR1 within the display area DA, the length and size of the bridging wire BRL can be reduced compared to the case where the drive circuits DC are only located at the outer edge of the display area DA. Therefore, the increase in signal noise caused by an excessively long bridging wire BRL can be prevented or reduced. Additionally, since the display panel DP includes a first shielding layer SHL1 and a second shielding layer SHL2, signal noise and / or signal coupling in the display area DA can be prevented or reduced. Therefore, the display quality of the display device DD can be improved.

[0177] Figure 7 The illustration includes Figure 3 A plan view of an example of a common voltage line in a display device. Figure 8 The illustration includes Figure 3 A plan view of another example of a common voltage line in a display device.

[0178] refer to Figure 3 , Figure 7 and Figure 8 The display panel DP of the display device DD may further include a means for transmitting the common voltage ELVSS (see...). Figure 2 A common voltage line VSL is transmitted to the light-emitting element ED. In an embodiment, the common voltage line VSL may be located in the display area DA. For example, each of the common voltage lines VSL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. Although not illustrated in the figures, each of the common voltage lines VSL may extend to the second peripheral area PA2 and may receive the common voltage ELVSS through the power pads located in the second peripheral area PA2.

[0179] In an embodiment, such as Figure 7 As shown, the common voltage line VSL can be located in the first display area where the pixel circuit PC is located, and may not be located in the second display area where the driving circuit DC is located. That is, in the plan view, each of the common voltage lines VSL may not overlap with the driving circuit DC. In other words, in the plan view, each of the common voltage lines VSL may be spaced apart from the driving circuit DC. The common voltage line VSL may be located in the first-first display area DA1a, the first-second display area DA1b, the first-third display area DA1c, the first-fourth display area DA1d, and the first-fifth display area DA1e, and may not be located in the second-first display area DA2a, the second-second display area DA2b, the second-third display area DA2c, and the second-fourth display area DA2d.

[0180] In an embodiment, such as Figure 8 As shown, a common voltage line VSL can be disposed in either the first display area where the pixel circuit PC is disposed or the second display area where the driving circuit DC is disposed. That is, in the plan view, at least one of the common voltage lines VSL can overlap with the driving circuit DC. The common voltage line VSL can be disposed in the first-first display area DA1a, the first-second display area DA1b, the first-third display area DA1c, the first-fourth display area DA1d, the first-fifth display area DA1e, the second-first display area DA2a, the second-second display area DA2b, the second-third display area DA2c, and the second-fourth display area DA2d.

[0181] Each of the common voltage lines VSL may include a common electrode CE connected to the light-emitting element ED (see...). Figure 6The connection portion CPa. In an embodiment, each of the common voltage lines VSL may include connection portions CPa spaced apart from each other on the second direction DR2.

[0182] According to an embodiment, the common voltage line VSL for transmitting the common voltage ELVSS to the common electrode CE can be connected to the common electrode CE in the display area DA. Correspondingly, the common voltage line VSL is located in the peripheral area (e.g., Figure 3 Compared to the case where the first peripheral region PA1 is connected to the common electrode CE, the unused space of the display device DD can be further reduced.

[0183] Figure 9 The illustration includes Figure 3 A cross-sectional view of an example of the connection portion of the common voltage line in a display device. Figure 10 The illustration includes Figure 3 A cross-sectional view of another example of the connection portion of the common voltage line in a display device.

[0184] In the following text, reference will be made to Figure 9 and Figure 10 An example describing the connection structure between the connection portion CPa of the common voltage line VSL and the common electrode CE. Figure 9 and Figure 10 The diagram illustrates the common voltage line VSL and Figure 6 The second shielding layer SHL2 is disposed in the same layer (i.e., disposed between the fifth insulating layer IL5 and the sixth insulating layer IL6), but this is an example and the embodiment is not limited thereto, and the common voltage line VSL can be with the pixel electrode PE (see Figure 6 ) is set in the same layer as the bridged BRL (see Figure 6 ) is set in the same layer, or with the first shielding layer SHL1 (see Figure 6 Set in the same layer.

[0185] refer to Figure 9 In an embodiment, the common voltage line VSL may have a multilayer structure including a first layer VSLa, a second layer VSLb, and a third layer VSLc. For example, each of the first layer VSLa and the third layer VSLc may include Ti and the second layer VSLb may include Al, but the embodiment is not limited thereto.

[0186] In an embodiment, an insulating layer (e.g., a sixth insulating layer IL6 and a pixel defining layer PDL) disposed above the common voltage line VSL can define an opening OP that exposes at least a portion of the upper surface of the common voltage line VSL (e.g., the upper surface of the third layer VSLc). An insulating layer OP disposed above the pixel defining layer PDL and the emitter layer EL (see...) Figure 6A portion of the second functional layer FU above the opening OP can be located inside the opening OP and can contact the upper surface of the common voltage line VSL.

[0187] The second functional layer FU can define a via TH that exposes a portion of the upper surface of the common voltage line VSL in the opening OP. For example, after forming the second functional layer FU, the via TH can be formed by a laser drilling process to penetrate the second functional layer FU in the thickness direction within the opening OP.

[0188] A portion of the common electrode CE, positioned above the second functional layer FU, may be located inside the opening OP and may contact the portion of the upper surface of the common voltage line VSL exposed by the via TH in the second functional layer FU. Accordingly, the common electrode CE may be electrically connected to the common voltage line VSL and the common voltage ELVSS (see...). Figure 2 It can be transmitted to the common electrode CE.

[0189] refer to Figure 10 In an embodiment, the common voltage line VSL may have a multilayer structure comprising a first layer VSLa, a second layer VSLb, and a third layer VSLc. The common voltage line VSL may include a tip structure. For example, the side surface of each of the first layer VSLa and the third layer VSLc may protrude from the side surface of the second layer VSLb in a direction away from the center of the common voltage line VSL (e.g., in an outward direction). For example, the second layer VSLb may be etched using an etch material with a higher etch rate than that for the first layer VSLa and the third layer VSLc, thereby forming the common voltage line VSL with the tip structure.

[0190] In an embodiment, an insulating layer (e.g., a sixth insulating layer IL6 and a pixel defining layer PDL) disposed above the common voltage line VSL can define an opening OP' that exposes the entire upper and side surfaces of the common voltage line VSL.

[0191] Set in the pixel confinement layer (PDL) and the emission layer (EL) (see Figure 6 A portion of the second functional layer FU above the common voltage line VSL can be located within the opening OP'. The second functional layer FU can be separated (or disconnected) within the opening OP' by the tip structure of the common voltage line VSL. Because the second functional layer FU is separated (or disconnected) by the tip structure of the common voltage line VSL, the second functional layer FU can expose at least a portion of the side surface of the second layer VSLb. Accordingly, the common electrode CE can contact the side surface of the second layer VSLb within the opening OP'. Accordingly, the common electrode CE can be electrically connected to the common voltage line VSL and the common voltage ELVSS (see...). Figure 2 It can be transferred to the common electrode CE.

[0192] Figure 11 This is a plan view illustrating an example of traces included in a display panel according to an embodiment. Figure 12 It is a diagram. Figure 11 A cross-sectional view of an example display panel.

[0193] In addition to the display panel DP', which further includes the encapsulation layer ENC, the input sensing layer ISL, the sensing pads IPD, and the traces TL, see below for reference. Figure 11 and Figure 12 The described display panel DP' can be compared with the above reference. Figure 3 and Figure 6 The described display panels (DP) are essentially the same or similar. Therefore, repeated descriptions will be omitted or simplified.

[0194] refer to Figure 11 and Figure 12 The encapsulation layer ENC can be disposed on the light-emitting element layer EDL. The encapsulation layer ENC can be disposed on the common electrode CE. The encapsulation layer ENC can seal the light-emitting element ED disposed in the display area DA.

[0195] The encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation layer ENC may include a first inorganic encapsulation layer IEL1 disposed on the common electrode CE, an organic encapsulation layer OEL disposed on the first inorganic encapsulation layer IEL1, and a second inorganic encapsulation layer IEL2 disposed on the organic encapsulation layer OEL.

[0196] In one embodiment, the organic encapsulation layer (OEL) may be entirely disposed within the display area DA and may extend to the portion of the first peripheral area PA1 adjacent to the display area DA (e.g., the inner portion). Alternatively, the organic encapsulation layer (OEL) may not be disposed in another portion of the first peripheral area PA1 away from the display area DA (e.g., the outer portion).

[0197] The input sensing layer ISL can be disposed on the encapsulation layer ENC. In an embodiment, the input sensing layer ISL may include a first sensing insulating layer IIL1, a first sensing conductive layer ICL1, a second sensing insulating layer IIL2, a second sensing conductive layer ICL2, and a third sensing insulating layer IIL3. In an embodiment, the first sensing insulating layer IIL1 may be omitted.

[0198] Each of the first sensing conductive layer ICL1 and the second sensing conductive layer ICL2 may include a conductive material such as a metal, alloy, or transparent conductive material. Each of the first sensing conductive layer ICL1 and the second sensing conductive layer ICL2 may have a single-layer structure or a multilayer structure including multiple conductive layers.

[0199] The second sensing insulating layer IIL2 may cover the first sensing conductive layer ICL1, and the third sensing insulating layer IIL3 may cover the second sensing conductive layer ICL2. Each of the first to third sensing insulating layers IIL1, IIL2 and IIL3 may include inorganic insulating material or organic insulating material.

[0200] like Figure 11 As shown, the input sensing layer ISL may include multiple sensing electrodes TE. The sensing electrodes TE may include a first sensing electrode TE1 and a second sensing electrode TE2.

[0201] Each of the first sensing electrodes TE1 may extend along a first direction DR1 and may be disposed along a second direction DR2. Each of the first sensing electrodes TE1 may include a first sensing pattern SP1 and a first conductive pattern BP1. In an embodiment, the first sensing pattern SP1 and the first conductive pattern BP1 may be formed integrally.

[0202] The second sensing electrodes TE2 may each extend in the second direction DR2 and may be disposed in the first direction DR1. Each of the second sensing electrodes TE2 may include a second sensing pattern SP2 and a second conductive pattern BP2. Each of the second conductive patterns BP2 may be a bridging pattern for connecting two second sensing patterns SP2 that are adjacent to each other in the second direction DR2.

[0203] In the embodiments, although not in Figure 11 The detailed illustration shows that each of the first sensing electrode TE1 and the second sensing electrode TE2 may include multiple wires intersecting each other, and may have a grid shape defining multiple openings in the plan view. For example, each of the first sensing pattern SP1 and the second sensing pattern SP2 may have a grid shape in the plan view.

[0204] In an embodiment, each of the first sensing pattern SP1, the second sensing pattern SP2, the first conductive pattern BP1, and the second conductive pattern BP2 may include in... Figure 12 The first sensing conductive layer ICL1 and / or the second sensing conductive layer ICL2 may be included in the first sensing conductive layer ICL1 and / or the second sensing conductive layer ICL2. For example, the first sensing pattern SP1, the second sensing pattern SP2 and the first conductive pattern BP1 may be included in the second sensing conductive layer ICL2 and the second conductive pattern BP2 may be included in the first sensing conductive layer ICL1, but the embodiments are not limited thereto.

[0205] The sensing pad IPD can be located in the peripheral area PA. In an embodiment, the sensing pad IPD can be located in the second peripheral area PA2. The sensing pad IPD can receive sensing signals from the sensing drive circuit.

[0206] The trace TL can connect the sensing electrode TE and the sensing pad IPD, respectively. The trace TL can include a first trace TL1 and a second trace TL2.

[0207] Each of the first traces TL1 can electrically connect a corresponding one of the first sensing electrodes TE1 disposed on the second direction DR2 to a corresponding one of the sensing pads IPD. In an embodiment, in a plan view, a portion of each of the first traces TL1 can overlap with the display area DA.

[0208] In an embodiment, such as Figure 12 As shown, the first trace TL1 can be disposed below the light-emitting element ED. The first trace TL1 can be included in the circuit layer CL. In an embodiment, the first trace TL1 can be disposed between the first shielding layer SHL1 and the second shielding layer SHL2, but the embodiment is not limited thereto.

[0209] Each of the first traces TL1 may include a first end TL1a connected to a corresponding one of the sensing pads IPD, a second end TL1b connected to a corresponding one of the first sensing electrodes TE1, and a connection portion TL1c connecting the first end TL1a and the second end TL1b.

[0210] In this embodiment, the first end TL1a can be connected to a corresponding sensing pad IPD in the second peripheral region PA2. The second end TL1b can be connected to a corresponding first sensing electrode TE1 in the first peripheral region PA1. The connection portion TL1c between the first end TL1a and the second end TL1b can extend through the display area DA.

[0211] In an embodiment, the second end TL1b of the first trace TL1 can be connected to a corresponding one of the first sensing electrodes TE1 in the outer portion of the first peripheral region PA1 where no organic encapsulation layer OEL is disposed. That is, the second end TL1b of the first trace TL1 can be connected to a corresponding one of the first sensing electrodes TE1 outside the organic encapsulation layer OEL in a plan view. For example, a first sensing pattern SP1 of each of the first sensing electrodes TE1 connected to the first trace TL1 may include an extension SP1e that extends to overlap with the second end TL1b of a corresponding strip of the first trace TL1. The extension SP1e can be connected to the second end TL1b of the corresponding strip of the first trace TL1 through a contact hole CNT penetrating an insulating layer (e.g., the first sensing insulating layer IIL1) disposed below the extension SP1e. The contact hole CNT can be located in the outer portion of the first peripheral region PA1 where no organic encapsulation layer OEL is disposed. That is, in a plan view, the contact hole CNT may not overlap with the organic encapsulation layer OEL.

[0212] Each of the second traces TL2 can electrically connect a corresponding one of the second sensing electrodes TE2 set on the first direction DR1 to a corresponding one of the sensing pads IPD.

[0213] In an embodiment, the second trace TL2 may be disposed in the same layer as the first trace TL1. That is, the first trace TL1 and the second trace TL2 may comprise the same material and may be formed substantially simultaneously.

[0214] In this embodiment, unlike the first trace TL1, each of the second traces TL2 may not overlap with the display area DA in the plan view. For example, the first end of each of the second traces TL2 may be connected to a corresponding one of the sensing pads IPD in the second peripheral area PA2. The second end of each of the second traces TL2 may be connected to a corresponding one of the second sensing electrodes TE2 in the portion of the first peripheral area PA1 located between the display area DA and the second peripheral area PA2.

[0215] In an embodiment, the second end of the second trace TL2 may be connected to a corresponding one of the second sensing electrodes TE2 in the outer portion of the first peripheral region PA1 where no organic encapsulation layer OEL is disposed. That is, the second end of the second trace TL2 may be connected to a corresponding one of the second sensing electrodes TE2 outside the organic encapsulation layer OEL in a plan view. For example, one of the second sensing patterns SP2 of each of the second sensing electrodes TE2 connected to the second trace TL2 may include an extension SP2e that extends to overlap with the second end of a corresponding line in the second trace TL2. The extension SP2e may be connected to the second end of the corresponding line in the second trace TL2 through a contact hole penetrating an insulating layer (e.g., the first sensing insulating layer IIL1) disposed below the extension SP2e. The contact hole may be located in the outer portion of the first peripheral region PA1 where no organic encapsulation layer OEL is disposed (e.g., the region between the organic encapsulation layer OEL and the bending region BA). That is, in a plan view, the contact hole may not overlap with the organic encapsulation layer OEL.

[0216] According to an embodiment, the trace TL for connecting the sensing pad IPD and the sensing electrode TE can be included in the circuit layer CL, and therefore, at least some of the traces TL can be configured to partially overlap with the display area DA. Accordingly, compared to the case where all of the traces TL are configured to overlap only with the peripheral area PA outside the display area DA, the unused space of the display device DD can be further reduced.

[0217] Figure 13 This is a block diagram illustrating an electronic device according to an embodiment.

[0218] refer to Figure 13 In this embodiment, the electronic device 900 may include a processor 910, a memory device 920, a storage device 930, an input / output (“I / O”) device 940, a power supply 550, and a display device 960. Here, the display device 960 may correspond to the display device DD described above. The electronic device 900 may further include multiple ports for communicating with video cards, sound cards, memory cards, or Universal Serial Bus (“USB”) devices, etc.

[0219] Processor 910 can perform various computing functions or tasks. In embodiments, processor 910 may be a microprocessor, a central processing unit (“CPU”), or an application processor (“AP”), etc. Processor 910 may be electrically connected to other components via address buses, control buses, or data buses, etc. In embodiments, processor 910 may be electrically connected to an expansion bus such as a peripheral component interconnect (“PCI”) bus. Processor 910 may include one or more processors. One or more processors may be configured to perform computing functions or tasks individually, as a group, or as a subset of a processor group.

[0220] The memory device 920 may store data for the operation of the electronic device 900. In embodiments, for example, the memory device 920 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, or a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, or a mobile DRAM device.

[0221] In an embodiment, storage device 930 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, or a CD-ROM device, etc. In an embodiment, I / O device 940 may include an input device such as a keyboard, keypad, mouse device, touch panel, or touch screen, or an output device such as a printer or speaker.

[0222] Power supply 950 can provide power for the operation of electronic device 900. Display device 960 can be electrically connected to other components via a bus or other communication link. In an embodiment, display device 960 may be included in I / O device 940.

[0223] Figure 14 It is shown in the diagram. Figure 13 The electronic device is implemented as an example view of a smartphone. Figure 15 yes Figure 14 An exploded perspective view of an electronic device.

[0224] refer to Figure 14In this embodiment, the electronic device 900 can be implemented as a smartphone. However, the electronic device 900 is not limited to this, and for example, it can be implemented as a television, mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation system, computer monitor, laptop computer, head-mounted display (“HMD”), or kiosk, etc. Reference will be made below to… Figure 14 and Figure 15 An embodiment in which the electronic device 900 is implemented as a smartphone is described in more detail.

[0225] refer to Figure 14 and Figure 15 In one embodiment, the electronic device 900 may include a window WU, a display device 960, and a housing HM. The window WU and the housing HM may be combined to define the appearance of the electronic device 900.

[0226] Display device 960 can display an image. Display device 960 may include a display area DA for displaying the image and a peripheral area PA surrounding the display area DA. Pixels PX used to generate the image may be disposed in the display area DA. Display device 960 may correspond to the aforementioned display device DD.

[0227] The window WU may define the front surface of the electronic device 900. The window WU may have light-transmitting properties. For example, the window WU may include a resin film such as polyimide or ultra-thin glass.

[0228] The housing HM can be integrated with the window WU. The housing HM can be integrated with the window WU to provide internal space. The display device 960 can be housed within the internal space provided between the housing HM and the window WU. Various components such as optical films, pads, heating layers, processors, memory devices, storage devices, I / O devices, or power supplies can be further housed within the internal space. The housing HM can comprise a material with relatively high rigidity. The housing HM can stably protect the components housed within the internal space from external impacts.

[0229] Therefore, due to the layout of the display area and the components within the display area as described above, the display panel and the electronic device including the display panel can have reduced unused space and improved display quality.

[0230] Although embodiments and implementations have been described herein, other embodiments and modifications will be apparent from that description. Therefore, this disclosure is not limited to such embodiments, but rather to the broader scope of the claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, comprising: A substrate includes a display area and a peripheral area, the display area including a first-first display area, a first-second display area spaced apart from the first-first display area in a first direction, and a second-first display area located between the first-first display area and the first-second display area in the first direction; Pixel circuits are disposed in the first-first display area and the first-second display area; A first driving circuit is disposed in the second-first display area, and the first driving circuit is configured to provide a first driving signal to the pixel circuit; A light-emitting element is disposed in each of the first-first display area, the first-second display area, and the second-first display area; A first data output pad is disposed in the peripheral area, and the first data output pad is electrically connected to the first pixel circuit disposed in the first display area of ​​the pixel circuit. The second data output pad is disposed in the peripheral area. The second data output pad is electrically connected to the second pixel circuit disposed in the first-second display area in the pixel circuit. The second data output pad is spaced apart from the first data output pad in the first direction. as well as A first control output pad is disposed in the peripheral area. The first control output pad is electrically connected to the first drive circuit. The first control output pad is located between the first data output pad and the second data output pad in the first direction.

2. The display device according to claim 1, wherein, The first data output pad, the second data output pad, and the first control output pad are arranged in a row in the first direction.

3. The display device according to claim 1, further comprising: A first data line is disposed in the first display area, and the first data line is electrically connected to the first data output pad. A second data line is disposed in the first-second display area, and the second data line is electrically connected to the second data output pad; The first data connection line connects the first data output pad to the first data line. The second data connection line connects the second data output pad and the second data line, and the second data connection line is spaced apart from the first data connection line in the first direction; as well as A first control connection line connects the first control output pad and the first drive circuit, and the first control connection line is located between the first data connection line and the second data connection line in the first direction.

4. The display device according to claim 3, further comprising: A first crack detection circuit is disposed in a second direction intersecting the first direction between the first data output pad and the first-first display area; as well as A second crack detection circuit is disposed in the second direction between the second data output pad and the first-second display area, and the second crack detection circuit is spaced apart from the first crack detection circuit in the first direction. The first control connection line is located between the first crack detection circuit and the second crack detection circuit in the first direction.

5. The display device according to claim 1, wherein, The display area further includes a first-third display area spaced apart from the first-second display area in the first direction, and a second-second display area located between the first-second display area and the first-third display area in the first direction. The pixel circuit is further disposed in the first-third display area, and The light-emitting element is further disposed in the first-third display area and the second-second display area.

6. The display device according to claim 5, further comprising: A second driving circuit is disposed in the second-second display area, and the second driving circuit is configured to provide a second driving signal to the pixel circuit. A third data output pad is disposed in the peripheral area. The third data output pad is electrically connected to the third pixel circuit disposed in the first-third display area in the pixel circuit. The third data output pad is spaced apart from the second data output pad in the first direction. as well as A second control output pad is disposed in the peripheral area. The second control output pad is electrically connected to the second drive circuit. The second control output pad is located between the second data output pad and the third data output pad in the first direction.

7. The display device according to claim 6, wherein, Each of the first driving circuit and the second driving circuit is a scanning driving circuit or a transmitting driving circuit.

8. The display device according to claim 1, wherein, The pixel circuit further includes a third pixel circuit disposed in the first-first display area, and The light-emitting element includes a first light-emitting element disposed in the second-first display area and electrically connected to the first pixel circuit, and a second light-emitting element disposed in the first-first display area and electrically connected to the third pixel circuit.

9. The display device according to claim 8, wherein, The first pixel circuit is located between the second-first display area and the third pixel circuit in the first direction.

10. The display device according to claim 8, further comprising: The bridging wire includes a first end electrically connected to the first pixel circuit in the first-first display area and a second end electrically connected to the first light-emitting element in the second-first display area; and A first shielding layer is disposed between the bridge wire and the first drive circuit.

11. The display device according to claim 10, wherein, The first shielding layer defines the first through hole and the first dummy hole. The conductive pattern, located in the same layer as the first shielding layer, is disposed inside the first through-hole, and There is no conductive pattern inside the first dummy hole.

12. The display device according to claim 10, further comprising: A drive signal line is disposed on the first shielding layer, and the drive signal line is configured to transmit the first drive signal provided by the first drive circuit to the first pixel circuit and the third pixel circuit.

13. The display device according to claim 12, wherein, The drive signal line and the bridge wire are located on the same layer.

14. The display device according to claim 10, further comprising: The second shielding layer is disposed on the bridge wire.

15. The display device according to claim 1, further comprising: A common voltage line is provided in the display area and is subject to a common voltage. The common voltage line is connected to the common electrode of the light-emitting element in the display area.

16. The display device according to claim 1, further comprising: An organic encapsulation layer is disposed on the light-emitting element; An input sensing layer is disposed on the organic encapsulation layer, and the input sensing layer includes a first sensing electrode and a second sensing electrode; as well as A first trace is disposed below the light-emitting element, and the first trace is electrically connected to the first sensing electrode and the first sensing pad.

17. The display device according to claim 16, wherein, The first trace includes: The first end is connected to the first sensing pad in the peripheral area; The second end is connected to the first sensing electrode in the peripheral region; and The connecting portion connects the first end and the second end, and the connecting portion extends through the display area.

18. The display device according to claim 17, wherein, The second end of the first trace is connected to the first sensing electrode outside the organic encapsulation layer in the plan view.

19. The display device according to claim 16, further comprising: The second trace is located in the same layer as the first trace, and the second trace is electrically connected to the second sensing electrode and the second sensing pad.

20. An electronic device comprising: The display device according to any one of claims 1 to 19 displays an image; as well as A housing that contains the display device.

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