Electronic device and host device coupled to memory device

Abstract

The present invention relates to an electronic device and a host device coupled to a memory device. In one embodiment of the present invention, a host device coupled to a memory device is disclosed, the host device comprising a processor, and the processor performs the following operations: (a) setting a plurality of transfer request description units in a memory; (b) sequentially writing a plurality of command description units into the memory, wherein the number of the plurality of command description units is greater than the number of the plurality of transfer request description units; (c) sequentially and cyclically selecting a transfer request description unit from the plurality of transfer request description units, and sequentially and non-repetitively determining a command description unit; (d) modifying the transfer request description unit according to the command description unit; (e) reading the content of the transfer request description unit to transmit a command in the command description unit to the memory device.

Description

Technical Field

[0001] This invention relates to a master device coupled to a flash memory controller. Background Technology

[0002] In current flash memory controllers conforming to the Universal Flash Storage (UFS) standard, to test the controller's performance when processing multiple commands, the host device sends multiple commands to the flash memory controller to observe its characteristics in processing these commands. However, because the current software architecture of the host device cannot quickly transmit a large number of commands to the flash memory controller, it is not possible to effectively test the limits of the flash memory controller in processing multiple commands. Summary of the Invention

[0003] Therefore, the present invention proposes a command processing method that allows the host device to quickly send a large number of commands to the flash memory controller for processing, thereby solving the problems described in the prior art.

[0004] In one embodiment of the present invention, a main device coupled to a memory device is disclosed, wherein the memory device includes a flash memory controller and a flash memory module, and the main device includes a processor, which performs the following operations: (a) setting a plurality of transfer request description units in a memory; (b) sequentially writing a plurality of command description units into the memory, wherein the number of the plurality of command description units is greater than the number of the plurality of transfer request description units; (c) sequentially and cyclically selecting a transfer request description unit from the plurality of transfer request description units, and sequentially and non-repeatingly determining a command description unit; (d) modifying the transfer request description unit according to the command description unit; (e) reading the contents of the transfer request description unit to transmit a command in the command description unit to the memory device; and (f) determining whether the last command description unit among the plurality of command description units has been processed; if not, the process returns to step (c), and steps (c) to (f) are executed sequentially.

[0005] In one embodiment of the present invention, an electronic device is disclosed, comprising a memory device and a main device, wherein the memory device includes a flash memory controller and a flash memory module, and the main device includes a processor, the processor performing the following operations: (a) setting a plurality of transmission request description units in a memory; (b) sequentially writing a plurality of command description units into the memory, wherein the number of the plurality of command description units is greater than the number of the plurality of transmission request description units; (c) sequentially and cyclically selecting a transmission request description unit from the plurality of transmission request description units, and sequentially and non-repeatingly determining a command description unit; (d) modifying the transmission request description unit according to the command description unit; (e) reading the contents of the transmission request description unit to transmit a command in the command description unit to the memory device; and (f) determining whether the last command description unit among the plurality of command description units has been processed, if not, the process returns to step (c), and steps (c) to (f) are executed sequentially. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0007] Figure 2 This is a schematic diagram illustrating the arrangement of multiple UTRDs and multiple UCDs according to an embodiment of the present invention.

[0008] Figure 3 This is a flowchart of a command processing method according to an embodiment of the present invention.

[0009] [Symbol Explanation]

[0010] 10: Electronic devices

[0011] 50: Main unit

[0012] 52: Processor

[0013] 54: Dynamic Random Access Memory

[0014] 100: Memory device

[0015] 110: Flash memory controller

[0016] 112: Microprocessor

[0017] 112M: Read-Only Memory

[0018] 112C: Program Code

[0019] 114: Memory Interface Circuit

[0020] 116: Buffer memory

[0021] 118: Transmission Interface Circuit

[0022] 118M:M physical layer circuit

[0023] 118P: Unipro layer

[0024] 118U: UFS Controller

[0025] 120: Flash memory module

[0026] 122-1-122-N: Flash memory element

[0027] 142: Command processing circuit

[0028] 144: Temporary Register

[0029] 202_1~202_N: Doorbell temporary register

[0030] 210_1~210_N:UTRD

[0031] 220_1~220_M:UCD

[0032] 300-312: Steps Detailed Implementation

[0033] Figure 1 This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a main device 50 and a memory device 100. The main device 50 may include at least one processor 52 to control the operation of the main device 50, and the main device 50 may further include dynamic random access memory (DRAM) coupled to the processor 52. The memory device 100 can be used to provide storage space to the main device 50 and obtain one or more drive voltages from the main device 50 as power for the memory device 100. In one embodiment, the main device 50 may be a multi-function mobile phone, a wearable device, a tablet computer, a personal computer, or any other electronic product, and the memory device 100 may be an embedded storage device, such as an embedded storage device conforming to the UFS standard. According to this embodiment, the memory device 100 may include a flash memory controller 110 and a flash memory module 120, wherein the memory controller 110 is used to control the operation of the memory device 100 and access the flash memory module 120, and the flash memory module 120 is used to store information. Flash memory module 120 may include at least one flash memory element (e.g., one or more flash memory chips or one or more flash memory dies), such as multiple flash memory elements 122-1, 122-2, ..., and 122-N, where N is a positive integer greater than one.

[0034] like Figure 1 As shown, the flash memory controller 110 may include a microprocessor 112, a read-only memory (ROM) 112M, a memory interface circuit 114, a buffer memory 116, and a transmission interface circuit 118, wherein the above components can be coupled to each other via a bus. The buffer memory 116 is implemented using a static random access memory (SRAM), and the buffer memory 116 can be used to provide internal storage space for the memory controller 110. In addition, the read-only memory 112M in this embodiment is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the flash memory 120. Note that in some examples, program code 112C may be stored in the buffer memory 116 or any type of memory. Additionally, the memory interface circuit may include an encoder and a decoder to encode data written to or read from the flash memory module 120; and the transmission interface circuit 118 may conform to a specific communication standard (e.g., the Universal Flash Storage (UFS) standard) and may communicate according to that specific communication standard, for example, for communication between the memory device 100 and the host device 50. The transmission interface circuit 118 may include a UFS controller 118U, an M-PHY circuit 118M conforming to one of the relevant specifications of the MIPI Alliance, and a Unified Protocol (commonly referred to as UniPro) layer 118P, which can interact with each other, and the UFS controller 118U includes at least a command processing circuit 142 and a register 144.

[0035] In addition, the main device 50 also includes an interface transmission circuit 56 coupled to the memory device 100, wherein the memory transmission circuit 56 includes a UFS controller 132, a Unipro layer 134 and an M physical layer circuit 136 conforming to one of the relevant MIPI Alliance specifications.

[0036] In this embodiment, the master device 50 may send multiple commands to the flash memory controller 110, which then performs read or write operations on the flash memory module 120 according to these commands from the master device 50.

[0037] In this embodiment, in order to test the performance and limits of the memory device 100 in processing multiple commands,

[0038] The master device 50 continuously sends a large number of commands, for example, approximately 10,000 to 50,000 commands, to the memory device 100. As described in the prior art, the architecture of a conventional master device cannot quickly transmit a large number of commands to the memory device 100, resulting in low efficiency on the test memory device 100. Therefore, this embodiment proposes a command processing method in the master device 50 that allows the master device 50 to quickly send a large number of commands to the flash memory controller 110 for processing.

[0039] Specifically, refer to Figure 2The processor 52 in the host device 50 configures multiple UFS transport protocol layer transport request descriptors (UTRDs) 210_1 to 210_N in the DRAM 54. These UTRDs are used by the host device 50 to transmit commands to the memory device 100. In this embodiment, UTRDs 210_1 to 210_N can be based on the architecture defined in UFS Host Controller Interface (HCI) version 3.0 developed by the Joint Electron Device Engineering Council (JEDEC). Specifically, the processor 52 configures 32 UTRDs (i.e., N equals 32), and each UTRD's data structure includes at least a command type, a Crypto config.index (CCI), the lower 32 bits of the data unit number (DUNL), the overall command status, and the upper 32 bits of the data unit number (DUNL). The UTRDs include the upper 32 bits (DUNU), the base address of the UTP command descriptor, the upper 32 bits of the UTP command descriptor base address, the offset of the Response UFS Protocol Information Unit (UPIU), the length of the Response UPIU, the offset of the Physical Region Description Table (PRDT), the length of the PRDT, and so on. It should be noted that the UTRDs 210_1 to 210_N described in this embodiment can conform to or be compatible with the UTRDs described in JEDEC UFS HCI version 3.0. Since those skilled in the art can understand the functions and contents of UTRDs 210_1 to 210_N, detailed descriptions are not provided here.

[0040] The processor 52 in the main device 50 also has multiple UTP Command Descriptor (UCD) 220_1 to 220_M configured in the DRAM 54. The number of UCDs 220_1 to 220_M can be determined according to the number of test commands that the main device 50 needs to send to the memory device 100. For example, if the main device 50 needs to send 10,000 commands to the memory device 100 for testing, then the number of UCDs 220_1 to 220_M is 10,000 (that is, M equals 10,000). In this embodiment, each of UCDs 220_1 to 220_M has the same size, and each of UCDs 220_1 to 220_M includes a command UPIU, a response UPIU, and a PRDT. The command UPIU refers to a command encapsulated in a UPIU packet, the response UPIU refers to a response message from memory device 100 encapsulated in a UPIU packet, and the PRDT describes information pointing to the address of one or more data buffers. In one embodiment, UCDs 220_1 to 220_M have contiguous addresses in DRAM 54, but this invention is not limited thereto.

[0041] Furthermore, the UFS controller 132 internally contains multiple doorbell registers (DBRs) 202_1 to 202_N, which correspond to UTRDs 210_1 to 210_N, respectively. Each doorbell register indicates whether its corresponding UTRD is in a state where commands can be transmitted. For example, if the value of doorbell register 202_1 is "0", it means that UTRD 210_1 cannot currently transmit commands; while if the value of doorbell register 202_1 is "1", it means that UTRD 210_1 is in a state where commands can be transmitted. In this embodiment, only one of the doorbell registers 202_1 to 202_N has a value of "1", while the rest of the doorbell registers are all "0", and the doorbell registers 202_1 to 202_N sequentially and cyclically have values ​​of "1". Furthermore, in this embodiment, a doorbell register is defined as one bit, but this definition is not a limitation of the invention. In other embodiments, multiple bits can be considered as a doorbell register, for example, 32 bits can be considered as a doorbell register, and each bit corresponds to a UTRD, that is, in this case... Figure 2 The "DBR" shown is considered as a bit in the doorbell register.

[0042] In the operation of the main device 50 in this embodiment, the processor 52 first generates multiple commands (UPIU) sequentially. These commands can include various types of commands, such as UFS-based Small Computer System Interface (SCSI) inquiry commands, mode selection commands, pre-fetch commands, security protocol commands, read commands, write commands, verify commands, etc. The read and write commands are considered commands that require user data transfer, the security protocol commands transmit security-related user data or data for setting protected areas, the inquiry and mode selection commands transmit non-user data, and the remaining commands can be considered commands that do not require data transfer. At this time, the processor 52 sets the doorbell register 202_1 to "1" and modifies the contents of UTRD 210_1 corresponding to the doorbell register 202_1 to describe the information of UCD 220_1. For example, since each of UCDs 220_1 to 220_M has the same size, and the size / length of the command UPIU, response UPIU, and PRDT is known, the processor 52 can modify the contents of UTRD 210_1 to describe the starting address, response UPIU offset, response UPIU length, PRDT offset, PRDT length, etc. of UCD 220_1. Furthermore, UCDs 220_1 to 220_M form a software sequence. The processor 52 writes the first command UPIU to the first field (command UPIU) of UCD 220_1. If this command UPIU is neither a read nor a write command, since this command does not require data transfer, the PRDT in UCD 220_1 can remain blank or not point to any meaningful data buffer. If this command UPIU is a read or write command, since this command requires data transfer, the PRDT in UCD 220_1 will point to a data buffer in DRAM 54. This data buffer contains data to be written to memory device 100 or used to store data read from memory device 100. It should be noted that at this time, the response UPIU in UCD 220_1 is blank or does not contain any valid data.

[0043] In addition, the processor 52 simultaneously writes the subsequent command UPIUs into the subsequent UCDs 220_2 to 220_M. Similarly, if the command UPIU is not a read command or a write command, the PRDT in the corresponding UCD can remain blank or not point to any meaningful data buffer; if the command UPIU is a read command or a write command, the PRDT in the corresponding UCD will point to a data buffer in the DRAM 54, where the data buffer contains data that needs to be written into the memory device 100 or is used to store data read from the memory device 100.

[0044] After the processor 52 completes the write / modification of UTRD 210_1 and UCD 220_1, a Direct Memory Access (DMA) circuit in the host device 50 reads UTRD 210_1 and, based on the contents of UTRD 210_1, transmits the command UPIU in UCD 220_1 to the memory device 100. Furthermore, after the command UPIU in UCD 220_1 is transmitted to the memory device 100, the flash memory controller 110 in the memory device 100 executes the command UPIU and, depending on whether the execution of the command UPIU was successful, sends a response message to the host device 50. At this time, the response message is written to the response UPIU in UCD 220_1.

[0045] In this embodiment, to accelerate the transmission of commands from the master device 50 to the memory device 100, after the processor 52 learns through the direct memory access circuit that the command UPIU in UCD 220_1 has been transmitted to the memory device 100, regardless of whether a response is received from the memory device 100, the processor 52 sets the doorbell register 202_1 to "0", sets the doorbell register 202_2 to "1", and modifies the contents of UTRD 210_2 corresponding to the doorbell register 202_2 to describe the information of UCD 220_2. For example, since each of UCDs 220_1 to 220_M has the same size, and the size / length of the command UPIU, response UPIU, and PRDT is known, the processor 52 can modify the contents of UTRD 210_2 to describe the starting address, response UPIU offset, response UPIU length, PRDT offset, PRDT length, etc. of UCD 220_2.

[0046] After processor 52 completes the modification of UTRD 210_2, the direct memory access circuit in host device 50 reads UTRD 210_2 and, based on the contents of UTRD 210_2, transmits the command UPIU in UCD 220_2 to memory device 100. Furthermore, after the command UPIU in UCD 220_2 is transmitted to memory device 100, flash memory controller 110 in memory device 100 executes the command UPIU and, depending on whether the execution of the command UPIU was successful, transmits a response message to host device 50. At this time, the response message is written into the response UPIU in UCD 220_2.

[0047] Similarly, after the processor 52 learns through the direct memory access circuit that the command UPIU in UCD 220_2 has been transmitted to the memory device 100, regardless of whether a response is received from the memory device 100, the processor 52 will set the doorbell register 202_2 to "0", set the doorbell register 202_3 to "1", and modify the contents of UTRD 210_3 corresponding to the doorbell register 202_3 to describe the information of UCD 220_3.

[0048] Based on similar operations, processor 52 sequentially modifies the contents of UTRDs 210_4 to 210_32 and sequentially transmits the relevant command UPIUs to memory device 100. Next, processor 52 returns to the first UTRD 210_1 for processing, but the UCD portion does not return to the first UCD 220_1; instead, it continues processing UCD 220_33, which has not yet had commands written to it. Specifically, processor 52 sets doorbell register 202_1 to "1" and modifies the contents of UTRD 210_1 corresponding to doorbell register 202_1 to describe the information of UCD 220_33. Simultaneously, processor 52 writes the command UPIU to the first field of UCD 220_33. Afterward, the direct memory access circuit reads UTRD 210_33 and, based on the contents of UTRD 210_33, transmits the command UPIUs in UCD 220_33 to memory device 100.

[0049] Next, based on a similar operation, the processor 52 sequentially modifies the contents of UTRD 210_2 to 210_32, and sequentially transmits the relevant commands UPIU stored in UCD 220_34 to 220_64 to the memory device 100.

[0050] Similarly, the processor 52 sequentially and cyclically modifies UTRDs 210_1 to 210_32 and sequentially and non-repeatingly writes data to the remaining UCDs until the last UCD 220_M command UPIU is transmitted to the memory device 100.

[0051] As described above, since the processor 52 does not need to consider whether each command UPIU can be successfully executed by the flash memory controller 110 during the process of transmitting the command UPIU to the memory device 100, that is, it does not need to read the response UPIU of each UCD to make a judgment, the processor 52 can quickly transmit many command UPIUs to the memory device 100 to improve the efficiency of command testing.

[0052] Furthermore, after all the command UPIUs generated by the processor 52 are transmitted to the memory device 100, the processor 52 begins to retrieve the response UPIUs from each UCD 220_1 to 220_M to determine which of the UCDs 220_1 to 220_M has encountered a command execution error, so that engineers can analyze the results of these command tests later.

[0053] It should be noted that the above embodiments use UTRD and UCD from the UFS specification for illustration, but the present invention is not limited thereto. In other embodiments, UTRD can be replaced with a transfer request description unit corresponding to other flash memory specifications, and UCD can be replaced with a command description unit corresponding to other flash memory specifications.

[0054] Figure 3 This is a flowchart of a command processing method according to an embodiment of the present invention. Referring to the above embodiments, the flow of the command processing method is as follows.

[0055] Step 300: Process begins.

[0056] Step 302: Set up multiple transfer request description units in a memory.

[0057] Step 303: Write multiple command description units sequentially into the memory, wherein the number of multiple command description units is greater than the number of multiple transmission request description units.

[0058] Step 304: Select a transmission request description unit from the plurality of transmission request description units sequentially and cyclically, and determine a command description unit sequentially and without repetition.

[0059] Step 306: Modify the transmission request description unit according to the command description unit.

[0060] Step 308: Read the contents of the transmission request description unit to transmit a command in the command description unit to a memory device, and after the memory device executes the command, transmits a response message and writes it to the command description unit.

[0061] Step 310: Determine whether the last command description unit has been processed. If yes, proceed to step 312; otherwise, return to step 302.

[0062] Step 312: Begin reading the response messages from all command description units for analysis.

[0063] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A main device coupled to a memory device, wherein the memory device includes a flash memory controller and a flash memory module, and the main device includes a processor that performs the following operations: (a) Multiple transfer request description units are set in a memory; (b) A plurality of command description units are sequentially written into the memory, wherein the number of the plurality of command description units is greater than the number of the plurality of transmission request description units; (c) Select a transmission request description unit sequentially and cyclically from the plurality of transmission request description units, and determine a command description unit sequentially and without repetition. (d) Modify the transmission request description unit according to the command description unit; (e) Reading the contents of the transmission request description unit to transmit a command from the command description unit to the memory device; and (f) Determine whether the last command description unit among the multiple command description units has been processed. If not, the process returns to step (c) and executes steps (c) to (f) in sequence.

2. The main device as described in claim 1, characterized in that, Each of the plurality of transport request descriptors is a Universal Flash Storage (UFS) transport protocol layer transport request descriptor (UTRD), and each of the plurality of command descriptors is a Universal Flash Storage (UFS) transport protocol (UTP) command descriptor (UCD).

3. The main device as described in claim 2, characterized in that, Each of the multiple command description units contains a command UFS Protocol Information Unit (UPIU), a response UPIU, and a Physical Region Description Table (PRDT).

4. The main device as described in claim 3, characterized in that, In step (d), after the memory device executes the command, it will send a response message and write it to the response UPIU of the UCD. During the execution of steps (a) to (f), the processor will not refer to the content of the response UPIU of the UCD.

5. The main device as described in claim 1, characterized in that, In step (d), after the memory device executes the command, it sends a response message and writes it to the UCD. And in step (f), when it is determined that the last UCD among the plurality of UCDs has been processed, the processor further performs the following operations: (g) Begin reading all response messages from the UCD for analysis.

6. An electronic device comprising: A memory device, comprising a flash memory controller and a flash memory module; and A host device coupled to the memory device, wherein the host device includes a processor, and the processor performs the following operations: (a) Multiple transfer request description units are set in a memory; (b) A plurality of command description units are sequentially written into the memory, wherein the number of the plurality of command description units is greater than the number of the plurality of transmission request description units; (c) Select a transmission request description unit sequentially and cyclically from the plurality of transmission request description units, and determine a command description unit sequentially and without repetition. (d) Modify the transmission request description unit according to the command description unit; (e) Reading the contents of the transmission request description unit to transmit a command from the command description unit to the memory device; and (f) Determine whether the last command description unit among the multiple command description units has been processed. If not, the process returns to step (c) and executes steps (c) to (f) in sequence.

7. The electronic device as claimed in claim 6, characterized in that, Each of the plurality of transport request descriptors is a Universal Flash Storage (UFS) transport protocol layer transport request descriptor (UTRD), and each of the plurality of command descriptors is a Universal Flash Storage (UFS) transport protocol layer command descriptor (UCD).

8. The electronic device as claimed in claim 7, characterized in that, Each of the multiple command description units contains a command UFS Protocol Information Unit (UPIU), a response UPIU, and a Physical Region Description Table (PRDT).

9. The electronic device as claimed in claim 8, characterized in that, In step (d), after the memory device executes the command, it will send a response message and write it to the response UPIU of the UCD. During the execution of steps (a) to (f), the processor will not refer to the content of the response UPIU of the UCD.

10. The electronic device as claimed in claim 6, characterized in that, In step (d), after the memory device executes the command, it sends a response message and writes it to the UCD. And in step (f), when it is determined that the last UCD among the plurality of UCDs has been processed, the processor further performs the following operations: (g) Begin reading all response messages from the UCD for analysis.

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