A method for checking high current wiring in a chip

Abstract

The invention discloses a method for inspecting large current routing in a chip, and belongs to the technical field of chip layout design. The invention determines a metal layer in a layout that passes a conventional inspection, obtains the minimum width and number of through holes of each metal layer corresponding to different current sizes at an extreme operating temperature of the chip, and then writes a DRC rule according to the minimum width and number of through holes of each metal layer corresponding to different current sizes. The Calibre DRC tool is used to execute the DRC rule to identify a first metal layer area and display it through a Calibre RVE tool, generate width information and through hole information of each first metal layer area, and provide modification information for the first metal layer area according to the current size of a test current that needs to pass through. The inspection is performed based on preset DRC rules, and the model is simple, the computing resource requirement is low, the inspection time is reduced, the inspection efficiency is improved, and manual inspection is reduced to improve accuracy.

Description

Technical Field

[0001] The invention relates to the technical field of chip layout design, in particular to a method for inspecting high-current wiring in a chip. Background Art

[0002] The current routing needs to ensure sufficient current density to prevent excessive current density from causing local overheating or even burning the chip. In addition, large current will cause a large amount of heat to be generated inside the chip. If the heat dissipation is poor, the chip temperature may be too high, affecting the life and stability of the chip. Therefore, the inspection of large current routing in the chip is a very important and indispensable part in chip layout design.

[0003] In the prior art, inspection of high-current routing in chips is mostly done by running EM using the Totem tool. Electromagnetic simulation usually involves complex physical models and a large amount of calculations. Especially under high-resolution and multi-frequency conditions, the simulation time may be very long, affecting the design progress. In addition, for large and complex chips, there is no way to complete all EM inspections, and they can only be done through manual inspection, which is not accurate enough. Summary of the invention

[0004] The present invention is to solve the technical problems existing in the prior art. The present invention provides a method for inspecting a large current wiring in a chip, comprising the following steps:

[0005] S1, perform a routine check on the chip layout according to the preset layout design rules. If the routine check is qualified, execute step S2, otherwise, prompt to modify the layout according to the preset layout design rules;

[0006] S2. Determine the metal layer in the layout;

[0007] S3, obtaining the minimum width and number of through holes required for each metal layer to pass different currents at the extreme operating temperature of the chip;

[0008] S4, writing DRC rules according to the minimum width and number of through holes required for each metal layer to pass different currents, and obtaining a preset DRC rule file;

[0009] S5. Mark the test current required to pass through the high current trace in the layout;

[0010] S6. Execute the preset DRC rule file using the Calibre DRC tool, identify the first metal layer area in the layout, and display it through the Calibre RVE tool, where the first metal layer area is a metal layer area that cannot carry the test current required to pass therethrough;

[0011] S7, generating width information and through-hole information of each first metal layer region, and providing modification information for the first metal layer region according to the current size of the test current required to pass through, wherein the modification information includes the required minimum width and the required number of through-holes.

[0012] Furthermore, determining the metal layers in the layout also includes setting each metal layer in the layout to a different color.

[0013] Furthermore, the obtaining of the minimum width and number of through holes required for each metal layer to pass different currents at the extreme operating temperature of the chip is specifically as follows:

[0014] Obtain the maximum allowable current density of each metal layer and the maximum allowable current density of the through hole at the extreme operating temperature of the chip through the chip process manual;

[0015] Based on the maximum allowable current density of each metal layer and the maximum allowable current density of a single through-hole, the current density formula is used to calculate the minimum width and number of through-holes required for each metal layer to pass different current sizes at the chip's extreme operating temperature.

[0016] Furthermore, the DRC rules are written according to the minimum width and number of through holes required for each metal layer to pass different current sizes, and the DRC rules are specifically written in SVRF language format.

[0017] Furthermore, the magnitude of the test current required to be passed is marked on the high current routing line in the layout, and specifically a text label is added to the high current routing line in the layout using a text tool, and the text label is the magnitude of the test current required to be passed.

[0018] The present invention also provides a system for inspecting high current wiring in a chip, comprising:

[0019] A routine inspection module is used to perform routine inspection on the chip layout according to preset layout design rules. If the routine inspection fails, it prompts to modify the layout according to the preset layout design rules;

[0020] A metal layer determination module is used to select and determine the metal layer in the layout;

[0021] A calculation and analysis module, used to analyze the minimum width and number of through holes required for each metal layer to pass different current sizes under the extreme operating temperature of the chip;

[0022] A rule writing module, used for writing DRC rules according to the minimum width and number of through holes required for each metal layer to pass different currents, and obtaining a preset DRC rule file;

[0023] The marking module is used to mark the test current required to pass through the high current traces in the layout;

[0024] A Calibre DRC module is used to execute the preset DRC rule file, identify the first metal layer area in the layout, and display it through the Calibre RVE tool, where the first metal layer area is a metal layer area that cannot carry the corresponding test current required to pass;

[0025] The information generation module is used to generate width information and through-hole information of each first metal layer area, and provide modification information for the first metal layer area according to the current size of the test current required to pass through, wherein the modification information includes the required minimum width and the required number of through-holes.

[0026] Furthermore, the analysis of the chip at the extreme operating temperature, the minimum width and number of through holes required for each metal layer to pass different current sizes, specifically:

[0027] Obtain the maximum allowable current density of each metal layer and the maximum allowable current density of the through hole at the extreme operating temperature of the chip through the chip process manual;

[0028] Based on the maximum allowable current density of each metal layer and the maximum allowable current density of a single through-hole, the current density formula is used to calculate the minimum width and number of through-holes required for each metal layer to pass different current sizes at the chip's extreme operating temperature.

[0029] Furthermore, the DRC rules are written according to the minimum width and number of through holes required for each metal layer to pass different current sizes, and the DRC rules are specifically written in SVRF language format.

[0030] Furthermore, the magnitude of the test current required to be passed is marked on the high current routing line in the layout, and specifically a text label is added to the high current routing line in the layout using a text tool, and the text label is the magnitude of the test current required to be passed.

[0031] The present invention also provides an electronic device, comprising: a memory for storing at least one set of computer instruction sets; a processor for implementing any of the above-mentioned methods for inspecting high current routing in a chip by calling and executing the instruction set stored in the memory.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention first presets layout design rules to perform routine inspection on the layout, and then performs high-current routing inspection after passing the inspection, so as to ensure that the chip layout design meets basic design specifications and standards, and avoid subsequent high-current routing inspection on these layouts, thereby saving time and computing resources, optimizing the inspection process, and improving work efficiency;

[0034] Based on the consideration of temperature influence, the present invention obtains the minimum width and number of through-holes required for each metal layer to pass different currents at the extreme operating temperature of the chip, and compiles DRC rules based on this to ensure that the inspection result is more accurate and reliable. Then, the Calibre DRC tool is used to execute the DRC rules to identify the metal layer area that cannot carry the corresponding test current required to pass, and the Calibre RVE tool is used to display it, so as to realize automatic inspection, reduce manual inspection, and improve accuracy. At the same time, the inspection is based on the preset DRC rules, the model is simple, the computing resource requirements are low, the inspection time is reduced, and the inspection efficiency is improved.

[0035] The present invention obtains the minimum width and number of through-holes required for each metal layer to pass different current sizes under the extreme operating temperature of the chip, obtains the maximum allowable current density data from the chip process manual, and then uses the current density formula to calculate, thereby improving the reliability of calculating the minimum width and number of through-holes required, thereby ensuring that the inspection result is more accurate and reliable;

[0036] The present invention finally uses the Calibre RVE tool to display the metal layer area that cannot carry the corresponding test current that needs to pass through and generates width information and through-hole information of each first metal layer area, and then provides modification information for the first metal layer area according to the current size of the test current that needs to pass through. The modification information includes the required minimum width and the required number of through-holes, thereby improving the intuitiveness of the inspection results, thereby improving the inspection and design efficiency, and providing modification information to further improve the inspection and design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0039] Figure 1 The present invention is a flow chart of a method for inspecting high current wiring in a chip. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0042] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0043] Embodiment 1

[0044] See also Figure 1 As shown, the present invention provides a method for inspecting a high current routing in a chip, which specifically includes the following steps:

[0045] S1, perform a routine check on the chip layout according to the preset layout design rules. If the routine check is qualified, execute step S2, otherwise, prompt to modify the layout according to the preset layout design rules;

[0046] S2. Determine the metal layer in the layout;

[0047] S3, obtaining the minimum width and number of through holes required for each metal layer to pass different currents at the extreme operating temperature of the chip;

[0048] S4, writing DRC rules according to the minimum width and number of through holes required for each metal layer to pass different currents, and obtaining a preset DRC rule file;

[0049] S5. Mark the test current required to pass through the high current trace in the layout;

[0050] S6. Execute the preset DRC rule file using the Calibre DRC tool, identify the first metal layer area in the layout, and display it through the Calibre RVE tool, where the first metal layer area is a metal layer area that cannot carry the test current required to pass therethrough;

[0051] S7, generating width information and through-hole information of each first metal layer region, and providing modification information for the first metal layer region according to the current size of the test current required to pass through, wherein the modification information includes the required minimum width and the required number of through-holes.

[0052] In the above step S2, the step of determining the metal layers in the layout also includes setting each metal layer in the layout to a different color to facilitate identification.

[0053] In integrated circuit design, layout refers to the physical design of the chip. Layout design is a key step in converting the logical design into physical implementation, ensuring that the chip can work correctly during the actual manufacturing process. The high current routing of the chip is mainly on the metal layer. In integrated circuit design, the metal layer is the main medium for signal and power transmission.

[0054] In some embodiments, for the above step S3, the step of obtaining the minimum width and number of through holes required for each metal layer to pass different currents at the extreme operating temperature of the chip is specifically as follows:

[0055] Obtain the maximum allowable current density of each metal layer and the maximum allowable current density of the through hole at the extreme operating temperature of the chip through the chip process manual;

[0056] Based on the maximum allowable current density of each metal layer and the maximum allowable current density of a single through-hole, the current density formula is used to calculate the minimum width and number of through-holes required for each metal layer to pass different current sizes at the chip's extreme operating temperature.

[0057] The specific calculation formula belongs to the prior art and will not be described in detail here.

[0058] In some embodiments, for the above step S4, the DRC rules are written according to the minimum width and number of through holes required for each metal layer to pass different current sizes, and specifically the DRC rules are written in SVRF language format.

[0059] SVRF (Standard Verification Rule Format) is a standard format for describing Design Rule Check (DRC). In the design and manufacturing process of integrated circuits (ICs), DRC is an important step to ensure that the circuit layout meets the requirements of the manufacturing process and avoid manufacturing defects caused by improper design.

[0060] SVRF provides a standardized way to express design rules, which helps share and communicate rules between different tools and different design teams, improves efficiency and reduces misunderstandings. At the same time, SVRF supports a wide range of rule types, including but not limited to minimum spacing, minimum width, overlap requirements, etc. This flexibility enables it to adapt to changes in different process nodes and design requirements.

[0061] In some embodiments, for the above step S5, the required test current size is marked on the high current routing line in the layout, specifically by using a text tool to add a text label on the high current routing line in the layout, and the text label is the required test current size.

[0062] For the above step S6, the preset DRC rule file is executed using the Calibre DRC tool, and the first metal layer area is identified in the layout and displayed through the Calibre RVE tool. The first metal layer area is a metal layer area that cannot carry the corresponding test current required to pass, specifically:

[0063] The Calibre DRC tool identifies the test current required to pass through the high current routing line marked in the publication drawing, and executes the preset DRC rule file. The preset DRC rule file determines the metal layer area that cannot carry the test current required to pass through the high current routing line marked in the corresponding layout according to the stored DRC rules, and uses the metal layer area as the first metal layer area.

[0064] Embodiment 2

[0065] The present invention also provides a system for inspecting high current wiring in a chip, which specifically includes:

[0066] A routine inspection module is used to perform routine inspection on the chip layout according to preset layout design rules. If the routine inspection fails, it prompts to modify the layout according to the preset layout design rules;

[0067] A metal layer determination module is used to select and determine the metal layer in the layout;

[0068] A calculation and analysis module, used to analyze the minimum width and number of through holes required for each metal layer to pass different current sizes under the extreme operating temperature of the chip;

[0069] A rule writing module, used for writing DRC rules according to the minimum width and number of through holes required for each metal layer to pass different currents, and obtaining a preset DRC rule file;

[0070] The marking module is used to mark the test current required to pass through the high current traces in the layout;

[0071] A Calibre DRC module is used to execute the preset DRC rule file, identify the first metal layer area in the layout, and display it through the Calibre RVE tool, where the first metal layer area is a metal layer area that cannot carry the corresponding test current required to pass;

[0072] The information generation module is used to generate width information and through-hole information of each first metal layer area, and provide modification information for the first metal layer area according to the current size of the test current required to pass through, wherein the modification information includes the required minimum width and the required number of through-holes.

[0073] In some embodiments, selecting and determining the metal layer in the layout further includes setting each metal layer in the layout to a different color to facilitate distinction and identification.

[0074] In some embodiments, the analysis of the chip at the extreme operating temperature, the minimum width and number of through holes required for each metal layer to pass different current sizes, is specifically:

[0075] Obtain the maximum allowable current density of each metal layer and the maximum allowable current density of the through hole at the extreme operating temperature of the chip through the chip process manual;

[0076] Based on the maximum allowable current density of each metal layer and the maximum allowable current density of a single through-hole, the current density formula is used to calculate the minimum width and number of through-holes required for each metal layer to pass different current sizes at the chip's extreme operating temperature.

[0077] In some embodiments, the DRC rules are written according to the minimum width and number of through holes required for each metal layer to pass different current sizes, and specifically, the DRC rules are written in SVRF language format.

[0078] In some embodiments, the required test current size is marked on the high current routing line in the layout, and specifically a text label is added to the high current routing line in the layout using a text tool, and the text label is the required test current size.

[0079] Embodiment 3

[0080] The present invention also provides an electronic device, including: a processor, a sending device, an input device, an output device and a memory. The processor can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in the embodiment of the present application. The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM), and is used to store computer program code. The computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes a method as described in any of the above possible implementation methods.

[0081] Embodiment 4

[0082] The present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a method as described in any possible implementation manner.

[0083] The beneficial effects of the present invention are:

[0084] The present invention first presets layout design rules to perform routine inspection on the layout, and then performs high-current routing inspection after passing the inspection, so as to ensure that the chip layout design meets basic design specifications and standards, and avoid subsequent high-current routing inspection on these layouts, thereby saving time and computing resources, optimizing the inspection process, and improving work efficiency;

[0085] Based on the consideration of temperature influence, the present invention obtains the minimum width and number of through-holes required for each metal layer to pass different currents at the extreme operating temperature of the chip, and compiles DRC rules based on this to ensure that the inspection result is more accurate and reliable. Then, the Calibre DRC tool is used to execute the DRC rules to identify the metal layer area that cannot carry the corresponding test current required to pass, and the Calibre RVE tool is used to display it, so as to realize automatic inspection, reduce manual inspection, and improve accuracy. At the same time, the inspection is based on the preset DRC rules, the model is simple, the computing resource requirements are low, the inspection time is reduced, and the inspection efficiency is improved.

[0086] The present invention obtains the minimum width and number of through-holes required for each metal layer to pass different current sizes under the extreme operating temperature of the chip, obtains the maximum allowable current density data from the chip process manual, and then uses the current density formula to calculate, thereby improving the reliability of calculating the minimum width and number of through-holes required, thereby ensuring that the inspection result is more accurate and reliable;

[0087] The present invention finally uses the Calibre RVE tool to display the metal layer area that cannot carry the corresponding test current that needs to pass through and generates width information and through-hole information of each first metal layer area, and then provides modification information for the first metal layer area according to the current size of the test current that needs to pass through. The modification information includes the required minimum width and the required number of through-holes, thereby improving the intuitiveness of the inspection results, thereby improving the inspection and design efficiency, and providing modification information to further improve the inspection and design efficiency.

[0088] In the description of the specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0089] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (RandomAccess Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0090] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for inspecting high current routing in a chip, characterized in that: The following steps are involved: S1, perform a routine check on the chip layout according to the preset layout design rules. If the routine check is qualified, execute step S2, otherwise, prompt to modify the layout according to the preset layout design rules; S2. Determine the metal layer in the layout; S3, obtaining the minimum width and number of through holes required for each metal layer to pass different currents at the extreme operating temperature of the chip; S4, writing DRC rules according to the minimum width and number of through holes required for each metal layer to pass different currents, and obtaining a preset DRC rule file; S5. Mark the test current required to pass through the high current trace in the layout; S6. Execute the preset DRC rule file using the Calibre DRC tool, identify the first metal layer area in the layout, and display it through the Calibre RVE tool, where the first metal layer area is a metal layer area that cannot carry the test current required to pass therethrough; S7, generating width information and through-hole information of each first metal layer region, and providing modification information for the first metal layer region according to the current size of the test current required to pass through, wherein the modification information includes the required minimum width and the required number of through-holes.

2. The method for inspecting high current routing in a chip according to claim 1, characterized in that: The step of determining the metal layers in the layout further includes setting each metal layer in the layout to a different color.

3. The method for inspecting high current wiring in a chip according to claim 1, characterized in that: The obtaining of the minimum width and number of through holes required for each metal layer to pass different currents at the extreme operating temperature of the chip is specifically as follows: Obtain the maximum allowable current density of each metal layer and the maximum allowable current density of the through hole at the extreme operating temperature of the chip through the chip process manual; Based on the maximum allowable current density of each metal layer and the maximum allowable current density of a single through-hole, the current density formula is used to calculate the minimum width and number of through-holes required for each metal layer to pass different current sizes at the chip's extreme operating temperature.

4. The method for inspecting high current routing in a chip according to claim 1, characterized in that: The DRC rules are written according to the minimum width and number of through holes required for each metal layer to pass different current sizes, and the DRC rules are specifically written in SVRF language format.

5. The method for inspecting high current routing in a chip according to claim 1, characterized in that: The large current routing in the layout is marked with the size of the test current that needs to pass through, and specifically a text tool is used to add a text label on the large current routing in the layout, and the text label is the size of the test current that needs to pass through.

6. A system for inspecting large current wiring in a chip, applied to the method for inspecting large current wiring in a chip as claimed in any one of claims 1 to 5, characterized in that: include: A routine inspection module is used to perform routine inspection on the chip layout according to preset layout design rules. If the routine inspection fails, it prompts to modify the layout according to the preset layout design rules; A metal layer determination module is used to select and determine the metal layer in the layout; A calculation and analysis module, used to analyze the minimum width and number of through holes required for each metal layer to pass different current sizes under the extreme operating temperature of the chip; A rule writing module, used for writing DRC rules according to the minimum width and number of through holes required for each metal layer to pass different currents, and obtaining a preset DRC rule file; The marking module is used to mark the test current required to pass through the high current traces in the layout; A Calibre DRC module is used to execute the preset DRC rule file, identify the first metal layer area in the layout, and display it through the Calibre RVE tool, where the first metal layer area is a metal layer area that cannot carry the corresponding test current required to pass; The information generation module is used to generate width information and through-hole information of each first metal layer area, and provide modification information for the first metal layer area according to the current size of the test current required to pass through, wherein the modification information includes the required minimum width and the required number of through-holes.

7. The inspection system for high current routing in a chip according to claim 6, characterized in that: The analysis of the chip at the extreme operating temperature, the minimum width and number of through holes required for each metal layer to pass different current sizes, specifically: Obtain the maximum allowable current density of each metal layer and the maximum allowable current density of the through hole at the extreme operating temperature of the chip through the chip process manual; Based on the maximum allowable current density of each metal layer and the maximum allowable current density of a single through-hole, the current density formula is used to calculate the minimum width and number of through-holes required for each metal layer to pass different current sizes at the chip's extreme operating temperature.

8. The inspection system for high current routing in a chip according to claim 6, characterized in that: The DRC rules are written according to the minimum width and number of through holes required for each metal layer to pass different current sizes, and the DRC rules are specifically written in SVRF language format.

9. The inspection system for high current routing in a chip according to claim 6, characterized in that: The large current routing in the layout is marked with the size of the test current that needs to pass through, and specifically a text tool is used to add a text label on the large current routing in the layout, and the text label is the size of the test current that needs to pass through.

10. An electronic device, characterized in that: include: A memory for storing at least one set of computer instructions; A processor, configured to implement the method for inspecting high current routing in a chip as described in any one of claims 1 to 5 by calling and executing the instruction set stored in the memory.

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