Driving method of display panel, display device

Abstract

Embodiments of the present application provide a display panel driving method and display device, which improve the phenomenon of flashing screen during power-on and power-off. The display panel comprises a pixel circuit, and the pixel circuit comprises a driving transistor and a data writing transistor. The gate of the data writing transistor is electrically connected with a first scan signal line, the first electrode of the data writing transistor is electrically connected with a data line, the second electrode of the data writing transistor is electrically connected with the driving transistor, and the first scan signal line is used for providing a first enable voltage and a first non-enable voltage to the gate of the data writing transistor. The driving process of the display panel comprises a first stage and a display stage, and the first stage is located before and / or after the display stage. The display panel driving method comprises: during at least part of the time period of the first stage, the display driving chip provides a voltage smaller than the first non-enable voltage to the data line.

Description

[0001] This application is based on the parent application with the application date of June 22, 2022, the application number of 202210712141.0, and the invention name of "Driving method of display panel and display device".

TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a driving method of display panel and display device.

BACKGROUND

[0003] With the continuous development of display technology, users have higher and higher requirements for the performance of display devices. However, at present, due to the unreasonable design of power-on and power-off timing, the display device sometimes has a power-on and power-off flashing screen phenomenon. Although this flashing screen phenomenon is short, it can still be seen by users, which greatly affects the user experience.

SUMMARY

[0004] Therefore, the embodiments of the present application provide a driving method of display panel and display device to effectively improve the flashing screen phenomenon of the display device during power-on and power-off.

[0005] In one aspect, the present application provides a driving method of display panel, the display panel comprising a pixel circuit, the pixel circuit comprising a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected with a first scan signal line, a first electrode of the data writing transistor is electrically connected with a data line, a second electrode of the data writing transistor is electrically connected with the driving transistor, and the first scan signal line is used to provide a first enable voltage and a first non-enable voltage to the gate of the data writing transistor.

[0006] The driving process of the display panel comprises a first stage and a display stage, and the first stage is located before and / or after the display stage.

[0007] The driving method comprises: during at least part of the time period of the first stage, the display driving chip provides a voltage smaller than the first non-enable voltage to the data line.

[0008] In another aspect, the present application provides a display device, comprising:

[0009] a display panel comprising a pixel circuit, the pixel circuit comprising a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected with a first scan signal line, a first electrode of the data writing transistor is electrically connected with a data line, a second electrode of the data writing transistor is electrically connected with the driving transistor, and the first scan signal line is used to provide a first enable voltage and a first non-enable voltage to the gate of the data writing transistor.

[0010] a display driving chip, electrically connected with the data line, for providing a voltage less than the first non-enabling voltage to the data line in the first stage, and providing a data voltage to the data line in a display stage, the first stage being before and / or after the display stage

[0011] One of the above technical solutions has the following beneficial effects:

[0012] The inventor found in the research process that the leakage of the data line to the light emitting element is one of the main factors leading to the up and down power flashing screen. In the first stage, that is, in the up and down power stage, the first scan signal line normally refreshes the pixel circuit of the first row to the last row line by line, when the pixel circuit is not refreshed by the first scan signal line, the gate of the data writing transistor in the pixel circuit receives the first non-enabling voltage, and the embodiment of the application can make the gate-source voltage Vgs1 (Vgs1=V GH -V Data ) greater than 0, so that the gate-source voltage Vgs1 is much greater than the threshold voltage of the data writing transistor, at this time, the data writing transistor can be controlled to be in a completely cut-off state, effectively cutting off the connection path between the data line and the light emitting element, and avoiding the leakage of the voltage on the data line to the light emitting element. Since the time when the pixel circuit is not refreshed by the first scan signal line is much greater than the time when the pixel circuit is refreshed by the first scan signal line in a frame time, the embodiment of the application can effectively avoid the abnormal light emission of the light emitting element in the up and down power process, and further effectively improve the flashing screen phenomenon in the up and down power process. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0014] Figure 1 A structural schematic diagram of a display device provided by the embodiment of the application;

[0015] Figure 2 A structural schematic diagram of a pixel circuit provided by the embodiment of the application;

[0016] Figure 3 A timing diagram corresponding to the pixel circuit provided by the embodiment of the application;

[0017] Figure 4A timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0018] Figure 5 Another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0019] Figure 6 Still another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0020] Figure 7 Yet another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0021] Figure 8 Still another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0022] Figure 9 Yet another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0023] Figure 10 Still another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0024] Figure 11 A circuit structure schematic diagram of the first emission shift circuit provided for the embodiment of the present application;

[0025] Figure 12 Still another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0026] Figure 13 Yet another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0027] Figure 14 Still another timing diagram of the display panel in the first stage and the display stage is provided for the embodiment of the present application;

[0028] Figure 15 Another structure schematic diagram of the display device provided for the embodiment of the present application;

[0029] Figure 16 Another structure schematic diagram of the pixel circuit provided for the embodiment of the present application;

[0030] Figure 17 Another timing diagram corresponding to the pixel circuit provided for the embodiment of the present application;

[0031] Figure 18Another timing diagram of the display panel in the first stage and the display stage provided in the embodiments of the present invention;

[0032] Figure 19 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0033] Figure 20 This is another timing diagram corresponding to the pixel circuit provided in the embodiment of the present invention.

Detailed Implementation Methods

[0034] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0036] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0037] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0038] This invention provides a driving method for a display panel, which can be applied to... Figure 1 In the display device shown.

[0039] like Figure 1 As shown, Figure 1 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes a display panel 100 and a display driver chip 200. The display panel 100 includes a pixel circuit 1 and a light-emitting element 2 that are electrically connected.

[0040] like Figure 2 and Figure 3 As shown, Figure 2 This is a schematic diagram of a pixel circuit 1 provided in an embodiment of the present invention. Figure 3This is a timing diagram corresponding to the pixel circuit 1 provided in the embodiment of the present invention. The pixel circuit 1 includes a driving transistor M0 and a data writing transistor M1. The gate of the data writing transistor M1 is electrically connected to the first scan signal line Scan1, the first terminal of the data writing transistor M1 is electrically connected to the data line Data, and the second terminal of the data writing transistor M1 is electrically connected to the driving transistor M0. Specifically, it can be electrically connected to the first terminal of the driving transistor M0.

[0041] The first scan signal line Scan1 is used to provide a first enable voltage V to the gate of the data writing transistor M1. GL and the first non-enable voltage V GH When the first scan signal line Scan1 provides the first enable voltage, the data write transistor M1 is turned on, transmitting the data voltage V on the data line Data. Data When the first scan signal line Scan1 provides a first disabled voltage, the data write transistor M1 is turned off, and the data voltage V... Data Unable to write to drive transistor M0.

[0042] like Figure 4 As shown, Figure 4 This invention provides a timing diagram of a display panel 100 in a first stage T1 and a display stage T2. The driving process of the display panel 100 includes a first stage T1 and a display stage T2, with the first stage T1 located before and / or after the display stage T2. This invention illustrates an example where the driving process of the display panel 100 includes two first stages T1. One first stage T1 is located before the display stage T2, and this first stage T1 is the power-on stage before the display panel 100 enters normal display mode, such as a power-on stage / wake-up stage. The other first stage T1 is located after the display stage T2, and this first stage T1 is the power-off stage after the display panel 100 ends normal display mode, such as a power-off stage / sleep stage.

[0043] Based on this, combined Figures 1-3 The driving method provided in this embodiment of the invention includes: during at least a portion of a time period in the first stage T1, the display driver chip 200 provides a voltage less than a first disabling voltage V to the data line Data. GH The voltage.

[0044] In pixel circuit 1, both driving transistor M0 and data writing transistor M1 are P-type transistors. The threshold voltage of a P-type transistor is less than 0, for example, the threshold voltage can be between -1V and -2V.

[0045] The inventors found in the research process that the leakage of the data line Data to the light emitting element 2 is one of the main factors causing the up and down power-on screen. In the first stage T1, the first scan signal line Scan1 normally refreshes the pixel circuit 1 in the first row to the last row by row, and when the pixel circuit 1 is not refreshed by the first scan signal line Scan1, the gate of the data writing transistor M1 in the pixel circuit 1 receives the first non-enabling voltage V GH The embodiment of the present application can make the gate-source voltage Vgs1 (Vgs1 = V GH -V Data ) of the data writing transistor M1 greater than 0 by providing a voltage less than the first non-enabling voltage V GH to the data line Data during at least part of the first stage T1, so that the gate-source voltage Vgs1 is much greater than the threshold voltage of the data writing transistor M1, and the data writing transistor M1 can be controlled to be completely cut off, effectively cutting off the connection path between the data line Data and the light emitting element 2, and avoiding the leakage of the voltage on the data line Data to the light emitting element 2. Since the time when the pixel circuit 1 is not refreshed by the first scan signal line Scan1 is much greater than the time when the pixel circuit 1 is refreshed by the first scan signal line Scan1 in a frame time, the embodiment of the present application can effectively avoid the abnormal light emission of the light emitting element 2 during the power-on and power-off processes, and further effectively improve the screen flicker phenomenon during the power-on and power-off processes.

[0046] In addition, it also needs to be explained that, referring again to Figure 2 , the pixel circuit 1 further includes a second light emitting control transistor M2, and the second light emitting control transistor M2 is also a P-type transistor. The gate of the second light emitting control transistor M2 is electrically connected with the light emitting control signal line Emit, the first pole of the second light emitting control transistor M2 is electrically connected with the driving transistor M0, and specifically is electrically connected with the second pole of the driving transistor M0, and the second pole of the second light emitting control transistor M2 is electrically connected with the light emitting element 2. In combination with Figure 3 , the light emitting control signal line Emit is used to provide the light emitting enabling voltage V GL ' and the light emitting non-enabling voltage V GH ' to the gate of the second light emitting control transistor M2, wherein the light emitting enabling voltage V GL ' can be equal to the first enabling voltage V GL , and the light emitting non-enabling voltage V GH ' can be equal to the first non-enabling voltage V GH .

[0047] When the light emitting control signal line Emit provides the light emitting enabling voltage V GL ', the second light emitting control transistor M2 is turned on, the driving current flows to the light emitting element 2, and the light emitting element 2 is controlled to emit light. When the light emitting control signal line Emit provides the light emitting non-enabling voltage V GHWhen the second light emitting control transistor M2 is off, the driving current cannot flow to the light emitting element 2, resulting in that the light emitting element 2 does not emit light.

[0048] In the first stage T1, when the light emitting control signal line Emit provides the light emitting non-enabling voltage V GH to the pixel circuit 1, the first electrode of the second light emitting control transistor M2 receives a voltage less than the light emitting non-enabling voltage V GH . GL When the data write transistor M1 is turned on, the voltage transmitted on the data line Data is transmitted to the first electrode of the second light emitting control transistor M2, so that the first electrode of the second light emitting control transistor M2 receives a voltage less than the light emitting non-enabling voltage V GH (the first non-enabling voltage V GH ). GH At this time, the gate-source voltage Vgs2 (Vgs2=V Data ′-V GH ) of the second light emitting control transistor M2 is greater than 0, and is much greater than the threshold voltage of the second light emitting control transistor M2, thereby further improving the off-state reliability of the second light emitting control transistor M2, avoiding the leakage current flowing to the light emitting element 2, and more greatly avoiding the abnormal light emission of the light emitting element 2.

[0049] In order to more greatly improve the screen flashing phenomenon in the power-on and power-off processes, in the embodiment of the present application, the display driving chip 200 provides a voltage less than the first non-enabling voltage V GH to the data line Data throughout the first stage T1.

[0050] In a feasible implementation, referring again to Figure 1 and Figure 2 , the display device further comprises a power supply driving chip 300. The pixel circuit 1 further comprises a first light emitting control transistor M3, which is a P-type transistor. The gate electrode of the first light emitting control transistor M3 is electrically connected with the light emitting control signal line Emit, the first electrode of the first light emitting control transistor M3 is electrically connected with the power supply signal line PVDD, and the second electrode of the first light emitting control transistor M3 is electrically connected with the driving transistor M0, specifically, the first electrode of the driving transistor M0. The light emitting control signal line Emit is used to provide the light emitting enabling voltage V GL ′ and the light emitting non-enabling voltage V GH ′ to the gate electrode of the first light emitting control transistor M3, wherein the light emitting enabling voltage V GLThe first enable voltage V GL The first non-enable voltage V GH ′ can be equal to the first non-enable voltage V GH .

[0051] When the light emission control signal line Emit provides the light emission enable voltage V GL ′, the first light emission control transistor M3 is turned on, and the power supply signal provided by the power supply signal line PVDD is written to the first electrode of the drive transistor M0. When the light emission control signal line Emit provides the light emission non-enable voltage V GH ′, the first light emission control transistor M3 is turned off, and the power supply signal cannot be written to the first electrode of the drive transistor M0.

[0052] Based on this, referring again to Figure 4 , the first stage T1 includes a non-supply period t1 and a supply period t2, and the supply period t2 is located between the non-supply period t1 and the display stage T2. The driving method further includes: in the non-supply period t1, the power supply driving chip 300 does not provide the power supply voltage to the power supply signal line PVDD; and in the supply period t2, the power supply driving chip 300 provides the power supply voltage V PVDD to the power supply signal line PVDD.

[0053] Taking the first stage T1 as the power-on stage as an example, when the display panel 100 is powered on, the display panel 100 first enters the non-supply period t1. If a flash screen phenomenon occurs in the non-supply period t1, the flash screen phenomenon is more likely to be detected by the human eye because there is a certain time interval between the non-supply period t1 and the subsequent display stage T2. For example: when the display panel is turned off, in order to reduce power consumption, basically all signals are in a floating state. Especially the data lines. Therefore, some charges may accumulate on the data lines when the screen is off, causing the potentials of each data line to be different. If the supply period t2 is entered at the beginning, and the power supply signal line PVDD provides the corresponding potential, the panel has the basic condition for light emission. The accumulated charges on the data lines will greatly increase the probability of flash screen. Entering the non-supply period t1 first can reduce the risk of flash screen. Therefore, by making the power supply driving chip 300 not supply power to the power supply signal line PVDD in the non-supply period t1, the pixel circuit 1 cannot receive the power supply voltage V PVDD , so that the light emitting element 2 can be more effectively prevented from abnormally emitting light in the non-supply period t1.

[0054] In addition, it should be noted that, since the embodiment of the present application can control the data writing transistor M1 to be turned off when the data writing transistor M1 is not refreshed, and control the second light emitting control transistor M1 to be turned off when the data writing transistor M1 is refreshed, so as to cut off the connection path between the data writing transistor M1 and the light emitting element 2, even if the power supply driving chip 300 normally supplies power to the power supply signal line PVDD in the power supply period t2, the light emitting element 2 can still avoid abnormal light emission in the power supply period t2.

[0055] In a possible implementation, as shown in Figure 5 , Figure 5 another timing diagram of the display panel 100 provided by the embodiment of the present application in the first stage T1 and the display stage T2 is shown in the following table. GMP It should be noted that the black state voltage V GMP is less than the first non-enabled voltage V GH , and the black state voltage can be a voltage of 0 gray scale.

[0056] The embodiment of the present application can provide the black state voltage V GMP to the data line Data in the power supply period t2, so that even if the data writing transistor M1 is refreshed by the first scan signal line Scan1 to write the black state voltage V GMP to the driving transistor M0, the light emitting element 2 will only present a black state under the action of the black state voltage V GMP , and will not be bright.

[0057] In a possible implementation, again referring to Figure 5 , in the first stage T1, the process of the display driving chip 200 providing voltage to the data line Data further includes: in the non-power supply period t1, the display driving chip 200 provides a constant voltage V1 to the data line Data, and the constant voltage V1 is less than the first non-enabled voltage V GH , so as to effectively control the working state of the data writing transistor M1, and reduce the voltage jump on the data line Data, thereby reducing power consumption.

[0058] Further, the voltage difference between the constant voltage V1 and the first non-enabled voltage V GH is ΔV, and in order to ensure that the gate-source voltage Vgs1 of the data writing transistor M1 is greater than the threshold voltage of the data writing transistor M1 to a greater extent, ΔV can be greater than or equal to 1V.

[0059] In a possible implementation, in combination with Figure 5 , as shown in Figure 6 ,Figure 6 Another timing diagram of the display panel 100 provided in the embodiments of the present invention in the first stage T1 and the display stage T2, wherein in the first stage T1, the process of the display driver chip 200 providing voltage to the data line Data further includes: during the non-power supply period t1, the display driver chip 200 providing a voltage less than or equal to the black state voltage V to the data line Data. GMP The voltage.

[0060] During the non-power supply period t1, a voltage less than or equal to the black state voltage V is supplied to the data line Data. GMP The voltage can be adjusted to avoid excessively high data voltage during this period, thus saving power consumption to some extent. Specifically, see... Figure 6 When the constant voltage V1 is equal to the black-state voltage V GMP At that time, the display driver chip 200 provides a black state voltage V to the data line Data during both the power supply period t2 and the non-power supply period t1. GMP The data line (Data) experiences no voltage fluctuations throughout the entire first phase (T1), resulting in lower power consumption.

[0061] In one feasible implementation, such as Figure 7 As shown, Figure 7 This invention provides another timing diagram for the display panel 100 in the first stage T1 and the display stage T2. The non-power supply period t1 includes x sub-periods t11, where the voltage supplied to the data line Data in sub-period t11_i is less than the voltage supplied to the data line Data in sub-period t11_i+1, and x is a positive integer greater than or equal to 2, where 1 ≤ i ≤ x-1. For clarity, Figure 6 The i-th sub-time period is denoted by the attached figure t11_i.

[0062] In this configuration, during x sub-periods t11 of the non-powered period t1, the voltage supplied by the display driver chip 200 to the data line Data is gradually increased until it is increased to the same level as the black state voltage V in the xth sub-period t11_x. GMP Approximate to or equal to the black-state voltage V GMP This prevents the voltage jump on the data line from being too large and impacting the screen when transitioning from a non-powered period t1 to a powered period t2.

[0063] Furthermore, the duration of sub-time period t11 is t0. Where k is a positive integer greater than or equal to 1, and f1 is the frequency of the first scan signal output by the first scan signal line Scan1 during the display stage T2. One frame is the time interval.

[0064] With this configuration, the duration of each sub-period t11 is an integer multiple of the frame time. Therefore, within one frame, when the first scan signal line Scan1 refreshes the first row of sub-pixel circuits 1 to the last row of pixel circuits 1 in one round, the data voltage V written by the first row of sub-pixel circuits 1 to the last row of pixel circuits 1... Data Each corresponds to a single, constant data voltage V supplied to the data line Data within a single sub-period t11. Data That is, the data voltage V written by the multi-row pixel circuit 1 Data They are the same, therefore, within one frame, the data voltage V Data The same degree of control is applied to the data writing transistor M1 in the multi-row pixel circuit 1, which improves the uniformity of control over different pixel circuits 1 within the same frame time.

[0065] Furthermore, in the first sub-period t11_1, the voltage supplied to the data line Data is less than 2.5V, or, in the first sub-period t11_1, a ground voltage is supplied to the data line Data.

[0066] In the above configuration, by providing a voltage less than 2.5V to the data line Data in the first sub-period t11_1, or by directly providing a ground voltage, the voltage provided to the data line Data in the first sub-period t11_1 can be made smaller. That is, the voltage provided to the data line Data in the first sub-period t11_1 is made smaller than the black state voltage V. GMP There is a large voltage difference between them. If the non-power supply period t1 includes a large number of sub-periods t11, the subsequent sub-periods t11 will affect the data voltage V. Data When gradually increasing the voltage, there is a large potential for improvement, which in turn affects the data voltage V corresponding to other sub-time periods t11. Data The design is more flexible.

[0067] In one feasible implementation, the display panel 100 has at least two display modes, such as a normal mode, an always-on display (AOD) mode, and a high brightness (HBM) mode. When the display panel 100 executes the always-on display mode during display phase T2, the display panel 100 typically displays only part of the content, such as only displaying time information. Therefore, in this display mode, the display panel 100 typically displays at a lower brightness. However, when the display panel 100 executes the high brightness mode during display phase T2, in order to optimize display performance, the display panel 100 typically displays at a higher brightness.

[0068] Since different display modes correspond to different brightness levels, when the display panel 100 executes different display modes during display phase T2, the black state voltage V corresponding to each display mode will vary. GMP Power supply voltage V PVDD and the first non-enable voltage V GH They can also be different. For example, compared to the normal mode, the brightness level in the high-brightness mode is higher. Therefore, when the display panel 100 executes the high-brightness mode during the display phase T2, its corresponding black state voltage V... GMP Larger.

[0069] like Figure 8 As shown, Figure 8 This is another timing diagram of the display panel 100 provided in the embodiments of the present invention in the first stage T1 and the display stage T2. When the display panel 100 executes different display modes in the display stage T2, the first disabling voltage V corresponding to the first stage T1 is... GH Equal, power supply voltage V PVDD Equal, black-state voltage V GMP They are also equal.

[0070] Taking the first stage T1 as the power-on stage as an example, regardless of the display mode executed by the display panel 100 after entering the display stage T2 after power-on, within the first stage T1, the data voltage V supplied to the data line Data is set. Data At that time, the data voltage V Data They are all based on the same first non-enable voltage V. GH This is set, for example, the first disabling voltage V. GH The first disabled voltage V corresponding to the display panel 100 executing the normal mode during the display phase T2. GH1 The voltage supplied by the power driver chip 300 to the power signal line PVDD is also the same power supply voltage V. PVDD For example, the power supply voltage V PVDD The power supply voltage V corresponding to the display panel 100 executing the normal mode during the display phase T2. PVDD1 The display driver chip 200 provides a black-state voltage V to the data line Data during power supply period t2. GMP It is also the same voltage, for example, the black-state voltage V. GMP The black state voltage V corresponding to the display panel 100 in normal mode during display phase T2. GMP1 .

[0071] With this setting, regardless of the display mode executed by the display panel 100 in the display phase T2, the same voltage setting is followed for the same type of voltage in the first phase T1, making the setting of each voltage in the first phase T1 simpler.

[0072] Alternatively, in another possible implementation, the display panel 100 can also perform different voltage settings for the same type of voltage in the first stage T1 when performing different display modes in the display stage T2.

[0073] The first stage T1 is before the display stage T2, and the display panel 100 performs the first display mode after the first stage T1 ends, or the first stage T1 is after the display stage T2, and the display panel 100 performs the first display mode before entering the first stage T1.

[0074] It should be noted that the display panel 100 can switch the display mode performed by the display panel 100 according to the user's use demand in the display stage T2. The first display mode refers to the display mode that the display panel 100 needs to perform first when the display panel 100 enters the display stage T2, or the display mode that the display panel 100 performs last when the display panel 100 ends the display stage T2. For example, taking the first stage T1 as the power-on stage, when the display panel 100 ends the power-on and starts normal picture display, the display panel 100 performs the normal mode first in the display stage T2, and then switches to the highlight mode after a period of time. At this time, the first display mode refers to the normal mode.

[0075] As shown in FIG. 1, Figure 9 Figure 9 FIG. 1 is another timing diagram of the display panel 100 provided by the embodiment of the present application, which is corresponding to the timing diagram shown in FIG. 1. The first display mode is the normal mode, the first stage T1 corresponds to the first non-enabling voltage V GH1 , the power supply voltage V PVDD1 , and the black state voltage V GMP1 . The first non-enabling voltage V GH1 , the power supply voltage V PVDD1 , and the black state voltage V GMP1 are respectively the first non-enabling voltage, the power supply voltage, and the black state voltage corresponding to the normal mode performed by the display panel 100 in the display stage T2.

[0076] When the first display mode is the highlight mode, the first stage T1 corresponds to the first non-enabling voltage V GH2 , the power supply voltage V PVDD2 , and the black state voltage V GMP2 . The first non-enabling voltage V GH2 , the power supply voltage V PVDD2 , and the black state voltage V GMP2 ​respectively. The first non-enabling voltage, the power voltage and the black state voltage in the display stage T2 correspond to the high-brightness mode. Since the high-brightness mode gives priority to performance requirements, compared with the normal mode, the first non-enabling voltage, the power voltage and the black state voltage in the high-brightness mode can be adjusted upward. Referring to Figure 9 When the first display mode is the high-brightness mode, the first non-enabling voltage V GH2 , the power voltage V PVDD2 and the black state voltage V GMP2 in the first stage T1 satisfy: V GH2 >V GH1 , V PVDD2 >V PVDD1 , V GMP2 >V GMP1 , V GH2 -V GH1 ≥V GMP2 -V GMP1 ≥V PVDD2 -V PVDD1 .

[0077] When the first display mode is the normal mode, the first non-enabling voltage V GH3 , the power voltage V PVDD3 and the black state voltage V GMP3 in the first stage T1 satisfy: V GH3 <V PVDD3 , V GMP3 <V GH3 . The first non-enabling voltage V PVDD3 , the power voltage V GMP3 and the black state voltage V GH1 in the display stage T2 correspond to the normal mode. Since the brightness level corresponding to the normal mode is not as high as that corresponding to the high-brightness mode, in order to save power consumption, compared with the high-brightness mode, the upward adjustment degree of each voltage in the normal mode can be smaller. Referring to Figure 9 When the first display mode is the normal mode, the first non-enabling voltage V GH3 , the power voltage V GH2 and the black state voltage V PVDD1 in the first stage T1 satisfy: V PVDD3 <V PVDD2 , V GMP1 <V GMP3 , V GMP2 <V GH3 , V GH1 -V GMP3 ≥V GMP1 -V PVDD3 ≥V PVDD1.

[0078] Or, for greater degree of reducing power consumption, such as Figure 10 As shown, Figure 10 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 is provided, when the first display mode is the always-on mode, the first non-supply voltage V GH3 , the power supply voltage V PVDD3 and the black state voltage V GMP3 Also can satisfy: V GH3 <V GH1 , V PVDD3 <V PVDD1 , V GMP3 <V GMP1 , and V GH1 -V GH3 ≤V GMP1 -V GMP3 ≤V PVDD1 -V PVDD3 .

[0079] In a possible implementation, the length of the non-supply period t1 is t1, The length of the supply period t2 is t2, Wherein, f1 is the frequency of the first scanning signal output by the first scanning signal line Scan1 in the display stage T2.

[0080] By setting the length of the non-supply period t1 and the supply period t2 as at least one frame, in the non-supply period t1 and the supply period t2, the first scanning signal line Scan1 can perform at least one complete refresh on the 1st row of pixel circuits 1 to the last row of pixel circuits 1, so that the voltage transmitted on the data line Data can effectively control all pixel circuits 1, and ensure that the screen flashing phenomenon of different areas of the display area is effectively improved. By further setting the length of the non-supply period t1 and the supply period t2 as at most three frames, the long power-on and power-off process can be avoided to affect the user experience.

[0081] In a possible implementation, the first scanning signal output by the first scanning signal line Scan1 in the display stage T2 has a plurality of frequencies, and f1 is the maximum value of the frequencies of the first scanning signal. It can be understood that the higher the frequency of the first scanning signal, the shorter the corresponding frame time. When the display panel 100 is driven by frequency conversion in the display stage T2, by setting f1 as the maximum value of the frequencies of the first scanning signal, the time of the power-on and power-off process can be shortened, and the user experience can be optimized.

[0082] In a possible implementation, the length of the non-supply period t1 is t1, The length of the power supply period t2 is t2, m and n are integers greater than or equal to 0. Wherein, f1 is the frequency of the first scanning signal output by the first scanning signal line Scan1 in the display stage T2, and f2 is the frequency of the light-emitting control signal output by the light-emitting control signal line Emit in the display stage T2.

[0083] When the display panel 100 is driven at a low frequency, in order to improve flicker, the refresh frequency of the light-emitting control signal can be greater than the refresh frequency of the first scanning signal, for example, in combination with Figure 3 , the frequency of the first scanning signal is 30Hz, and the frequency of the light-emitting control signal can be 60Hz, that is In order to shorten the power-on and power-off time, the non-power supply period t1 and the power supply period t2 can not be set to an integer multiple of one frame as long as they meet An integer multiple of 1 frame can also be.

[0084] In a feasible implementation, the lengths of the non-power supply period t1 and the power supply period t2 can be set to be unequal.

[0085] Since the power supply period t2 needs to be powered on with a power supply voltage, there is a long time delay, in order to ensure that the voltage is switched to stable, the power supply period t2 can have a greater length, that is, the length of the non-power supply period t1 is less than the length of the power supply period t2. Exemplarily, the length of the non-power supply period t1 is 2 frames, and the length of the power supply period t2 is 3 frames.

[0086] In a feasible implementation, again referring to Figure 1 and Figure 2 , the pixel circuit 1 includes a second light-emitting control transistor M2, the gate of the second light-emitting control transistor M2 is electrically connected with the light-emitting control signal line Emit, the first electrode of the second light-emitting control transistor M2 is electrically connected with the driving transistor M0, and the second electrode of the second light-emitting control transistor M2 is electrically connected with the light-emitting element 2. The light-emitting control signal line Emit is used to provide a light-emitting enable voltage V GL ′ and a light-emitting non-enable voltage V GH ′ to the gate of the second light-emitting control transistor M2.

[0087] The display panel 100 further includes a plurality of cascaded emission shift circuits 3, the emission shift circuit 3 is electrically connected with the light-emitting control signal line Emit, and the emission shift circuit 3 includes a first emission shift circuit 4, and the first emission shift circuit 4 is further electrically connected with the emission frame start signal line STV_E.

[0088] As shown in Figure 11 , Figure 11A circuit structure schematic diagram of the first emission shift circuit 4 provided by the embodiment of the present application, the first emission shift circuit 4 further comprises a first control transistor M1' and a first output transistor M2'. The first control transistor M1' is electrically connected between the emission frame start signal line STV_E and the gate of the first output transistor M2', the first pole of the first output transistor M2' is electrically connected with the first fixed potential signal line VGL, and the second pole of the first output transistor M2' is electrically connected with the emission control signal line Emit, wherein the first fixed potential signal line VGL is used to provide the emission enable voltage V GL ′.

[0089] As Figure 12 shown, Figure 12 another timing diagram of the display panel 100 provided by the embodiment of the present application in the first stage T1 and the display stage T2, the driving method further comprises: in the first stage T1, the display driving chip 200 provides the non-enable voltage of the first output transistor M2' to the emission frame start signal line STV_E, and the non-enable voltage can be equal to the first non-enable voltage V GH .

[0090] It should be noted that, in combination with Figure 11 and Figure 12 , the emission shift register is further respectively connected with the first emission clock signal line CK1_E and the second emission clock signal line CK2_E, and in the first stage T1, the first emission clock signal line CK1_E and the second emission clock signal line CK2_E can normally provide pulse signals in the first stage T1.

[0091] Based on the circuit structure of the current emission shift register, when the non-enable voltage of the first output transistor M2' is provided to the emission frame start signal line STV_E, the non-enable voltage is transmitted to the first output transistor M2' via the turned-on first control transistor M1', the first output transistor M2' is controlled to be cut off, the first emission shift circuit 4 cannot output the emission enable voltage V GL ′, and the sequential downward shift cannot be realized. In this way, the emission enable voltage V GL ′ transmitted by the emission shift circuit 3 to the emission control signal line can be avoided, the second emission control transistor M2 in the pixel circuit 1 is prevented from being turned on, the drain current of the data line Data is prevented from flowing to the light emitting element 2, and the problem of up and down electric flash screen is improved to a greater extent.

[0092] Further, referring again to Figure 11The first emitter shift circuit 4 includes a protection transistor M3', the gate of which is electrically connected to the control signal line RST, the first terminal of which is electrically connected to the second fixed potential signal line VGH, which provides a de-enabling voltage to the first output transistor M2', the second terminal of which is electrically connected to the gate of the first output transistor M2', and the control signal line RST provides a second enable voltage V to the gate of the protection transistor M3'. GL1 Second non-enabling voltage V GH1 The second enabling voltage V GL1 It can be used with the first enable voltage V GL Equal to the second disabled voltage V GH1 It can be used with the first non-enable voltage V GH equal.

[0093] See you again Figure 12 The driving method for the display panel 100 includes: in the first stage T1, the display driver chip 200 provides a second disable voltage V to the control signal line RST. GH1 .

[0094] In the emitter shift circuit 3, the protection transistor M3′ is a transistor to prevent abnormal power failure. In the first stage T1, it provides a second disabling voltage V to the control signal line RST. GH1 The protection transistor M3' remains off, and the high level provided by the second fixed potential signal line VGH charges the parasitic capacitance in the protection transistor M3'. If an abnormal power outage occurs during the power supply process of the first stage T1, the protection transistor M3' can transmit its stored high level to the gate of the first output transistor M2', ensuring that the first output transistor M2' is off, thus preventing the first emitter shift circuit 4 from outputting the light-emitting enable voltage V. GL This prevents the light-emitting element 2 from emitting light and prevents the first emission shift circuit 4 from shifting downwards.

[0095] In addition, it should be noted that the first transmit shift circuit 4 may also include: the second control transistor M4′ to the sixth control transistor M8′, the second output transistor M9′, the first capacitor C1, the second capacitor C2 and the third capacitor C3. The connection method of the above structure is the same as that of the prior art, and will not be described again here.

[0096] In another feasible implementation, such as Figure 13 As shown, Figure 13The another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present application is shown in FIG. 6. In the power supply period t2, the display driving chip 200 can also provide the clock signal to the emission frame start signal line STV_E, that is, control the light emitting control signal line Emit to normally refresh the pixel circuit 1.

[0097] Since the embodiment of the present application can cut off the connection path between the data line Data and the light emitting element 2 in the first stage T1, even if the light emitting control signal line Emit normally drives the pixel circuit 1 in the first stage T1, the flicker phenomenon can still be effectively improved.

[0098] In a feasible implementation, referring again to Figure 1 , the display panel further comprises a plurality of first scanning shift circuits 5 arranged in cascade, and the first scanning shift circuits 5 are respectively electrically connected with the first alpha scanning clock signal line CK1_S1, the first beta scanning clock signal line CK2_S1 and the first scanning signal line Scan1. The first scanning shift circuit 5 comprises a first alpha scanning shift circuit 6, and the first alpha scanning shift circuit 6 is further electrically connected with the first scanning frame start signal line STV_S1.

[0099] Based on this, as shown in Figure 14 , Figure 14 The another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present application is shown in FIG. 6. In the power supply period t2, the display driving chip 200 can also provide the clock signal to the emission frame start signal line STV_E, that is, control the light emitting control signal line Emit to normally refresh the pixel circuit 1.

[0100] In the above setting method, the first scanning shift circuit normally works in the first stage T1, so that the first scanning signal line Scan1 normally refreshes the pixel circuit 1, but as described above, based on the setting of the data voltage V Data in the first stage T1 by the embodiment of the present application, even if the first scanning signal line Scan1 normally refreshes the pixel circuit 1, the light emitting element 2 can still avoid abnormal light emission in the first stage T1.

[0101] In a feasible setting mode, as shown in Figures 15-17 , Figure 15 Another structural schematic diagram of the display device provided by the embodiment of the present application is shown in FIG. 7. Figure 16 Another structural schematic diagram of the pixel circuit 1 provided by the embodiment of the present application is shown in FIG. 8. Figure 17Another timing diagram corresponding to the pixel circuit 1 provided by the embodiment of the present application, the pixel circuit 1 comprises a control transistor M7, the gate of the control transistor M7 is electrically connected with the second scan signal line Scan2, the first electrode of the control transistor M7 is electrically connected with the control signal line DVH, and the second electrode of the control transistor M7 is electrically connected with the driving transistor M0, specifically, the first electrode of the driving transistor M0.

[0102] Cai Jiajin Figure 15 The display panel 100 further comprises a plurality of second scan shift circuits 7 arranged in cascade, and the second scan shift circuits 7 are respectively electrically connected with the second alpha scan clock signal line CK1_S2, the second beta scan clock signal line CK2_S2 and the second scan signal line Scan2. The second scan shift circuit 7 comprises a second alpha scan shift circuit 8, and the second alpha scan shift circuit 8 is further electrically connected with the second scan frame start signal line STV_S2.

[0103] As shown in Figure 18 , Figure 18 Another timing diagram of the display panel 100 provided by the embodiment of the present application in the first stage T1 and the display stage T2, and the driving method further comprises: in the first stage T1, the display driving chip 200 provides pulse signals to the second alpha scan clock signal line CK1_S2, the second beta scan clock signal line CK2_S2 and the second scan frame start signal line STV_S2 respectively.

[0104] The pixel circuit 1 comprises a control transistor M7, and the control transistor M7 is controlled to be turned on before the gate of the driving transistor M0 is reset. Figure 17 The bias voltage provided by the control signal line DVH can be written to the first electrode of the driving transistor M0, the potential of the first electrode of the driving transistor M0 is refreshed, the device characteristics of the driving transistor M0 are set to a determined initial state, and the influence of the data signal written in the last frame on the device characteristics of the driving transistor M0 is eliminated. Data After the data voltage V Data is written to the driving transistor M0, the voltage of the first electrode of the driving transistor M0 will leak, especially under low-frequency driving, the leakage is more obvious, which causes a large deviation of the potential of the first electrode of the driving transistor M0. At this time, the control transistor M7 is controlled to be turned on, and the bias voltage is written to the first electrode of the driving transistor M0 by the control transistor M7, so that the bias state of the driving transistor M0 is consistent with the bias state when the data voltage V Data is written, thereby improving the stability of the working state of the driving transistor M0.

[0105] In addition, it should be further pointed out that, referring to Figure 2 and Figure 16The pixel circuit 1 further comprises a storage capacitor Cst, a first reset transistor M4, a second reset transistor M5 and a threshold compensation transistor M6. In one embodiment, the first reset transistor M4, the second reset transistor M5 and the threshold compensation transistor M6 can all be P-type transistors.

[0106] The gate of the first reset transistor M4 is electrically connected with the third scan signal line Scan3, the first electrode of the first reset transistor M4 is electrically connected with the reset signal line Vref, and the second electrode of the first reset transistor M4 is electrically connected with the gate of the driving transistor M0. The first reset transistor M4 is used to write the reset signal provided by the reset signal line Vref into the gate of the driving transistor M0 in response to the low level provided by the third scan signal line Scan3, so as to reset the gate of the driving transistor M0.

[0107] The gate of the second reset transistor M5 is electrically connected with the third scan signal line Scan3, the first electrode of the second reset transistor M5 is electrically connected with the reset signal line Vref, and the second electrode of the second reset transistor M5 is electrically connected with the anode of the light emitting element 2. The second reset transistor M5 is used to write the reset signal provided by the reset signal line Vref into the anode of the light emitting element 2 in response to the low level provided by the third scan signal line Scan3, so as to reset the anode of the light emitting element 2.

[0108] The gate of the threshold compensation transistor M6 is electrically connected with the first scan signal line Scan1, the first electrode of the threshold compensation transistor M6 is electrically connected with the second electrode of the driving transistor M0, and the second electrode of the threshold compensation transistor M6 is electrically connected with the gate of the driving transistor M0. The threshold compensation transistor M6 is used to compensate the threshold of the driving transistor M0 in response to the low level (the first enable voltage V GL ) provided by the first scan signal line Scan1.

[0109] Alternatively, in another embodiment, as shown in Figure 19 and Figure 20 , the pixel circuit 1 provided by the embodiment of the present application is another structure diagram, Figure 19 , the pixel circuit 1 provided by the embodiment of the present application is another timing diagram, Figure 20 , the second reset transistor M5 is a P-type transistor, and in order to reduce the influence of the leakage current on the stability of the gate potential of the driving transistor M0, the first reset transistor M4 and the threshold compensation transistor M6 can also be Indium Gallium Zinc Oxide (IGZO) transistors, i.e., the first reset transistor M4 and the threshold compensation transistor M6 are N-type transistors.

[0110] At this time, the gate of the first reset transistor M4 is electrically connected with the fourth scan signal line Scan4, the first electrode of the first reset transistor M4 is electrically connected with the reset signal line Vref, and the second electrode of the first reset transistor M4 is electrically connected with the driving transistor M0, specifically, the gate of the driving transistor M0. The first reset transistor M4 is used for writing the reset signal provided by the reset signal line Vref into the gate of the driving transistor M0 in response to the high level provided by the fourth scan signal line Scan4, so as to realize the reset of the gate of the driving transistor M0.

[0111] The gate of the second reset transistor M5 is electrically connected with the second scan signal line Scan2, the first electrode of the second reset transistor M5 is electrically connected with the reset signal line Vref, and the second electrode of the second reset transistor M5 is electrically connected with the anode of the light emitting element 2. The second reset transistor M5 is used for writing the reset signal provided by the reset signal line Vref into the anode of the light emitting element 2 in response to the low level provided by the second scan signal line Scan2, so as to realize the reset of the anode of the light emitting element 2. It should be noted that the second scan signal line Scan2 is low twice in one frame time, so the second reset transistor M5 can realize the reset of the anode of the light emitting element 2 twice.

[0112] The gate of the threshold compensation transistor M6 is electrically connected with the fifth scan signal line Scan5, the first electrode of the threshold compensation transistor M6 is electrically connected with the second electrode of the driving transistor M0, and the second electrode of the threshold compensation transistor M6 is electrically connected with the gate of the driving transistor M0. The threshold compensation transistor M6 is used for threshold compensation of the driving transistor M0 in response to the high level provided by the fifth scan signal line Scan5.

[0113] Based on the same inventive concept, the embodiment of the present application also provides a display device, referring again to Figure 1 and Figure 2 The display device comprises a display panel 100 and a display driving chip 200.

[0114] The display panel 100 comprises a pixel circuit 1, and the pixel circuit 1 comprises a driving transistor M0 and a data writing transistor M1. The gate of the data writing transistor M1 is electrically connected with a first scan signal line Scan1, the first electrode of the data writing transistor M1 is electrically connected with a data line Data, and the second electrode of the data writing transistor M1 is electrically connected with the driving transistor M0. The first scan signal line Scan1 is used for providing a first enable voltage V GL and a first non-enable voltage V GH to the gate of the data writing transistor M1.

[0115] The display driving chip 200 is electrically connected with the data line Data, and is used for providing a voltage smaller than the first non-enable voltage VGH During the display phase, T2 provides the data voltage V to the data line Data. Data The first stage T1 is located before and / or after the display stage T2.

[0116] In the first stage T1, the first scan signal line Scan1 performs normal line-by-line refresh of pixel circuit 1 from the first row to the last row. When pixel circuit 1 is not refreshed by the first scan signal line Scan1, the gate of the data writing transistor M1 in pixel circuit 1 receives the first disabled voltage V. GH In this embodiment of the invention, a voltage less than a first disabling voltage V is provided to the data line Data for at least a portion of the time period in the first stage T1. GH The voltage is such that the gate-source voltage Vgs1 of the data writing transistor M1 is greater than 0, making it much higher than the threshold voltage of the data writing transistor M1. At this time, the data writing transistor M1 can be controlled to be in a completely off state, effectively cutting off the connection path between the data line Data and the light-emitting element 2, and preventing the voltage on the data line Data from leaking to the light-emitting element 2. Since the time during which the pixel circuit 1 is not refreshed by the first scan signal line Scan1 is much longer than the time during which it is refreshed by the first scan signal line Scan1 within one frame, the embodiment of the present invention can effectively prevent the light-emitting element 2 from abnormally emitting light during power-on and power-off, thereby effectively improving the screen flickering phenomenon during power-on and power-off.

[0117] Furthermore, see again Figure 1 and Figure 2 The pixel circuit 1 also includes a first light-emitting control transistor M3. The gate of the first light-emitting control transistor M3 is electrically connected to the light-emitting control signal line Emit. The first terminal of the first light-emitting control transistor M3 is electrically connected to the power supply signal line PVDD. The second terminal of the first light-emitting control transistor M3 is electrically connected to the driving transistor M0.

[0118] The first phase T1 includes a non-power supply period t1 and a power supply period t2, with the power supply period t2 located between the non-power supply period t1 and the display phase T2. The display device also includes a power driver chip 300, configured to not supply power voltage to the power signal line PVDD during the non-power supply period t1 of the first phase T1, and to supply power voltage V to the power signal line PVDD during the power supply period t2. PVDD .

[0119] Taking the first stage T1 as the power-on stage as an example, when the display panel 100 is powered on, the display panel 100 first enters the non-power supply period t1. If a flashing screen phenomenon occurs in the non-power supply period t1, the flashing screen phenomenon is more likely to be perceived by the human eye because the non-power supply period t1 is separated from the subsequent display stage T2 for a certain time length. Therefore, by causing the power supply driving chip 300 to not supply power to the power supply signal line PVDD in the non-power supply period t1, the pixel circuit 1 cannot receive the power supply voltage V PVDD Thus, the abnormal light emission of the light emitting element 2 in the non-power supply period t1 can be avoided to a greater extent.

[0120] In addition, it should be noted that, because the embodiment of the present application can control the data writing transistor M1 to be turned off when the data writing transistor M1 is not refreshed, and control the second light emitting control transistor M1 to be turned off when the data writing transistor M1 is refreshed, so as to cut off the connection path between the data writing transistor M1 and the light emitting element 2, even if the power supply driving chip 300 normally supplies power to the power supply signal line PVDD in the power supply period t2, the abnormal light emission of the light emitting element 2 in the power supply period t2 can still be avoided.

[0121] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0122] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving method of a display panel, characterized in that, the display panel comprises a pixel circuit, the pixel circuit comprises a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected with a first scan signal line, a first electrode of the data writing transistor is electrically connected with a data line, a second electrode of the data writing transistor is electrically connected with the driving transistor, and the first scan signal line is configured to provide a first enable voltage and a first non-enable voltage to the gate of the data writing transistor; a driving process of the display panel comprises a first stage and a display stage, the first stage is located before and / or after the display stage; wherein the first stage is a power-on stage before the display panel enters normal display and / or a power-off stage after the display panel ends normal display; the pixel circuit comprises a second light-emitting control transistor, a gate of the second light-emitting control transistor is electrically connected with a light-emitting control signal line, a first electrode of the second light-emitting control transistor is electrically connected with the driving transistor, a second electrode of the second light-emitting control transistor is electrically connected with a light-emitting element, and the light-emitting control signal line is configured to provide a light-emitting enable voltage and a light-emitting non-enable voltage to the gate of the second light-emitting control transistor; the light-emitting non-enable voltage is equal to the first non-enable voltage; the driving method comprises: during at least part of the time period of the first stage, a display driving chip provides a voltage smaller than the first non-enable voltage to the data line.

2. The driving method of claim 1, characterized in that, the pixel circuit further comprises a first light-emitting control transistor, a gate of the first light-emitting control transistor is electrically connected with the light-emitting control signal line, a first electrode of the first light-emitting control transistor is electrically connected with a power supply signal line, and a second electrode of the first light-emitting control transistor is electrically connected with the driving transistor; the first stage comprises a non-power supply period and a power supply period, and the power supply period is located between the non-power supply period and the display stage; the driving method further comprises: during the non-power supply period, a power supply driving chip does not provide a power supply voltage to the power supply signal line, and during the power supply period, the power supply driving chip provides the power supply voltage to the power supply signal line.

3. The driving method of claim 2, characterized in that, during the first stage, the process of the display driving chip providing the voltage to the data line comprises: during the power supply period, the display driving chip provides a black state voltage to the data line.

4. The driving method of claim 2, characterized in that, during the first stage, the process of the display driving chip providing the voltage to the data line further comprises: during the non-power supply period, the display driving chip provides a constant voltage to the data line.

5. The driving method of claim 4, characterized in that, a voltage difference between the constant voltage and the first non-enable voltage is △V, and △V≥1V.

6. The driving method of claim 2, characterized in that, In the first stage, the process that the display driving chip provides the voltage to the data line further includes: in the non-power supply period, the display driving chip provides a voltage less than or equal to the black state voltage to the data line.

7. The driving method of claim 6, wherein, the non-power supply period includes x sub-periods, a voltage provided to the data line in an i-th sub-period is less than a voltage provided to the data line in an i+1-th sub-period, x is a positive integer greater than or equal to 2, and 1≤i≤x-1.

8. The driving method of claim 7, wherein, The time length of the sub-period is t0, Wherein, k is a positive integer greater than or equal to 1, f1 is the frequency of the first scanning signal output by the first scanning signal line in the display stage.

9. The driving method of claim 7, wherein, the voltage provided to the data line in the 1st sub-period is less than 2.5V, or a ground voltage is provided to the data line in the 1st sub-period.

10. The driving method of claim 3, wherein, the display panel has at least two display modes, and the first non-enabling voltage corresponding to the first stage, the power supply voltage, and the black state voltage are equal when the display panel executes different display modes in the display stage.

11. The driving method of claim 3, wherein, the first stage is before the display stage, and a first display mode is executed by the display panel after the first stage ends, or the first stage is after the display stage, and the first display mode is executed by the display panel before the first stage is entered. The first display mode is a normal mode, the first non-enabled voltage corresponding to the first stage is V GH1 , the power supply voltage is V PVDD1 , the black state voltage is V GMP1 ; The first display mode is a highlight mode, the first non-enabling voltage corresponding to the first stage is V GH2 , the power voltage is V PVDD2 , the black state voltage is V GMP2 , wherein V GH2 >V GH1 , V PVDD2 >V PVDD1 , V GMP2 >V GMP1 , and V GH2 -V GH1 ≥V GMP2 -V GMP1 ≥V PVDD2 -V PVDD1 ; The first display mode is a constant display mode, the first non-enabled voltage corresponding to the first stage is V GH3 , the power voltage is V PVDD3 , the black state voltage is V GMP3 , wherein V GH1 <V GH3 <V GH2 , V PVDD1 <V PVDD3 <V PVDD2 , V GMP1 <V GMP3 <V GMP2 , and V GH3 -V GH1 ≥V GMP3 -V GMP1 ≥V PVDD3 -V PVDD1 , or V GH3 <V GH1 , V PVDD3 <V PVDD1 , V GMP3 <V GMP1 , and V GH1 -V GH3 ≤V GMP1 -V GMP3 ≤V PVDD1 -V PVDD3 .

12. The driving method of claim 2, wherein, A length of the non-power supply period is t1, A length of the power supply period is t2, Wherein, f1 is a frequency of the first scanning signal output by the first scanning signal line in the display stage.

13. The driving method of claim 12, wherein, a first scan signal output by the first scan signal line in the display stage has a plurality of frequencies, and f1 is a maximum value of the frequencies of the first scan signal.

14. The driving method of claim 2, wherein, The length of the non-power supply period is t1, The length of the power supply period is t2, m and n are integers greater than or equal to 0, respectively; f1 is a frequency of a first scan signal output by the first scan signal line in the display stage, and f2 is a frequency of a light emitting control signal output by the light emitting control signal line in the display stage.

15. The driving method of claim 2, wherein, a length of the non-power supply period is less than a length of the power supply period.

16. The driving method of claim 1, wherein, the display panel further includes a plurality of cascaded emission shift circuits, the emission shift circuits are electrically connected with the light emitting control signal line, and the emission shift circuits include a first emission shift circuit, and the first emission shift circuit is further electrically connected with an emission frame start signal line. The first emission shift circuit includes a first control transistor and a first output transistor, the first control transistor is electrically connected between the emission frame start signal line and the gate of the first output transistor, the first pole of the first output transistor is electrically connected with a first fixed potential signal line, and the second pole of the first output transistor is electrically connected with the light-emitting control signal line, wherein the first fixed potential signal line is used to provide the light-emitting enable voltage. The driving method further includes: in the first stage, the display driving chip provides the non-enable voltage of the first output transistor to the emission frame start signal line.

17. The driving method of claim 16, wherein, The emission shift circuit further includes a protection transistor, the gate of the protection transistor is electrically connected with a control signal line, the first pole of the protection transistor is electrically connected with a second fixed potential signal line, and the second pole of the protection transistor is electrically connected with the gate of the first output transistor, the control signal line is used to provide the second enable voltage and the second non-enable voltage to the gate of the protection transistor; The driving method of the display panel further includes: in the first stage, the display driving chip provides the second non-enable voltage to the control signal line.

18. The driving method of claim 1, wherein, The display panel further includes a plurality of first scan shift circuits arranged in cascade, and the first scan shift circuits are respectively electrically connected with a first alpha scan clock signal line, a first beta scan clock signal line and the first scan signal line; wherein the first scan shift circuit includes a first alpha scan shift circuit, and the first alpha scan shift circuit is further electrically connected with a first scan frame start signal line; The driving method further includes: in the first stage, the display driving chip provides pulse signals to the first alpha scan clock signal line, the first beta scan clock signal line and the first scan frame start signal line respectively.

19. The driving method of claim 1, wherein, The pixel circuit includes a regulation transistor, the gate of the regulation transistor is electrically connected with a second scan signal line, the first pole of the regulation transistor is electrically connected with a regulation signal line, and the second pole of the regulation transistor is electrically connected with the driving transistor; The display panel further includes a plurality of second scan shift circuits arranged in cascade, and the second scan shift circuits are respectively electrically connected with a second alpha scan clock signal line, a second beta scan clock signal line and the second scan signal line; wherein the second scan shift circuit includes a second alpha scan shift circuit, and the second alpha scan shift circuit is further electrically connected with a second scan frame start signal line; The driving method further includes: in the first stage, the display driving chip provides pulse signals to the second alpha scan clock signal line, the second beta scan clock signal line and the second scan frame start signal line respectively.

20. A display device comprising: including: The display panel comprises a pixel circuit, the pixel circuit comprises a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected with a first scanning signal line, a first pole of the data writing transistor is electrically connected with a data line, a second pole of the data writing transistor is electrically connected with the driving transistor, the first scanning signal line is used for providing a first enable voltage and a first non-enable voltage to the gate of the data writing transistor; the pixel circuit further comprises a second light-emitting control transistor, a gate of the second light-emitting control transistor is electrically connected with a light-emitting control signal line, a first pole of the second light-emitting control transistor is electrically connected with the driving transistor, a second pole of the second light-emitting control transistor is electrically connected with a light-emitting element, the light-emitting control signal line is used for providing a light-emitting enable voltage and a light-emitting non-enable voltage to the gate of the second light-emitting control transistor; the light-emitting non-enable voltage is equal to the first non-enable voltage; The display driving chip is electrically connected with the data line, used for providing a voltage smaller than the first non-enable voltage to the data line in a first stage, and providing a data voltage to the data line in a display stage, the first stage is located before and / or after the display stage; wherein the first stage is a power-on stage before the display panel enters normal display and / or a power-off stage after the display panel ends normal display; wherein the display driving chip provides the voltage smaller than the first non-enable voltage to the data line in the first stage.

21. The display device of claim 20, wherein, The pixel circuit further comprises a first light-emitting control transistor, a gate of the first light-emitting control transistor is electrically connected with a light-emitting control signal line, a first pole of the first light-emitting control transistor is electrically connected with a power supply signal line, a second pole of the first light-emitting control transistor is electrically connected with the driving transistor; The first stage comprises a non-power supply period and a power supply period, the power supply period is located between the non-power supply period and the display stage; The display device further comprises a power supply driving chip, used for not providing a power supply voltage to the power supply signal line in the non-power supply period of the first stage, and providing the power supply voltage to the power supply signal line in the power supply period.

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