A LCD pixel driving circuit based on dual-gate transistors

Abstract

The present invention discloses an LCD pixel driving circuit based on a dual-gate transistor, comprising a first transistor, a pre-storage capacitor, a first dual-gate transistor, a second dual-gate transistor and a liquid crystal capacitor, wherein the first source and drain of the first transistor are coupled to a data signal line, the gate is coupled to a control signal line, the second source and drain are coupled to the first gate of the first dual-gate transistor and one end of the pre-storage capacitor, and the second source and drain are coupled to the first gate of the second dual-gate transistor through a control electrode; one end of the pre-storage capacitor away from the second source and drain of the first transistor is coupled to a second global signal line; the first source and drain of the first dual-gate transistor are coupled to the first global signal line, the second source and drain are coupled to the liquid crystal capacitor through a pixel electrode, and the second gate is coupled to the second global signal line; the first source and drain of the second dual-gate transistor are coupled to the first global signal line, the second source and drain are coupled to the liquid crystal capacitor, and the second gate is coupled to the second global signal line.

Description

Technical Field

[0001] The present invention relates to the field of pixel driving technology, and in particular to an LCD pixel driving circuit based on a dual-gate transistor. Background Art

[0002] In field sequential or color sequential display technologies, the backlight cannot be turned on until all liquid crystals in the display are deflected to a stable state to avoid image distortion. Therefore, how to speed up the liquid crystal driving time and increase the backlight on time is an urgent problem to be solved in this field.

[0003] The pixel driver circuit of a traditional color sequential LCD displays first charges each row of pixel electrodes sequentially within a frame, then waits for all liquid crystals to stabilize before turning on the backlight. If the backlight is turned on immediately after the last row of pixels has finished charging, the liquid crystals corresponding to the later-charged pixels will not have stabilized yet, resulting in differences in brightness and color at the top and bottom of the screen, leading to a chaotic image. As a result, the pixel driver circuit leaves very little time for the backlight to be on within a frame, making it difficult to achieve high brightness and high-frequency display. This also places high demands on backlight brightness specifications and lifespan, increasing product costs.

[0004] In summary, the conventional pixel driving circuit has the problem of being unable to balance light output quality and light output brightness. Summary of the Invention

[0005] In view of this, the present invention provides an LCD pixel driving circuit based on a dual-gate transistor, which solves the problem of the traditional pixel driving circuit that cannot take into account both light output quality and light output brightness by improving the circuit structure.

[0006] To solve the above problems, the technical solution of the present invention is to adopt an LCD pixel driving circuit based on a dual-gate transistor, including: a first transistor, a pre-storage capacitor, a first dual-gate transistor, a second dual-gate transistor and a liquid crystal capacitor, wherein the first source and drain of the first transistor are coupled to the data signal line, the gate is coupled to the control signal line, the second source and drain are coupled to the first gate of the first dual-gate transistor and one end of the pre-storage capacitor, and at the same time, the second source and drain are coupled to the first gate of the second dual-gate transistor through the control electrode; the end of the pre-storage capacitor away from the second source and drain of the first transistor is coupled to the second global signal line; the first source and drain of the first dual-gate transistor are coupled to the first global signal line, the second source and drain are coupled to the liquid crystal capacitor through the pixel electrode, and the second gate is coupled to the second global signal line; the first source and drain of the second dual-gate transistor are coupled to the first global signal line, the second source and drain are coupled to the liquid crystal capacitor through the pixel electrode, and the second gate is coupled to the second global signal line.

[0007] Optionally, the first dual-gate transistor and the second dual-gate transistor are configured as follows: the first dual-gate transistor is an N-type dual-gate thin-film field-effect transistor, and the second dual-gate transistor is a P-type dual-gate thin-film field-effect transistor; or the first dual-gate transistor is a P-type dual-gate thin-film field-effect transistor, and the second dual-gate transistor is an N-type dual-gate thin-film field-effect transistor.

[0008] Optionally, during the backlight on time, the first transistor is controlled to turn on based on a control signal, and the first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor until all pixels complete voltage pre-storage.

[0009] Optionally, when the first dual-gate transistor is an N-type dual-gate thin-film field-effect transistor and the second dual-gate transistor is a P-type dual-gate thin-film field-effect transistor: when the data signal of the Nth frame is high and the backlight is turned off, the first global signal jumps to a high potential and the second global signal jumps to a low potential, the second dual-gate transistor turns on and resets the pixel electrode to a high potential, after the pixel electrode is reset, the first global signal jumps to a low potential and the second global signal jumps to a high potential, the first dual-gate transistor turns on, the positive charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; when entering the N+1th frame, the backlight turns on.

[0010] Optionally, when the first dual-gate transistor is an N-type dual-gate thin-film field-effect transistor and the second dual-gate transistor is a P-type dual-gate thin-film field-effect transistor: when the data signal of the N+1 frame is low and the backlight is turned off, the first global signal jumps to a low potential and the second global signal jumps to a high potential, the first dual-gate transistor turns on and resets the pixel electrode to a low potential, after the pixel electrode is reset, the first global signal jumps to a high potential and the second global signal jumps to a low potential, the second dual-gate transistor turns on, and the negative charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; when entering the N+2 frame, the backlight turns on.

[0011] Optionally, when the first dual-gate transistor is a P-type dual-gate thin-film field-effect transistor and the second dual-gate transistor is an N-type dual-gate thin-film field-effect transistor, when the data signal of the Nth frame is a high potential and the backlight is turned off, the first global signal jumps to a high potential and the second global signal jumps to a low potential, the first dual-gate transistor turns on and resets the pixel electrode to a high potential, after the pixel electrode is reset, the first global signal jumps to a low potential and the second global signal jumps to a high potential, the second dual-gate transistor turns on, the positive charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; when entering the N+1th frame, the backlight turns on.

[0012] Optionally, when the first dual-gate transistor is a P-type dual-gate thin-film field-effect transistor and the second dual-gate transistor is an N-type dual-gate thin-film field-effect transistor, when the data signal of the N+1 frame is low and the backlight is turned off, the first global signal jumps to a low potential and the second global signal jumps to a high potential, the second dual-gate transistor turns on and resets the pixel electrode to a low potential, after the pixel electrode is reset, the first global signal jumps to a high potential and the second global signal jumps to a low potential, the first dual-gate transistor turns on, and the negative charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; when entering the N+2 frame, the backlight turns on.

[0013] Optionally, when the LCD pixel driving circuit further includes a third global signal line, the first source and drain of the second dual-gate transistor are configured to be coupled to the third global signal line.

[0014] Optionally, when the LCD pixel driving circuit further includes a third global signal line, the second gate of the second double-gate transistor is configured to be coupled to the third global signal line.

[0015] Optionally, one end of the liquid crystal capacitor away from the pixel electrode is coupled to the common electrode line.

[0016] The primary improvement of the present invention is the provided LCD pixel driving circuit based on a dual-gate transistor. By setting a pre-storage unit, a pre-charge voltage is stored using a pre-storage capacitor during the backlight emission time of the current frame, so that all pixels can synchronously read the pre-charge voltage in the next frame. This greatly reduces the writing time of the pixel voltage and relatively increases the backlight emission time, thereby increasing the light output brightness while ensuring the light output quality, solving the problem of traditional pixel driving circuits that cannot take into account both light output quality and light output brightness.

[0017] At the same time, by arranging P-type TFTs and N-type TFTs in coordination, the present invention enables the driver circuit to control the discharge of the reset pixel electrode based on the data signal, regardless of whether the pixel electrode is reset to a high or low potential via a first global signal, by switching the potentials of the first and second global signals. This allows the pixel electrode to generate the voltage required for the liquid crystal to flip to the target angle. Firstly, in this discharge mode, the time required for the pixel electrode to generate the voltage required for the liquid crystal to flip to the target angle is much shorter than in a conventional charging mode. Secondly, in this discharge mode, the polarity of the pixel electrode potential can be flexibly and accurately switched, thereby avoiding aging and damage to the liquid crystal caused by prolonged operation in a single polarity state. Thirdly, the gate-source voltage difference and the gate-drain voltage difference of the first and second dual-gate transistors are reversed in odd and even frames, so that the first and second dual-gate transistors are in the PBTS and NBTS states, respectively, in odd and even frames. These two effects offset each other, thus solving the problem of TFT device degradation and display life reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a simplified circuit diagram of an LCD pixel driving circuit based on a dual-gate transistor of the present invention;

[0019] Figure 2 This is a driving timing diagram of the LCD pixel driving circuit based on the dual-gate transistor of the present invention;

[0020] Figure 3 is a simplified circuit diagram of an LCD pixel driving circuit based on a dual-gate transistor according to a preferred embodiment of the present invention;

[0021] Figure 4 FIG. 4 is a simplified circuit diagram of an LCD pixel driving circuit based on dual-gate transistors according to another preferred embodiment of the present invention. Implementation Method

[0022] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0025] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0027] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0028] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0029] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0030] Specifically, such as Figure 1 As shown, an LCD pixel driving circuit based on a dual-gate transistor includes: a first transistor M1, a pre-storage capacitor Cst, a first dual-gate transistor M2, a second dual-gate transistor M3 and a liquid crystal capacitor Clc, wherein the first source and drain of the first transistor M1 are coupled to the data signal line date (Vdate is the voltage of the data signal), the gate is coupled to the control signal line scan (Vscan is the voltage of the control signal), the second source and drain are coupled to the first gate of the first dual-gate transistor M2 and one end of the pre-storage capacitor Cst, and the second source and drain are coupled to the second gate of the second dual-gate transistor M3 through the control electrode. A gate; one end of the pre-storage capacitor Cst away from the second source and drain of the first transistor M1 is coupled to the second global signal line st2 (Vst2 is the voltage of the second global signal); the first source and drain of the first dual-gate transistor M2 are coupled to the first global signal line st1 (Vst1 is the voltage of the first global signal), the second source and drain are coupled to the liquid crystal capacitor Clc through the pixel electrode, and the second gate is coupled to the second global signal line; the first source and drain of the second dual-gate transistor M3 are coupled to the first global signal line, the second source and drain are coupled to the liquid crystal capacitor Clc through the pixel electrode, and the second gate is coupled to the second global signal line. Wherein, one end of the liquid crystal capacitor Clc away from the pixel electrode is coupled to the common electrode line.

[0031] Further, the first dual-gate transistor M2 and the second dual-gate transistor M3 are configured as follows: the first dual-gate transistor M2 is an N-type dual-gate thin-film field-effect transistor, and the second dual-gate transistor M3 is a P-type dual-gate thin-film field-effect transistor; or the first dual-gate transistor M2 is a P-type dual-gate thin-film field-effect transistor, and the second dual-gate transistor M3 is an N-type dual-gate thin-film field-effect transistor.

[0032] Specifically, to facilitate understanding of the working timing of the pixel driving circuit, as shown in FIG. Figure 2 As shown, taking the first dual-gate transistor M2 as an N-type dual-gate thin film field effect transistor and the second dual-gate transistor M3 as a P-type dual-gate thin film field effect transistor as an example:

[0033] During the backlight on (herein defined as first-order programming / display) time of the Nth frame (herein defined as an odd frame), the data signal is high, and the first transistor M1 is controlled to be turned on based on the control signal. The first transistor M1 outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor Cst until all pixels complete voltage pre-storage; when the backlight is turned off in the Nth frame, the first global signal jumps to a high potential and the second global signal jumps to a low potential. At this time, the second dual-gate transistor M3 has a positive bias in Vth due to the low second gate potential, and the control electrode potential is coupled and pulled low by the pre-storage capacitor Cst, so the second dual-gate transistor M3 is turned on and Finally, it operates in the linear region and resets the pixel electrode to a high potential. After the pixel electrode is reset, the first global signal jumps to a low potential and the second global signal jumps to a high potential. At this time, the Vth of the first dual-gate transistor M2 is negatively biased due to the high second gate potential, and the control electrode potential is coupled and pulled up by the pre-storage capacitor Cst. The first dual-gate transistor M2 is turned on and finally operates in the saturation region. The positive charge stored in the pixel electrode flows to the first global signal line to form a source-drain current. The magnitude of the source-drain current is determined by the voltage difference between the control electrode and the first global signal. The voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode (which can be defined as second-order programming here);

[0034] When entering the N+1 frame (which can be defined as an even frame here), the backlight is turned on, the data signal of the N+1 frame is configured to be low, and the first transistor M1 outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor Cst until all pixels complete voltage pre-storage; when the backlight of the N+1 frame is turned off, the first global signal jumps to a low potential and the second global signal jumps to a high potential. At this time, the first dual-gate transistor M2 has a negative bias in Vth due to the high potential of the second gate, and the potential of the control electrode is coupled and pulled high by the pre-storage capacitor Cst, and the first dual-gate transistor M2 is turned on. The pixel electrode is turned on and finally operates in the linear region, and resets the pixel electrode to a low potential. After the pixel electrode is reset, the first global signal jumps to a high potential and the second global signal jumps to a low potential. At this time, the second dual-gate transistor M3 is positively biased due to the low second gate potential, and the control electrode potential is coupled and pulled down by the pre-storage capacitor Cst. The second dual-gate transistor M3 is turned on and finally operates in the saturation region. The negative charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode. When entering the N+2 frame, the backlight is turned on.

[0035] It should be noted here that N is an odd number and a positive integer, and in the above embodiment can be configured as 1, 3, 5, 7... At the same time, in order to fully illustrate the signal changes required for different polarity reversals of the liquid crystal, the present invention limits the frames to N and N+1. Here, it is assumed by default that the liquid crystal needs to perform polarity reversal in every frame, but the technical solution claimed by the present invention is also applicable to the polarity reversal of the liquid crystal every M frames, M∈(2,+∞). Therefore, the descriptions of the Nth frame, the N+1th frame, etc. used above to accurately illustrate the technical solution claimed by the present invention should not be regarded as limiting the scope of protection of this application.

[0036] It should be noted that the terms "high potential" and "low potential" used in the present invention refer to the potential relative to the common electrode potential. For example, a potential higher than Vcom is considered a high potential, while a potential lower than Vcon is considered a low potential.

[0037] The present invention sets a pre-storage unit so that during the backlight emission time of the current frame, the pre-charge voltage is stored by using a pre-storage capacitor, so that all pixels can synchronously read the pre-charge voltage in the next frame, which greatly reduces the writing time of the pixel voltage and relatively increases the backlight emission time, thereby increasing the light output brightness while ensuring the light output quality, and solving the problem of the traditional pixel driving circuit that cannot take into account both the light output quality and the light output brightness.

[0038] At the same time, the inventors noted the difficulty of polarity reversal caused by the use of dual-gate transistors. Therefore, the present invention utilizes a P-type TFT and an N-type TFT in conjunction with each other, so that whether the driver circuit resets the pixel electrode to a high or low potential via a first global signal, it can achieve discharge control of the reset pixel electrode based on the data signal by transforming the potential of the first global signal with the second global signal, so that the voltage required to flip the liquid crystal to the target angle is formed on the pixel electrode. On the one hand, in this discharge operating mode, the time required for the pixel electrode to form the voltage required to flip the liquid crystal to the target angle is much shorter than in the traditional charging operating mode. On the other hand, in this discharge operating mode, the pixel electrode's potential polarity can be flexibly and accurately changed, avoiding the aging and damage problems that may occur when the liquid crystal operates in a single polarity state for a long time.

[0039] Furthermore, when the first dual-gate transistor M2 is a P-type dual-gate thin-film field-effect transistor and the second dual-gate transistor M3 is an N-type dual-gate thin-film field-effect transistor, when the data signal of the Nth frame is a high potential and the backlight is turned off, the first global signal jumps to a high potential and the second global signal jumps to a low potential, the first dual-gate transistor M2 turns on and resets the pixel electrode to a high potential, after the pixel electrode is reset, the first global signal jumps to a low potential and the second global signal jumps to a high potential, the second dual-gate transistor M3 turns on, the positive charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; when entering the N+1th frame, the backlight turns on. When the data signal of the N+1 frame is at a low potential and the backlight is turned off, the first global signal jumps to a low potential and the second global signal jumps to a high potential, the second dual-gate transistor M3 is turned on and resets the pixel electrode to a low potential. After the pixel electrode is reset, the first global signal jumps to a high potential and the second global signal jumps to a low potential, the first dual-gate transistor M2 is turned on, and the negative charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; when entering the N+2 frame, the backlight is turned on.

[0040] Furthermore, Figure 3 As shown, without considering the pixel aperture ratio or without affecting the pixel aperture ratio, in order to facilitate more flexible control of the reset of the pixel electrode, the LCD pixel driving circuit may further include a third global signal line st3 (Vst3 is the voltage of the third global signal), and the first source and drain of the second dual-gate transistor M3 are configured to be coupled to the third global signal line.

[0041] Furthermore, Figure 4 As shown, when the LCD pixel driving circuit further includes a third global signal line, the second gate of the second dual-gate transistor M3 can also be configured to be coupled to the third global signal line.

[0042] The above is an LCD pixel driving circuit based on a dual-gate transistor provided in an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0043] Those skilled in the art will further appreciate that the elements and algorithmic steps of each example described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described above by function. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A skilled person may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the present invention. The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, software modules executed by a processor, or a combination of the two. The software modules can be stored in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Claims

1. An LCD pixel driving circuit based on a dual-gate transistor, characterized in that: include: a first transistor (M1), a pre-storage capacitor (Cst), a first dual-gate transistor (M2), a second dual-gate transistor (M3) and a liquid crystal capacitor (Clc), wherein the first source and drain of the first transistor (M1) are coupled to a data signal line, the gate is coupled to a control signal line, the second source and drain are coupled to the first gate of the first dual-gate transistor (M2) and one end of the pre-storage capacitor (Cst), and the second source and drain are coupled to the first gate of the second dual-gate transistor (M3) through a control electrode; the end of the pre-storage capacitor (Cst) away from the second source and drain of the first transistor (M1) is coupled to a second global signal line; the first source and drain of the first dual-gate transistor (M2) are coupled to the first global signal line, the second source and drain are coupled to the liquid crystal capacitor (Clc) through a pixel electrode, and the second gate is coupled to the second global signal line; the first source and drain of the second dual-gate transistor (M3) are coupled to the first global signal line, the second source and drain are coupled to the liquid crystal capacitor (Clc) through a pixel electrode, and the second gate is coupled to the second global signal line; The first dual-gate transistor (M2) and the second dual-gate transistor (M3) are configured as follows: the first dual-gate transistor (M2) is an N-type dual-gate thin-film field-effect transistor, and the second dual-gate transistor (M3) is a P-type dual-gate thin-film field-effect transistor; or the first dual-gate transistor (M2) is a P-type dual-gate thin-film field-effect transistor, and the second dual-gate transistor (M3) is an N-type dual-gate thin-film field-effect transistor; wherein, In the case where the first dual-gate transistor (M2) is an N-type dual-gate thin-film field-effect transistor and the second dual-gate transistor (M3) is a P-type dual-gate thin-film field-effect transistor: When the data signal of the Nth frame is high and the backlight is turned off, the first global signal jumps to a high potential and the second global signal jumps to a low potential, the second dual-gate transistor (M3) is turned on and resets the pixel electrode to a high potential. After the pixel electrode is reset, the first global signal jumps to a low potential, the second global signal jumps to a high potential, the first dual-gate transistor (M2) is turned on, the positive charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; When entering the N+1th frame, the backlight is turned on.

2. The LCD pixel driving circuit according to claim 1, wherein: During the backlight on time, the first transistor (M1) is controlled to be turned on based on a control signal, and the first transistor (M1) outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor (Cst) until all pixels complete voltage pre-storage.

3. The LCD pixel driving circuit according to claim 1, wherein: When the data signal of the N+1th frame is at a low potential and the backlight is turned off, the first global signal jumps to a low potential and the second global signal jumps to a high potential, the first dual-gate transistor (M2) is turned on and resets the pixel electrode to a low potential. After the pixel electrode is reset, the first global signal jumps to a high potential, the second global signal jumps to a low potential, the second dual-gate transistor (M3) is turned on, the negative charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; When entering the N+2 frame, the backlight is turned on.

4. The LCD pixel driving circuit according to claim 1, wherein: In the case where the first double-gate transistor (M2) is a P-type double-gate thin-film field-effect transistor and the second double-gate transistor (M3) is an N-type double-gate thin-film field-effect transistor, When the data signal of the Nth frame is high and the backlight is turned off, the first global signal jumps to a high potential and the second global signal jumps to a low potential, the first dual-gate transistor (M2) is turned on and resets the pixel electrode to a high potential. After the pixel electrode is reset, the first global signal jumps to a low potential, the second global signal jumps to a high potential, the second dual-gate transistor (M3) is turned on, the positive charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; When entering the N+1th frame, the backlight is turned on.

5. The LCD pixel driving circuit according to claim 4, wherein: When the data signal of the N+1th frame is at a low level and the backlight is turned off, the first global signal jumps to a low level and the second global signal jumps to a high level, the second dual-gate transistor (M3) is turned on and resets the pixel electrode to a low level. After the pixel electrode is reset, the first global signal jumps to a high potential, the second global signal jumps to a low potential, the first dual-gate transistor (M2) is turned on, the negative charge stored in the pixel electrode flows to the first global signal line, and the voltage required for the liquid crystal to flip the target angle is formed on the pixel electrode; When entering the N+2 frame, the backlight is turned on.

6. The LCD pixel driving circuit according to claim 1, wherein: When the LCD pixel driving circuit further includes a third global signal line, the first source and drain of the second dual-gate transistor (M3) are configured to be coupled to the third global signal line.

7. The LCD pixel driving circuit according to claim 1, wherein: When the LCD pixel driving circuit further includes a third global signal line, the second gate of the second dual-gate transistor (M3) is configured to be coupled to the third global signal line.

8. The LCD pixel driving circuit according to claim 1, wherein: One end of the liquid crystal capacitor (Clc) away from the pixel electrode is coupled to the common electrode line.

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