RRAM storage array and architecture
By designing the basic storage units of two-dimensional matrix arrangement in the RRAM storage array and configuring BL bit lines, WL word lines and LSL local source lines, combined with the design of group partition areas and SL common source lines, the line resistance increase problem caused by the increase in the trace length of the source line of the traditional RRAM storage array is solved, and higher memory cell operation accuracy and overall performance are achieved.
Patent Information
- Application Number
- CN202411750650.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-03-21
AI Technical Summary
The source line trace length of the traditional RRAM storage array increases, resulting in increased line resistance, increased load, and uneven voltage distribution, which affects the writing and reading operation accuracy of the memory cell.
A RRAM storage array is designed, the basic storage units are arranged through a two-dimensional matrix, and the BL bit line, WL word line and LSL local source line are configured in the matrix, and a group partition area is set. An SL common source line is arranged in each group partition area. The SL common source line is parallel to the BL bit line, and the LSL partial source line in the group partition area is sequentially connected.
The LSL local source line is controlled by the SL shared source line after grouping and partitioning, which reduces the source line load and reduces the source line resistance, ensures the writing and reading operation accuracy of the storage unit, and improves the overall performance of the RRAM storage array.
Smart Images
Figure CN119673236A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of random access memory technology, and more particularly to a RRAM storage array and architecture. Background Art
[0002] Resistive Random Access Memory (RRAM) is an emerging non-volatile memory technology that achieves data storage by switching resistive cells between high and low resistance states. It has the advantages of simple structure, low power consumption, fast writing speed, and high storage density. It is considered to be a strong candidate for future high-density memory. However, with the widespread promotion of RRAM devices in large-scale integrated applications, its array structure design faces many challenges. In related technologies, the source line (Source Line, SL) of the traditional RRAM storage array is connected by directly crossing the bit line (Bit Line, BL). As the array scale increases, the SL routing length increases accordingly, resulting in increased line resistance, increased load, and uneven voltage distribution, which affects the write and read operation accuracy of the storage unit. This situation needs to be changed. Summary of the invention
[0003] In view of this, the present application provides a RRAM storage array and architecture to solve the above-mentioned technical problems.
[0004] To achieve the above objectives, according to the first aspect, the technical solution adopted is:
[0005] A RRAM storage array, comprising:
[0006] A basic storage unit, wherein a plurality of the basic storage units are arranged in a two-dimensional matrix;
[0007] BL bit lines, the BL bit lines are respectively arranged in each row of the two-dimensional matrix, and the basic storage units in each row of the two-dimensional matrix are electrically connected to the BL bit lines;
[0008] A WL word line, wherein the WL word line is arranged in each column of the two-dimensional matrix, and the basic storage unit of each column of the two-dimensional matrix is electrically connected to the WL word line;
[0009] LSL local source lines, the LSL local source lines are respectively arranged in each column of the two-dimensional matrix, and the basic storage units in each column of the two-dimensional matrix are electrically connected to the LSL local source lines;
[0010] The two-dimensional matrix is provided with a plurality of group isolation areas, each of which is correspondingly provided with an SL common source line, the SL common source line is parallel to the BL bit line and is sequentially connected to the LSL local source lines in the group isolation area.
[0011] The present application is further configured as follows: the two-dimensional matrix includes m rows of BL bit lines, n columns of WL word lines and n / 2 columns of LSL local source lines, wherein m is a positive integer and n is a positive even number;
[0012] The same basic storage unit is connected to a row of the BL bit lines, two columns of the WL word lines and a column of the LSL local source line, and the LSL local source line on the same basic storage unit is configured between the two WL word lines.
[0013] The present application is further configured as follows: the number of the grouped isolation areas is set to x, each of the grouped isolation areas has L WL word lines and L / 2 LSL local source lines, then the number of the SL common source lines is x, and the SL common source line in the same grouped isolation area is correspondingly connected to the L / 2 LSL local source lines.
[0014] The present application is further configured as follows: the mapping relationship between the SL common source line and L / 2 LSL local source lines in the same group isolation area includes:
[0015] (SL common source line <0> →LSL local source line <l 2:0>).
[0016] The present application is further configured as follows: the SL common source line is also connected to a driving unit for dynamically adjusting the electrical signal on the SL common source line.
[0017] The present application is further configured as follows: the two-dimensional matrix extends along a first direction and a second direction, the first direction is the extension direction of the rows of the two-dimensional matrix, the second direction is the extension direction of the columns of the two-dimensional matrix, the BL bit line and the SL common source line are parallel to the first direction, and the WL word line and the LSL local source line are parallel to the second direction.
[0018] The present application is further configured as follows: the basic storage unit includes a first resistor, a second resistor, a first transistor and a second transistor.
[0019] The present application is further configured as follows: the first resistor and the second resistor include bipolar resistors, and the bipolar resistors have symmetrical high-resistance state and low-resistance state switching characteristics.
[0020] The present application is further configured as follows: in the two-dimensional matrix, the drain of the first transistor of the same basic storage unit is connected to one end of the first resistor, the drain of the second transistor is connected to one end of the second resistor, the other ends of the first resistor and the second resistor are connected to the BL bit line, the sources of the first transistor and the second transistor are connected to the LSL local source line, and the gates of the first transistor and the second transistor are respectively connected to the adjacent WL word lines.
[0021] According to the second aspect, the technical solution adopted is:
[0022] An RRAM storage architecture includes a plurality of RRAM storage arrays as described in any one of the above embodiments, wherein the capacities of the plurality of RRAM storage arrays are different.
[0023] In summary, compared with the prior art, the present application discloses an RRAM storage array and architecture, wherein a plurality of basic storage cells of the RRAM storage array are arranged in a two-dimensional matrix, BL bit lines are respectively arranged in each row of the two-dimensional matrix and electrically connected to the basic storage cells of each row, WL word lines are respectively arranged in each column of the two-dimensional matrix and electrically connected to the basic storage cells of each column, and LSL local source lines are respectively arranged in each column of the two-dimensional matrix and electrically connected to the basic storage cells of each column, wherein the two-dimensional matrix is provided with a plurality of grouping partition areas, and each grouping partition area is correspondingly provided with an SL common source line, the SL common source line is parallel to the BL bit line and sequentially connected to the LSL local source lines in the grouping partition area, that is, through the above-mentioned setting, the RRAM storage array has a routing steering function, and the source line load and the source line resistance are reduced by controlling the longitudinal LSL local source line through the lateral SL common source line after the grouping partition, thereby ensuring the writing and reading operation accuracy of the storage unit, thereby improving the overall performance of the RRAM storage array. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0025] Figure 1 is a schematic diagram of the structure of the RRAM storage array of this embodiment;
[0026] Figure 2 is a partial structural schematic diagram of the RRAM storage array of this embodiment;
[0027] Figure 3 It is a schematic structural diagram of the basic storage unit of this embodiment. DETAILED DESCRIPTION
[0028] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0029] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.
[0030] It should be further understood that the terms "comprising" and "including" indicate the presence of the described features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or", "and / or", "including at least one of the following", etc. used in this application may be interpreted as inclusive, or mean any one or any combination. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C", and for another example, "A, B or C" or "A, B and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.
[0031] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, as used herein, the singular forms "a", "an", and "the" are intended to also include plural forms, unless otherwise indicated in the context.
[0032] It should be understood that the orientations or positional relationships indicated by terms such as "top", "bottom", "up", "down", "vertical", and "horizontal" are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0033] For ease of description, in the following embodiments, the orthogonal space formed by the horizontal plane and the vertical direction is used as an example for explanation, and this premise should not be understood as a limitation to the present application.
[0034] As described in the background technology, the source line (SourceLine, SL) of the traditional RRAM storage array is connected by directly crossing the bit line (BitLine, BL). As the array scale increases, the SL line length increases accordingly, resulting in increased line resistance, increased load, and uneven voltage distribution, thereby affecting the write and read operation accuracy of the storage unit. Based on this, the present application discloses an RRAM storage array and architecture.
[0035] refer to Figures 1 to 3 The RRAM storage array of the embodiment of the present application includes a basic storage unit 10, a BL bit line 20, a WL word line 30 and an LSL local source line 40.
[0036] In a specific implementation process, a plurality of basic storage units 10 are arranged in a two-dimensional matrix, wherein the BL bit lines 20 are respectively configured in each row of the two-dimensional matrix, and the basic storage units 10 in each row of the two-dimensional matrix are electrically connected to the BL bit lines 20, the WL word lines 30 are configured in each column of the two-dimensional matrix, and the basic storage units 10 in each column of the two-dimensional matrix are electrically connected to the WL word lines 30, and the LSL local source lines 40 are respectively configured in each column of the two-dimensional matrix, and the basic storage units 10 in each column of the two-dimensional matrix are electrically connected to the LSL local source lines 40.
[0037] Furthermore, the two-dimensional matrix is provided with a plurality of group partitioning areas 50, and each group partitioning area 50 is correspondingly provided with an SL common source line 60 which is sequentially connected to the LSL local source lines 40 in the group partitioning area 50, and the SL common source line 60 is parallel to the BL bit line 20. Thus, the RRAM storage array can be divided into a plurality of groups through the group partitioning area 50, and the SL common source line 60 of each group is connected to all the LSL local source lines 40 in the group partitioning area 50, that is, the RRAM storage array controls the LSL local source line through the SL common source line after group partitioning to reduce the source line load and reduce the source line resistance, thereby ensuring the writing and reading operation accuracy of the RRAM storage array and improving the overall performance of the RRAM storage array.
[0038] It should be noted that a plurality of basic storage cells 10 are arranged in a two-dimensional matrix, that is, the basic storage cells 10 of the RRAM storage array are arranged in the form of rows and columns to form a regular two-dimensional storage network structure. Specifically, each row in the two-dimensional matrix represents a set of basic storage cells connected to the BL bit line 20, and each column in the two-dimensional matrix represents a set of basic storage cells connected to the WL word line 30 and the LSL local source line 40. Thus, through the matrix arrangement, more basic storage cells 10 can be placed in a limited chip area, thereby increasing the capacity of the memory. At the same time, the matrix arrangement allows writing or reading operations to be performed on multiple rows or columns of cells at the same time, thereby improving the operation efficiency. By providing a plurality of group isolation areas 50, each group isolation area 50 is correspondingly configured with an SL common source line 60 that is sequentially connected to the LSL local source line 40 in the group isolation area 50, thereby reducing cross-area interference and avoiding the disadvantage that the source line of the traditional RRAM storage array increases with the increase of the array scale, the source line routing length increases accordingly, resulting in increased line resistance, increased load, and uneven voltage distribution, thereby affecting the write and read operation accuracy of the storage unit.
[0039] In a specific implementation process, the SL common source line 60 is parallel to the BL bit line 20, and based on the row and column design of the two-dimensional matrix, the BL bit line 20 is configured in each row of the two-dimensional matrix, and the LSL local source line 40 is configured in each column of the two-dimensional matrix, then the SL common source line 60 can be regarded as being staggered with the LSL local source line 40 in rows and columns. Compared with the traditional RRAM storage array, the RRAM storage array of the embodiment of the present application controls the LSL local source lines 40 arranged in columns in the group isolation area 50 by the SL common source lines 60 arranged in rows, that is, by routing and utilizing the partition The group partition method optimizes the original long-distance routing of one SL source line across all columns into local control within each group partition area, greatly reducing the impact of line resistance on array performance, thereby ensuring the write and read operation accuracy of the RRAM storage array and improving the overall performance of the RRAM storage array. At the same time, the group partition design based on the group partition area 50 can also flexibly adjust the number of basic storage units 10 in the group partition area 50 according to specific storage capacity requirements, and is suitable for storage array architectures of various sizes and specifications, further enhancing its adaptability and practical value.
[0040] Preferably, the row and column design of the two-dimensional matrix can be regarded as extending along the first direction and the second direction. Specifically, the first direction is the extension direction of the rows of the two-dimensional matrix, and the second direction is the extension direction of the columns of the two-dimensional matrix. The BL bit line 20 and the SL common source line 60 are parallel to the first direction, and the WL word line 30 and the LSL local source line 40 are parallel to the second direction. That is, the first direction is the extension direction of the rows in the two-dimensional matrix, representing the routing direction of the BL bit line 20 and the SL common source line 60, and the second direction is the extension direction of the columns in the two-dimensional matrix, representing the routing direction of the WL word line 30 and the LSL local source line 40. By clearly dividing the rows and columns in the first direction and the second direction, different types of signal lines can achieve good regional isolation in the two-dimensional matrix to avoid signal interference, and the number of staggered wiring and complex intersections can be reduced, and the wiring impedance can be reduced, so as to structurally optimize the working efficiency of the RRAM storage array.
[0041] Optionally, the first direction is perpendicular to the second direction.
[0042] It should be noted that a plurality of grouped partitioning regions 50 are divided by columns in a two-dimensional matrix, and each grouped partitioning region 50 covers a plurality of columns of WL word lines 30 and LSL local source lines 40 .
[0043] In one embodiment, the basic storage unit 10 includes a first resistor 11, a second resistor 12, a first transistor 13 and a second transistor 14, that is, the basic storage unit 10 can be regarded as a 2T2R structure storage unit, then each row in a two-dimensional matrix constructed by a number of basic storage units 10 represents a basic storage unit set connected to a BL bit line 20, and each column in the two-dimensional matrix represents a basic storage unit set connected to two WL word lines 30 and an LSL local source line 40.
[0044] It can be understood that the 2T2R structure (first resistor 11, second resistor 12, first transistor 13 and second transistor 14) of the basic storage unit 10 of the embodiment of the present application can store more data in a smaller physical space, and because the 2T2R structure includes two transistors as switching elements, it can more accurately control the flow of current and ensure the accuracy of read and write operations, and each basic storage unit 10 controls two resistors respectively through two WL word lines 30, which can perform independent or parallel read and write operations, thereby improving data processing efficiency. The two resistors can improve storage reliability through redundant design, such as double writing or cross-verification.
[0045] Further, the drain of the first transistor 13 of the same basic storage unit 10 is connected to one end of the first resistor 11, the drain of the second transistor 14 is connected to one end of the second resistor 12, the other ends of the first resistor 11 and the second resistor 12 are connected to the BL bit line 20, the source of the first transistor 13 and the second transistor 14 are connected to the LSL local source line 40, and the gates of the first transistor 13 and the second transistor 14 are respectively connected to the adjacent WL word line 30, wherein the WL word line 30 is used to select to turn on or off the transistor by applying a voltage signal, and the BL bit line 20 is used to read or write The LSL local source line 40 is used to input data, and the LSL local source line 40 is used to provide current. During the operation of the RRAM storage array, the first transistor 13 and the second transistor 14 are respectively used as switching elements to control the flow of current. The first resistor 11 and the second resistor 12 store data by changing their resistance values (different data states are represented by high resistance or low resistance states). When a read or write operation is required, the voltage signal applied to the WL word line 30 controls the switch of the transistor, thereby adjusting the current path, and with the cooperation of the BL bit line 20 and the LSL local source line 40, the data read or write operation can be completed.
[0046] In the RRAM storage array of the embodiment of the present application, a plurality of basic storage cells 10 are arranged in a two-dimensional matrix, wherein the BL bit lines 20 are respectively arranged in each row of the two-dimensional matrix, and one end of the first resistor 11 and the second resistor 12 of the basic storage cell 10 in each row of the two-dimensional matrix is electrically connected to the BL bit line 20, the WL word line 30 is arranged in each column of the two-dimensional matrix, and the gates of the first transistor 13 and the second transistor 14 of the basic storage cell 10 in each column of the two-dimensional matrix are respectively electrically connected to the WL word line 30, and the LSL local source lines 40 are respectively arranged in each column of the two-dimensional matrix, and the first transistor 13 and the second transistor 14 of the basic storage cell 10 in each column of the two-dimensional matrix are respectively electrically connected to the WL word line 30. The source of the RRAM storage array is connected to the LSL local source line 40, and the two-dimensional matrix is provided with a plurality of group partition areas 50, each of which is correspondingly provided with SL common source lines 60 arranged in rows and sequentially connected to the LSL local source lines 40 in the group partition area 50. Thus, the RRAM storage array can be divided into multiple groups through the group partition area 50, and the SL common source line 60 of each group is connected to all the LSL local source lines 40 in the group partition area 50, that is, the RRAM storage array controls the LSL local source line through the SL common source line after the group partition to reduce the source line load and reduce the source line resistance, thereby ensuring the writing and reading operation accuracy of the RRAM storage array and improving the overall performance of the RRAM storage array.
[0047] In one embodiment, the two-dimensional matrix may include m rows of BL bit lines 20 , n columns of WL word lines 30 , and n / 2 columns of LSL local source lines 40 , where m is a positive integer and n is a positive even number.
[0048] Among them, the same basic storage unit 10 is connected to a row of BL bit lines 20, two columns of WL word lines 30 and a column of LSL local source lines 40, and the LSL local source line 40 on the same basic storage unit 10 is configured between two WL word lines 30, or it can be regarded as a two-dimensional matrix constructed by a number of basic storage units 10, with a set of m rows of basic storage units 10 and a set of n / 2 columns of basic storage units 10, the m rows of BL bit lines 20 are correspondingly connected to the m rows of basic storage units 10, and the n / 2 columns of WL word lines 30 and LSL local source lines 40 are correspondingly connected to the n / 2 columns of basic storage units 10.
[0049] Further, the number of group isolation areas 50 is set to x, each group isolation area 50 has L WL word lines 30 and L / 2 LSL local source lines 40, then the number of SL common source lines 60 is x, and the SL common source lines 60 in the same group isolation area 50 are correspondingly connected to L / 2 LSL local source lines 40, and x and L are positive integers.
[0050] And, the mapping relationship between the SL common source line 60 and L / 2 LSL local source lines 40 in the same group isolation area 50 includes:
[0051] (SL common source line 60 <0> →LSL Local Source Line 40 <l 2:0>)
[0052] Here, SL common source line 60 <0> It can be represented as the first line of the SL common source line 60 in the two-dimensional matrix, then the LSL local source line 40 <l 2:0>It can be represented as a single SL common source line 60 being divided and mapped to L / 2 LSL local source lines, that is, the RRAM storage array controls the LSL local source lines 40 arranged in columns within the group isolation area 50 through the SL common source lines 60 arranged in rows, that is, by turning the lines and using group isolation, the original long-distance routing of one SL source line across all columns is optimized to local control within each group isolation area, which greatly reduces the impact of line resistance on array performance, thereby ensuring the write and read operation accuracy of the RRAM storage array.
[0053] Optionally, the two-dimensional matrix is provided with a plurality of group partition areas 50, and the number of LSL local source lines 40 in each group partition area 50 may be the same, then L=n / 2x, for example, the two-dimensional matrix may include 80 rows of BL bit lines 20, 200 columns of WL word lines 30 and 100 columns of LSL local source lines 40, wherein the two-dimensional matrix is configured with 4 group partition areas 50 and 4 SL common source lines 60, then each group partition area 50 has 25 LSL local source lines 40, that is, the SL common source line 60 in the same group partition area 50 is correspondingly connected to the 25 LSL local source lines 40.
[0054] In one embodiment, the SL common source line 60 is also connected to a driving unit for dynamically adjusting the electrical signal on the SL common source line 60 to meet the requirements for the electrical signal in different operation modes and achieve precise control.
[0055] In one embodiment, the first resistor 11 and the second resistor 12 include bipolar resistors, which have symmetrical high-resistance and low-resistance switching characteristics. Specifically, the bipolar resistor can switch from a high-resistance state (HRS) to a low-resistance state (LRS) or from a low-resistance state (LRS) to a high-resistance state (HRS) by applying a forward or reverse voltage. For example, a forward voltage triggers switching from HRS to LRS, and a reverse voltage triggers switching from LRS to HRS. The characteristics of the bipolar resistor under forward and reverse voltages are symmetrical, and the switching voltage and response time are similar, thereby ensuring the write and read operation accuracy of the RRAM storage array.
[0056] An embodiment of the present application further provides an RRAM storage architecture, comprising a plurality of RRAM storage arrays of any of the above embodiments, wherein the capacities of the plurality of RRAM storage arrays are different.
[0057] That is, the RRAM storage architecture can select RRAM storage arrays of different capacities according to specific configuration needs, thereby achieving capacity expansion and flexible assembly to meet the needs of various application scenarios, avoid unnecessary power consumption, and extend the life cycle of the storage architecture.
[0058] The RRAM storage architecture of the embodiment of the present application can divide the RRAM storage array into multiple groups through the group isolation area 50, and the SL common source line 60 of each group is connected to all LSL local source lines 40 in the group isolation area 50, that is, the RRAM storage array controls the LSL local source line through the SL common source line after the group isolation to reduce the source line load and reduce the source line resistance, thereby ensuring the writing and reading operation accuracy of the RRAM storage array and improving the overall performance of the RRAM storage array.
[0059] For other working principles and processes of the RRAM storage architecture of this embodiment, please refer to the description of the RRAM storage array in the above embodiment of the present invention, which will not be repeated here.
[0060] The above is a detailed introduction to a RRAM storage array and architecture provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. It should be noted that in the present application, the descriptions of various embodiments have different focuses. For parts that are not described or recorded in detail in a particular embodiment, please refer to the relevant descriptions of other embodiments.
[0061] The above are only preferred embodiments of the present application, and the patent scope of the present application is not limited thereto. The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of this application, or directly or indirectly used in other related technical fields, as long as there is no contradiction in the combination of these technical features, are equally included in the patent protection scope of the present application.< / l> < / l> < / l>
Claims
1. A RRAM storage array, characterized in that: include: A basic storage unit, wherein a plurality of the basic storage units are arranged in a two-dimensional matrix; BL bit lines, the BL bit lines are respectively arranged in each row of the two-dimensional matrix, and the basic storage units in each row of the two-dimensional matrix are electrically connected to the BL bit lines; A WL word line, wherein the WL word line is arranged in each column of the two-dimensional matrix, and the basic storage unit of each column of the two-dimensional matrix is electrically connected to the WL word line; LSL local source lines, the LSL local source lines are respectively arranged in each column of the two-dimensional matrix, and the basic storage units in each column of the two-dimensional matrix are electrically connected to the LSL local source lines; The two-dimensional matrix is provided with a plurality of group isolation areas, each of which is correspondingly provided with an SL common source line, the SL common source line is parallel to the BL bit line and is sequentially connected to the LSL local source lines in the group isolation area.
2. The RRAM storage array according to claim 1, wherein: The two-dimensional matrix includes m rows of BL bit lines, n columns of WL word lines and n / 2 columns of LSL local source lines, wherein m is a positive integer and n is a positive even number; The same basic storage unit is connected to a row of the BL bit lines, two columns of the WL word lines and a column of the LSL local source line, and the LSL local source line on the same basic storage unit is configured between the two WL word lines.
3. The RRAM storage array according to claim 2, wherein: Set the number of the grouped isolation areas to x, each of the grouped isolation areas has L WL word lines and L / 2 LSL local source lines, then the number of the SL common source lines is x, and the SL common source line in the same grouped isolation area is correspondingly connected to L / 2 LSL local source lines.
4. The RRAM storage array according to claim 3, wherein: The mapping relationship between the SL common source line and L / 2 LSL local source lines in the same group isolation area includes: (SL common source line <0> →LSL local source line <l 2:0> )。< / l> 5. The RRAM storage array according to claim 1, wherein: The SL common source line is also connected to a driving unit for dynamically adjusting the electrical signal on the SL common source line.
6. The RRAM storage array according to claim 1, wherein: The two-dimensional matrix extends along a first direction and a second direction, the first direction is the extension direction of the rows of the two-dimensional matrix, the second direction is the extension direction of the columns of the two-dimensional matrix, the BL bit line and the SL common source line are parallel to the first direction, and the WL word line and the LSL local source line are parallel to the second direction.
7. The RRAM storage array according to claim 1, wherein: The basic storage unit includes a first resistor, a second resistor, a first transistor and a second transistor.
8. The RRAM storage array according to claim 7, wherein: The first resistor and the second resistor include bipolar resistors, and the bipolar resistors have symmetrical high-resistance state and low-resistance state switching characteristics.
9. The RRAM storage array according to claim 7, wherein: In the two-dimensional matrix, the drain of the first transistor of the same basic storage unit is connected to one end of the first resistor, the drain of the second transistor is connected to one end of the second resistor, the other ends of the first resistor and the second resistor are connected to the BL bit line, the sources of the first transistor and the second transistor are connected to the LSL local source line, and the gates of the first transistor and the second transistor are respectively connected to the adjacent WL word lines.
10. A RRAM storage architecture, characterized in that: The method comprises a plurality of RRAM storage arrays as claimed in any one of claims 1 to 9, wherein the capacities of the plurality of RRAM storage arrays are different.