Sot-mram circuit cell based on 2t2m differential structure and its storage-computing array circuit

Abstract

The present application relates to the field of non-volatile memory, in particular to a kind of SOT-MRAM circuit unit based on 2T2M differential structure and its storage and calculation array circuit.The SOT-MRAM unit includes first magnetic tunnel junction, second magnetic tunnel junction, first field effect transistor, second field effect transistor, first inverter, second inverter, write line, read line, input line and output line, and the above each component has specific connection relationship.The SOT-MRAM circuit unit is designed by special 2T2M differential structure and combined with the excellent performance of spin-orbit torque magnetic tunnel junction, and the storage and operation performance and efficiency of 2T2MSOT-MRAM differential circuit unit array are improved as a whole, the dependence on MTJ itself performance is reduced, so that it has more optimal energy efficiency ratio, more stable read-write speed and precision, and excellent reliability and stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of non-volatile memory, in particular to a SOT-MRAM circuit unit based on a 2T2M differential structure and a storage and calculation array circuit thereof. BACKGROUND

[0002] Artificial intelligence is developing rapidly and is widely used and successful in many fields such as natural language processing, computer vision, intelligent recommendation, etc., and has promoted social progress. The development of artificial intelligence is mainly based on the development of neural networks, such as convolutional neural networks (CNN), whose operation principle is multiplication and addition operation, which requires using multi-bit input (IN), weight (W) and output (OUT) to perform multiplication and accumulation (MAC) operation, so a large amount of weight information needs to be stored, and the transmission speed of the weight information limits the performance of the system.

[0003] In the traditional von Neumann computer architecture, the storage unit and the operation unit are separated, and the flow of data between the storage unit and the operation unit limits the operation speed of the system itself and occupies 90% of the power consumption of the system, greatly limiting the performance of the system. The current mainstream optimization method is to shorten the physical distance between the operation unit and the storage unit, but this scheme cannot fundamentally solve the problem. Another scheme is to use transistors combined with various new types of non-volatile memories, such as memristors, ferroelectric memories, phase change memories and magnetic memories, to realize the design of storage and calculation integration. In such a storage and calculation integration design, the selection of non-volatile storage units and the structure design between them and transistors are very important, which will greatly affect the reliability, stability, operation speed and operation density of the storage and calculation integration design.

[0004] For storage and calculation integration design, common structures include a 1T1R structure composed of one transistor and one memristor (T represents a transistor and R represents a memristor), a 1T1M structure composed of one transistor and one magnetic memory (M represents a magnetic memory), a 1T2M structure composed of one transistor and two magnetic memories, and a 2T2M structure using two transistors and two spin transfer magnetic memories (STT-MRAM). These structures can all achieve storage and calculation integration design to some extent, but all the above structures have certain deficiencies, such as slow read and write speed, low operation precision and accuracy, difficult to guarantee operation reliability, high power consumption, low storage density, poor reliability and durability, etc. The above problems need to be solved. SUMMARY

[0005] The purpose of the present application is to overcome the problems of the prior art, and to provide a SOT-MRAM circuit unit based on a 2T2M differential structure and a storage and calculation array circuit thereof.

[0006] In order to achieve the above-mentioned purpose, the application provides a SOT-MRAM circuit unit based on a 2T2M differential structure in one aspect, which comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first inverter, a second inverter, a write line, a read line, an input line and an output line; the read line is connected to the top electrode of the first magnetic tunnel junction and the second magnetic tunnel junction respectively; the write line is connected to the input end of the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction through the first inverter, and the first inverter is used to keep the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction opposite at all times; the output end of the heavy metal layer of the first magnetic tunnel junction is connected to the source of the first field effect transistor, and the output end of the heavy metal layer of the second magnetic tunnel junction is connected to the source of the second field effect transistor; the output line is connected to the drain of the first field effect transistor and the second field effect transistor respectively; and the input line is connected to the gate of the first field effect transistor and the second field effect transistor through the second inverter, and the second inverter is used to switch the first field effect transistor or the second field effect transistor to be in a conducting state.

[0007] The application provides a SOT-MRAM memory and computing array circuit in a second aspect, which comprises a plurality of the above-mentioned SOT-MRAM circuit units, wherein the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction of the lowest level SOT-MRAM circuit unit is connected to the ground wire through a grounding switch or is not connected to the ground wire, and when the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction of the lowest level SOT-MRAM circuit unit is connected to the ground wire through the grounding switch, the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction of all the SOT-MRAM circuit units are connected to the ground wire through the grounding switch.

[0008] The application provides a data operation method of the above-mentioned SOT-MRAM circuit unit in a third aspect, which comprises the following steps: writing first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; after the first data is written, pulling down the write line, inputting a strobe signal generated based on second data through the input line, and the strobe signal is used to select the first field effect transistor or the second field effect transistor to be in a conducting state; at the same time, inputting a voltage signal which does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction through the read line, so that the output line outputs an operation current signal based on the voltage signal; and extracting the operation result of the first data and the second data based on the current signal.

[0009] In a fourth aspect, the present application provides a data operation method of the SOT-MRAM computing array circuit, the data operation method comprising: writing corresponding first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write lines of each stage; and controlling the corresponding ground switch to be in an on state to avoid the write current of the SOT-MRAM circuit unit of the previous stage flowing into the SOT-MRAM circuit unit of the next stage, while controlling the remaining ground switches to be in an on state to avoid data being written into SOT-MRAM circuit units of different columns at the same time; after the first data is written, the write lines of each stage are pulled down, a selected communication signal generated based on corresponding second data is input through the input lines of each stage, and the selected communication signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each stage to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction is input through the read line of the highest stage, so that each column completes operation based on the voltage signal and outputs a final circuit signal through the output line of the corresponding lowest stage; and based on the final circuit signal of each column, the operation results of the first data and the second data of each column are extracted respectively.

[0010] In a fifth aspect, the present application provides a data operation device based on the SOT-MRAM circuit unit, the data operation device comprising: a first writing module configured to write first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write lines; a first operation module configured to, after the first data is written, pull down the write lines, input a selected communication signal generated based on second data through the input lines, and use the selected communication signal to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, input a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction through the read line, so that the output line outputs an operation current signal based on the voltage signal; and a first extraction module configured to extract the operation results of the first data and the second data based on the current signal.

[0011] In a sixth aspect, the present application provides a data operation device based on the SOT-MRAM computing array circuit, which comprises: a second writing module, configured to write corresponding first data into each stage of the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the writing lines, control the corresponding ground switch to be in a conductive state to avoid the writing current of the upper stage SOT-MRAM circuit unit flowing into the lower stage SOT-MRAM circuit unit, and control the remaining ground switches to be in a conductive state to avoid data being written into SOT-MRAM circuit units of different columns at the same time; a second operation module, configured to, after the first data is written, pull down the writing lines, input a selected signal generated based on corresponding second data through the input lines, and the selected signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each stage to be conductive; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction is input through the reading line of the highest stage, so that each column completes operation based on the voltage signal and outputs a final circuit signal through the output line of the corresponding lowest stage; and a second extraction module, configured to extract the operation results of the first data and the second data of each column based on the final circuit signal of each column.

[0012] The SOT-MRAM circuit unit of the present application integrates the storage unit and the computing unit in a small structure, and has high integration and compactness. The opposite storage information can be written into the two magnetic tunnel junctions at the same time through the setting of the first inverter, the selection of the operation channel is realized through the input line and the second inverter, at the same time, the reading line and the writing line are separated, the influence of the voltage signal on the magnetic tunnel junction in the operation process is reduced, and the stability and reliability of the magnetic tunnel junction are improved. The SOT-MRAM circuit unit of the present application is designed by a special 2T2M differential structure and combined with the excellent performance of the spin-orbit torque magnetic tunnel junction (SOT-MTJ), and the storage and operation performance and efficiency of the 2T2M SOT-MRAM differential circuit unit array are improved as a whole. Compared with the conventional design, the energy consumption is reduced by 20%-30%, the optimized current path reduces the leakage current, the structural design reduces the dependence on the performance of the MTJ itself, the change range of the resistance value is 10%-20%, the demand for the stability of the MTJ is reduced, and the anti-interference ability of the MTJ itself is utilized, so that the MTJ can still exhibit a certain stability under high temperature and high pressure, and can usually withstand a voltage of 1.5 times the rated voltage, and exhibits excellent reliability and stability. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A schematic diagram of the SOT-MRAM circuit unit of the embodiment of the present application;

[0014] Figure 2 SOT-MRAM in-memory computing array circuit (3x3) schematic diagram for embodiments of the present application;

[0015] Figure 3 Schematic diagram of spin orbit torque magnetic tunnel junction for the present application;

[0016] Figure 4 Test method schematic diagram for embodiments of the present application. DETAILED DESCRIPTION

[0017] The endpoints of the ranges and any values claimed herein are not to be understood as limited to the precise values recited as exactly that endpoint. Any values that fall within the range, including the upper or lower limit, are contemplated as if they were specifically and individually recited herein. For values that are lesser than or greater than the limits of the ranges, these are also contemplated. For values ranging between the upper and lower limits, any business of the values between the upper and lower limits are also contemplated. Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed

[0018] In the present application, the terms "first", "second" and the like are used to distinguish similar objects, so as to facilitate the description and understanding, and are not used to describe a specific order or sequence.

[0019] The SOT-MRAM circuit unit and its read-write method proposed in the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. The accompanying drawings are all in a very simplified form and all use non-precise proportions, only to facilitate, clearly assist the purpose of explaining the technical solutions of the present application, and the drawings shown are only one specific scheme within the protection scope of the present application.

[0020] In one aspect, the application provides an SOT-MRAM circuit unit based on a 2T2M differential structure, which comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first inverter, a second inverter, a write line, a read line, an input line and an output line; the read line is connected to the top electrode of the first magnetic tunnel junction and the second magnetic tunnel junction respectively; the write line is connected to the input end of the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction through the first inverter, and the first inverter is used to keep the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction opposite at all times; the output end of the heavy metal layer of the first magnetic tunnel junction is connected to the source of the first field effect transistor, and the output end of the heavy metal layer of the second magnetic tunnel junction is connected to the source of the second field effect transistor; the output line is connected to the drain of the first field effect transistor and the second field effect transistor respectively; and the input line is connected to the gate of the first field effect transistor and the second field effect transistor through the second inverter, and the second inverter is used to switch the first field effect transistor or the second field effect transistor to be in a conductive state.

[0021] According to the application, the first magnetic tunnel junction and the second magnetic tunnel junction can be selected from the conventional spin-orbit torque magnetic tunnel junction (SOT-MTJ) in the field, and the structural composition of the spin-orbit torque magnetic tunnel junction can also be a known structure in the field, and can also be extended to any non-volatile unit. The magnetic tunnel junction mentioned in the application refers to the spin-orbit torque magnetic tunnel junction.

[0022] According to the application, the structure adopted by the first magnetic tunnel junction and the second magnetic tunnel junction in the application comprises, from top to bottom, the top electrode, the reference layer, the insulating layer, the free layer and the heavy metal layer, as shown in Figure 3 The thicknesses of the top electrode, the reference layer, the insulating layer, the free layer and the heavy metal layer and the materials adopted by each of them can be selected within a wide range, as long as the function of the spin transfer torque magnetic tunnel junction can be realized. In order to further improve the stability and energy consumption ratio of the magnetic tunnel junction, preferably, the material of the reference layer can be selected from one or more of NiO, CoO, FeMn alloy, MnIr alloy and MnPt alloy, and the thickness is 5-15 nm. The material of the insulating layer is selected from one or more of MgO, AlN, Al2O3 and HfO2, and the thickness is 1-3 nm. The material of the free layer is selected from one or more of NiO, CoO, FeMn alloy, MnIr alloy and MnPt alloy, and the thickness is 10-25 nm. The material of the heavy metal layer is selected from one or more of Ta, Pt and W, and the thickness is 5-30 nm.

[0023] According to the application, the reference layer has a fixed magnetization direction, and the magnetization direction of the free layer can be switched between two opposite magnetization directions. When the magnetization directions of the reference layer and the free layer are the same, the magnetic tunnel junction presents a low resistance state, denoted as -1; when the magnetization directions of the reference layer and the free layer are opposite, the magnetic tunnel junction presents a high resistance state, denoted as +1. In addition, the principle of reading and writing data of the magnetic tunnel junction is as follows: after the state of the magnetic tunnel junction is initialized, when a current flows through the heavy metal layer of the magnetic tunnel junction, the magnetic polarization of the free layer can be triggered to flip, at this time, the resistance state of the magnetic tunnel junction also changes, thereby writing the storage data. Then, by inputting a current from the top electrode to flow through the entire magnetic tunnel junction, according to the different resistance states of the magnetic tunnel junction, the output current information is also different, thereby the corresponding storage data can be extracted.

[0024] According to the application, in order to prevent logic disorder during operation of the SOT-MRAM circuit unit, preferably, the input end of the first inverter is connected to the input end of the heavy metal layer of the first magnetic tunnel junction, and the input end of the second inverter is connected to the gate of the first field effect transistor. Alternatively, the input end of the first inverter is connected to the input end of the heavy metal layer of the second magnetic tunnel junction, and the input end of the second inverter is connected to the gate of the second field effect transistor.

[0025] According to the application, the first inverter and the second inverter can be selected within a wide range, as long as the input voltage signal and the output voltage signal are opposite, which can be used to control the reading and writing of the magnetic tunnel junction and the conduction of the field effect transistor. Preferably, the first inverter and the second inverter are both inverters composed of an operational amplifier, which are used to provide two voltage information with opposite polarities. The function of the first inverter is to make the voltage information input to the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction opposite, so that the two magnetic tunnel junctions always maintain opposite resistance states, thereby recording opposite storage data on the two magnetic tunnel junctions. The function of the second inverter is to control the conduction state of the first field effect transistor and the second field effect transistor, so that one of them can be selected as the operation channel when reading data.

[0026] According to the application, the first field effect transistor and the second field effect transistor can be selected within a wide range, as long as they can be switched on or off as switches. Preferably, the first field effect transistor and the second field effect transistor are NMOS tubes.

[0027] The second aspect of the present application provides a SOT-MRAM compute-in-memory array circuit, comprising a plurality of the above-mentioned SOT-MRAM circuit units, wherein the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction of the lowest-level SOT-MRAM circuit unit is connected to the ground wire through a ground switch or is not connected to the ground wire, and when the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction of all the SOT-MRAM circuit units is connected to the ground wire through a ground switch, the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction of all the SOT-MRAM circuit units is connected to the ground wire through a ground switch.

[0028] According to the present application, the terms "lowest level", "highest level", "each level", and the like refer to the relative relationship of each SOT-MRAM circuit unit in the vertical direction after a plurality of SOT-MRAM circuit units form a SOT-MRAM compute-in-memory array circuit. The "highest level" refers to the SOT-MRAM circuit unit or row at the top, and the read line of the highest level SOT-MRAM circuit unit is directly connected to an external circuit. The "lowest level" refers to the SOT-MRAM circuit unit or row at the bottom, and the output line of the lowest level SOT-MRAM circuit unit is directly connected to an external circuit.

[0029] According to the present application, the SOT-MRAM compute-in-memory array circuit is formed by vertically and / or horizontally expanding a plurality of SOT-MRAM circuit units.

[0030] Preferably, the vertical expansion is achieved by vertically connecting at least two SOT-MRAM circuit units in series, and the output line of the SOT-MRAM circuit unit at the upper level of the two adjacent SOT-MRAM circuit units is connected to the read line of the SOT-MRAM circuit unit at the lower level. Preferably, the ground switches connected by each SOT-MRAM circuit unit in series are the same. Preferably, the ground switch is an NMOS transistor.

[0031] Preferably, the horizontal expansion is achieved by horizontally connecting at least two SOT-MRAM circuit units by sharing the write line and the input line. The specific connection relationship of each SOT-MRAM circuit unit in the SOT-MRAM compute-in-memory array circuit can be referred to Figure 2 .

[0032] According to the application, in the SOT-MRAM computing array circuit, the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of the SOT-MRAM circuit unit are connected to the ground wire through the grounding switch, so as to avoid that a large current of the SOT-MRAM circuit unit of the previous stage flows to the magnetic tunnel junction of the SOT-MRAM circuit unit of the next stage through the transistor during the write operation of the multi-bit operation, thereby causing the loss or damage of the magnetic tunnel junction.

[0033] The third aspect of the application provides a data operation method of the SOT-MRAM circuit unit, the data operation method comprising: writing first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; after the first data is written, pulling down the write line, inputting a selected signal generated based on second data through the input line, and the selected signal is used to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction is input through the read line, so that the output line outputs an operation current signal based on the voltage signal; based on the current signal, the operation result of the first data and the second data is extracted.

[0034] According to the application, the step of extracting the operation result of the first data and the second data based on the current signal comprises: performing a capacitive integration operation on the current signal to obtain a time length during which the voltage of the capacitor reaches a threshold voltage; and determining the operation result of the first data and the second data based on the time length.

[0035] The fourth aspect of the present application provides a data operation method of the SOT-MRAM computing array circuit, the data operation method comprising: writing corresponding first data into each stage of the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up each stage of the write line; and controlling the corresponding ground switch to be in an on state to avoid the write current of the upper level SOT-MRAM circuit unit flowing into the lower level SOT-MRAM circuit unit, and controlling the remaining ground switches to be in an on state to avoid data being written into SOT-MRAM circuit units of different columns at the same time; after the first data is written, the write line of each stage is pulled down, a selected signal generated based on corresponding second data is input through each stage of the input line, and the selected signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each stage to be turned on; at the same time, a voltage signal that does not change the current resistance state of each stage of the first magnetic tunnel junction and the second magnetic tunnel junction is input through the read line of the highest stage, so that each column completes operation based on the voltage signal and outputs a final circuit signal through the output line of the corresponding lowest stage; and based on the final circuit signal of each column, the operation results of the first data and the second data of each column are extracted respectively.

[0036] According to the present application, the step of extracting the operation results of the first data and the second data of each column based on the final circuit signal of each column comprises: performing a capacitive integration operation on the final current signal of each column to obtain the time length during which the voltage of the capacitor reaches the threshold voltage; and based on the time length, dividing the time length interval to determine the operation results of the first data and the second data of each column.

[0037] The fifth aspect of the present application provides a data operation device based on the SOT-MRAM circuit unit, the data operation device comprising: a first writing module for writing first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; a first operation module for, after the first data is written, pulling down the write line, inputting a selected signal generated based on second data through the input line, and using the selected signal to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, inputting a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction through the read line, so that the output line outputs the current signal after operation based on the voltage signal; and a first extraction module for extracting the operation results of the first data and the second data based on the current signal.

[0038] The sixth aspect of the present application provides a data operation device based on the above-mentioned SOT-MRAM computing array circuit, which comprises: a second writing module, configured to write corresponding first data into each stage of the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the writing lines of each stage, and control the corresponding ground switch to be in a conductive state to avoid the writing current of the upper level SOT-MRAM circuit unit flowing into the lower level SOT-MRAM circuit unit, while controlling the remaining ground switches to be in a conductive state to avoid data being written into SOT-MRAM circuit units of different columns at the same time; a second operation module, configured to, after the first data is written, pull down the writing lines of each stage, input a selected communication signal generated based on corresponding second data through the input lines of each stage, and the selected communication signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each stage to be conductive; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each stage is input through the reading line of the highest stage, so that each column completes the operation based on the voltage signal and outputs the final circuit signal through the output line of the corresponding lowest stage; and a second extraction module, configured to extract the operation results of the first data and the second data of each column based on the final circuit signal of each column.

[0039] The SOT-MRAM circuit unit of the present application improves the reliability, stability and operation density of the conventional memory-computing integrated architecture, proposes a 2T2M differential structure design based on a spin orbit torque magnetic tunnel junction, uses the reading and writing operation characteristics of the spin orbit torque magnetic tunnel junction itself to separate the reading and writing signal lines, reduces the influence of the voltage signal on the magnetic tunnel junction in the operation process, improves the system operation speed, energy consumption ratio, operation density and service life without affecting the operation efficiency. At the same time, the specific 2T2M architecture has high flexibility and programmability, can be customized and optimized according to different application requirements, supports high parallel computing capability, can process the computing tasks of multiple neural network nodes at the same time, and accelerates the training and inference process of the neural network. Compared with the traditional computing architecture, this parallel computing capability can reduce the energy consumption ratio of the system, does not need to refresh the weight value of the neural network at all times, makes the static energy consumption of the system close to 0, the smaller reading voltage and switching mechanism also reduces the dynamic power consumption of the system by 30-50%, and the improvement of the switching speed reduces the response time by 20-30%, which can accelerate the training and inference process of the model.

[0040] The present application will be described in detail below with reference to the accompanying drawings.

[0041] The SOT-MRAM circuit unit of the present embodiment is as shown in Figure 1The read line IN is connected to the top electrode of the first magnetic tunnel junction MTJ_1 and the second magnetic tunnel junction MTJ_2 respectively. The write line WEN is connected to the input end of the heavy metal layer of the first magnetic tunnel junction MTJ_1 and the second magnetic tunnel junction MTJ_2 through the first inverter N1 respectively, wherein the input end of the first inverter N1 is connected to the input end of the heavy metal layer of the second magnetic tunnel junction MTJ_2, and the output end of the first inverter N1 is connected to the input end of the heavy metal layer of the first magnetic tunnel junction MTJ_1. The output end of the heavy metal layer of the first magnetic tunnel junction MTJ_1 is connected to the source of the first field effect transistor NP1, and the output end of the heavy metal layer of the second magnetic tunnel junction MTJ_2 is connected to the source of the second field effect transistor NP2. The drain of the first field effect transistor NP1 and the drain of the second field effect transistor NP2 are connected to the output line OUT respectively. The input line W is connected to the gate of the first field effect transistor NP1 and the gate of the second field effect transistor NP2 through the second inverter N2 respectively, wherein the input end of the second inverter N2 is connected to the gate of the second field effect transistor NP2, and the output end of the second inverter N2 is connected to the gate of the first field effect transistor NP1. The first magnetic tunnel junction MTJ_1 and the second magnetic tunnel junction MTJ_2 are spin-orbit torque magnetic tunnel junctions, wherein the material of the reference layer is selected from FeMn alloy, and the thickness is 10 nm. The material of the insulating layer is selected from MgO, and the thickness is 2 nm. The material of the free layer is selected from FeMn alloy, and the thickness is 20 nm. The material of the heavy metal layer is selected from Ta / Pt, and the thickness is 5 / 25 nm. The first inverter N1 and the second inverter N2 are both inverters composed of an operational amplifier. The first field effect transistor NP1 and the second field effect transistor NP2 are both NMOS transistors.

[0042] The SOT-MRAM circuit unit is subjected to a data operation: first, a write operation is performed by pulling up the write line WEN, and the write line WEN inputs a voltage signal +10V. At this time, the first field effect transistor NP1 and the second field effect transistor NP2 are turned on, the voltage of the second magnetic tunnel junction MTJ_2 is +10V, and the voltage of the first magnetic tunnel junction MTJ_1 is -10V under the action of the first inverter N1, so that the resistance states of the first magnetic tunnel junction MTJ_1 and the second magnetic tunnel junction MTJ_2 are opposite. After the write operation is completed, the write line WEN is pulled down, so that the voltage of the write line WEN is 0V. Then, a read and operation operation is started, a voltage signal +1.8V is input to the read line IN, and a voltage signal +1.8V is input to the input line W at the same time. At this time, the second field effect transistor NP2 is turned on, and the first field effect transistor NP1 is turned off under the action of the second inverter N2. After the current flows through the entire second magnetic tunnel junction MTJ_2, a current signal is output on the output line OUT. An integral operation is performed on the current signal using a capacitor, the time length when the voltage of the capacitor reaches the threshold voltage is obtained, and thus the operation result is obtained.

[0043] The magnetic tunnel junction of the SOT-MRAM circuit unit is tested, and the testing method is as shown in Figure 4 The direct current and radio frequency power are applied in the three-terminal device, which is mainly used for testing after the high resistance state, and the radio frequency power is used for injecting pulses, which is used for current-induced switching and time-resolved measurement. The pulse generator generates two matched and opposite pulse voltages with a rise time of 0.2 ns and a voltage of 10 V, and the two inputs V1 and V2 have the same amplitude and opposite signs, which ensures that the voltage in the vertical direction of the magnetic tunnel junction can be ignored. A small current (100 uA-5 mA) is injected in the vertical direction of the magnetic tunnel junction after each pulse read and write for resistance measurement, and the resistance measurement result can be used to judge the resistance state change. The magnetic tunnel junction of the SOT-MRAM unit is tested after tens of thousands of read and write operations, and the result shows that it still has stable read and write voltages, and the resistance error of the magnetic tunnel junction in the low resistance and high resistance states is not more than 0.5 KΩ.

[0044] Nine SOT-MRAM circuit units described above are expanded in the horizontal and vertical directions to obtain a SOT-MRAM computing array circuit (3x3) as shown in Figure 2 The top electrode of the highest-level SOT-MRAM circuit unit is directly connected to the read line IN. The highest-level SOT-MRAM circuit unit shares a write line WEN1 and an input line W1. The middle-level SOT-MRAM circuit unit shares a write line WEN2 and an input line W2. The lowest-level SOT-MRAM circuit unit shares a write line WEN3 and an input line W3. The cascade operation data of each vertical column SOT-MRAM circuit unit is output by the output line OUT1, the output line OUT2 and the output line OUT3. The heavy metal layer of the magnetic tunnel junction of each column SOT-MRAM circuit unit is connected to the ground, and is controlled by the ground switch NG1, the ground switch NG2 and the ground switch NG3, respectively.

[0045] The preferred embodiments of the present application are described in detail above, but the present application is not limited thereto. Within the technical concept of the present application, various simple modifications can be made to the technical solutions of the present application, including the combination of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as disclosed by the present application and fall within the protection scope of the present application.

Claims

1. An SOT-MRAM circuit cell based on 2T2M differential structure, characterized in that, The circuit unit comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first inverter, a second inverter, a write line, a read line, an input line and an output line; The read line is connected to the top electrode of the first magnetic tunnel junction and the second magnetic tunnel junction respectively; The write line is connected to the input end of the heavy metal layer of the first magnetic tunnel junction and the second magnetic tunnel junction through the first inverter, and the first inverter is used to keep the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction opposite at all times; The output end of the heavy metal layer of the first magnetic tunnel junction is connected to the source of the first field effect transistor, and the output end of the heavy metal layer of the second magnetic tunnel junction is connected to the source of the second field effect transistor; The output line is connected to the drain of the first field effect transistor and the second field effect transistor respectively; The input line is connected to the gate of the first field effect transistor and the second field effect transistor through the second inverter, and the second inverter is used to switch the first field effect transistor or the second field effect transistor to be in a conducting state.

2. The SOT-MRAM circuit cell of claim 1, wherein, The input end of the first inverter is connected to the input end of the heavy metal layer of the first magnetic tunnel junction, and the input end of the second inverter is connected to the gate of the first field effect transistor; And / or, the input end of the first inverter is connected to the input end of the heavy metal layer of the second magnetic tunnel junction, and the input end of the second inverter is connected to the gate of the second field effect transistor; And / or, the first inverter and the second inverter are inverters formed by an operational amplifier, which are used to provide two voltage information with opposite polarities.

3. An SOT-MRAM in-memory computing array circuit, comprising: The SOT-MRAM memory and computing array circuit comprises a plurality of SOT-MRAM circuit units as claimed in claim 1 or 2, wherein the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of the lowest-level SOT-MRAM circuit unit are not connected to the ground wire through a grounding switch, or are connected to the ground wire through a grounding switch, and when the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of all the SOT-MRAM circuit units are connected to the ground wire through a grounding switch, the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of all the SOT-MRAM circuit units are connected to the ground wire through a grounding switch.

4. The SOT-MRAM in-memory computing array circuit of claim 3, wherein, At least two SOT-MRAM circuit units are longitudinally connected in series, and the output line of the SOT-MRAM circuit unit at the upper level of the two adjacent SOT-MRAM circuit units is connected to the read line of the SOT-MRAM circuit unit at the lower level.

5. The SOT-MRAM in-memory computing array circuit of claim 4, wherein, The grounding switches connected by each SOT-MRAM circuit unit longitudinally connected in series are the same; And / or, the grounding switch is an NMOS tube.

6. The SOT-MRAM in-memory computing array circuit of any of claims 3-5, wherein, At least two SOT-MRAM circuit units are horizontally connected by sharing the write line and the input line.

7. A data operation method based on the SOT-MRAM circuit unit as claimed in claim 1 or 2, the data operation method comprising: writing first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; After the first data is written, the write line is pulled low, an input signal based on second data is input through the input line, and the input signal is used to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction is input through the read line, so that the output line outputs a calculated current signal based on the voltage signal; Based on the current signal, the operation result of the first data and the second data is extracted.

8. The method of data operation of the SOT-MRAM circuit cell according to claim 7, wherein, The step of extracting the operation result of the first data and the second data based on the current signal comprises: Capacitive integration is performed on the current signal to obtain the time length during which the voltage of the capacitor reaches the threshold voltage; Based on the time length, the operation result of the first data and the second data is determined.

9. A data operation method based on the SOT-MRAM computing array circuit of any one of claims 3-6, the data operation method comprising: By pulling up the write line of each stage, the corresponding first data is written into the first magnetic tunnel junction and the second magnetic tunnel junction of each stage; And control the corresponding ground switch to be in the on state to avoid the write current of the upper level SOT-MRAM circuit unit flowing into the lower level SOT-MRAM circuit unit, and control the remaining ground switches to be in the on state to avoid data being written into different columns of SOT-MRAM circuit units at the same time; After the first data is written, the write line of each stage is pulled low, an input signal based on the corresponding second data is input through the input line of each stage, and the input signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each stage to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each stage is input through the read line of the highest stage, so that each column of SOT-MRAM circuit units completes the calculation based on the voltage signal and outputs a final current signal through the output line of the corresponding lowest stage; Based on the final current signal of each column, the operation result of the first data and the second data of each column is extracted respectively.

10. The method of data operation of the SOT-MRAM in-memory computing array circuit of claim 9, wherein, The step of extracting the operation result of the first data and the second data of each column based on the final current signal of each column comprises: Capacitive integration is performed on the final current signal of each column to obtain the time length during which the voltage of the capacitor reaches the threshold voltage; Based on the time length, the time length interval is divided, and the operation result of the first data and the second data of each column is determined.

11. A data operation device based on the SOT-MRAM circuit unit of claim 1 or 2, the data operation device comprising: A first write module is configured to write first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line. The first operation module is configured to, after the first data is written, pull down the write line, input a selection signal generated based on the second data through the input line, and use the selection signal to select the first field effect transistor or the second field effect transistor to be turned on; meanwhile, input a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction through the read line, so that the output line outputs an operation current signal based on the voltage signal. The first extraction module is configured to extract an operation result of the first data and the second data based on the current signal.

12. A data operation device based on the SOT-MRAM operation array circuit in any one of claims 3-6, comprising: The second write module is configured to write corresponding first data into the first magnetic tunnel junction and the second magnetic tunnel junction of each stage by pulling up the write line of each stage. And control the corresponding ground switch to be in a conductive state to avoid the write current of the upper level SOT-MRAM circuit unit flowing into the lower level SOT-MRAM circuit unit, and control the remaining ground switches to be in a conductive state to avoid data being written into SOT-MRAM circuit units of different columns at the same time. The second operation module is configured to, after the first data is written, pull down the write line of each stage, input a selection signal generated based on the corresponding second data through the input line of each stage, and use the selection signal to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each stage to be turned on; meanwhile, input a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each stage through the read line of the highest stage, so that each column completes the operation based on the voltage signal and outputs a final current signal through the output line of the corresponding lowest stage. The second extraction module is configured to extract an operation result of the first data and the second data of each column based on the final current signal of each column.

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