Chip Failure Analysis Method, Device and Electronic Equipment

Abstract

The present invention relates to a method, apparatus and electronic device for chip failure analysis. The method includes: providing a stacked package chip having a failure point; the stacked package chip includes a substrate and a device layer disposed on the substrate; performing hot spot localization on the front and back surfaces of the stacked package chip respectively to obtain a hot spot localization result for the failure point; wherein, the front surface is the surface on which the device layer is formed, and the back surface is opposite to the front surface; based on the hot spot localization result, thinning the substrate starting from the back surface, and performing failure recurrence processing during the thinning process until the position information of the failure point in the stacked package chip is determined. The present invention can improve the success rate of failure analysis.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method and apparatus for chip failure analysis and an electronic device. Background Art

[0002] Electronic products are currently developing towards miniaturization, high density, high reliability, and low power consumption. With the development of semiconductor technology, the development direction of chips is also towards miniaturization, high density, high reliability, and low power consumption. In order to reduce the chip size, the industry uses multi-chip stacked packaging, where multiple chip dies are stacked together to form a stacked packaging chip. However, the packaging structure of the stacked packaging chip is complex, and it is very difficult to find the physical location of the failure by traditional chip failure methods, and the success rate is not high. Summary of the Invention

[0003] Based on this, it is necessary to provide a method and apparatus for chip failure analysis and an electronic device for the problem of low success rate of failure analysis in the prior art.

[0004] In a first aspect, this application provides a method for chip failure analysis, the method including:

[0005] Providing a stacked packaging chip with a failure point; the stacked packaging chip includes a substrate and a device layer disposed on the substrate;

[0006] Performing hot spot localization on the front and back of the stacked packaging chip respectively to obtain a hot spot localization result for the failure point; wherein, the front is the side where the device layer is formed, and the back is opposite to the front;

[0007] Thinning the substrate from the back based on the hot spot localization result and performing failure reproduction processing during the thinning process until the position information of the failure point in the stacked packaging chip is determined.

[0008] In one embodiment, providing a stacked packaging chip with a failure point includes:

[0009] Performing electrical analysis on the stacked packaging chip to obtain an electrical analysis result;

[0010] When it is determined based on the electrical analysis result that the stacked packaging chip has a short circuit failure, the stacked packaging chip is used as the stacked packaging chip with a failure point.

[0011] In one embodiment, the electrical analysis result includes an IV curve; the failure reproduction processing includes reproducing the IV curve on the substrate holes or metal lines of each stop layer.

[0012] In one embodiment, the stacked packaging chip is made based on a packaging process that matches the function of the HBM chip.

[0013] In one embodiment, the packaging process is a 3D packaging process or a 2.5D packaging process.

[0014] In one embodiment, the execution order of hot spot localization on the back side of the stacked packaged chip is before that on the front side of the stacked packaged chip.

[0015] In one embodiment, hot spot localization is performed on the front and back sides of the stacked packaged chip respectively to obtain hot spot localization results for the failure point, including:

[0016] When a hot spot area is obtained through hot spot localization on the back side, the hot spot localization result is determined as the first localization result indicating that the failure point is located in the lower part area of the stacked packaged chip;

[0017] When a hot spot area is obtained through hot spot localization on the front side, the hot spot localization result is determined as the second localization result indicating that the failure point is located in the upper part area of the stacked packaged chip.

[0018] In one embodiment, thinning the substrate starts from the back side based on the hot spot localization result, including:

[0019] Based on the first localization result, the substrate is ground using a first grinding process; the first grinding process includes grinding the substrate layer by layer;

[0020] Based on the second localization result, the substrate is ground using a second grinding process; the second grinding process includes grinding to the substrate layer related to the failure point according to the substrate design structure.

[0021] In one embodiment, failure recurrence processing is performed during the thinning process until the position information of the failure point in the stacked packaged chip is determined, including:

[0022] During the process of thinning the substrate until the device layer is exposed, if it is determined based on the failure recurrence processing that there is an abnormal position corresponding to the hot spot area on the substrate, the position information of the failure point is obtained based on the abnormal position;

[0023] During the process of thinning the substrate until the device layer is exposed, if it is determined based on the failure recurrence processing that there is no abnormal position corresponding to the hot spot area on the substrate, positioning processing for the hot spot area is performed on the stacked packaged chip with the exposed device layer to obtain the abnormal position corresponding to the hot spot area, and the position information of the failure point is obtained based on the abnormal position.

[0024] In one embodiment, obtaining the position information of the failure point based on the abnormal position includes:

[0025] Scanning the abnormal position with an electron microscope to obtain the position information of the failure point.

[0026] In one embodiment, a positioning process for a stacked package chip with the device layer exposed is performed for a hot spot area to obtain an abnormal position corresponding to the hot spot area, including:

[0027] Perform X-ray scans on the hot spot area and the corresponding die respectively to confirm the failure relationship; the failure relationship represents the corresponding relationship between the failure point and the abnormal position;

[0028] Cut the stacked package chip based on the failure relationship to obtain the abnormal position.

[0029] In one embodiment, perform X-ray scans on the hot spot area and the related wafer respectively to confirm the failure relationship, including:

[0030] When performing an X-ray scan on the area near the center of the hot spot area in 3D mode to obtain failure information, perform an X-ray scan on the die in 2D mode to obtain the overall structure information;

[0031] According to the package design data, the overall structure information, and the failure information, confirm the failure position to determine the failure relationship based on the failure position.

[0032] In a second aspect, the present application also provides a chip failure analysis device, which includes:

[0033] A chip providing module for providing a stacked package chip with a failure point; the stacked package chip includes a substrate and a device layer provided on the substrate;

[0034] A hot spot positioning module for performing hot spot positioning on the front and back of the stacked package chip respectively to obtain a hot spot positioning result for the failure point; wherein, the front is the side where the device layer is formed, and the back is opposite to the front;

[0035] A failure analysis module for thinning the substrate starting from the back based on the hot spot positioning result and performing a failure reproduction process during the thinning until the position information of the failure point in the stacked package chip is determined.

[0036] In a third aspect, the present application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the above method are implemented.

[0037] In a fourth aspect, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0038] In a fifth aspect, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the above method are implemented.

[0039] The above chip failure analysis method, device, and electronic device respectively perform hot spot localization on the front and back of a stacked package chip with a failure point to obtain a hot spot localization result for the failure point. Based on the hot spot localization result, the substrate is thinned starting from the back, and failure reproduction processing is performed during the thinning process until the position information of the failure point in the stacked package chip is determined. Among them, the stacked package chip includes a substrate and a device layer disposed on the substrate. The front side is the side where the device layer is formed, and the back side is opposite to the front side. In this application, hot spot localization is performed on both the front and back of the chip to preliminarily determine the position of the failure point in the chip, and then the position information of the failure point in the chip is determined during the substrate thinning process, which can improve the success rate of failure analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0041] Figure 1 is a flowchart of traditional failure analysis;

[0042] Figure 2 is a schematic flowchart of a chip failure analysis method in an embodiment;

[0043] Figure 3 is a schematic structural diagram of a stacked package chip in an embodiment;

[0044] Figure 4 is a schematic flowchart of providing a stacked package chip with a failure point in an embodiment;

[0045] Figure 5 is a schematic flowchart of determining an abnormal position in an embodiment;

[0046] Figure 6 is a schematic flowchart of determining a failure relationship in an embodiment;

[0047] Figure 7 is a specific schematic flowchart of a chip failure analysis method in an embodiment;

[0048] Figure 8 is a schematic diagram of a hot spot localization result in an embodiment;

[0049] Figure 9 is a schematic diagram of scanning a hot spot area in an embodiment;

[0050] Figure 10 Schematic diagram of obtaining failure relationships through scanning in an embodiment

[0051] Figure 11 Schematic diagram of abnormal location positioning in an embodiment

[0052] Figure 12 Schematic diagram of taking an optical microscope photo of an abnormal location in an embodiment

[0053] Figure 13 Schematic diagram of taking a scanning electron microscope photo of an abnormal location in an embodiment Detailed implementation manners

[0054] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0057] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upward and downward orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0058] As used herein, the singular forms "a", "an" and "the" may also include the plural unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not excluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0059] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, such that variations in the shapes shown are to be expected due to, for example, manufacturing techniques and / or tolerances. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

[0060] Existing chip failure analysis techniques can be divided into non-destructive analysis and destructive analysis of the chip, and under these two types of analysis, there are respectively electrical analysis and physical analysis. In traditional solutions, after a chip failure occurs, according to the failure phenomenon, non-destructive analysis is first carried out. When it is confirmed that there is no external damage to the chip, electrical tests are usually carried out; after the electrical tests confirm the failure, circuit analysis and hot spot location are carried out; after the hot spot location confirms the failure position, destructive analysis is introduced, and the chip is cut, ground, delayered, etc., and finally the physical position causing the failure is found.

[0061] However, as Figure 1As shown in the figure, in the prior art, after discovering that there is a short circuit between pins of a chip and locating the failure hot spot, destructive slicing analysis is immediately carried out. However, for stacked package chips, their package structures are complex, the number of chip micro-bumps is huge, and the number of stacked layers is relatively large. After obtaining the chip hot spot position and directly performing destructive slicing analysis, it is very difficult to finally find the failure physical position, and the success rate is not high. It should be noted that Figure 1 In Figure 1 , ATE refers to the automatic test equipment used for chip testing, and the IV test represents the current-voltage characteristic test.

[0062] Based on the above traditional technology, an embodiment of the present application proposes a chip failure analysis method. In view of the failure phenomenon, by combining non-destructive and destructive analysis means, the FA (Failure Analysis) analysis process is reasonably optimized, high-quality FA samples are prepared, and the success rate of FA analysis is improved. Among them, the present application is applicable to the chip failure analysis of stacked package chips. Exemplarily, the stacked package chips may include, but are not limited to, HBM (High Bandwidth Memory) chips with 2.5D / 3D packaging. It should be noted that the beneficial effects brought by the embodiments of the present application or the technical problems solved are not limited to this one, and there may also be other implicit or related problems. For details, please refer to the description of the following embodiments.

[0063] Before introducing the specific embodiments of the present application, the professional terms involved in the present application will be explained first:

[0064] HBM: High Bandwidth Memory, high bandwidth memory.

[0065] ATE: Automatic Test Equipment, automatic test equipment.

[0066] FA: Failure Analysis, failure analysis.

[0067] TIM: Thermal Interface Material, thermal interface material.

[0068] ASIC: Application-Specific Integrated Circuit, application-specific integrated circuit.

[0069] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0070] In an exemplary embodiment, as Figure 2 shown, a chip failure analysis method is provided. Taking the application of this method to the chip failure analysis of a stacked package chip as an example, the method includes the following steps 202 to 206. Among them:

[0071] Step 202: Provide a stacked package chip with a failure point; the stacked package chip includes a substrate and a device layer disposed on the substrate.

[0072] In the embodiment of the present application, after a failure occurs inside the stacked package chip, the failure point can be located; among them, the stacked package chip with a failure point can refer to a stacked package chip in which a failure structure exists in the corresponding chip area. Optionally, the chip area can include the substrate and the area where the device layer is located, and the failure structure can include a failure pin, for example, a short circuit pin corresponding to a chip short circuit failure.

[0073] Specifically, the chip can be determined whether it has a failure point by performing electrical analysis on the stacked package chip. Exemplarily, it is confirmed whether a chip short circuit failure occurs through electrical analysis. It can be understood that the above electrical analysis and failure point determination, etc., can also adopt other forms, rather than being limited to the forms already mentioned in the above embodiments. The present application provides a stacked package chip with a failure point as the chip to be analyzed, so as to improve the success rate of chip failure analysis by preparing high-quality failure analysis samples.

[0074] In the embodiment of the present application, the stacked package chip can include a substrate and a device layer disposed on the substrate. Among them, the substrate can refer to a package substrate. Optionally, the device layer is related to the function of the stacked package chip. For example, the device layer can refer to various structures such as an integrated circuit layer, a micro-structure, or a sensor layer stacked on the substrate, which can implement various functions such as signal detection, control, storage, and physical quantity conversion.

[0075] Exemplarily, taking the HBM chip with 2.5D packaging as the stacked package chip as an example, as Figure 3 shown, the device layer can include an interposer 302 and a chip located on the interposer 302. Among them, the chip can include an integrated circuit chip (such as an ASIC chip) and a memory stack. The memory stack can include multiple memory chips and logic chips. The memory chips are stacked on the logic chip and connected to the logic chip. Figure 3 In, the chips are placed side by side on the top of the interposer 302, and the interconnection is realized through the micro-bumps 304 (ubump) of the chips and the wiring in the interposer 302. The interposer 302 realizes the interconnection of the upper and lower layers through through-silicon vias (TSV), and is then welded to the package substrate 300 through solder balls 306 (C4).

[0076] It can be understood that the above stacked package chips can also adopt other structural forms, not limited to the forms mentioned in the above embodiments, as long as they can achieve the corresponding functions of stacked packaging. Among them, the memory chip can be a memory semiconductor chip, and the memory semiconductor chip can be a volatile memory semiconductor chip (such as Dynamic Random Access Memory (DRAM)). The substrate in the embodiments of the present application is the carrier of semiconductor packaging, and the packaging substrate can be made by using existing packaging substrate manufacturing processes. The packaging substrate can include a ball grid array packaging substrate. Regarding the material and type of the substrate, the embodiments of the present application do not make specific limitations.

[0077] Step 204: Perform hot spot localization on the front and back of the stacked package chip respectively to obtain the hot spot localization result for the failure point; wherein, the front is the side where the device layer is formed, and the back is opposite to the front.

[0078] Specifically, in the case of obtaining a stacked package chip with a failure point, the present application proposes to perform hot spot localization on the front and back of the stacked package chip respectively to obtain the hot spot localization result for the failure point. This hot spot localization result can represent the preliminary judgment result of the position of the failure point in the stacked package chip. For example, there is a failure structure in the upper part area of the stacked package chip, or there is a failure structure in the lower part area of the stacked package chip. It can be understood that the front of the stacked package chip is the side where the device layer is formed, and the back is opposite to the front.

[0079] In some embodiments, performing hot spot localization on the back of the stacked package chip does not require destroying the structure of the stacked package chip. However, performing hot spot localization on the front of the stacked package chip may destroy the structure of the stacked package chip. For example, if the chip package has a metal upper cover, the metal upper cover and TIM glue need to be removed before performing hot spot localization on the front. It can be understood that when the stacked package chip is a bare die, there is no need to remove the metal upper cover, etc. Further, regardless of whether a hot spot area is obtained by performing hot spot localization on the back of the stacked package chip, the present application will perform hot spot localization on the front of the stacked package chip, and vice versa.

[0080] By performing hot spot localization on both the front and back of the stacked package chip with a failure point, the chip failure analysis process is optimized, so that the embodiments of the present application can preliminarily determine the approximate position of the failure point, laying a foundation for subsequently determining the position information of the failure point, and improving the analysis success rate.

[0081] Step 206: Thin the substrate starting from the back based on the hot spot localization result, and perform failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined.

[0082] Specifically, in the case of obtaining the hot spot positioning result, the substrate can be thinned starting from the back of the stacked package chip; wherein, the way of thinning the substrate is related to the results of the above-mentioned hot spot positioning on the front and back, that is, in this application, the substrate is thinned starting from the back based on the hot spot positioning result.

[0083] It can be understood that by performing hot spot positioning on the front and back of the stacked package chip respectively above to determine the approximate position of the failure point, different grinding methods can be used to thin the substrate from the back, thereby optimizing the substrate grinding process and improving the success rate of failure analysis. It should be noted that the embodiments of this application do not limit the grinding method, as long as the function of thinning the substrate can be achieved.

[0084] Furthermore, in this application, failure reproduction processing is performed during the substrate thinning process until the position information of the failure point in the stacked package chip is determined. This failure reproduction can refer to the process of reproducing failure data to avoid the situation where the failure point may be damaged during the substrate thinning process, thereby ensuring the accuracy of failure point positioning and improving the success rate of chip failure analysis.

[0085] The above chip failure analysis method can significantly improve the success rate of failure analysis by performing hot spot positioning on both the front and back of the chip to initially judge the position of the failure point in the chip, and then determining the position information of the failure point in the chip through failure reproduction processing during the substrate thinning process.

[0086] In an exemplary embodiment, as Figure 4 shown, step 202 includes steps 302 to 304. Among them:

[0087] Step 302, perform electrical analysis on the stacked package chip to obtain an electrical analysis result.

[0088] Specifically, this application can perform electrical analysis on the stacked package chip to obtain an electrical analysis result. Among them, the electrical analysis can include ATE test and / or IV test. It can be understood that this application does not limit the specific test types of the electrical analysis.

[0089] Step 304, when it is determined based on the electrical analysis result that the stacked package chip has a short circuit failure, then regard the stacked package chip as a stacked package chip with a failure point.

[0090] Specifically, the embodiments of the present application are applicable to chip short - circuit failures. Regarding determining the existence of short - circuit failures in stacked packaged chips based on electrical analysis results, for example, in the case where low - resistance failures between pins are found during ATE testing, an IV test can be performed to confirm the short - circuit failure. Another example is that taking the stacked packaged chip as an HBM chip, after it is determined through ATE testing and IV testing that a short - circuit occurs between the pins of the HBM particle, it is determined that a chip short - circuit failure has occurred.

[0091] The embodiments of the present application determine the stacked packaged chips with failure points through electrical analysis, ensuring the quality of failure analysis samples and improving the success rate of chip failure analysis.

[0092] In practical applications, the failure reproduction process of the embodiments of the present application is related to the test process for determining whether the stacked packaged chips have failure points. In one embodiment, the electrical analysis results may include IV curves; the failure reproduction process includes reproducing the IV curves on the substrate holes or metal lines of each stop layer.

[0093] Specifically, during the substrate thinning process, the embodiments of the present application avoid damaging the failure points during the substrate thinning process by reproducing the failure data detected at the failure points. Taking the example of hotspot localization on the back of a stacked packaged chip to obtain a hotspot area, for a stacked packaged chip with a failure point, Thermography hotspot localization can be performed on the back of the chip (i.e., the substrate surface) according to the current - voltage of the IV test, and then during the substrate thinning process, pay attention to the located hotspot area and reproduce the failure IV curves on the substrate holes or metal lines of each stop layer.

[0094] Exemplarily, taking the example of thinning the substrate by grinding, during grinding, the substrate can be ground to the stop layer, that is, stop grinding when reaching the stop layer, and then reproduce the failure IV curves on the substrate holes or metal lines of each stop layer. It can be understood that taking the substrate as a packaging substrate, the packaging substrate may include metal lines, and the metal lines can be arranged in the packaging substrate. Further, the packaging substrate may also include substrate holes penetrating through it, and then during the substrate thinning process, the failure IV curves can be reproduced on the substrate holes or metal lines of each stop layer.

[0095] In one embodiment, the stacked packaged chip is made based on a packaging process that matches the function of the HBM chip.

[0096] Specifically, the stacked packaged chips of the embodiments of the present application can be made based on a packaging process that matches the function of the HBM chip, that is, the stacked packaged chips can adopt HBM chips.

[0097] In one embodiment, the packaging process is a 3D packaging process or a 2.5D packaging process.

[0098] Specifically, this application is applicable to the short - circuit failure of HBM chips in 2.5D / 3D packaging. For the case where the HBM chip particle packaging structure in 2.5D / 3D packaging is complex, the number of chip micro - bumps is huge, and the stacking levels are numerous, this application can, in view of the failure phenomenon, combine non - destructive and destructive analysis means, reasonably optimize the FA analysis process, prepare high - quality FA samples, and improve the success rate of FA analysis.

[0099] Regarding the hot - spot localization of the front and back sides of the stacked packaged chip respectively to obtain the hot - spot localization results for the failure point, this application proposes corresponding failure analysis strategies, which can further improve the success rate of failure analysis. In one embodiment, the execution order of hot - spot localization on the back side of the stacked packaged chip is before the hot - spot localization on the front side of the stacked packaged chip.

[0100] Specifically, this application proposes a sequential requirement for the execution order of hot - spot localization. Among them, the execution order of hot - spot localization on the back side of the stacked packaged chip is before the hot - spot localization on the front side of the stacked packaged chip, that is, first perform hot - spot localization on the back side of the stacked packaged chip, and then perform hot - spot localization on the front side of the stacked packaged chip, so as to avoid damaging the chip structure as much as possible and determine the approximate position of the failure point through non - destructive analysis means. It should be noted that regardless of whether a hot - spot area is located on the back side, the embodiments of this application will perform hot - spot localization on the front side of the stacked packaged chip.

[0101] In addition, preferentially performing hot - spot localization on the back side of the stacked packaged chip is more applicable to the analysis of low - resistance short - circuit failures of chips, further reduces the difficulty of finding the physical location of the failure, and ensures the success rate of failure analysis.

[0102] In some embodiments, the hot - spot localization of the front and back sides of the stacked packaged chip respectively to obtain the hot - spot localization results for the failure point includes:

[0103] When a hot - spot area is obtained by hot - spot localization on the back side, the hot - spot localization result is determined as the first localization result indicating that the failure point is located in the lower part area of the stacked packaged chip;

[0104] When a hot - spot area is obtained by hot - spot localization on the front side, the hot - spot localization result is determined as the second localization result indicating that the failure point is located in the upper part area of the stacked packaged chip.

[0105] Specifically, when a hot - spot area is obtained by hot - spot localization on the back side, the hot - spot localization result can be determined as the first localization result, which indicates that the failure point is located in the lower part area of the stacked packaged chip. When a hot - spot area is obtained by hot - spot localization on the front side, the hot - spot localization result can be determined as the second localization result, which indicates that the failure point is located in the upper part area of the stacked packaged chip.

[0106] It can be understood that by distinguishing whether the failure point is located in the upper area or the lower area of ​​the stacked packaged chip, the present application can make a preliminary judgment on the position of the failure point on the Z axis of the chip based on hotspot positioning on both the front and back sides of the chip, thereby improving the success rate of failure analysis.

[0107] In one embodiment, thinning the substrate from the back side based on the hot spot location result includes:

[0108] Based on the first positioning result, the substrate is ground using a first grinding process; the first grinding process includes grinding the substrate layer by layer;

[0109] Based on the second positioning result, a second grinding process is used to grind the substrate; the second grinding process includes grinding to a substrate layer related to the failure point according to the design structure of the substrate.

[0110] Specifically, when the hotspot location result is the first location result, that is, it is determined that the failure point is located in the lower part of the stacked package chip (there is a hotspot area on the back of the chip), the first grinding process can be used to grind the substrate, for example, grinding the substrate layer by layer. Exemplarily, the first grinding process can be to grind and thin the package substrate layer by layer.

[0111] When the hotspot location result is the second location result, that is, it is determined that the failure point is located in the upper area of ​​the stacked package chip (there is no hotspot area on the back of the chip), the second grinding process can be used to grind the substrate, for example, grinding to the substrate layer related to the failure point according to the substrate design structure. For example, taking the failure structure as a failed pin as an example, the second grinding process can be grinding to the substrate layer involved in the failed pin, for example, grinding to the substrate layer related to the short-circuit pin according to the substrate design structure.

[0112] Furthermore, during the grinding process, attention needs to be paid to the located hot spot areas. For example, the substrate structure can be checked under a high-resolution optical microscope to see if there are any abnormalities in the hot spot areas that may cause short circuit failures, and the failure data (such as IV curves) can be reproduced on the substrate holes or metal wires on each stop layer to determine whether physical abnormalities corresponding to electrical failures are found on the substrate.

[0113] By coordinating different hotspot positioning results and using different substrate grinding processes, the present application can avoid damaging the failure point, optimize the failure analysis process, and improve the success rate of failure analysis. It should be noted that the present application does not limit the specific grinding process, as long as the function of thinning the substrate can be achieved. For example, the above-mentioned grinding process can reduce the thickness of the substrate to expose the device layer or the substrate layer involved in the failed pin. In an exemplary embodiment, the substrate can be thinned using a thinning process such as a mechanical process.

[0114] In one embodiment, during the thinning process, a failure reproduction process is performed until the position information of the failure point in the stacked package chip is determined, including:

[0115] During the process of thinning the substrate until the device layer is exposed, if it is determined based on the failure reproduction process that there is an abnormal position corresponding to the hot spot area on the substrate, the position information of the failure point is obtained based on the abnormal position;

[0116] During the process of thinning the substrate until the device layer is exposed, if it is determined based on the failure reproduction process that there is no abnormal position corresponding to the hot spot area on the substrate, a positioning process for the hot spot area is performed on the stacked package chip with the exposed device layer to obtain the abnormal position corresponding to the hot spot area, and the position information of the failure point is obtained based on the abnormal position.

[0117] Specifically, during the process of thinning the substrate until the device layer is exposed, it is necessary to pay attention to the located hot spot area, and through the failure reproduction process, determine whether a corresponding abnormal position is found on the substrate. If there is no abnormal position on the substrate, further determine whether the abnormal position is in the device layer of the stacked package chip. Among them, the above abnormal position can be understood as a physical abnormality corresponding to the electrical failure, that is, the abnormal physical position.

[0118] Exemplarily, taking the thinning of the substrate by grinding as an example, thinning the substrate until the device layer is exposed can be understood as grinding the substrate to a target thickness, and the target thickness can be the thickness of the substrate. For example, the substrate is thinned to the first layer (L1).

[0119] Optionally, if it is determined based on the failure reproduction process that there is an abnormal position corresponding to the hot spot area on the substrate, the position information of the failure point can be obtained based on the abnormal position, that is, it is determined that the failure point is located in the substrate. If it is determined based on the failure reproduction process that there is no abnormal position corresponding to the hot spot area on the substrate, a positioning process for the hot spot area can be performed on the stacked package chip with the exposed device layer until the abnormal position corresponding to the hot spot area is obtained, and the position information of the failure point is obtained based on the abnormal position.

[0120] In this application, during the process of thinning the substrate, by confirming whether the failure point is located in the substrate, the specific positioning method for the failure point is further determined, thereby optimizing the failure analysis process. Among them, grinding and thinning the substrate before determining whether the failure point is in the device layer process can further improve the success rate of failure analysis, and performing the positioning analysis of the specific position of the failure point before cutting the chip can obtain an abnormal position judgment smaller than the hot spot area.

[0121] Regarding obtaining the position information of the failure point based on the abnormal position, in one embodiment, obtaining the position information of the failure point based on the abnormal position includes:

[0122] Use an electron microscope to scan the abnormal position to obtain the position information of the failure point.

[0123] Specifically, in the case of obtaining the abnormal position, the abnormal position can be scanned by an electron microscope, and then the position information of the failure point can be obtained, thus ending the chip failure analysis. Exemplarily, using an electron microscope to scan the abnormal position can be taking photos of the abnormal position with a high-resolution optical microscope and a scanning electron microscope, and the present application is not limited thereto.

[0124] In an exemplary embodiment, perform a positioning process on the stacked package chip with the device layer exposed for the hot spot area to obtain the abnormal position corresponding to the hot spot area. As Figure 5 shown, it may include step 402 to step 404, where:

[0125] Step 402, perform X-ray scans on the hot spot area and the corresponding die respectively to confirm the failure relationship; the failure relationship represents the corresponding relationship between the failure point and the abnormal position.

[0126] Specifically, for the stacked package chip with the device layer exposed, the present application confirms the failure relationship by performing X-ray scans on the hot spot area and the corresponding die respectively, and this failure relationship can represent the corresponding relationship between the failure point and the abnormal position.

[0127] Among them, after thinning the substrate, by performing an X-ray scan (X-ray scan) on the hot spot area, the specific position of the failure point corresponding to the hot spot area can be confirmed, and by performing an X-ray scan on the die corresponding to the hot spot area, the overall structure situation can be confirmed. Then, based on the specific position of the failure point corresponding to the hot spot area and the overall structure situation, the corresponding relationship between the failure point and the abnormal position is obtained, that is, the corresponding relationship between the failure phenomenon and the abnormal position is confirmed.

[0128] Step 404, cut the stacked package chip based on the failure relationship to obtain the abnormal position.

[0129] Specifically, after obtaining the failure relationship, the stacked package chip can be cut according to the failure relationship to obtain the abnormal position. Among them, cutting the stacked package chip can be slicing the chip cross-sectionally to cut out the abnormal point.

[0130] In the embodiment of the present application, thinning the substrate before the X-ray scan can not only simplify the analysis process and cost (because the failure point may be in the substrate layer), improve the success rate of failure analysis, but also greatly improve the clarity of X-ray imaging and ensure the quality of X-ray imaging. In addition, by performing an X-ray scan before cutting the chip in the present application, a judgment of the failure point position with a smaller range than the hot spot area can be obtained.

[0131] In one embodiment, as Figure 6 shown, step 402 may include steps 502 to 504. Among them:

[0132] Step 502, when using X-ray to scan the area near the center of the hot spot region in 3D mode to obtain failure information, use X-ray to scan the grains in 2D mode to obtain the overall structure information.

[0133] Specifically, in the embodiment of the present application, X-ray is used to scan the area near the center of the hot spot region in 3D mode. Among them, using X-ray to scan in 3D mode may refer to performing 3D X-ray scanning.

[0134] Exemplarily, the area near the center of the hot spot region may refer to a small range of the hot spot center region (abbreviated as a small area range). By scanning the area near the center of the hot spot region in the present application, the clarity of 3D-X-ray can be improved. Optionally, the area size of the area near the center can be selected according to requirements. For example, the area size can be 2mm * 2mm * 2mm. The present application has no limitation on the specific value of this area size.

[0135] Further, the failure information may indicate that an abnormality is found in the 3D X-ray scan, such as confirming the position of the failure point corresponding to the hot spot region. When the failure information is obtained, X-ray can be used to scan the grains in 2D mode to obtain the overall structure information. Among them, using X-ray to scan in 2D mode may refer to performing 2D X-ray scanning. Taking a stacked package chip using HBM chips as an example, the grains may refer to HBM particles, that is, in the embodiment of the present application, 2D X-ray scanning and photographing can be performed on the entire HBM particles involved.

[0136] Optionally, the overall structure information may refer to an overall diagram representing the overall structure of the grains, such as an overall diagram corresponding to 2D X-ray. By obtaining the failure information and the overall diagram in the embodiment of the present application, the position of the failure point can be confirmed more accurately, and the success rate of failure analysis can be improved. Among them, thinning the substrate before X-ray scanning can not only simplify the analysis process and cost, but also greatly improve the clarity of 3D X-ray imaging.

[0137] Step 504, according to the package design data, the overall structure information, and the failure information, confirm the failure position to determine the failure relationship based on the failure position.

[0138] Specifically, when the overall structure information and the failure information are obtained, the failure position can be confirmed according to the package design data, the overall structure information, and the failure information to determine the failure relationship based on the failure position.

[0139] Among them, the failure location can refer to the specific location of the failure point, such as pin information, etc. Further, the package design data can be a package design document. After confirming the failure information (finding the abnormal location) through 3D X-ray scanning, it can correspond to the overall 2D X-ray image. Referring to the package design document, the pin information involved in the abnormal location can be found, and then the correspondence between the failure point (failure phenomenon) and the abnormal location can be confirmed.

[0140] The above chip failure analysis method performs 3D X-ray before cutting the chip, which can obtain a judgment of the abnormal location with a smaller range than the hot spot area. Grinding and thinning the substrate before 3D X-ray can improve the success rate of failure analysis and ensure the imaging quality of 3D X-ray.

[0141] To further illustrate the solution of the present application, a specific example is given below. Taking a stacked package chip using a 2.5D / 3D package HBM chip and performing short-circuit failure analysis as an example, as Figure 7 shown, the chip failure analysis process may include: After the 2.5D / 3D package chip confirms through ATE and IV tests (such as IV probe) that the short circuit occurs between the pins of the HBM particles, when the resistance value is small, the thermography hot spot positioning can be first performed on the back of the chip (i.e., the substrate surface) according to the current and voltage of the IV probe; Whether or not a hot spot is obtained on the back, a hot spot positioning must be performed again on the front of the chip. If the chip package has a metal top cover, the metal top cover and TIM (Thermal interface material) glue should be removed before the front positioning.

[0142] Based on the results of the above two hot spot positionings, as Figure 7 shown, grind the substrate layer by layer (such as grind the package substrate layer by layer in a planar manner), or grind to the substrate layer involved in the failed pin (such as according to the substrate design structure, grind the substrate layer related to the short-circuit pin), pay attention to the located hot spot area during the grinding process, confirm whether physical abnormalities corresponding to electrical failures are found on the substrate (for example, it can be checked under a high-resolution optical microscope whether there are abnormalities causing short-circuit failures in the hot spot area of the substrate structure), and reproduce the failed IV curve of the above IV test on the substrate holes or metal lines at each stop layer.

[0143] After the substrate is thinned until the device layer is exposed, if no abnormality is found, the thinned substrate chip is subjected to X-ray scanning. A 3D X-ray scan is performed on a small area (e.g., 2mm * 2mm * 2mm) of the hotspot center region, and a 2D X-ray scan and photograph are taken of the entire HBM particles involved. After an abnormality is found by 3D X-ray scanning, the corresponding 2D X-ray overall image can be referred to, and with reference to the package design document, the pin information involved in the abnormal position can be found to confirm the correspondence between the failure phenomenon and the abnormal position, confirm the failure position, and then the chip can be cut to find the abnormal position (e.g., perform a cross-sectional slice of the chip to cut out the abnormal point), and optical microscopy and electron microscopy photographs are taken of the abnormal position, and the analysis is completed.

[0144] Among them, taking the short-circuited pin as VDDA_25_MEN (pin name) as an example, Figure 8 The following shows the hotspot localization result of the short-circuited pin ( Figure 8 The two boxes in it can represent HBM particles). Taking Figure 8 The hotspot area on the left as an example, by 3D X-ray scanning the area near the center of the HBM hotspot area, as Figure 9 shown, it is found that a microbump (ubump) on the HBM die is suspected to be abnormal. Further, as Figure 10 shown, the positional relationship between the abnormal microbump and the C4 bump can be found through the 2D&3D X-ray diagram. As Figure 11 shown, the abnormal microbump (VDDA_25_MEN) can be found in the package design document. In addition, after cutting the chip, the abnormal position is found. As Figure 12 shown, the following is a high-resolution optical microscopy image of the abnormal position, Figure 13 and the following is a scanning electron microscopy image of the abnormal position.

[0145] For the above chip failure analysis method, in view of the failure phenomenon, by combining non-destructive and destructive analysis means, such as hotspot localization, substrate grinding, IV measurement, and X-ray, etc., the FA analysis process is reasonably optimized, high-quality FA samples are prepared, and the FA analysis success rate is improved. Among them, in the embodiments of the present application, hotspot localization is performed on both the front and back of the chip, and a preliminary judgment on the position of the failure point on the Z-axis of the chip is made. 3D X-ray is performed before cutting the chip to obtain a judgment of the abnormal position smaller than the hotspot range. The substrate is ground and thinned before 3D X-ray to improve the failure analysis success rate and ensure the imaging quality of 3D X-ray.

[0146] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indication of the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order limit for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0147] Based on the same inventive concept, an embodiment of the present application also provides a chip failure analysis device for implementing the chip failure analysis method involved above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the chip failure analysis device provided below can refer to the limitations on the chip failure analysis method in the above text, and will not be repeated here.

[0148] In an exemplary embodiment, a chip failure analysis device is provided, including:

[0149] A chip providing module, configured to provide a stacked package chip with a failure point; the stacked package chip includes a substrate and a device layer provided on the substrate;

[0150] A hot spot positioning module, configured to perform hot spot positioning on the front and back of the stacked package chip respectively to obtain a hot spot positioning result for the failure point; wherein, the front is the side where the device layer is formed, and the back is opposite to the front;

[0151] A failure analysis module, configured to thin the substrate starting from the back based on the hot spot positioning result, and perform failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined.

[0152] In one of the embodiments, the chip providing module is configured to perform electrical analysis on the stacked package chip to obtain an electrical analysis result; and when it is determined based on the electrical analysis result that the stacked package chip has a short circuit failure, the stacked package chip is used as the stacked package chip with a failure point.

[0153] In one of the embodiments, the electrical analysis result includes an IV curve; the failure reproduction processing includes reproducing the IV curve on the substrate holes or metal lines at each stop layer.

[0154] In one of the embodiments, the stacked package chip is made based on a packaging process that matches the function of the HBM chip.

[0155] In one embodiment, the packaging process is a 3D packaging process or a 2.5D packaging process.

[0156] In one embodiment, the execution order of hotspot localization on the back side of the stacked packaged chip is before hotspot localization on the front side of the stacked packaged chip.

[0157] In one embodiment, the hotspot localization module is configured to, when a hotspot area is obtained by hotspot localization on the back side, determine the hotspot localization result as a first localization result indicating that the failure point is located in the lower part area of the stacked packaged chip; and when a hotspot area is obtained by hotspot localization on the front side, determine the hotspot localization result as a second localization result indicating that the failure point is located in the upper part area of the stacked packaged chip.

[0158] In one embodiment, the failure analysis module is configured to grind the substrate using a first grinding process based on the first localization result; the first grinding process includes grinding the substrate layer by layer; and grind the substrate using a second grinding process based on the second localization result; the second grinding process includes grinding to the substrate layer related to the failure point according to the substrate design structure.

[0159] In one embodiment, the failure analysis module is configured to, during the process of thinning the substrate until the device layer is exposed, if it is determined based on the failure recurrence process that there is an abnormal position corresponding to the hotspot area on the substrate, obtain the position information of the failure point based on the abnormal position; and during the process of thinning the substrate until the device layer is exposed, if it is determined based on the failure recurrence process that there is no abnormal position corresponding to the hotspot area on the substrate, perform a localization process for the hotspot area on the stacked packaged chip with the device layer exposed, obtain the abnormal position corresponding to the hotspot area, and obtain the position information of the failure point based on the abnormal position.

[0160] In one embodiment, the failure analysis module is configured to scan the abnormal position using an electron microscope to obtain the position information of the failure point.

[0161] In one embodiment, the failure analysis module includes:

[0162] A scanning module configured to perform X-ray scanning on the hotspot area and the corresponding die respectively to confirm the failure relationship; the failure relationship represents the corresponding relationship between the failure point and the abnormal position;

[0163] A cutting module configured to cut the stacked packaged chip based on the failure relationship to obtain the abnormal position.

[0164] In one embodiment, the scanning module is configured to scan the area near the center of the hot spot region in 3D mode using X-rays to obtain failure information, and then scan the grains in 2D mode using X-rays to obtain overall structure information; and confirm the failure location based on the package design data, the overall structure information, and the failure information, so as to determine the failure relationship based on the failure location.

[0165] Each module in the above chip failure analysis device can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in the processor of the electronic device in hardware form or be independent of it, or can be stored in the memory of the electronic device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0166] In one embodiment, an electronic device is further provided, which includes a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0167] It can be understood that the above electronic device can be a server, a terminal device, or a chip failure analysis system, which can include, but is not limited to, ATE test devices, IV test devices, etc.

[0168] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0169] In one embodiment, a computer program product is provided, which includes a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0170] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0171] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0172] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A chip failure analysis method, characterized in that: The method comprises: A stacked package chip having a failure point is provided; the stacked package chip comprises a substrate and a device layer arranged on the substrate; Performing hotspot location on the front and back sides of the stacked packaged chip respectively to obtain a hotspot location result for the failure point; wherein the front side is a side on which the device layer is formed, and the back side is opposite to the front side; Based on the hotspot positioning result, the substrate is thinned from the back side, and failure reproduction processing is performed during the thinning process until the position information of the failure point in the stacked package chip is determined; the failure reproduction processing includes reproducing the failure data of the failure point in the substrate hole or metal wire of each stop layer; the hotspot positioning result includes the hotspot area obtained by hotspot positioning, and the hotspot positioning result includes a first positioning result indicating that the failure point is located in the lower part of the stacked package chip, and a second positioning result indicating that the failure point is located in the upper part of the stacked package chip; based on the hotspot positioning result, the substrate is thinned from the back side, including: based on the first positioning result, grinding the substrate using a first grinding process; the first grinding process includes grinding the substrate layer by layer; based on the second positioning result, grinding the substrate using a second grinding process; the second grinding process includes grinding to the substrate layer related to the failure point according to the substrate design structure; The performing of failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined includes: In the process of thinning the substrate to expose the device layer, if it is determined based on the failure reproduction process that there is no abnormal position corresponding to the hot spot area on the substrate, positioning processing is performed on the stacked package chip that exposes the device layer for the hot spot area to obtain the abnormal position corresponding to the hot spot area, and the position information of the failure point is obtained based on the abnormal position; the abnormal position includes an abnormal physical position corresponding to the electrical failure; The step of performing positioning processing on the stacked package chip exposing the device layer with respect to the hot spot area to obtain the abnormal position corresponding to the hot spot area includes: Performing X-ray scanning on the hot spot area and the corresponding grains respectively to confirm the failure relationship; the failure relationship represents the corresponding relationship between the failure point and the abnormal position; Cutting the stacked package chip based on the failure relationship to obtain the abnormal position; Perform X-ray scanning on the hot spot area and the corresponding grains respectively to confirm the failure relationship, including: In the case where the X-ray is used to scan the area near the center of the hot spot area in a 3D mode to obtain failure information, the X-ray is used to scan the grain in a 2D mode to obtain overall structural information; The failure position is confirmed according to the package design data, the overall structure information and the failure information, so as to determine the failure relationship based on the failure position.

2. The method according to claim 1, characterized in that Provides stacked packaged chips with failure points, including: Performing electrical analysis on the stacked packaged chip to obtain an electrical analysis result; When it is determined based on the electrical analysis result that the stacked package chip has a short circuit failure, the stacked package chip is used as the stacked package chip with a failure point.

3. The method according to claim 2, characterized in that The electrical analysis result includes an IV curve; and the failure reproduction process includes reproducing the IV curve on a substrate hole or a metal line of each stop layer.

4. The method according to claim 1, characterized in that: The stacked package chip is manufactured based on a packaging process that matches the function of the HBM chip.

5. The method according to claim 4, characterized in that The packaging process is a 3D packaging process or a 2.5D packaging process.

6. The method according to claim 1, characterized in that The hotspot positioning on the back side of the stacked package chip is performed before the hotspot positioning on the front side of the stacked package chip.

7. The method according to any one of claims 1 to 6, characterized in that: Performing hotspot location on the front and back sides of the stacked packaged chip respectively to obtain a hotspot location result for the failure point includes: When a hot spot area is obtained by performing hot spot positioning on the back surface, the hot spot positioning result is determined as a first positioning result indicating that the failure point is located in a lower part of the stacked package chip; When a hotspot area is obtained by performing hotspot positioning on the front side, the hotspot positioning result is determined as a second positioning result indicating that the failure point is located in an upper region of the stacked package chip.

8. The method according to claim 7, characterized in that Performing failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined includes: In the process of thinning the substrate to expose the device layer, if it is determined based on the failure reproduction process that an abnormal position corresponding to the hot spot area exists on the substrate, the position information of the failure point is obtained based on the abnormal position.

9. The method according to claim 8, characterized in that Obtaining the location information of the failure point based on the abnormal location includes: The abnormal position is scanned by an electron microscope to obtain the position information of the failure point.

10. A chip failure analysis device, characterized in that: The device comprises: A chip providing module, used for providing a stacked package chip with a failure point; the stacked package chip comprises a substrate and a device layer arranged on the substrate; A hotspot positioning module, used to perform hotspot positioning on the front and back sides of the stacked packaged chip, respectively, to obtain a hotspot positioning result for the failure point; wherein the front side is a side on which the device layer is formed, and the back side is opposite to the front side; A failure analysis module, for thinning the substrate from the back side based on the hotspot positioning result, and performing failure reproduction processing during the thinning process until the position information of the failure point in the stacked package chip is determined; the failure reproduction processing includes reproducing the failure data of the failure point in the substrate hole or metal wire of each stop layer; the hotspot positioning result includes the hotspot area obtained by hotspot positioning, and the hotspot positioning result includes a first positioning result indicating that the failure point is located in the lower part of the stacked package chip, and a second positioning result indicating that the failure point is located in the upper part of the stacked package chip; the failure analysis module is used to grind the substrate using a first grinding process based on the first positioning result; the first grinding process includes grinding the substrate layer by layer; based on the second positioning result, the substrate is ground using a second grinding process; the second grinding process includes grinding to the substrate layer related to the failure point according to the substrate design structure; The failure analysis module is used to perform positioning processing on the stacked package chip exposed by the device layer for the hot spot area during the process of thinning the substrate to expose the device layer, if it is determined based on the failure reproduction processing that there is no abnormal position corresponding to the hot spot area on the substrate, to obtain the abnormal position corresponding to the hot spot area, and obtain the position information of the failure point based on the abnormal position; the abnormal position includes an abnormal physical position corresponding to the electrical failure; wherein the failure analysis module includes: a scanning module, configured to perform X-ray scanning on the hot spot area and the corresponding die respectively to confirm the failure relationship; the failure relationship indicates the corresponding relationship between the failure point and the abnormal position; wherein the scanning module is configured to scan the die in a 2D mode using X-rays to obtain overall structural information when the area near the center of the hot spot area is scanned in a 3D mode using X-rays to obtain failure information; and to confirm the failure position according to the package design data, the overall structural information and the failure information, so as to determine the failure relationship based on the failure position; A cutting module is used to cut the stacked packaged chips based on the failure relationship to obtain the abnormal position.

11. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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