Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method thereof. The electronic device includes a substrate, a buffer layer, a conductive member, a first circuit structure, an electronic component and a plurality of first connectors. The substrate has a first surface, a second surface opposite to the first surface, and a through hole, wherein an inner wall of the through hole is connected to the first surface and the second surface. The buffer layer covers the first surface, the second surface and the inner wall. The conductive piece is arranged in the through hole. The first circuit structure is disposed on the first side. The electronic component is arranged on the first circuit structure. The plurality of first connecting pieces are arranged on the second surface and are electrically connected to the electronic element through the conductive pieces and the first circuit structure. The through hole has a width W and a depth D, W / D being greater than or equal to 0.01 and less than or equal to 0.5, and a thickness T of the buffer layer being greater than or equal to 0.01 [mu] m and less than or equal to 10 [mu] m.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a manufacturing method thereof. Background Art

[0002] Although the development of electronic devices has gradually matured, there are still many problems in electronic devices that need to be improved. For example, the substrate in the electronic device has reduced structural strength due to the formation of through holes for accommodating conductive parts. In addition, the manufacturing process of electronic devices is often accompanied by thermal processes, and the mismatch in thermal expansion coefficients between the conductive parts and the substrate can easily cause cracks in the substrate or interface delamination during the heating and cooling process. Summary of the invention

[0003] The present disclosure provides an electronic device and a manufacturing method thereof, which are helpful to improve the structural strength of a substrate and reduce the generation of cracks or interface delamination on the substrate.

[0004] According to an embodiment of the present disclosure, an electronic device includes a substrate, a buffer layer, a conductive member, a first circuit structure, an electronic component, and a plurality of first connecting members. The substrate has a first surface, a second surface relative to the first surface, and a through hole, wherein the inner wall of the through hole is connected to the first surface and the second surface. The buffer layer covers the first surface, the second surface, and the inner wall. The conductive member is disposed in the through hole. The first circuit structure is disposed on the first surface. The electronic component is disposed on the first circuit structure. A plurality of first connecting members are disposed on the second surface and are electrically connected to the electronic component through the conductive member and the first circuit structure. The through hole has a width W and a depth D, W / D is greater than or equal to 0.01 and less than or equal to 0.5, and the thickness T of the buffer layer is greater than or equal to 0.01 μm and less than or equal to 10 μm.

[0005] According to an embodiment of the present disclosure, a method for manufacturing an electronic device includes: forming a through hole in a substrate, wherein an inner wall of the through hole is connected to a first surface of the substrate and a second surface of the substrate, and the second surface is opposite to the first surface; covering the first surface, the second surface and the inner wall with a buffer layer; forming a conductive member in the through hole; forming a first circuit structure on the first surface; disposing an electronic component on the first circuit structure; and forming a plurality of first connecting members on the second surface, wherein the plurality of first connecting members are electrically connected to the electronic component through the conductive member and the first circuit structure, and wherein the through hole has a width W and a depth D, W / D is greater than or equal to 0.01 and less than or equal to 0.5, and a thickness T of the buffer layer is greater than or equal to 0.01 μm and less than or equal to 10 μm.

[0006] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1Fis a partial cross-sectional schematic diagram of a manufacturing process of an electronic device according to some embodiments of the present disclosure;

[0008] Figure 2 yes Figure 1C A magnified schematic diagram of the middle region R1;

[0009] Figure 3 is a partial cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0010] Figure 4 yes Figure 3 An enlarged schematic diagram of the middle region R2;

[0011] Figure 5 as well as Figure 6 They are partial cross-sectional schematic diagrams of two electronic devices according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0013] Certain words are used throughout the specification and claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to..."

[0014] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0015] It should be understood that relative terms may be used in various embodiments, such as "lower" or "bottom" or "higher" or "top" to describe the relative relationship of one component of the drawings to another component. It is understood that if the device of the drawings is flipped upside down, the components described on the "lower" side will become components on the "higher" side. Therefore, when describing that a certain structure is set on other structures, it is only for the convenience of description and does not limit the process steps or sequence. The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered to be part of the disclosure.

[0016] A structure (or layer, component, substrate) described in the present disclosure is located on / above another structure (or layer, component, substrate), which may refer to the two structures being adjacent and directly connected, or it may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate gap) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is disposed "on" another structure, it may refer to that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0017] The terms "approximately", "substantially" or "substantially" are generally interpreted as within 10% of a given value or range, or as within 5%, 3%, 2%, 1% or 0.5% of a given value or range. In addition, the phrases "a range is from a first value to a second value", "a range is between a first value and a second value" indicate that the range includes the first value, the second value and other values ​​therebetween.

[0018] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify components. They do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claims.

[0019] The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but it is not limited to these.

[0020] In the present disclosure, the thickness, length and width can be measured by using an optical microscope (OM), and the thickness or width can be measured by using a cross-sectional image in an electron microscope, but the present disclosure is not limited thereto. The surface roughness can be measured by using a scanning electron microscope (SEM), a transmission electron microscope (TEM), etc., to observe the surface undulations at the same appropriate magnification, and the undulations can be compared per unit length (e.g., 10 μm). An appropriate magnification means that at least one surface can have at least 10 undulating peaks in the field of view at this magnification. The roughness (Rz) or average roughness (Ra) of the surface.

[0021] In addition, any two values ​​or directions used for comparison may have a certain error. In addition, the phrases "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value", or "a given range is between a first value and a second value" indicate that the given range includes the first value, the second value, and other values ​​therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0023] In the present disclosure, the electronic device may include a power device, a semiconductor packaging device, a display device, a backlight device, an antenna device, a packaging device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The display device may, for example, include liquid crystal, light-emitting diode, fluorescence, phosphor, quantum dot (quantum dot, QD), other suitable display media or a combination of the foregoing. The antenna device may, for example, include a reconfigurable surface (Reconfigurable Intelligent Surface, RIS), a frequency selective surface (Frequency Selective Surface, FSS), a radio frequency filter (RF-Filter), a polarizer (Polarizer), a resonator (Resonator) or an antenna (Antenna), etc. The antenna may be a liquid crystal type antenna or a varactor diode (Varactor Diodes) antenna. The sensing device may be a sensing device that senses capacitance, light, heat energy or ultrasound, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as known good die (KGD), capacitors, resistors, inductors, diodes, transistors, varactors, variable capacitors, filters, sensors, micro-electromechanical system components (MEMS), liquid crystal chips, semiconductor-related process structures, or semiconductor-related process structures disposed on a substrate (such as polyimide, glass, silicon substrate or other suitable substrate materials), but not limited thereto. The diode may include a light-emitting diode, a varactor diode or a photodiode. The light-emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED or a quantum dot light-emitting diode (quantum dot LED), but not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but not limited thereto. It should be noted that the electronic device may be any combination of the foregoing, but not limited thereto.The packaging device may be a packaging device suitable for wafer-level package (WLP) technology or panel-level package (WLP) technology, such as a chip first process or a chip last (chiplast / RDL first) process. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (such as including augmented reality or virtual reality), a vehicle-mounted device (such as including a car windshield) or a splicing device.

[0024] The following embodiments illustrate some implementation forms of electronic devices using packaging devices as examples, but are not limited thereto. According to the embodiments of the present disclosure, the manufacturing method of the provided electronic device can be applied, for example, to a wafer-level package (WLP) process or a panel-level package (PLP) process, and a chip first process or a chip last / RDL first process can be adopted. According to the embodiments of the present disclosure, the packaging structure of the electronic device may include a system on a chip (SoC), a system in package (SiP), an antenna in package (AiP) or a combination thereof, but is not limited thereto. According to the embodiments of the present disclosure, the electronic device can be applied to a power module, a semiconductor packaging device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto.

[0025] Figures 1A to 1F is a partial cross-sectional schematic diagram of a manufacturing process of an electronic device according to some embodiments of the present disclosure. Figure 2 yes Figure 1C Enlarged schematic diagram of the middle area R1. Figure 3 is a partial cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure. Figure 4 yes Figure 3 A magnified schematic diagram of the middle region R2. Figure 5 as well as Figure 6 They are partial cross-sectional schematic diagrams of two electronic devices according to other embodiments of the present disclosure. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0026] According to some embodiments of the present disclosure, a method for manufacturing an electronic device may include: forming a through hole 100 in a substrate 10, wherein an inner wall S3 of the through hole 100 is connected to a first surface S1 of the substrate 10 and a second surface S2 of the substrate 10, and the second surface S2 is opposite to the first surface S1 (such as Figure 1A The buffer layer 11 covers the first surface S1, the second surface S2 and the inner wall S3 (as shown); Figure 1B A conductive member 12 is formed in the through hole 100 (as shown); Figure 1C ); forming a first circuit structure 13 on the first surface S1 (as shown); Figure 1D An electronic component 14 (as shown) is arranged on the first circuit structure 13 Figure 1E ); and forming a plurality of first connectors 15 on the second surface S2, wherein the plurality of first connectors 15 are electrically connected to the electronic component 14 through the conductive member 12 and the first circuit structure 13, and wherein the through hole 100 has a width W and a depth D, W / D is greater than or equal to 0.01 and less than or equal to 0.5, and the thickness T of the buffer layer 11 is greater than or equal to 0.01 μm and less than or equal to 10 μm (as shown in FIG. Figure 1D , Figure 1E , Figure 1F and / or Figure 2 shown).

[0027] For details, please refer to Figure 1A , the manufacturing method of the electronic device may include forming a through hole 100 in a substrate 10. In some embodiments, the material of the substrate 10 may include glass, ceramic, wafer or other inorganic materials. When the substrate of the electronic device has a through hole, the energy loss caused by the leakage current can be reduced or the heating problem caused by the leakage current under high-speed operation can be improved, so that the manufactured electronic device can better meet the energy saving and carbon reduction standards.

[0028] In some embodiments, the method of forming the through hole 100 may include: irradiating a partial area of ​​the substrate 10 (such as the area indicated by the dotted line) with a laser; and removing the partial area of ​​the substrate 10 irradiated with the laser (such as the area indicated by the dotted line) with an etchant. Specifically, the area to be removed of the substrate 10 (for example, the area where the through hole 100 is to be formed, such as the area indicated by the dotted line) can be modified by laser, and then the area of ​​the substrate 10 modified by the laser can be removed by an etchant to form the through hole 100. The "modification" referred to in the present disclosure is to destroy the bonds of a local area of ​​the substrate 10 by laser or other suitable process methods, so as to weaken the structural strength of the local area. According to some embodiments, the etchant may include acid or alkaline, wherein the acidic etchant includes hydrofluoric acid and the alkaline etchant includes sodium hydroxide, but is not limited thereto.

[0029] The through hole 100 is an opening that penetrates the substrate 10, and the inner wall S3 of the through hole 100 is connected to the first surface S1 and the second surface S2 of the substrate 10. In other words, the depth D of the through hole 100 is equal to the thickness T10 of the substrate 10, wherein the thickness T10 of the substrate 10 is the maximum distance between the first surface S1 of the substrate 10 and the second surface S2 of the substrate 10 in the direction D3. According to some embodiments, the inner wall S3 may have an arc-shaped profile.

[0030] Figure 1A The schematic diagram shows seven through holes 100 arranged along the direction D1, and the cross-sectional shape of each through hole 100 is an hourglass shape. In other words, in the cross-sectional view, Figure 1A As shown in FIG. 1 , the width W of the through hole 100 decreases from the surface of the substrate 10 (such as the first surface S1 or the second surface S2) to the center of the substrate 10, that is, the through hole 100 has a minimum width, wherein the distance between the position of the minimum width and the surface of the substrate 10 (such as the first surface S1 or the second surface S2) is greater than or equal to 0.4D and less than or equal to 0.6D. However, the number of through holes 100, the arrangement of through holes 100 and / or the cross-sectional shape of through holes 100 and other design parameters can be changed according to actual needs, and are not limited to the above. Figure 1A The through holes 100 are shown as shown. For example, the cross-sectional shape of the through hole 100 may be a rectangle or other polygon. In addition, the substrate 10 may include more or fewer through holes 100, and the plurality of through holes 100 may be arranged in an array along the direction D1 and the direction D2, wherein the direction D1 and the direction D2 intersect each other and are both perpendicular to the direction D3. In some embodiments, the direction D1 and the direction D2 may be perpendicular to each other, but not limited thereto. Through the above design, the quality of electrical signal transmission of the electronic device may be improved, but not limited thereto.

[0031] In some embodiments, considering process cost, time, yield and / or structural strength of substrate 10, the ratio of depth D of through hole 100 to width W of through hole 100 (e.g., maximum width of through hole 100) is greater than or equal to 2 and less than or equal to 100, greater than or equal to 5 and less than or equal to 15, greater than or equal to 7 and less than or equal to 12, that is, 2≤D / W≤100.

[0032] Please refer to Figure 1B The method for manufacturing an electronic device may further include covering at least a portion of the first surface S1, at least a portion of the second surface S2, and at least a portion of the inner wall S3 with a buffer layer 11. That is, the buffer layer 11 may directly contact at least a portion of the first surface S1, at least a portion of the second surface S2, and at least a portion of the inner wall S3. The buffer layer 11 may be used to enhance the contact between the substrate 10 and the subsequently formed conductive member 12 (see Figure 1C), thereby improving the desorption problem between the substrate 10 and the conductive member 12. In addition, the buffer layer 11 can utilize strain to release the internal stress generated by heat or other processes, thereby improving the structural strength of the substrate 10 or reducing the generation of cracks in the substrate 10. For example, the material of the buffer layer 11 may include polyimide (PI), parylene, benzocyclobutene (BCB), epoxy, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene terephthalate (PEN), carbide, silicide, sulfide, other suitable materials or combinations thereof. According to some embodiments, the buffer layer 11 may include a single layer of material or a multilayer stack of materials, wherein the multilayer materials may be the same or different from each other.

[0033] In some embodiments, the method of forming the buffer layer 11 may include forming the material of the buffer layer 11 on the first surface S1, the second surface S2, and the inner wall S3 by chemical vapor deposition, atomic deposition (ALD), chemical plating, electroplating, liquid deposition, or other suitable process methods. For example, a first chemical vapor deposition may be performed from one side of the substrate 10 (such as the side where one of the first surface S1 and the second surface S2 is located), and then the substrate 10 is flipped, and then a second chemical vapor deposition is performed from the other side of the substrate 10 (such as the side where the other of the first surface S1 and the second surface S2 is located) to form the buffer layer 11 covering the first surface S1, the second surface S2, and the inner wall S3. Alternatively, chemical vapor deposition may be performed from a single side of the substrate 10 (such as the side where one of the first surface S1 and the second surface S2 is located) to form the buffer layer 11 covering the first surface S1, the second surface S2, and the inner wall S3. Alternatively, chemical vapor deposition may be performed simultaneously on both sides of the substrate 10 (eg, one side of the first surface S1 and the second surface S2 ) to form the buffer layer 11 covering the first surface S1 , the second surface S2 and the inner wall S3 .

[0034] In other embodiments, the method of forming the buffer layer 11 may include immersing the substrate 10 having the through hole 100 in a polymer solution. Before immersing the substrate 10 having the through hole 100 in the polymer solution, the substrate 10 may be selectively subjected to surface treatment to enhance the adhesion of the buffer layer 11 to the substrate 10 or reduce the risk of the buffer layer 11 desorbing from the substrate 10. The surface treatment may include a cleaning step, a laser irradiation step, a chemical treatment step, a heating step, other suitable steps, or a combination thereof.

[0035] In some embodiments, considering the process cost, time, yield and / or the structural strength of the substrate 10, the thickness T of the buffer layer 11 (refer to Figure 2) is greater than or equal to 0.01 μm and less than or equal to 10 μm, that is, 0.01 μm ≤ T ≤ 10 μm. The thickness T of the buffer layer 11 is measured in a direction perpendicular to the setting surface (such as the first surface S1, the second surface S2 and the inner wall S3) (or called the normal direction). Figure 2 As shown, the thickness T of the buffer layer 11 may include the thickness T1 of the buffer layer 11 covering the first surface S1, the thickness T2 of the buffer layer 11 covering the second surface S2, and the thickness T3 of the buffer layer 11 covering the inner wall S3. In some embodiments, the thickness T1 of the buffer layer 11 covering the first surface S1 and the thickness T2 of the buffer layer 11 covering the second surface S2 are greater than the thickness T3 of the buffer layer 11 covering the inner wall S3. In addition, the thickness T3 increases, for example, from the thickness center of the substrate 10 to the surface of the substrate 10 (such as the first surface S1 or the second surface S2).

[0036] In some embodiments, the ratio of the thickness T of the buffer layer 11 to the width W of the through hole 100 is greater than or equal to 0.002 and less than or equal to 0.2, that is, 0.002≤T / W≤0.2, so as to improve the structural strength of the substrate 10 and reduce the damage to the substrate 10 caused by the internal stress generated by the subsequent process. For example, when W=5μm, T is greater than or equal to 0.1μm and less than or equal to 1μm; when W=50μm, T is greater than or equal to 0.1μm and less than or equal to 5μm; when W=100μm, T is greater than or equal to 2μm and less than or equal to 10μm.

[0037] Please refer to Figure 1C , the method for manufacturing an electronic device may further include forming a conductive member 12 in the through hole 100. The conductive member 12 may be used to electrically connect a plurality of conductive structures respectively located on the first surface S1 and the second surface S2 of the substrate 10. For example, the material of the conductive member 12 may include metal, alloy, or a combination thereof, and the method for forming the conductive member 12 may include electroplating, chemical plating, atomic deposition (ALD), or a combination thereof, but is not limited thereto. In some embodiments, as Figure 1C As shown, the number of the conductive members 12 can be multiple, and the multiple conductive members 12 are respectively formed in the multiple through holes 100. For example, each through hole 100 can be provided with a corresponding conductive member 12, and the conductive member 12 can fill the space outside the buffer layer 11 in the through hole 100, but it is not limited thereto. Figure 1C For example, the conductive member 12 may include a conductive column 120, and the cross-sectional shape of the conductive column 120 may be an hourglass shape. In other words, in the cross-sectional view, Figure 2 As shown, the width W120 of the conductive pillar 120 increases gradually from the center of the thickness of the substrate 10 toward the surface of the substrate 10 (such as the first surface S1 or the second surface S2). Figure 1CAs shown, the conductive member 12 may further include a circuit 122 disposed on the first surface S1 and a circuit 124 disposed on the second surface S2, but the present invention is not limited thereto. The opposite ends of each conductive column 120 may be connected to a corresponding circuit 122 and a corresponding circuit 124, respectively.

[0038] Please refer to Figure 1D The method for manufacturing an electronic device may further include forming a first circuit structure 13 on the first surface S1. The first circuit structure 13 may also be referred to as a first redistribution structure, which may be electrically connected to other components (such as a plurality of second connectors 17) through a plurality of connectors (such as a plurality of second connectors 17). Figure 1E The first circuit structure 13 may include one or more dielectric layers and one or more conductive layers. Figure 1D In the example, two dielectric layers and two conductive layers are used, but the first circuit structure 13 may include more or fewer dielectric layers and conductive layers according to the needs. Through at least one dielectric layer and at least one conductive layer, the circuit can be re-routed and / or the circuit fan-out or fan-in area can be increased, or different electronic components can be electrically connected to each other through the rewiring structure. For example, the pitch of two adjacent contact pads at one end of the rewiring structure contacting the electronic component 14 can be less than or equal to the pitch of two adjacent contact pads at one end of the rewiring structure away from the electronic component 14, so the rewiring structure can adjust the circuit fan-out condition or electrically connect the circuit structure / electronic component with a first pitch to the circuit structure / electronic component with a second pitch, wherein the width of the contact pad at one end of the rewiring structure contacting the electronic component 14 can be less than the width of the contact pad at one end of the rewiring structure away from the electronic component 14, but it is not limited thereto. The method of forming the first circuit structure 13 may include using a photolithography etching process, a surface treatment process, a laser process, an electroplating process, a deposition process or other processes to form at least one dielectric layer and at least one conductive layer. The surface treatment process includes roughening the surface of the dielectric layer or the conductive layer to improve its adhesion.

[0039] by Figure 1DFor example, the first circuit structure 13 includes a dielectric layer IN1, a conductive layer C1, a dielectric layer IN2, and a conductive layer C2 sequentially formed on the first surface S1, but not limited thereto. The materials of the dielectric layer IN1 and the dielectric layer IN2 may include polyimide (PI), photosensitive polyimide (PSPI), polybenzoxazole (PBO), epoxy resin, polymer, Ajinomoto Build-up Film (ABF), silicon oxide, silicon nitride, or a combination thereof, but not limited thereto. Each of the conductive layer C1 and the conductive layer C2 may be a single conductive layer or a conductive stack. In addition, the materials of the conductive layer C1 and the conductive layer C2 may include metal, alloy, or a combination thereof. For example, when the conductive layer C1 and the conductive layer C2 are conductive stacks, the conductive layer may include a stack of a seed layer and a conductor layer, wherein the seed layer may increase the bonding force between a subsequent film layer and a previous film layer, or may improve the quality of subsequent film layer formation during the process, such as improving the continuity of subsequent film layers, but the present invention is not limited thereto. The material of the conductive layer may include copper, titanium, ruthenium, rubidium, tungsten, tantalum, gallium, nickel, gold, palladium, cobalt, alloys, combinations thereof, or other suitable materials, but the present invention is not limited thereto.

[0040] The dielectric layer IN1 is disposed on the buffer layer 11 and the conductive member 12 and includes a plurality of through holes TH1. Each through hole TH1 exposes a local area of ​​a corresponding circuit 122. The conductive layer C1 may be a patterned conductive layer and may include a plurality of circuits CK1 and a plurality of conductive through holes V1. The plurality of circuits CK1 may be disposed on the dielectric layer IN1. Each conductive through hole V1 is disposed in a corresponding through hole TH1. Each circuit CK1 may be electrically connected to a corresponding circuit 122 through a corresponding conductive through hole V1. The dielectric layer IN2 is disposed on the dielectric layer IN1 and the conductive layer C1 and includes a plurality of through holes TH2. Each through hole TH2 exposes a local area of ​​a corresponding circuit CK1. The conductive layer C2 may be a patterned conductive layer and may include a plurality of contact pads CK2. Each contact pad CK2 is disposed in a corresponding through hole TH2 and may selectively extend onto the dielectric layer IN2. According to some embodiments, a portion of the dielectric layer IN1 may be patterned to form a plurality of dummy pads CD, wherein in the direction D1, the spacing between two adjacent dummy pads CD is less than or equal to half of the maximum thickness TIN1 of the dielectric layer IN1 in the direction D3. The provision of the dummy pads CD may improve the alignment accuracy in the process or the bonding capability between different film layers, but is not limited thereto.

[0041] In some embodiments, the ratio of the toughness of the buffer layer 11 to the toughness of the dielectric layer (such as the dielectric layer IN1) of the first circuit structure 13 is greater than or equal to 0.1 and less than or equal to 10. In this way, the buffer layer 11 can effectively utilize strain to release the internal stress generated by heat or other processes, thereby improving the structural strength of the substrate 10 or reducing the generation of cracks in the substrate 10. In some embodiments, the toughness of the buffer layer 11 is greater than or equal to 0.1 kJ / m 2 And less than or equal to 100kJ / m 2 In this paper, the toughness of the film layer can be obtained by integrating the area under the stress-strain curve, and the stress-strain curve can be obtained by performing a tensile test on the film layer using a universal testing machine.

[0042] In some embodiments, Figure 1D as well as Figure 2 As shown, the thickness of the dielectric layer (such as the dielectric layer IN1) of the first circuit structure 13 (such as the maximum thickness TIN1 of the dielectric layer IN1 in the direction D3) may be greater than the thickness T of the buffer layer 11. In some embodiments, the thickness of the dielectric layer (such as the dielectric layer IN1) of the first circuit structure 13 (such as the maximum thickness TIN1) is greater than or equal to 5 μm and less than or equal to 25 μm, that is, 5 μm≤TIN1≤25 μm, but is not limited thereto.

[0043] In some embodiments, Figure 1D As shown, the method for manufacturing an electronic device may further include forming a plurality of second connectors 17 on the first circuit structure 13. The plurality of second connectors 17 may be electrically connected to the plurality of contact pads CK2, respectively.

[0044] In some embodiments, Figure 1D As shown, the method for manufacturing an electronic device may further include forming a second circuit structure 16 on the second surface S2. The second circuit structure 16 may also be referred to as a second redistribution structure, which may be electrically connected to other components (not shown, such as a circuit board) through a plurality of connectors (such as a plurality of first connectors 15). The second circuit structure 16 may include one or more dielectric layers and one or more conductive layers. Figure 1DIn the example, two dielectric layers and two conductive layers are used, but the second circuit structure 16 may include more or fewer dielectric layers and conductive layers as required. By means of at least one dielectric layer and at least one conductive layer, the circuit can be re-wired and / or the circuit fan-out or fan-in area can be increased, or different electronic components can be electrically connected to each other through the second circuit structure 16. For example, the pitch of two adjacent contact pads at one end of the rewiring structure contacting the circuit board may be greater than or equal to the pitch of two adjacent contact pads at one end of the rewiring structure away from the circuit board, so that the rewiring structure can adjust the circuit fan-out condition or electrically connect the circuit structure / electronic component with the first pitch to the circuit structure / electronic component with the second pitch, but is not limited thereto. The method for forming the second circuit structure 16 may refer to the aforementioned method for forming the first circuit structure 13, which will not be repeated here.

[0045] by Figure 1D For example, the second circuit structure 16 includes a dielectric layer IN3, a conductive layer C3, a dielectric layer IN4, and a conductive layer C4 formed in sequence on the second surface S2, but the present invention is not limited thereto. The materials of the dielectric layer IN3 and the dielectric layer IN4 can refer to the materials of the dielectric layer IN1 and the dielectric layer IN2, and will not be repeated here. Each of the conductive layer C3 and the conductive layer C4 can be a single conductive layer or a conductive stack. In addition, the materials of the conductive layer C3 and the conductive layer C4 can refer to the materials of the conductive layer C1 and the conductive layer C2, and will not be repeated here.

[0046] The dielectric layer IN3 is disposed on the buffer layer 11 and the conductive member 12 and includes a plurality of through holes TH3. Each through hole TH3 exposes a local area of ​​a corresponding circuit 124. The conductive layer C3 may be a patterned conductive layer and may include a plurality of circuits CK3 and a plurality of conductive through holes V3. The plurality of circuits CK3 may be disposed on the dielectric layer IN3. Each conductive through hole V3 is disposed in a corresponding through hole TH3. Each circuit CK3 may be electrically connected to a corresponding circuit 124 through a corresponding conductive through hole V3. The dielectric layer IN4 is disposed on the dielectric layer IN3 and the conductive layer C3 and includes a plurality of through holes TH4. Each through hole TH4 exposes a local area of ​​a corresponding circuit CK3. The conductive layer C4 may be a patterned conductive layer and may include a plurality of contact pads CK4. Each contact pad CK4 is disposed in a corresponding through hole TH4 and may selectively extend to the dielectric layer IN4.

[0047] The method for manufacturing an electronic device may further include forming a plurality of first connecting members 15 on the second surface S2. Figure 1DFor example, the plurality of first connectors 15 can be electrically connected to the plurality of contact pads CK4, respectively, and the pitch P15 of the plurality of first connectors 15 is, for example, greater than the pitch P17 of the plurality of second connectors 17. Specifically, the pitch P15 of the plurality of first connectors 15 corresponds to the pitch of two adjacent contact pads CK4 at one end of the second circuit structure 16 contacting the unillustrated circuit board, and the pitch P17 of the plurality of second connectors 17 corresponds to the pitch of two adjacent contact pads CK2 at one end of the first circuit structure 13 contacting the electronic component 14. By adjusting the circuit fan-out condition through the first circuit structure 13, the conductive member 12, and the second circuit structure 16, circuit structures / electronic components with different pitches (such as the electronic component 14 and the unillustrated circuit board) can be electrically connected.

[0048] Please refer to Figure 1E The method for manufacturing an electronic device may further include arranging an electronic component 14 on the first circuit structure 13, wherein a plurality of first connectors 15 may be electrically connected to the electronic component 14 through a second circuit structure 16, a conductive member 12, the first circuit structure 13, and a plurality of second connectors 17. The electronic component 14 may be a digital chip, an analog chip, a mixed signal chip, a logic chip, a sensor chip, a structure of semiconductor-related processes, or a structure of semiconductor-related processes disposed on a substrate (e.g., polyimide, glass, silicon substrate, or other suitable substrate material) or other types of integrated circuit chips, or a combination thereof.

[0049] In some embodiments, the electronic component 14 can be transferred to the first circuit structure 13 by a pick and place (PnP) process, and the plurality of pads 140 of the electronic component 14 can be bonded to the plurality of second connectors 17. In other embodiments, although not shown in FIG. Figure 1E , multiple electronic components can be transferred to the first circuit structure 13 and bonded to the first circuit structure 13. The multiple electronic components may include multiple electronic components with different design parameters such as purpose, size, type, shape, number of pads and / or pad pitch, but are not limited thereto.

[0050] In some embodiments, the method for manufacturing an electronic device may further include forming an underfill 18 between the first circuit structure 13 and the electronic component 14 , wherein the underfill 18 surrounds the plurality of second connectors 17 to protect the plurality of second connectors 17 or enhance adhesion between the first circuit structure 13 and the electronic component 14 .

[0051] Please refer to Figure 1F, the method for manufacturing an electronic device may further include forming a packaging layer 19 on the first circuit structure 13, the bottom filler 18 and the electronic component 14. The material of the packaging layer 19 includes, for example, a molding compound, a resin (such as an epoxy resin), a polymer or a combination thereof, but is not limited thereto. In some embodiments, although not shown, the packaging layer 19 may be thinned by a planarization process to expose a surface of the electronic component 14 away from the substrate 10. This design may improve the heat dissipation capacity of the electronic device, but is not limited thereto. The planarization process may include a mechanical grinding process, a chemical mechanical polishing (CMP) process or a combination thereof.

[0052] It should be understood that Figures 1A to 1F This is just a schematic diagram of one manufacturing process of the electronic device 1. However, the manufacturing process of the electronic device 1 is not limited thereto. For example, the manufacturing sequence, the number of components / film layers, the arrangement of components, or the electrical connection method, etc., can be changed according to actual needs. For example, the plurality of first connectors 15 can be formed after the packaging layer 19 is formed, but this is not limited thereto.

[0053] In completion Figures 1A to 1F After the steps shown, the production of the electronic device 1 is preliminarily completed. According to some embodiments of the present disclosure, the electronic device 1 may include a substrate 10, a buffer layer 11, a conductive member 12, a first circuit structure 13, an electronic component 14 and a plurality of first connecting members 15. The substrate 10 has a first surface S1, a second surface S2 relative to the first surface S1 and a through hole 100, wherein an inner wall S3 of the through hole 100 is connected to the first surface S1 and the second surface S2. The buffer layer 11 covers the first surface S1, the second surface S2 and the inner wall S3. The conductive member 12 is disposed in the through hole 100. The first circuit structure 13 is disposed on the first surface S1. The electronic component 14 is disposed on the first circuit structure 13. A plurality of first connecting members 15 are disposed on the second surface S2 and are electrically connected to the electronic component 14 through the conductive member 12 and the first circuit structure 13. The through hole 100 has a width W and a depth D, W / D is greater than or equal to 0.01 and less than or equal to 0.5, and the thickness T of the buffer layer 11 is greater than or equal to 0.01 μm and less than or equal to 10 μm. According to some embodiments, the average surface roughness of the inner wall S3 may be between 0.01 and 1.2 μm. Through the above design, the bonding force between the subsequent film layer and the inner wall S3 can be improved.

[0054] In some embodiments, as described above, T / W may be greater than or equal to 0.002 and less than or equal to 0.2. In some embodiments, as described above, the electronic device 1 may further selectively include a second circuit structure 16, which is disposed on the second surface S2 and is located between the substrate 10 and the plurality of first connectors 15. In some embodiments, the electronic component 14 may be electrically connected to the second circuit structure 16 via the conductive member 12 and the first circuit structure 13. In some embodiments, as described above, the electronic device 1 may further selectively include a plurality of second connectors 17, wherein the electronic component 14 is electrically connected to the first circuit structure 13 via the plurality of second connectors 17, and the pitch P15 (refer to Figure 1D ) is, for example, greater than the pitch P17 of the plurality of second connecting members 17 (refer to Figure 1D In some embodiments, as described above, the ratio of the toughness of the buffer layer 11 to the toughness of the dielectric layer IN1 of the first circuit structure 13 may be greater than or equal to 0.1 and less than or equal to 10. In some embodiments, the toughness of the buffer layer 11 may be greater than or equal to 0.1 kJ / m 2 And less than or equal to 100kJ / m 2 In some embodiments, as described above, the thickness of the dielectric layer IN1 of the first circuit structure 13 (eg, the maximum thickness TIN1, see Figure 1D ) may be greater than the thickness T of the buffer layer 11 (refer to Figure 2 In some embodiments, the thickness of the dielectric layer IN1 of the first circuit structure 13 (eg, the maximum thickness TIN1, see Figure 1D ) may be greater than or equal to 5 μm and less than or equal to 25 μm. In some embodiments, the conductive member 12 may fill up the space in the through hole 100 other than the buffer layer 11 .

[0055] Please refer to Figure 3 as well as Figure 4 , the electronic device 1A and Figure 1F and Figure 2The main differences of the electronic device 1 shown are described as follows. In the electronic device 1A, according to some embodiments, the conductive element 12A is a conformal layer extending from the inner wall S3 to the first surface S1 and the second surface S2. Alternatively, according to some embodiments, a partial conductive element 12A of one of the first surface S1 or the second surface S2 may be formed first, and then a partial conductive element 12A of the other may be formed, so that the two are connected to form the final conductive element 12A. The thickness of the conductive element 12A on the first surface S1 or the second surface S2 (such as thickness T122 or thickness T124) is greater than the thickness of the buffer layer 11 covering the first surface S1 or the second surface S2 (such as thickness T1 or thickness T2), and the thickness of the buffer layer 11 covering the first surface S1 or the second surface S2 (such as thickness T1 or thickness T2) is greater than the thickness of the buffer layer 11 covering the inner wall S2 (such as thickness T3). Specifically, the conductive member 12A includes, for example, a circuit 122, a circuit 124 and a connecting line 126, wherein the circuit 122, the circuit 124 and the connecting line 126 are respectively arranged on the first surface S1, the second surface S2 and the inner wall S3, and the connecting line 126 is electrically connected to a corresponding circuit 122 and a corresponding circuit 124. The thickness of the conductive member 12A on the first surface S1 is the thickness T122 of the circuit 122, and the thickness of the conductive member 12A on the second surface S2 is the thickness T124 of the circuit 124. Based on considerations such as electrical transmission capability or reliability, the thickness T122 and / or the thickness T124 may be greater than the thickness T1 and / or the thickness T2. In addition, depending on the manufacturing method adopted, the thickness T1 and / or the thickness T2 may be greater than the thickness T3. Similarly, the thickness T122 and / or the thickness T124 may be greater than the thickness T126 of the connecting line 126. In some embodiments, as Figure 4 As shown, the thickness T126 of the connection line 126 may increase gradually from the thickness center of the substrate 10 toward the surface of the substrate 10 (eg, the first surface S1 or the second surface S2 ).

[0056] In some embodiments, the electronic device 1A may further include a dielectric layer 20, and the dielectric layer 20 may fill the space in the through hole 100 other than the buffer layer 11 and the conductive member 12A. In other words, the gap in the through hole 100 not occupied by the buffer layer 11 and the conductive member 12A may be filled by the dielectric layer 20. In some embodiments, the dissipation factor (Df) of the dielectric layer 20 may be less than 0.01 at an operating frequency of 10 MHz, so as to improve the electrical insulation capability of the substrate 10, thereby reducing the energy loss caused by the leakage current or improving the heating problem caused by the leakage current under high-speed operation.

[0057] Please refer to Figure 5 , the electronic device 1B and Figure 1FThe main differences of the electronic device 1 shown are described as follows. In the electronic device 1B, the cross-sectional shape of the conductive column 120 is rectangular. In addition, the electronic device 1B also includes a component integration layer 21, which is disposed between the substrate 10 and the first circuit structure 13B and includes another electronic component (such as an electronic component 210), and the other electronic component (such as the electronic component 210) is electrically connected to the electronic component 14 through the first circuit structure 13B. According to different requirements, the electronic component 210 may include an active component, a passive component, or a combination of the above. For example, the electronic component 210 may include an integrated passive device (IPD), a transistor, or a combination of the above, but is not limited thereto. In some embodiments, the component integration layer 21 may also include a dielectric layer IN5, and the electronic component 210 is located in the dielectric layer IN5. The dielectric layer IN5 may be a single layer or a composite layer, wherein when the dielectric layer IN5 is a composite layer (e.g., n layers), the total thickness TIN5 of the dielectric layer IN5 divided by n is, for example, less than or equal to the maximum thickness TIN1 of the dielectric layer IN1 in the direction D3. The material and other designs of the dielectric layer IN5 may refer to the description of the dielectric layer IN1 above, but the material of the dielectric layer IN5 may be different from the material of the dielectric layer IN1, which will not be repeated here. In some embodiments, Figure 5 As shown, the first circuit structure 13B may include a conductive layer C5 in addition to the dielectric layer IN1, the conductive layer C1, the dielectric layer IN2 and the conductive layer C2. The conductive layer C5 is disposed on the dielectric layer IN5 and may be a patterned conductive layer. For example, the conductive layer C5 may include a plurality of circuits CK5. At least one circuit CK5 may be electrically connected to the electronic component 210. The dielectric layer IN1 is disposed on the dielectric layer IN5 and the conductive layer C5 and each through hole TH1 exposes a local area of ​​a corresponding circuit CK5. Each circuit CK1 may be electrically connected to a corresponding circuit CK5 through a corresponding conductive through hole V1.

[0058] In some embodiments, Figure 5As shown, the electronic device 1B may also include a conductive through-hole substrate U, a bottom filler 18B, a packaging layer 19B and a plurality of third connectors 15B, but is not limited thereto. The conductive through-hole substrate U may be electrically connected to the second circuit structure 16 through a plurality of first connectors 15. The bottom filler 18B surrounds the plurality of first connectors 15 to protect the plurality of first connectors 15 or enhance the adhesion between the second circuit structure 16 and the conductive through-hole substrate U. The packaging layer 19B is disposed on the conductive through-hole substrate U and the bottom filler 18B and may surround the packaging layer 19, the substrate 10 and the second circuit structure 16. The material of the packaging layer 19B may refer to the material of the packaging layer 19, and will not be repeated here. The conductive through-hole substrate U may include a substrate 10B and a conductive member 12B, wherein the materials, manufacturing methods and / or relative arrangement relationships of the substrate 10B and the conductive member 12B may refer to the relevant descriptions of the substrate 10 and the conductive member 12, and will not be repeated here. In some embodiments, the conductive member 12B may include a plurality of circuits 122B and a plurality of circuits 124B, wherein the plurality of circuits 122B and the plurality of circuits 124B are respectively disposed on opposite surfaces of the substrate 10B. The plurality of circuits 122B may be respectively electrically connected to the plurality of first connectors 15, and the plurality of circuits 124B may be respectively electrically connected to the plurality of third connectors 15B.

[0059] Please refer to Figure 6 , the electronic device 1C and Figure 1FThe main differences of the electronic device 1 shown are described as follows. In the electronic device 1C, the conductive member 12C includes a conductive column 120 and does not include the aforementioned circuit 122 and circuit 124. The substrate 10C also includes a blind hole 102, and the electronic device 1C also includes another electronic component (such as an electronic component 22), which is disposed in the blind hole 102 and electrically connected to the electronic component 14 through the first circuit structure 13C. The electronic component 22 can be a connector or other types of electronic components, which are not limited here. In some embodiments, the electronic device 1C may also include an adhesive layer 23, a conductive member 24, and a filling layer 25. The electronic component 22 may be fixed in the blind hole 102 by the adhesive layer 23. The adhesive layer 23 includes, for example, a die attach film (Die Attach Film, DAF), polyimide, photosensitive polyimide, optical clear adhesive (Optical Clear Adhesive, OCA) or optical clear resin (Optical Clear Resin, OCR), but is not limited thereto. The electronic component 22 can be electrically connected to the first circuit structure 13C through the conductive member 24. The conductive member 24 includes, for example, a conductive bump or other conductive medium. The filling layer 25 can fill the space in the blind hole 102 that is not occupied by the electronic component 22, the adhesive layer 23, and the conductive member 24, and the filling layer 25 can expose one end of the conductive member 24 to be connected to the first circuit structure 13C. The material of the filling layer 25 may include a bottom filler or other insulating filling material. In some embodiments, the top surface of the conductive member 24 and the top surface of the filling layer 25 may be flush or at the same height, but is not limited thereto.

[0060] The first circuit structure 13C may further include a dielectric layer IN6 and a conductive layer C6 in addition to the dielectric layer IN1, the conductive layer C1, the dielectric layer IN2 and the conductive layer C2, and the dielectric layer IN6, the conductive layer C6, the dielectric layer IN1, the conductive layer C1, the dielectric layer IN2 and the conductive layer C2 are, for example, sequentially formed above the first surface S1. The materials of the dielectric layer IN6 and the conductive layer C6 may refer to the description of the dielectric layer IN1 and the conductive layer C1, and will not be repeated here. In addition, the electronic device 1C may further include a solder resist layer 26 covering the first circuit structure 13C. The solder resist layer 26 exposes a plurality of contact pads CK2, so as to facilitate the formation of a plurality of second connectors 17 on the plurality of contact pads CK2. In the electronic device 1C, the electronic component 14 is, for example, an electronic integrated circuit (EIC), and the electronic device 1C may further include an electronic component 27 and an optical fiber 28. A plurality of pads 270 of the electronic component 27 may be bonded to the plurality of contact pads CK2 through a plurality of second connectors 17. The electronic component 27 is, for example, a photonic integrated circuit (PIC), and the electronic component 27 is optically coupled to the optical fiber 28. For example, the optical fiber 28 may be embedded in the packaging layer 19 and the end of the optical fiber 28 may be connected to the electronic component 27, but the present invention is not limited thereto. Other optical coupling methods between the electronic component 27 and the optical fiber 28 are also included in the protection scope of the present disclosure.

[0061] The second circuit structure 16C may further include a dielectric layer IN7 in addition to the dielectric layer IN3, the conductive layer C3, the dielectric layer IN4, and the conductive layer C4, and the dielectric layer IN3, the conductive layer C3, the dielectric layer IN4, the conductive layer C4, and the dielectric layer IN7 are, for example, sequentially formed above the second surface S2. The material of the dielectric layer IN7 can refer to the description of the dielectric layer IN3, which will not be repeated here. In addition, the electronic device 1C may further include a solder resist layer 29 covering the second circuit structure 16C. The solder resist layer 29 exposes a plurality of contact pads CK4, so as to facilitate the formation of a plurality of first connectors 15 on the plurality of contact pads CK4.

[0062] In summary, in the embodiments disclosed herein, the structural strength of the substrate can be improved and cracks or interface delamination of the substrate can be reduced by providing a buffer layer and / or designing W / D or the thickness T of the buffer layer.

[0063] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0064] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure, and the features between the embodiments can be arbitrarily mixed and replaced with each other to form other new embodiments. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment. The scope of protection of the present disclosure shall be determined by the attached claims.

Claims

1. An electronic device, characterized in that: include: A substrate having a first surface, a second surface opposite to the first surface, and a through hole, wherein an inner wall of the through hole is connected to the first surface and the second surface; a buffer layer, covering the first surface, the second surface and the inner wall; A conductive member, disposed in the through hole; A first circuit structure, disposed on the first surface; an electronic component, disposed on the first circuit structure; as well as a plurality of first connecting members, disposed on the second surface and electrically connected to the electronic component through the conductive member and the first circuit structure, The through hole has a width W and a depth D, W / D is greater than or equal to 0.01 and less than or equal to 0.5, and the thickness T of the buffer layer is greater than or equal to 0.01 μm and less than or equal to 10 μm.

2. The electronic device according to claim 1, characterized in that: T / W is greater than or equal to 0.002 and less than or equal to 0.

2.

3. The electronic device according to claim 1, characterized in that: Also includes: The second circuit structure is disposed on the second surface and located between the substrate and the plurality of first connecting members.

4. The electronic device according to claim 3, characterized in that: The electronic component is electrically connected to the second circuit structure through the conductive member and the first circuit structure.

5. The electronic device according to claim 3, characterized in that: Also includes: A plurality of second connectors, wherein the electronic component is electrically connected to the first circuit structure through the plurality of second connectors, and a pitch between two adjacent first connectors in the plurality of first connectors is greater than a pitch between two adjacent second connectors in the plurality of second connectors.

6. The electronic device according to claim 1, characterized in that: A ratio of the toughness of the buffer layer to the toughness of the dielectric layer of the first circuit structure is greater than or equal to 0.1 and less than or equal to 10.

7. The electronic device according to claim 1, characterized in that: The toughness of the buffer layer is greater than or equal to 0.1 kJ / m 2 And less than or equal to 100kJ / m 2 .

8. The electronic device according to claim 1, characterized in that: The thickness of the dielectric layer of the first circuit structure is greater than the thickness of the buffer layer.

9. The electronic device according to claim 8, characterized in that: The thickness of the dielectric layer of the first circuit structure is greater than or equal to 5 μm and less than or equal to 25 μm.

10. The electronic device according to claim 1, characterized in that: The conductive member fills up the space in the through hole outside the buffer layer.

11. The electronic device according to claim 1, characterized in that: The thickness of the conductive element on the first surface or the second surface is greater than the thickness of the buffer layer covering the first surface or the second surface, and the thickness of the buffer layer covering the first surface or the second surface is greater than the thickness of the buffer layer covering the inner wall.

12. The electronic device according to claim 11, characterized in that: Also includes: The dielectric layer fills the space in the through hole other than the buffer layer and the conductive member.

13. The electronic device according to claim 12, characterized in that: The dissipation coefficient of the dielectric layer is less than 0.

01.

14. The electronic device according to claim 1, characterized in that: Also includes: The component integration layer is disposed between the substrate and the first circuit structure and includes another electronic component, and the other electronic component is electrically connected to the electronic component through the first circuit structure.

15. The electronic device according to claim 1, characterized in that: The substrate further comprises a blind hole, and the electronic device further comprises: Another electronic component is disposed in the blind hole and is electrically connected to the electronic component through the first circuit structure.

16. The electronic device according to claim 1, characterized in that: The material of the substrate includes glass or ceramic.

17. A method for manufacturing an electronic device, characterized in that: include: forming a through hole in the substrate, wherein an inner wall of the through hole is connected to a first surface of the substrate and a second surface of the substrate, and the second surface is opposite to the first surface; Covering the first surface, the second surface and the inner wall with a buffer layer; forming a conductive member in the through hole; forming a first circuit structure on the first surface; Disposing an electronic component on the first circuit structure; as well as A plurality of first connectors are formed on the second surface, wherein the plurality of first connectors are electrically connected to the electronic component through the conductive member and the first circuit structure, and wherein the through hole has a width W and a depth D, W / D is greater than or equal to 0.01 and less than or equal to 0.5, and a thickness T of the buffer layer is greater than or equal to 0.01 μm and less than or equal to 10 μm.

18. The method for manufacturing an electronic device according to claim 17, wherein: The method of forming the through hole comprises: irradiating a partial area of ​​the substrate with laser; and The portion of the substrate irradiated with the laser is removed by using an etchant.

19. The method for manufacturing an electronic device according to claim 17, wherein: The method of forming the buffer layer includes forming the material of the buffer layer on the first surface, the second surface and the inner wall by a chemical vapor deposition process.

20. The method for manufacturing an electronic device according to claim 17, wherein: The method of forming the buffer layer includes immersing the substrate having the through hole formed therein in a polymer solution.

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