Digital array antenna and digital circuit synchronization method, device, equipment and medium

Abstract

The present application relates to a digital array antenna and a method, device, equipment, and medium for synchronizing a digital circuit. The method for synchronizing the digital array antenna and the digital circuit includes: performing module preprocessing on a master module and a slave module, where the module preprocessing includes configuring FPGA codes and initializing radio frequency transceivers for the master module and the slave module; the master module triggers a module handshake request to the slave module and obtains the signal reception status of the slave module according to the module handshake request; the master module sends a synchronization trigger signal to trigger a synchronization pulse generator to generate a synchronization pulse signal, and the master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceivers through the first pulse of the clock signal and the synchronization pulse signal; the master module and all slave modules perform sampling clock synchronization, digital clock synchronization, and interface synchronization of an A / D converter and a D / A converter through the second pulse of the clock signal and the synchronization pulse signal to complete the synchronization. The present application has the effect of being able to synchronize the digital array antenna and the digital circuit.

Description

Technical Field

[0001] This application relates to the technical field of antenna and digital circuit synchronization, and particularly to a digital array antenna and a method, device, equipment, and medium for synchronizing a digital circuit. Background Art

[0002] Currently, a digital array antenna that can generate multiple beams is an essential device for mobile direct connection and Internet communication satellites. Among them, the multi-beam forming system is the key of the digital array antenna. It has two main functions: one is to convert the radio frequency signals received by each element of the array antenna into digital signals, perform the formation of multiple receiving beams on them, generate the digital baseband signals received by each beam, and transmit them to the communication device, thus completing multi-beam reception; the other is to receive the digital baseband signals of each beam from the communication device, perform the formation of multiple transmitting beams on them, generate the digital signals corresponding to each element of the array antenna, then convert the digital signals into radio frequency transmission signals, and transmit them to each element of the array antenna, thus realizing multi-beam transmission.

[0003] Low-Earth orbit communication satellites applied in the commercial space field are restricted by cost, volume, weight, and power consumption, and require the product to be as miniaturized and lightweight as possible. The array signal processing in a digital array antenna requires a large number of radio frequency receiving channels, transmitting channels, local oscillator frequency synthesizers, A / D converters, D / A converters, large-bandwidth interface circuits, resource-rich processing circuits, and complex synchronization circuits. It is a complex system integrating large-scale, distributed, radio frequency circuits and digital circuits, with high-speed operation and transmission. This requires simplifying the circuit design as much as possible, compressing the circuit scale, and preferably using large-scale integrated circuits and system-on-chip (SoC), and finally realizing an integrated, miniaturized, and distributed on-board digital array antenna multi-beam forming system.

[0004] The digital array antenna multi-beam forming system is a phase fully coherent system. To ensure that the received signals and the transmitted signals are aligned in time and fully coherent in phase, it is necessary to ensure the phase synchronization between the mixing local oscillator signals of all receiving channels, the phase synchronization between the mixing local oscillator signals of all transmitting channels, the sampling clock synchronization of all A / D converters, the sampling clock synchronization of all D / A converters, all digital signal processing clocks (i.e., digital clocks), and all high-speed digital interfaces.

[0005] The invention patent with the patent number CN109194360A discloses a 16-channel digital multi-beam transceiver front-end component, which generates a local oscillator signal using the same reference clock, and then uses a power divider and an amplifier circuit to convert one local oscillator signal into 16 signals, respectively providing a fully coherent local oscillator source for the mixers of 16 receiving channels. This solution is suitable for the situation where the number of array antenna elements is small and the local oscillator frequency synthesizer and the transceiver channels can be integrated into one module. When the number of array antenna elements is large, the scale of the above-mentioned power division and amplification circuit and its interconnection cables with the receiving channels will be too large to be acceptable.

[0006] The invention patent with the patent number CN109683137A discloses a multi-channel synchronization method applied to a phased array radar. The patent discloses a digital multi-channel system with a high sampling frequency, which consists of a common component and multiple digital components. The common component generates the power supply, clock, common signal, and synchronization trigger signal required by the digital components. The common signal and the clock signal need to be strictly synchronized, that is, the transmission paths of the signals to each digital component should be of equal length, and there is no strict requirement for the trigger signal. The digital components mainly consist of an A / D converter, a D / A converter, and an FPGA. The A / D converter, D / A converter, and FPGA are connected through a JESD204B high-speed serial port. To achieve the sampling clock synchronization of the A / D converter and D / A converter and the JESD204B serial port synchronization between different digital components, it is necessary to provide a strictly synchronized clock signal and synchronization pulse signal for all digital components. The method disclosed in this patent is as follows: The common component generates a clock signal, a common signal, and a trigger signal that does not require strict synchronization among all digital components. The common signal is a pulse signal with an initial high level. The common component generates a trigger signal at its first falling edge. The trigger signal is a pulse signal with an active high level, and its pulse width is much smaller than that of the common signal. The clock signal and the common signal transmitted from the common component to each digital component in the system are strictly of equal length, and the transmission delays are consistent. There is no requirement for the trigger signal to be of equal length, and the transmission delays can be different. In each digital component, the FPGA latches the level of the trigger signal at the rising edge of the first clock signal after the first falling edge of the common signal, and generates a synchronization pulse signal at the rising edge of the first clock signal after the second falling edge of the common signal. If the difference between the maximum transmission delay and the minimum transmission delay of the trigger signal from the common component to each digital component is less than the pulse width of a common signal, the synchronization pulse signals generated by each digital component can ensure strict synchronization. This patent discloses a method for achieving synchronization among digital components, but does not disclose how to maintain strict synchronization among multiple A / D converters, D / A converters, and FPGAs inside each digital component. In fact, the synchronization pulse signal generated by the FPGA needs to regenerate multiple synchronization pulse signals and distribute them to all A / D converters and D / A converters inside the digital component. If the FPGA generates multiple synchronization pulse signals, the signal path inside the FPGA is different, and the transmission delay is also different. Moreover, each time the code of the FPGA is recompiled and synthesized, it is difficult to ensure that the transmission delays between code versions are all consistent. Therefore, it is difficult to ensure the necessary synchronization relationship between each synchronization pulse and the clock signal, which greatly increases the difficulty of system synchronization. In addition, when the number of digital components is large, the interconnection signal resources between the common component and each digital component are limited and very precious, and the number of unnecessary signals transmitted between components should be minimized as much as possible. The method disclosed in this patent requires a dedicated trigger signal, which increases the burden of system interconnection.

[0007] Therefore, a synchronization method for radio frequency local oscillator synchronization, A / D converter and D / A converter sampling clock synchronization, digital clock synchronization, and high-speed digital interface synchronization of a miniaturized and distributed spaceborne digital array antenna multi-beamforming system is required. Summary of the Invention

[0008] In order to synchronize a digital array antenna and a digital circuit, the present application provides a synchronization method, device, equipment, and medium for a digital array antenna and a digital circuit.

[0009] The first above-mentioned inventive object of the present application is achieved through the following technical solutions:

[0010] A synchronization method for a digital array antenna and a digital circuit, including a backplane and a main module and several slave modules connected to the backplane, the synchronization method for the digital array antenna and the digital circuit includes:

[0011] Perform module preprocessing on the main module and the slave modules, where the module preprocessing includes configuring FPGA code and initializing radio frequency transceivers for the main module and the slave modules;

[0012] The main module triggers a module handshake request to the slave modules, and obtains the signal reception status of the slave modules according to the module handshake request;

[0013] The main module sends a synchronization trigger signal to trigger a synchronization pulse generator to generate a synchronization pulse signal, and the main module and all the slave modules perform radio frequency transceiver local oscillator phase synchronization through the first pulse of the clock signal and the synchronization pulse signal;

[0014] The main module and all the slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization, and interface synchronization through the second pulse of the clock signal and the synchronization pulse signal to complete the synchronization.

[0015] By adopting the above technical solution, first, through module preprocessing of the master module and slave modules, it is ensured that each module can correctly configure the FPGA code and initialize the radio frequency transceiver when starting up. This preprocessing step lays the foundation for subsequent synchronization operations, ensuring that all modules are in the same initial state, thus reducing the risk of synchronization failure caused by inconsistent initial states. Secondly, the master module triggers a module handshake request to the slave modules to obtain the signal reception status of the slave modules. This process is implemented through a serial bus interface, ensuring that the master module can accurately understand the status of each slave module. Specifically, the master module will send a clock signal handshake request and a synchronization pulse handshake request, and these two requests are combined into a module handshake request. After receiving these requests, the slave modules will feedback their own clock signal reception status and synchronization pulse reception status. After the master module collects this status information, it can determine which slave modules are ready to receive the synchronization signal and which ones need further adjustment. This step effectively avoids the overall synchronization failure caused by some modules not being ready during the synchronization process and improves the reliability of the system. Then, the master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. This synchronization pulse signal is one of the core signals for system synchronization, and it is used to ensure that all modules start to perform synchronization operations at the same moment. The master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceiver through the first pulse of the clock signal and the synchronization pulse signal. In this process, the role of the synchronization pulse signal is to provide an accurate time reference, so that the mixing local oscillator signals of all radio frequency transceivers can reach the same phase at the same moment. In this way, it is ensured that all radio frequency transceivers remain fully coherent when receiving and transmitting signals, which is crucial for multi-beamforming. Subsequently, the master module and all slave modules perform sampling clock synchronization, digital clock synchronization, and interface synchronization of the A / D converter and D / A converter through the second pulse of the clock signal and the synchronization pulse signal. In this step, the second pulse of the clock signal and the synchronization pulse signal are used to calibrate the sampling clocks of the A / D converters and D / A converters in each module to ensure that they sample at the same moment. At the same time, digital clock synchronization is also performed to ensure that the digital signal processing circuits in all modules operate at the same time point. Finally, the synchronization of the JESD204B interface is completed. This is an important interface for data transmission between the radio frequency transceiver and the FPGA, ensuring that there are no timing errors during data transmission. During the entire synchronization process, by adjusting the transmission delays of the internal clock distributors and synchronization pulse distributors in each module, it is ensured that there is a fixed timing relationship between the clock rising edges and the synchronization pulses among all modules. This method not only simplifies the hardware design, reduces the difficulty of printed circuit board wiring, but also improves the stability and reliability of the system.In this way, the present invention successfully solves the problems existing in the prior art, such as the large variety of synchronization signals and the tight interconnection signal resources, and realizes the efficient synchronization of the high-integration, miniaturized, and distributed spaceborne digital array antenna multi-beam forming system.

[0016] In a preferred example, this application can be further configured as follows: the master module triggers a module handshake request to the slave module, and obtains the signal reception status of the slave module according to the module handshake request. Specifically, it includes:

[0017] The master module triggers a clock signal handshake request and a synchronization pulse handshake request, and combines the clock signal handshake request and the synchronization pulse signal handshake request to form the module handshake request;

[0018] Obtain the clock signal reception status and the synchronization pulse reception status from each of the slave modules, and combine the clock signal reception status and the synchronization pulse reception status to form the signal reception status and send it to the master module.

[0019] By adopting the above technical solution, the master module can perform handshake operations with the slave modules efficiently and accurately, ensuring the reliability of system synchronization. The master module first triggers a clock signal handshake request and a synchronization pulse handshake request, and these two requests are combined into a module handshake request. This process ensures that the master module can actively initiate a synchronization request at the initial stage of system startup, avoiding synchronization failures caused by the failure of the slave modules to respond in time. Obtain the clock signal reception status and the synchronization pulse reception status from each slave module, and combine these two statuses to form the signal reception status and send it back to the master module. This step is crucial because it not only verifies that the slave module has successfully received the clock signal and the synchronization pulse signal, but also provides the basic data for subsequent synchronization operations. Through the above handshake process, the master module can confirm that all slave modules are ready to receive and process the clock signal and the synchronization pulse signal. This step eliminates the time deviation problem caused by inconsistent signal transmission paths, ensures that all modules start synchronization operations at the same moment, and improves the overall synchronization accuracy of the system. The board-level management controller (BMC) realizes the handshake and control information interaction between modules through a serial bus interface. This design reduces the number of internal signal lines of the system, reduces the wiring difficulty, and also improves the reliability and stability of the system. Each clock signal and synchronization pulse signal can be independently coarsely and finely adjusted for transmission delay, and equal-length wiring of printed circuit boards is not required. This feature enables the system to more flexibly cope with various environmental changes in practical applications, further enhancing the adaptability of the system. By dividing the multi-beam transceiver processing module into a master module and a slave module, the difference between the two modules is only that the master module needs to provide the clock signal and the synchronization pulse signal. This design not only simplifies the system architecture, but also facilitates production and maintenance, and reduces costs.

[0020] In a preferred example, the present application can be further configured as follows: the master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceiver through the first pulse of the clock signal and the synchronization pulse signal. Specifically, it includes:

[0021] Receive the clock signal and the synchronization pulse signal sent by the master module through the backplane.

[0022] By adopting the above technical solution, the master module and all slave modules can receive the clock signal and the synchronization pulse signal sent by the master module through the backplane, ensuring that the clock signal and the synchronization pulse signal received by each module are consistent in time and phase, so as to achieve precise synchronization of the local oscillator phase of the radio frequency transceiver. This synchronization mechanism reduces the delay difference caused by unequal signal transmission paths and improves the stability and reliability of the system.

[0023] In a preferred example, the present application can be further configured as follows: the master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceiver through the first pulse of the clock signal and the synchronization pulse signal. Specifically, it includes:

[0024] Obtain the signal establishment time and the signal duration corresponding to the synchronization pulse signal and the clock signal;

[0025] Obtain the timing relationship between the rising edges of the synchronization pulse signal and the clock signal according to the signal establishment time and the signal duration, and perform local oscillator phase synchronization according to the timing relationship.

[0026] By adopting the above technical solution, after the master module sends a synchronous trigger signal, it triggers the synchronous pulse generator to generate a synchronous pulse signal. At this time, the master module and all slave modules first receive the clock signal and the synchronous pulse signal. To ensure the accurate synchronization of the local oscillator phases of the radio frequency transceivers, it is necessary to accurately obtain the setup time and duration of the synchronous pulse signal and the clock signal. When the master module sends a synchronous trigger signal, the synchronous pulse generator generates a synchronous pulse signal. This synchronous pulse signal is transmitted to each slave module together with the clock signal generated by the master module. After each slave module receives these two signals, it first performs signal stability detection to ensure that the signal quality meets the requirements. Subsequently, the clock distributor and synchronous pulse distributor in the slave module further process these signals to ensure that their propagation delays within their respective modules are consistent. Next, the slave module reads the setup time and duration of the synchronous pulse signal and the clock signal. Here, the setup time refers to the minimum time interval during which the clock signal must be stable before the synchronous pulse signal arrives; the duration refers to the minimum time interval during which the clock signal must remain stable after the synchronous pulse signal arrives. By accurately measuring these parameters, it can be ensured that the timing relationship between the synchronous pulse signal and the clock signal always remains fixed. After determining the timing relationship between the rising edges of the synchronous pulse signal and the clock signal, the master module and the slave modules will synchronize the local oscillator phases of the radio frequency transceivers according to this timing relationship. Specifically, the mixer local oscillator circuit inside each radio frequency transceiver is reset at the rising edge of the synchronous pulse signal, so that the local oscillator signal phases of all radio frequency transceivers reach consistency at the same moment. In this way, whether in the receiving mode or the transmitting mode, the local oscillator signals of each radio frequency transceiver can maintain strict phase synchronization, thereby ensuring the coherence of the entire multi-beamforming system. In addition, to further improve the synchronization accuracy, the internal delay of the clock and synchronous pulse generator in the master module can also be adjusted to compensate for the time delay caused by unequal transmission path lengths. This means that even in practical applications, due to physical layout reasons, the signal transmission path lengths between different modules may be different, and through this dynamic adjustment mechanism, it can be ensured that the timing relationship between all modules always meets the requirements.

[0027] In a preferred example of the present application, it can be further configured that: the master module and all the slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization, and interface synchronization through the second pulse of the clock signal and the synchronous pulse signal to complete the synchronization, specifically including:

[0028] Obtain the synchronization status of each slave module, and send the synchronization status to the master module to complete the synchronization.

[0029] By adopting the above technical solution, it can ensure that the master module and all slave modules accurately complete the sampling clock synchronization, digital clock synchronization, and interface synchronization of the A / D converter and D / A converter under the action of the clock signal and the second pulse of the synchronization pulse signal. Through the communication mechanism between the master module and the slave module, the master module can monitor the synchronization status of each slave module in real time to ensure that each slave module has successfully completed the synchronization operation. Once a slave module completes synchronization, it will feedback its synchronization status to the master module, and the master module will confirm the synchronization status of the entire system based on this feedback information, thereby ensuring that all modules complete the synchronization operation at the same time. After receiving the synchronization confirmation from all slave modules, the master module confirms that the entire system has completed synchronization, ensuring the stability and reliability of the system. This technical solution monitors and feedbacks the synchronization status of each slave module, ensuring precise synchronization between multiple modules and improving the overall performance and stability of the system.

[0030] The second invention object of this application is achieved through the following technical solution:

[0031] A digital array antenna and digital circuit synchronization device, the digital array antenna and digital circuit synchronization device includes:

[0032] An initialization module, used to perform module preprocessing on the master module and the slave module, where the module preprocessing includes configuring FPGA code for the master module and the slave module and initializing the radio frequency transceiver;

[0033] A handshake request module, used for the master module to trigger a module handshake request to the slave module and obtain the signal reception status of the slave module according to the module handshake request;

[0034] A first synchronization module, used for the master module to send a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal, and the master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceiver through the first pulse of the clock signal and the synchronization pulse signal;

[0035] A second synchronization module, used for the master module and all slave modules to perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization, and interface synchronization through the second pulse of the clock signal and the synchronization pulse signal to complete the synchronization.

[0036] By adopting the above technical solution, first, through module preprocessing of the master module and slave modules, it is ensured that each module can correctly configure the FPGA code and initialize the radio frequency transceiver when starting up. This preprocessing step lays the foundation for subsequent synchronization operations, ensuring that all modules are in the same initial state, thus reducing the risk of synchronization failure caused by inconsistent initial states. Secondly, the master module triggers a module handshake request to the slave modules to obtain the signal reception status of the slave modules. This process is implemented through a serial bus interface, ensuring that the master module can accurately understand the status of each slave module. Specifically, the master module will send a clock signal handshake request and a synchronization pulse handshake request, and these two requests are combined into a module handshake request. After receiving these requests, the slave modules will feedback their own clock signal reception status and synchronization pulse reception status. After the master module collects this status information, it can determine which slave modules are ready to receive the synchronization signal and which ones still need further adjustment. This step effectively avoids the overall synchronization failure caused by some modules not being ready during the synchronization process and improves the reliability of the system. Then, the master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. This synchronization pulse signal is one of the core signals for system synchronization, and it is used to ensure that all modules start to perform synchronization operations at the same moment. The master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceiver through the first pulse of the clock signal and the synchronization pulse signal. During this process, the role of the synchronization pulse signal is to provide an accurate time reference, so that the mixing local oscillator signals of all radio frequency transceivers can reach the same phase at the same moment. In this way, it is ensured that all radio frequency transceivers maintain full coherence when receiving and transmitting signals, which is crucial for multi-beamforming. Subsequently, the master module and all slave modules perform sampling clock synchronization, digital clock synchronization, and interface synchronization of the A / D converter and D / A converter through the second pulse of the clock signal and the synchronization pulse signal. In this step, the second pulse of the clock signal and the synchronization pulse signal are used to calibrate the sampling clocks of the A / D converters and D / A converters in each module to ensure that they sample at the same moment. At the same time, digital clock synchronization is also performed to ensure that the digital signal processing circuits in all modules operate at the same time point. Finally, the synchronization of the JESD204B interface is completed. This is an important interface for data transmission between the radio frequency transceiver and the FPGA, ensuring that there are no timing errors during data transmission. During the entire synchronization process, by adjusting the transmission delays of the internal clock distributors and synchronization pulse distributors in each module, it is ensured that there is a fixed timing relationship between the clock rising edges and the synchronization pulses among all modules. This method not only simplifies the hardware design, reduces the difficulty of printed circuit board wiring, but also improves the stability and reliability of the system.In this way, the present invention successfully solves the problems existing in the prior art, such as a large variety of synchronization signals and tight interconnection signal resources, and realizes the efficient synchronization of a high-integration, miniaturized, distributed spaceborne digital array antenna multi-beamforming system.

[0037] The above-mentioned third object of the present application is achieved by the following technical solutions:

[0038] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above-mentioned digital array antenna and digital circuit synchronization method are implemented.

[0039] The above-mentioned fourth object of the present application is achieved by the following technical solutions:

[0040] A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the above-mentioned digital array antenna and digital circuit synchronization method are implemented.

[0041] In summary, the present application includes at least one of the following beneficial technical effects:

[0042] 1. Through the collaborative work of the master module and the slave module, a high-integration radio frequency transceiver is adopted to achieve mixing local oscillator phase synchronization, A / D converter and D / A converter sampling clock synchronization, digital clock synchronization, and high-speed digital interface synchronization, and solves the problems of excessive system complexity and cost in the traditional method when the number of array elements is large;

[0043] 2. Each clock signal and synchronization pulse signal can independently perform coarse and fine adjustment of the transmission delay, without the need for equal-length wiring of printed circuit boards, greatly reducing the wiring difficulty of the multi-beam transceiver processing module and the printed circuit board inside the backplane, and improving the flexibility and reliability of the system;

[0044] 3. The board-level resource manager (BMC) realizes handshake and control information interaction between modules through a serial bus interface, simplifies the system design, and improves the overall coordination and stability of the system;

[0045] 4. During the system synchronization process, the local oscillator phase of the radio frequency transceiver is synchronized through the first pulse of the clock signal and the synchronization pulse signal, ensuring that the mixing local oscillator signals of all receiving channels and transmitting channels are in the same phase, and improving the accuracy and stability of multi-beamforming. Description of the Drawings

[0046] Figure 1 It is a block diagram of the composition of the spaceborne digital array antenna multi-beamforming system in this embodiment.

[0047] Figure 2 It is the block diagram of the main on-chip circuits of the RF transceiver in this embodiment.

[0048] Figure 3 It is the block diagram of the clock and synchronization pulse generator in this embodiment.

[0049] Figure 4 It is the block diagram of the clock distributor in this embodiment.

[0050] Figure 5 It is the block diagram of the synchronization pulse distributor in this embodiment.

[0051] Figure 6 It is the system synchronization processing flowchart in this embodiment.

[0052] Figure 7 It is the first example diagram of the timing relationship between the clock and the synchronization pulse in this embodiment.

[0053] Figure 8 It is the second example diagram of the timing relationship between the clock and the synchronization pulse in this embodiment.

[0054] Figure 9 It is the schematic diagram of the device in an embodiment of this application. Specific implementation manners

[0055] The following further elaborates on this application in conjunction with the accompanying drawings.

[0056] According to Figure 1 As shown, the system consists of one multi-beam transceiver processing main module A, M multi-beam transceiver processing slave modules B, and a backplane. Among them, for clearly describing the system synchronization principle, only the signal interconnection relationships related to synchronization are shown in the figure, while other interconnection relationships unrelated to synchronization are not shown.

[0057] The main module A mainly consists of N RF transceivers, a large-scale FPGA with rich on-chip resources, a board-level resource manager (BMC), a clock and synchronization pulse distribution circuit, and a clock and synchronization pulse generator. The only difference between the main module A and the slave module B is that the main module A needs to provide a clock signal (DCLK) and a synchronization pulse signal (SYSREF) for the entire system (including one main module A and M slave modules B). Except for not having a clock and synchronization pulse generator, the other components of the slave module B are the same as those of the main module A. The main and slave modules can be produced by using the same printed circuit board and soldering different devices.

[0058] The main function of the radio frequency transceiver is to convert multiple radio frequency received signals into zero-intermediate frequency baseband received signals and transmit them to the FPGA, and convert the zero-intermediate frequency baseband transmitted signals sent by the FPGA into multiple radio frequency transmitted signals. The main function of the FPGA is to implement the digital beamforming algorithm for all radio frequency transceiver channels of this module and implement the synchronization interface with the radio frequency transceiver.

[0059] The function of the board-level resource manager (BMC) is to implement board-level resource management within the multi-beam transceiver processing module and realize handshake and control information interaction between modules through the serial bus interface. The serial bus interface can be an SPI interface, an I 2 C interface, a CAN bus interface, an RS-485 bus interface, etc.

[0060] The function of the clock and synchronization pulse generator (only the main module A has this part of the circuit) is to generate M + 1 clock signals and synchronization pulse signals required for system synchronization of one main module A and M slave modules B respectively.

[0061] The function of the clock and synchronization pulse distribution circuit is to receive the clock and synchronization pulse signals transmitted from the main module A through the backplane and generate multiple clock signals and synchronization pulse signals required for N radio frequency transceivers and the FPGA within this module. Although the number of clock and synchronization pulse signals for the FPGA described in the figure is the same as the number of radio frequency transceivers, different design schemes are allowed to use fewer clock and synchronization pulse signals.

[0062] The radio frequency transceiver is a highly integrated and high-performance system-on-chip (SoC) chip that integrates radio frequency circuits, mixed-signal circuits, and digital signal processing circuits in one chip. Its main function is to realize the transceiver of multiple radio frequency signals. Specifically, its functions include: mixing the radio frequency received signals, analog filtering, A / D conversion, digital filtering, decimation, DC offset correction, quadrature error correction, and transmitting the baseband received data to the FPGA; interpolating the baseband transmitted data from the FPGA, digital filtering, quadrature error correction, local oscillator leakage correction, D / A conversion, analog filtering, quadrature mixing, generating radio frequency transmitted signals and outputting them.

[0063] According to Figure 2 shown, Figure 2 the specific radio frequency transceiver given in

[0064] has four receive channels and four transmit channels. Radio frequency transceivers with different numbers of radio frequency transceiver channels can also be used. Currently available radio frequency transceivers can have two receive and two transmit, four receive and four transmit, or eight receive and eight transmit radio frequency channels per chip. Figure 2It can be seen that the radio frequency transceiver adopts an orthogonal mixing scheme and consists of multiple transceiver channels, multiple frequency synthesizers, a clock generation and synchronization circuit, a JESD204B high-speed interface, etc.

[0065] Among them, the transceiver channel consists of a receiving channel and a transmitting channel: the receiving channel consists of a digital control attenuator, an orthogonal mixer, a low-pass filter with programmable bandwidth, a high-speed A / D converter, a receiving digital processing circuit (including digital filtering, decimation, DC bias correction, and quadrature error correction), etc.; the transmitting channel consists of a transmitting digital processing circuit (including interpolation, digital filtering, local oscillator leakage correction, and quadrature error correction), a high-speed D / A converter, a low-pass filter with programmable bandwidth, an orthogonal mixer, a digital control attenuator, etc.

[0066] The frequency synthesizer consists of a receiving local oscillator frequency synthesizer, a transmitting local oscillator frequency synthesizer, and a digital clock frequency synthesizer, etc., which respectively generate the mixing local oscillator for the receiving channel, the mixing local oscillator for the transmitting channel, and the digital clock (including the clocks required for the A / D converter, D / A converter, receiving digital processing circuit, transmitting digital processing circuit, and JESD204B interface).

[0067] The function of the clock generation and synchronization circuit is to receive the clock and synchronization pulse signals input from outside the chip, generate multiple clock signals and synchronization pulse signals required by the three frequency synthesizers, and additionally generate the synchronization pulse signals required by the JESD204B high-speed digital interface.

[0068] The function of the JESD204B high-speed digital interface is to synchronously transmit digital baseband signals (including receiving signals and transmitting signals) between the radio frequency transceiver and the FPGA.

[0069] The function of the clock and synchronization pulse generator (only the main module A has this part of the circuit) is to generate M + 1 clock signals and synchronization pulse signals required for system synchronization of one main module A and M slave modules B respectively. The composition block diagram is shown in Figure 3 . In the figure, the reference clock (REFCLK) can be either an on-board clock or an external reference clock provided from the backplane. The reference clock is input to the frequency synthesizer, and the frequency synthesizer generates the clock source required by the system. The frequency synthesizer can be either an integer division frequency or a fractional division frequency.

[0070] The clock source generated by the frequency synthesizer is input into an integrated circuit named "Clock Distribution, Synchronization Generation and Distributor". Inside the integrated circuit, the input clock is driven by a driver and sent to the clock distributor and the synchronization pulse generator. The clock distributor converts a common input clock into M+1 output clocks, and the transmission delay of each clock can be coarsely and finely adjusted. The coarse adjustment step is half of the input clock period, and the fine adjustment step is generally dozens of picoseconds, with an adjustment range of generally several hundred picoseconds. The synchronization pulse generator uses the input clock signal as the working clock. After receiving the synchronization trigger signal from the board-level management controller (BMC), it generates the required synchronization pulse signal. The synchronization pulse signal can be a single pulse or a pulse sequence composed of multiple pulses. The synchronization pulse signal enters the synchronization pulse frequency divider, which converts a common synchronization pulse signal into M+1 synchronization pulse signals. The transmission delay of each step pulse signal can be coarsely and finely adjusted. The coarse adjustment step is half of the input clock period, and the fine adjustment step is generally dozens of picoseconds, with an adjustment range of generally several hundred picoseconds.

[0071] The output signals of the clock distribution, synchronization generation and distributor are generally differential levels that require transmission impedance matching, including but not limited to LVPECL, LVDS, HSTL, CML, etc. By controlling the characteristic impedance of the transmission line and the receiving end termination impedance, it is ensured that the rising edge and falling edge of the clock and synchronization pulse signals are steep enough, and the rise time and fall time are short enough, generally between 100 ps and 1000 ps. Since the clock distribution, synchronization generation and distributor has the above-mentioned transmission delay adjustment function, it is not necessary to require the M+1 clock signals and synchronization pulse signals to have strictly equal-length transmission paths. It is only necessary to control the difference in transmission line delay within the delay adjustment range of the integrated circuit, which greatly reduces the printed circuit board wiring difficulty of the multi-beam transceiver processing module and the backplane.

[0072] Both the main module A and the slave module B have clock and synchronization pulse distribution circuits. Their functions are: receiving the clock and synchronization pulse signals transmitted from the main module A through the backplane and generating multiple clock signals and synchronization pulse signals required by N radio frequency transceivers and FPGAs within the module.

[0073] The clock and synchronization pulse distribution circuit is divided into two parts: a clock distributor and a synchronization pulse distributor. The composition block diagrams are shown in Figure 4 and Figure 5 . The circuit structures of the clock distributor and the synchronization pulse distributor are the same. The difference is that: the clock signal is a pulse signal with a 50% duty cycle of high and low levels, so the circuit coupling method can be selected as DC coupling or AC coupling; the synchronization pulse signal is a burst pulse signal with a very low high-level duty cycle, so the circuit coupling method can only be selected as DC coupling and cannot be selected as AC coupling.

[0074] Both the clock distributor and the synchronization pulse distributor have functions of coarse adjustment and fine adjustment of transmission delay, and the adjustment range is the same as that of the above-mentioned clock distribution, synchronization generation and distributor. Since the delay can be adjusted by configuration, it is not necessary to require that the transmission paths of 2N clock signals and synchronization pulse signals are strictly equal in length. It is only necessary to control the difference in transmission line delay within the range of integrated circuit delay adjustment, which greatly reduces the difficulty of printed circuit board wiring inside the multi-beam transceiver processing module.

[0075] In one embodiment, as Figure 6 shown, the present application discloses a digital array antenna and a digital circuit synchronization method, which specifically includes the following steps:

[0076] S10: Perform module preprocessing on the master module and the slave modules. Among them, the module preprocessing includes configuring FPGA codes for the master module and the slave modules and initializing the radio frequency transceivers.

[0077] Specifically, after the master module and the slave modules are powered on, configure the FPGA codes, and initialize the radio frequency transceivers corresponding to the master module and each slave module.

[0078] S20: The master module triggers a module handshake request to the slave modules, and obtains the signal reception status of the slave modules according to the module handshake request.

[0079] S21: The master module triggers a clock signal handshake request and a synchronization pulse handshake request, and combines the clock signal handshake request and the synchronization pulse signal handshake request into a module handshake request.

[0080] S22: Obtain the clock signal reception status and the synchronization pulse reception status from each slave module, combine the clock signal reception status and the synchronization pulse reception status into a signal reception status, and send it to the master module.

[0081] Specifically, the board-level resource manager (BMC) of the master module sends a module handshake request through the serial bus interface to query whether each slave module is ready to receive the clock and synchronization pulse signals. The board-level resource managers (BMCs) of each slave module send the corresponding clock signal reception status and synchronization pulse signal reception status to the master module through the serial bus interface. After all slave modules are ready, the board-level resource manager (BMC) of the master module starts to initialize the on-board clock circuit to generate a clock signal.

[0082] S30: The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform phase synchronization of the local oscillator of the radio frequency transceiver through the first pulses of the clock signal and the synchronization pulse signal.

[0083] S31: Receive the clock signal and the synchronization pulse signal sent by the master module through the backplane.

[0084] S311: Obtain the signal setup time and signal duration corresponding to the synchronization pulse signal and the clock signal.

[0085] S312: Obtain the timing relationship between the rising edges of the synchronization pulse signal and the clock signal according to the signal setup time and the signal duration, and perform local oscillator phase synchronization according to the timing relationship.

[0086] S40: The master module and all slave modules perform A / D converter and D / A converter sampling clock synchronization, digital clock synchronization, and interface synchronization through the second pulse of the clock signal and the synchronization pulse signal to complete the synchronization.

[0087] S41: Obtain the synchronization status of each slave module, and send the synchronization status to the master module to complete the synchronization.

[0088] For all radio frequency transceivers and FPGAs in the multi-beamforming system, the clocks of each should be in phase with each other, and a fixed timing relationship should be maintained between the rising edges of their respective clocks and the synchronization pulse. As described above Figure 3 shown, by adjusting the internal delay of the clock and synchronization pulse generator of the master module A to compensate for the transmission path delay caused by the unequal lengths of the internal and backplane signal lines of the module, it is ensured that a fixed timing relationship is maintained between the rising edges of the clocks and the synchronization pulse among all modules. As described above Figure 4 and Figure 5 shown, by adjusting the internal delay of the clock distributor and synchronization pulse frequency divider of each module to compensate for the transmission path delay caused by the unequal lengths of the internal signal lines of the module, it is ensured that a fixed timing relationship is maintained between the rising edges of the clocks and the synchronization pulse among all radio frequency transceivers and among FPGAs.

[0089] After alignment, the timing relationship between the clock and the synchronization pulse (Example 1) is shown in Figure 7 . Figure 7 In, the timing relationship between the synchronization pulse and the rising edge of the clock is determined by the setup time t S and the hold time t H . Different devices have different requirements for the setup time and the hold time. By adjusting the above-mentioned transmission delay, it is easy to meet the timing requirements of specific devices.

[0090] As Figure 7 shown, the first synchronization pulse is used to synchronize the phases of the internal mixing local oscillator signals of all radio frequency transceivers in the system, and the second synchronization pulse is used to synchronize the sampling clock synchronization and digital clock synchronization of the internal A / D converters and D / A converters of all radio frequency transceivers in the system, and is also used for JESD204B interface synchronization between all radio frequency transceivers and the interconnected FPGAs.

[0091] The number of synchronization pulses is not limited to two, and various required synchronization pulse forms can be flexibly generated. Figure 8 An example of the timing relationship between a general clock and synchronization pulses is given. Figure 8 In it, the number of groups of synchronization pulses and the number of synchronization pulses in each group can be flexibly configured.

[0092] In this embodiment, a highly integrated and high-performance radio frequency transceiver that integrates a radio frequency circuit, a digital-analog hybrid circuit, and a digital signal processing circuit in one chip is adopted, so as to realize the miniaturization of the device and system. It consists of a main module and M slave modules. Each module has N radio frequency transceivers, and each radio frequency transceiver has four receiving channels and four transmitting channels, thus constituting a digital array antenna multi-beamforming system with (1 + M) × N × 4 antenna elements. According to the idea of the present invention, by expanding the number of output signals of the clock and synchronization pulse generator, the clock distributor, and the synchronization pulse distributor, a digital array antenna multi-beamforming system with a huge number of elements can be easily designed.

[0093] The multi-beam transceiver processing module is divided into a main module and a slave module. The difference between the two modules is only that the main module A needs to provide a clock signal and a synchronization pulse signal for the entire system. Except for not having a clock and synchronization pulse generator, the other components of the slave module are the same as those of the main module. The main and slave modules can be produced by using the same printed circuit board and soldering different devices.

[0094] Radio frequency transceivers with different numbers of radio frequency transceiver channels can be used. Currently available radio frequency transceivers can have two receive and two transmit, four receive and four transmit, or eight receive and eight transmit radio frequency channels on a single chip.

[0095] Only by using two signals, namely the clock signal and the synchronization pulse, the mixing local oscillator synchronization, the sampling clock synchronization of the A / D converter and the D / A converter, the digital clock synchronization, and the JESD204B interface synchronization between the radio frequency transceiver and the interconnected FPGA are realized, achieving the minimization of the types of synchronization signals.

[0096] Each clock signal and synchronization pulse signal can be independently coarsely and finely adjusted for transmission delay, without the need for the transmission signal lines to be strictly of equal length, greatly reducing the wiring difficulty of the printed circuit board inside the module and the backplane.

[0097] The board-level resource manager (BMC) realizes the handshake and control information interaction between modules through a serial bus interface. The serial bus interface can be in any form, including but not limited to SPI interface, I 2 C interface, CAN bus interface, RS-485 bus interface, etc.

[0098] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0099] In one embodiment, a digital array antenna and a digital circuit synchronization device are provided. The digital array antenna and the digital circuit synchronization device correspond one-to-one with the digital array antenna and the digital circuit synchronization method in the above embodiment. The digital array antenna and the digital circuit synchronization device include an initialization module, a handshake request module, a first synchronization module, and a second synchronization module. The detailed descriptions of each functional module are as follows:

[0100] The initialization module is used to perform module preprocessing on the master module and the slave module. Among them, the module preprocessing includes configuring FPGA codes for the master module and the slave module and initializing the radio frequency transceiver.

[0101] The handshake request module is used for the master module to trigger a module handshake request to the slave module and obtain the signal reception status of the slave module according to the module handshake request.

[0102] The first synchronization module is used for the master module to send a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceiver through the first pulse of the clock signal and the synchronization pulse signal.

[0103] The second synchronization module is used for the master module and all slave modules to perform sampling clock synchronization, digital clock synchronization, and interface synchronization of the A / D converter and the D / A converter through the second pulse of the clock signal and the synchronization pulse signal to complete the synchronization.

[0104] Optionally, the handshake request module includes:

[0105] The handshake request sending sub-module is used for the master module to trigger a clock signal handshake request and a synchronization pulse handshake request, and form a module handshake request by combining the clock signal handshake request and the synchronization pulse signal handshake request.

[0106] The handshake request response sub-module is used to obtain the clock signal reception status and the synchronization pulse reception status from each slave module, and form the signal reception status by combining the clock signal reception status and the synchronization pulse reception status and send it to the master module.

[0107] Optionally, the first synchronization module includes:

[0108] The signal sending sub-module is used to receive the clock signal and the synchronization pulse signal sent by the master module through the backplane.

[0109] Optionally, the first synchronization module includes:

[0110] A time acquisition sub-module, configured to acquire the signal setup time and the signal duration corresponding to the synchronization pulse signal and the clock signal;

[0111] A first synchronization sub-module, configured to acquire the timing relationship between the rising edges of the synchronization pulse signal and the clock signal according to the signal setup time and the signal duration, and perform local oscillator phase synchronization according to the timing relationship.

[0112] Optionally, the second synchronization module includes:

[0113] A synchronization feedback sub-module, configured to acquire the synchronization status of each slave module, send the synchronization status to the master module, and complete the synchronization.

[0114] For the specific limitations on the digital array antenna and the digital circuit synchronization device, reference can be made to the limitations on the digital array antenna and the digital circuit synchronization method in the above text, which will not be elaborated here. Each module in the above digital array antenna and digital circuit synchronization device can be implemented in whole or in part by software, hardware, and their combination. The above-mentioned modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above-mentioned modules.

[0115] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 9 shown. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a digital array antenna and digital circuit synchronization method.

[0116] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented:

[0117] Perform module preprocessing on the master module and the slave module, where the module preprocessing includes configuring FPGA code and initializing the radio frequency transceiver for the master module and the slave module;

[0118] The master module triggers a module handshake request to the slave module, and acquires the signal reception status of the slave module according to the module handshake request;

[0119] The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceiver through the first pulse of the clock signal and the synchronization pulse signal;

[0120] The master module and all slave modules perform sampling clock synchronization, digital clock synchronization, and interface synchronization of the A / D converter and D / A converter through the second pulse of the clock signal and the synchronization pulse signal to complete the synchronization.

[0121] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0122] Perform module preprocessing on the master module and slave modules. Among them, module preprocessing includes configuring FPGA code for the master module and slave modules and initializing the radio frequency transceiver;

[0123] The master module triggers a module handshake request to the slave module and obtains the signal reception status of the slave module according to the module handshake request;

[0124] The master module sends a synchronization trigger signal to trigger the synchronization pulse generator to generate a synchronization pulse signal. The master module and all slave modules perform local oscillator phase synchronization of the radio frequency transceiver through the first pulse of the clock signal and the synchronization pulse signal;

[0125] The master module and all slave modules perform sampling clock synchronization, digital clock synchronization, and interface synchronization of the A / D converter and D / A converter through the second pulse of the clock signal and the synchronization pulse signal to complete the synchronization.

[0126] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0127] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0128] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A digital array antenna and digital circuit synchronization method, characterized in that: It comprises a backplane, a master module connected to the backplane, and M slave modules, wherein the master module is composed of several RF transceivers, an FPGA, a board-level resource manager, a clock and synchronization pulse distribution circuit, and a clock and synchronization pulse generator, wherein the master module provides a clock signal and a synchronization pulse signal to the master module and each of the slave modules, and the slave modules have the same components as the master module except that they do not have a clock and synchronization pulse generator; wherein the function of the clock and synchronization pulse distribution circuit is to receive the clock signal and synchronization pulse signal from the master module and transmitted through the backplane, and to generate multiple clock signals and synchronization pulse signals required by several RF transceivers and the FPGA in the module; and the clock and synchronization pulse generator is used to generate M+1 clock signals and synchronization pulse signals required by the master module and the M slave modules for system synchronization respectively; The digital array antenna and digital circuit synchronization method comprises: Performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code and initializing a radio frequency transceiver on the master module and the slave module; The master module sends a module handshake request to the slave module, and acquires a signal receiving state of the slave module according to the module handshake request; The master module sends a synchronization trigger signal to trigger the clock and synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform phase synchronization of the local oscillator of the RF transceiver through the clock signal and the first pulse of the synchronization pulse signal; The master module and all the slave modules perform high-speed A / D converter and high-speed D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete synchronization, wherein the RF transceiver is composed of multiple transceiver channels, multiple frequency synthesizers, clock generation and synchronization circuits and JESD204B high-speed interfaces, and the transceiver channel is composed of a receiving channel and a transmitting channel: the receiving channel is composed of a digitally controlled attenuator, an orthogonal mixer, a bandwidth programmable low-pass filter, a high-speed A / D converter and a receiving digital processing circuit; the transmitting channel is composed of a transmitting digital processing circuit, a high-speed D / A converter, a bandwidth programmable low-pass filter, an orthogonal mixer and a digitally controlled attenuator.

2. The digital array antenna and digital circuit synchronization method according to claim 1, characterized in that: The master module sends a module handshake request to the slave module, and acquires a signal receiving state of the slave module according to the module handshake request, specifically including: The master module triggers a clock signal handshake request and a synchronization pulse handshake request, and combines the clock signal handshake request and the synchronization pulse handshake request into the module handshake request; Each of the slave modules acquires a clock signal receiving state and a synchronization pulse receiving state, combines the clock signal receiving state and the synchronization pulse receiving state into the signal receiving state and sends the result to the master module.

3. The digital array antenna and digital circuit synchronization method according to claim 1, characterized in that: The master module sends a synchronization trigger signal to trigger the clock and synchronization pulse generator to generate a synchronization pulse signal. The master module and all the slave modules perform phase synchronization of the RF transceiver local oscillator through the clock signal and the first pulse of the synchronization pulse signal, specifically including: The clock signal and the synchronization pulse signal sent by the clock and synchronization pulse generator in the main module are received through the backplane.

4. The digital array antenna and digital circuit synchronization method according to claim 3, characterized in that: The master module sends a synchronization trigger signal to trigger the clock and synchronization pulse generator to generate a synchronization pulse signal. The master module and all the slave modules perform phase synchronization of the RF transceiver local oscillator through the clock signal and the first pulse of the synchronization pulse signal, specifically including: Acquire the signal establishment time and signal duration corresponding to the synchronization pulse signal and the clock signal; The timing relationship between the rising edge of the synchronization pulse signal and the clock signal is acquired according to the signal establishment time and the signal duration, and the local oscillator phase synchronization is performed according to the timing relationship.

5. The digital array antenna and digital circuit synchronization method according to claim 1, characterized in that: The master module and all the slave modules perform high-speed A / D converter and high-speed D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the clock signal and the second pulse of the synchronization pulse signal to complete synchronization, specifically including: The synchronization status of each slave module is obtained, and the synchronization status is sent to the master module to complete the synchronization.

6. A digital array antenna and digital circuit synchronization device, characterized in that: It comprises a backplane, a master module connected to the backplane, and M slave modules, wherein the master module is composed of several RF transceivers, an FPGA, a board-level resource manager, a clock and synchronization pulse distribution circuit, and a clock and synchronization pulse generator, wherein the master module provides a clock signal and a synchronization pulse signal to the master module and each of the slave modules, and the slave modules have the same components as the master module except that they do not have a clock and synchronization pulse generator; wherein the function of the clock and synchronization pulse distribution circuit is to receive the clock signal and synchronization pulse signal from the master module and transmitted through the backplane, and to generate multiple clock signals and synchronization pulse signals required by several RF transceivers and the FPGA in the module; and the clock and synchronization pulse generator is used to generate M+1 clock signals and synchronization pulse signals required by the master module and the M slave modules for system synchronization respectively; The digital array antenna and digital circuit synchronization device comprises: An initialization unit, used for performing module preprocessing on the master module and the slave module, wherein the module preprocessing includes configuring FPGA code and initializing a radio frequency transceiver on the master module and the slave module; A handshake request unit, configured to enable the master module to send a module handshake request to the slave module, and obtain a signal receiving state of the slave module according to the module handshake request; A first synchronization unit is used to enable the master module to send a synchronization trigger signal to trigger the clock and synchronization pulse generator to generate a synchronization pulse signal, and the master module and all the slave modules perform phase synchronization of the local oscillator of the radio frequency transceiver through the clock signal and the first pulse of the synchronization pulse signal; The second synchronization unit is used to enable the master module and all the slave modules to perform high-speed A / D converter and high-speed D / A converter sampling clock synchronization, digital clock synchronization and interface synchronization through the second pulse of the clock signal and the synchronization pulse signal to complete synchronization, wherein the RF transceiver is composed of multiple transceiver channels, multiple frequency synthesizers, clock generation and synchronization circuits and JESD204B high-speed interfaces, and the transceiver channel is composed of a receiving channel and a transmitting channel: the receiving channel is composed of a digitally controlled attenuator, an orthogonal mixer, a bandwidth programmable low-pass filter, a high-speed A / D converter and a receiving digital processing circuit; the transmitting channel is composed of a transmitting digital processing circuit, a high-speed D / A converter, a bandwidth programmable low-pass filter, an orthogonal mixer and a digitally controlled attenuator.

7. The digital array antenna and digital circuit synchronization device according to claim 6, characterized in that: The handshake request unit comprises: A handshake request sending subunit, used to enable the main module to trigger a clock signal handshake request and a synchronization pulse handshake request, and to combine the clock signal handshake request and the synchronization pulse handshake request into the module handshake request; The handshake request response subunit is used to enable each of the slave modules to obtain a clock signal receiving state and a synchronization pulse receiving state, and to combine the clock signal receiving state and the synchronization pulse receiving state into the signal receiving state and send it to the master module.

8. The digital array antenna and digital circuit synchronization device according to claim 6, characterized in that: The first synchronization unit comprises: The signal sending subunit is used to enable the master module and the slave module to receive the clock signal and the synchronization pulse signal sent by the clock and synchronization pulse generator in the master module through the backplane.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the digital array antenna and digital circuit synchronization method according to any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the digital array antenna and digital circuit synchronization method according to any one of claims 1 to 5 are implemented.

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