Priority-based designated interface selection in link aggregation group

Abstract

Embodiments of the disclosure relate to priority-based designated interface selection in a link aggregation group. In some examples, a first electronic device includes a plurality of interfaces to network links that are part of a link aggregation group. The first clock selects a specified interface from the plurality of interfaces for a time synchronization process based on priorities associated with the plurality of interfaces, wherein the priorities include a first priority assigned to the first interface, a second priority assigned to the second interface, and a third priority assigned to the third interface. The first clock uses a specified interface to send a timing message of a time synchronization process to a second electronic device including a second clock to which the first clock of the first electronic device is to be synchronized according to the time synchronization process.

Description

Background Art

[0001] The electronic devices in the electronic device distribution system include clocks that generate time, which can be wall clock time or any other time representation. The time generated by the clocks in multiple electronic devices allows transactions occurring between the multiple electronic devices to be time-aligned with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Some implementations of the present disclosure are described with respect to the following figures.

[0003] Figure 1 is a block diagram of an arrangement including an electronic device including a corresponding clock according to some examples.

[0004] Figure 2 is a flow chart of a static priority-based link aggregation (LAG) interface selection process using static priorities according to some examples.

[0005] Figure 3 is a flow chart of a dynamic synchronization process using a dynamic priority-based LAG interface selection process according to another example.

[0006] Figure 4 is a block diagram of an electronic device according to some examples.

[0007] Figure 5 is a block diagram of a storage medium storing machine-readable instructions according to some examples.

[0008] Figure 6 is a flow diagram of a process according to some examples.

[0009] Throughout the drawings, the same reference numerals denote similar, but not necessarily identical, elements. The drawings are not necessarily to scale, and the size of some parts may be exaggerated to more clearly illustrate the examples shown. In addition, the drawings provide examples and / or implementations consistent with the description; however, the description is not limited to the examples and / or implementations provided in the drawings. DETAILED DESCRIPTION

[0010] In order to maintain synchronization between time clocks (or more simply referred to as "clocks") in electronic devices in a distributed system, a time synchronization process can be employed. In some examples, the time synchronization process can be based on a time synchronization protocol, such as the Precision Time Protocol (PTP) described by the Institute of Electrical and Electronics Engineers (IEEE) 1588 specification.

[0011] A distributed system may include a network for interconnecting electronic devices. The network includes physical network links (or more simply referred to as "network links") between electronic devices. In some cases, link aggregation may be employed, where multiple network links are aggregated into logical links (sometimes referred to as link aggregation groups or LAGs) between electronic devices. In some examples, link aggregation may be in accordance with the IEEE 802.3ad specification. Link aggregation allows load balancing of packets on the network links of the LAG between two electronic devices. Using load balancing, a source electronic device may send different packets to a target electronic device using different network links of the LAG.

[0012] PTP uses timing messages exchanged between electronic devices (or more specifically, between the clocks of electronic devices) to perform time synchronization. If link aggregation is used between electronic devices, PTP timing messages may traverse different network links in the forward direction and the reverse direction. A first electronic device can send a first PTP timing message to a second electronic device (in the forward direction) via a first network link of the LAG, but the second electronic device can send a second PTP timing message to the first electronic device (in the reverse direction) via a different second network link of the LAG. Using different network links of the LAG for PTP timing messages between electronic devices results in asymmetric communication paths in different directions between electronic devices, which may affect time offsets and other calculations associated with time synchronization because different network links of the LAG may have different link delays. The asymmetry of the communication paths used in the time synchronization process results in asymmetric time synchronization, which may result in inaccurate clock operation.

[0013] In some cases, in order to avoid time synchronization asymmetry, the first network link of the LAG is designated as the main link for the PTP control packet, and the second network link of the LAG is designated as the auxiliary link for the PTP control packet. The remaining network links of the LAG are designated as inoperable, that is, the remaining network links are not used to transmit information. If the main link becomes unavailable, the auxiliary link can be used to transmit the PTP control packet. However, if both the main link and the auxiliary link become unavailable (due to hardware failure or machine-readable instruction failure), none of the other network links of the LAG can be used for PTP time synchronization. As a result, if both the main link and the auxiliary link become unavailable, PTP time synchronization will be impossible.

[0014] In addition, during a failover from a primary link to a secondary link in response to the unavailability of the primary link, clock state swings may occur at the boundary clock. A "boundary time clock" (or more simply referred to as a "boundary clock") refers to a clock in an electronic device that is synchronized with a clock source upstream of the boundary clock and acts as a clock source for a clock sink downstream of the boundary clock. According to PTP, the clock source is a master clock and the clock sink is a slave clock. A clock can include multiple clock states, including a locked state in which the clock is aligned with the clock source in phase and frequency, and an unlocked state in which the clock is not aligned with the clock source in phase and frequency so that the time synchronization process must be restarted. "Clock state swing" refers to the clock state of a clock changing from a locked state to an unlocked state. Clock state swings at a boundary clock may cause clock fluctuations in a clock downstream of the boundary clock.

[0015] According to some embodiments of the present disclosure, a first electronic device includes multiple interfaces (also referred to as "ports") to corresponding network links of a given LAG. Such interfaces are referred to as "LAG interfaces" (or "LAG ports"). A first clock in the first electronic device selects a designated LAG interface from multiple LAG interfaces for a time synchronization process based on priorities associated with multiple LAG interfaces of a given LAG, wherein priorities are assigned to more than two LAG interfaces of a given LAG. The priority may include an assigned priority or a priority obtained from information associated with the LAG interface (such as an interface index of the LAG interface). The first clock uses the designated LAG interface to send a timing message of a time synchronization process to a second electronic device including a second clock, and the first clock of the first electronic device will be synchronized with the second clock according to the time synchronization process.

[0016] In some examples of the present disclosure, there are two general techniques related to selecting a specified LAG interface from among multiple LAG interfaces of a given LAG. The first general technique is a static priority technique, in which static priorities are assigned to multiple LAG interfaces of a given LAG. The static priorities can be assigned by a user (e.g., an administrator or another user) or by a different entity (e.g., a program or a machine). Once the static priorities are assigned, the clock will perform the selection of the specified LAG interface based on the static priorities of the time synchronization process. If the LAG interface with the highest static priority is available, the clock will select the LAG interface with the highest static priority. If the LAG interface with the highest static priority is unavailable (e.g., the interface is down or failed), the clock will select the LAG interface with the next highest static priority. Note that although the assigned priorities are static in any given LAG interface selection round of the time synchronization process, the assigned priorities can be changed by a user or another entity, and the changed assigned priorities (new static priorities) will be used by the clock in subsequent LAG interface selection rounds of the time synchronization process.

[0017] The second general technique is a dynamic priority technique, in which the clock obtains the initial priority of the LAG interface for a given LAG based on information associated with the LAG interface. For example, the information associated with the LAG interface may include an interface index of the LAG interface. "Interface index" refers to a number or string that distinguishes one LAG interface from another LAG interface in a given electronic device. If the interface index is a number, the interface index may be incremented for each LAG interface according to the order of the LAG interfaces (e.g., interface index 1 assigned to the first LAG interface, interface index 2 assigned to the second LAG interface, etc.). Using the dynamic priority technique, the clock can deviate from the initial priority determined for the LAG interface. For example, the clock can dynamically change the priority of any given LAG interface based on an event associated with the given LAG interface. For example, the event may include receiving a specific timing message on a given LAG interface. The following further explains the dynamic adjustment of the priority of the LAG interface starting from the initial priority of the LAG interface.

[0018] In some examples, PTP (Precision Time Protocol) can be used to exchange timing messages to synchronize the clocks of electronic devices (such as electronic devices connected to a packet-based network). The clocks of electronic devices can have different accuracy and stability. In a local area network (LAN), PTP can achieve clock accuracy in the sub-microsecond range.

[0019] Examples of electronic devices with clocks include any one or some combination of the following: network devices (e.g., switches, routers, gateways, etc.), computers (e.g., desktop computers, laptop computers, tablet computers, server computers, etc.), smart phones, vehicles, gaming equipment, storage systems, Internet-of-Things (IoT) devices, or any other type of electronic device.

[0020] A "clock" in an electronic device refers to a hardware circuit (or a combination of a hardware circuit and machine-readable instructions) that generates the current time. A clock can perform time synchronization processes with other clocks (such as according to PTP).

[0021] Figure 1 is a block diagram of an example arrangement including electronic devices 102, 104, and 106. Although Figure 1Only three electronic devices are depicted in FIG. 1 , but in other examples, there may be a different number of electronic devices (two or more). Electronic devices 102, 104, and 106 are coupled to a network. In some examples, electronic devices 102, 104, and 106 are network devices capable of forwarding packets along a network path of the network, such as switches or routers. In other examples, electronic devices 102, 104, and 106 may include different types of electronic devices.

[0022] Electronic device 104 is connected between electronic device 102 and electronic device 106. For example, if electronic device 104 is a network device, the network device can receive packets from electronic device 102 and forward the packets to other electronic devices including electronic device 106. Electronic devices 102 and 106 can also be network devices capable of forwarding packets.

[0023] Electronic devices 102 and 104 are connected to each other via network links 108-1, 108-2, and 108-3 of LAG 108. Electronic devices 104 and 106 are connected to each other via network links 110-1, 110-2, 110-3, and 110-4 of LAG 110. Although a particular number of network links is depicted for LAGs 108 and 110, in other examples, a LAG may include a different number of network links.

[0024] A “network link” may refer to a communication channel formed by communication resources (eg, frequency band, time slot, coding channel, etc.) on which information can be carried. The communication channel may be a wired channel or a wireless channel.

[0025] The electronic device 102 includes interfaces A, B, and C connected to the respective network links 108-1, 108-2, and 108-3 of the LAG 108. Similarly, the electronic device 104 includes interfaces 1, 2, and 3 connected to the respective network links 108-1, 108-2, and 108-3 of the LAG 108. The interface connected to the network link of the LAG is referred to as the "LAG interface". An "interface" may refer to the circuitry (or a combination of circuitry and machine-readable instructions) of an electronic device that communicates over a network link. The circuitry may include a transceiver that sends and receives signals and any network protocol layer that manages message exchanges according to one or more corresponding communication protocols.

[0026] Electronic device 104 also includes interfaces 4, 5, 6, and 7 connected to respective network links 110-1, 110-2, 110-3, and 110-4 of LAG 110. Similarly, electronic device 106 includes interfaces D, E, F, and G connected to respective network links 110-1, 110-2, 110-3, and 110-4 of LAG 110.

[0027] Note that any of the electronic devices 102, 104, and 106 may have additional interfaces (not shown) that are capable of connecting to other network links (whether or not part of a LAG).

[0028] The use of LAG provides load balancing and redundancy. In some examples, electronic devices can use the Link Aggregation Control Protocol (LACP) that defines messages for performing link aggregation. LACP is defined by the IEEE 802.3ad specification. Figure 1 As shown, the electronic device includes a LAG control engine that establishes and controls the LAG employed by the electronic device, such as according to LACP or any other protocol (whether standardized, open source or proprietary). Electronic device 102 includes LAG control engine 152, electronic device 104 includes LAG control engine 154, and electronic device 106 includes LAG control engine 156.

[0029] The LAG control engine may use a LAG hash algorithm on the packet header contents to select which LAG interface of the LAG to send the packet. A "packet" may refer to a data packet carrying data or a control packet carrying control information. A packet includes a header and a payload. The payload carries data or control information, while the header includes fields for forwarding the packet in the network and fields for identifying information of one or more communication protocols associated with the packet.

[0030] Different electronic devices can run their corresponding LAG hash algorithms independently of each other without coordination. The LAG hash algorithm involves applying a hash function to certain fields of the packet header to obtain a hash value, and the hash value is used to select from multiple LAG interfaces of the LAG. The LAG control engine in the first electronic device can apply the LAG hash algorithm to select the first LAG interface to send a packet to the second electronic device, and the LAG control engine of the second electronic device can apply the LAG hash algorithm to select the second LAG interface (different from the first LAG interface) to send a packet to the first electronic device.

[0031] Since independent hash algorithms are applied in different electronic devices connected to each other through LAG, timing messages of the time synchronization process may be transmitted on different network links of the LAG between the electronic devices, which results in time synchronization asymmetry as described above. The time synchronization process is performed between clocks in the electronic devices.

[0032] Electronic device 102 includes clock 122, electronic device 104 includes clock 124, and electronic device 106 includes clock 126. Clock 124 is a boundary clock (hereinafter referred to as "boundary clock 124") relative to clocks 122 and 126. Clock 122 is upstream of boundary clock 124 and is referred to as "upstream clock 122". Clock 126 is downstream of boundary clock 124 and is referred to as "downstream clock 126".

[0033] An "upstream clock" refers to a clock that is a clock source (provides a time reference) for a clock of another electronic device. A "downstream clock" refers to a clock that is a clock sink that uses a clock of another electronic device as a reference. Boundary clock 124 is a clock sink for upstream clock 122. In addition, boundary clock 124 is a clock source for downstream clock 126. Note that one or both of upstream clock 122 and downstream clock 126 may be boundary clocks relative to other clocks in other electronic devices.

[0034] A clock that is not connected to any downstream clock is called an "ordinary clock". Another type of clock is a transparent clock, which is an intermediate clock that can calculate time delays, but is not synchronized with other clocks.

[0035] The clock includes a synchronization engine for participating in a time synchronization process between the clock and a peer clock. As used herein, an "engine" may refer to a hardware processing circuit, which may include any one of a microprocessor, a core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, or another hardware processing circuit or some combination thereof. Alternatively, an "engine" may refer to a combination of a hardware processing circuit and machine-readable instructions (software and / or firmware) that may be run on the hardware processing circuit.

[0036] Upstream clock 122 includes synchronization engine 132, boundary clock 124 includes synchronization engine 134, and downstream clock 126 includes synchronization engine 136. Synchronization engines 132, 134, and 136 can perform a time synchronization process, such as a PTP process or a process according to other time synchronization protocols, whether standardized, open source, or proprietary.

[0037] The synchronization engine in the clock can initiate a time synchronization process in response to a triggering event, and the time synchronization process can be a PTP synchronization process according to some examples. The triggering event can be a periodic event that causes the clock to periodically perform the time synchronization process. Alternatively, the triggering event can be based on other conditions, such as any condition indicating that the time of different clocks is not aligned, the electronic device is restarted, or any other condition.

[0038] According to some examples of the present disclosure, the clock may further include a priority-based LAG interface selection engine, which selects a designated LAG interface from among a plurality of LAG interfaces of the LAG based on a priority (static or dynamic priority) assigned to the LAG interface. The "designated LAG interface" refers to an interface of an electronic device for sending a timing message (such as a PTP timing message) of a time synchronization process.

[0039] The upstream clock 122 may include a priority-based LAG interface selection engine 142 (in Figure 1 14), the boundary clock 124 may include a priority-based LAG interface selection engine 144, and the downstream clock 126 may include a priority-based LAG interface selection engine 146. In a further example, if dynamic priorities are used (discussed further below), the priority-based LAG interface selection engine may not be present in a clock such as the upstream clock 122.

[0040] In an example using static priorities, assigning static priorities to the respective LAG interfaces of each electronic device can be performed by a user at a user device 112 coupled to the electronic devices 102, 104, and 106 via a network (such as a management network or another type of network). The user device 112 may include a desktop computer, a notebook computer, a tablet computer, a smart phone, or any other type of electronic device. The user device 112 includes a display 114 in which a user interface (UI) 116 may be presented. The UI 116 is a remote command interface that includes control elements that can be activated by a user to set the static priority of the LAG interface of any one of the electronic devices 102, 104, and 106.

[0041] In other examples, different entities (programs or machines) can assign static priorities to the LAG interface of the electronic device. Note that after a static priority has been assigned (by a user or another entity), the user or other entity can later change the static priority.

[0042] The electronic device includes a memory for storing priority information of a LAG interface (referred to as "LAG interface priority information"). The LAG interface priority information 172, 174, or 176 may include a static priority or a dynamic priority assigned to the corresponding LAG interface. The electronic device 102 includes a memory 162 for storing the LAG interface priority information 172 of the LAG interface of the electronic device 102; the electronic device 104 includes a memory 164 for storing the LAG interface priority information 174 of the LAG interface of the electronic device 104; and the electronic device 106 includes a memory 166 for storing the LAG interface priority information 176 of the LAG interface of the electronic device 106. The memory may be implemented using one or more memory devices, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another type of memory device.

[0043] Some examples of timing messages, such as PTP timing messages, are discussed below.Timing messages may include announce messages, sync messages, follow-up messages, delay request messages, and delay response messages (as examples).

[0044] An announce message includes quality attributes about the clock that sent the announce message. For example, the quality attributes include class, priority, and / or clock quality. The synchronization engine in the first clock and the second clock can use the announce message exchanged between the first clock and the second clock (based on a comparison of the quality attributes) to determine which of the first clock and the second clock is a clock source and which of the first clock and the second clock is a clock sink.

[0045] A synchronization message (e.g., a PTP Sync message) is sent by a clock source to a clock sink to initiate a time synchronization process. The clock source may record an outgoing time (T1), which is the time at which the synchronization message is sent. If the clock source is a one-step clock, T1 may be carried in the synchronization message. If the clock source is a two-step clock, T1 is carried in a follow-up message (PTP Follow-Up message) sent after the synchronization message. Upon receiving a synchronization message, the clock sink records the incoming time (T2) at which the synchronization message is received by the clock sink. The clock sink also records the outgoing time (T1) from the clock source, where T1 may be included in a synchronization message or a follow-up message.

[0046] The clock sink sends a delay request message (e.g., a PTP DelayReq message) to the clock source. The clock sink may record the outgoing time (T3) of the delay request message sent from the clock sink. The clock source receives the delay request message and records the incoming time (T4) of the delay request message received at the clock source. The clock source then sends a delay response message (e.g., a PTP DelayResp) to the clock sink. The delay response message includes the incoming time (T4) of the delay request message.

[0047] Using T1, T2, T3, and T4, the clock sink can determine (such as using calculations according to PTP) an offset of the clock sink relative to the clock source.

[0048] Clocks 122, 124, and 126 may be one-step or two-step clocks. In addition, a boundary clock (e.g., 124 or any other boundary clock) may implement an end-to-end or peer-to-peer delay mechanism for calculating path delays, time offsets, dwell times, etc., as described in IEEE 1588. Techniques or mechanisms according to some implementations of the present disclosure may be employed with one-step clocks or two-step clocks and may be used with an end-to-end delay mechanism or a peer-to-peer delay mechanism.

[0049] LAG interface selection based on static priority

[0050] In some examples, the priority-based LAG interface selection engine may implement a static priority-based LAG interface selection process in which a designated LAG interface is selected from a plurality of LAG interfaces of a LAG based on static priorities assigned to corresponding LAG interfaces of the electronic device.

[0051] Figure 2 is a flow chart of a static priority-based LAG interface selection process performed in the electronic device 104. Note that a similar static priority-based LAG interface selection process may be performed in the electronic device 102 or 106.

[0052] The priority-based LAG interface selection engine 144 in the boundary clock 124 of the electronic device 104 receives (at 202) a static priority of a LAG interface assigned to a given LAG (e.g., 108 or 110) of the electronic device 104. For example, the static priority may be set by a user at the user device 112 ( Figure 1). In such an example, the user device 112 can obtain information of the LAG interfaces of a given LAG from the LAG control engine 154. The LAG interfaces can be presented in the UI 116 of the user device 112, and the user can assign static priorities to the presented LAG interfaces. For example, the user can enter a static priority value into a field associated with the corresponding LAG interface presented in the UI 116. Different static priority values ​​represent different static priorities.

[0053] The assigned static priority is sent by the user device 112 to the electronic device 104. In other examples, different entities may assign static priorities to LAG interfaces and send the assigned static priorities to the electronic device 104. Upon receiving the assigned static priority, the priority-based LAG interface selection engine 144 in the electronic device 104 may save the assigned static priority as part of the LAG interface priority information 174 stored in the memory 164 of the electronic device 104. The saved static priority may be retrieved for use in selecting a specified LAG interface.

[0054] The priority-based LAG interface selection engine 144 selects (at 204) a designated LAG interface from among the LAG interfaces of a given LAG based on the assigned static priority for use in a time synchronization process. The selection of the designated LAG interface is based on a comparison of the static priorities assigned to the LAG interfaces by the priority-based LAG interface selection engine 144. The priority-based LAG interface selection engine 144 selects the available LAG interface with the highest static priority as the designated LAG interface. The assigned priorities may be represented using different static priority values. In some cases, a lower static priority value indicates a higher priority relative to a higher priority value. In other examples, a higher priority value indicates a higher priority relative to a lower priority value.

[0055] Note that a LAG interface of an electronic device may be unavailable for some reason. For example, the LAG interface may be shut down (e.g., due to a hardware or software failure) or may otherwise be indicated as unavailable for use. If the LAG interface with the highest static priority is unavailable, the priority-based LAG interface selection engine 144 selects an available LAG interface with the next highest static priority.

[0056] Once the designated LAG interface has been selected, the priority-based LAG interface selection engine 144 sets (at 206) the remaining LAG interfaces of the given LAG to a non-designated standby mode. The "remaining" LAG interfaces are the LAG interfaces of the given LAG other than the designated LAG interface. In the non-designated standby mode, the LAG interface can receive timing messages of the time synchronization process, but the LAG interface cannot send timing messages.

[0057] After selection of the designated LAG interface, the priority-based LAG interface selection engine 144 may receive (at 208) an indication that the designated LAG interface has become unavailable (such as due to a failure or for any other reason). The indication may include status information of the designated LAG interface. The status information may indicate whether the LAG interface is operational or unavailable.

[0058] In response to the indication that the designated LAG interface has become unavailable, the priority-based LAG interface selection engine 144 performs (at 210) a LAG interface failover by selecting an available LAG interface having a next highest static priority to serve as the designated LAG interface.

[0059] Note that the priority-based LAG interface selection engine may receive an incoming timing message (e.g., a follow-up message or a delayed response message) from a peer clock at a LAG interface that is not a designated LAG interface (in a non-designated standby mode). In this case, the priority-based LAG interface selection engine may remap the incoming timing message (received at the non-designated LAG interface) to the designated LAG interface so that any response to the incoming timing message is sent through the designated LAG interface.

[0060] Assigning static priorities to LAG interfaces allows a user (or another entity) to control which LAG interfaces of a given LAG are used as designated LAG interfaces for a time synchronization process, which provides predictability. In addition, according to some examples of the present disclosure, more than two LAG interfaces of a given LAG may be employed to perform a time synchronization process. Thus, even if two LAG interfaces of a given LAG become unavailable, the remaining LAG interface(s) of the LAG may be selected to be used as designated LAG interfaces.

[0061] As described above, the user or another entity may modify the static priority at a later time. If the priority-based LAG interface selection engine receives an indication that the static priority has changed, the selection may be repeated using the changed static priority. Figure 2 process.

[0062] LAG interface selection based on dynamic priority

[0063] In an alternative example, a dynamic priority-based LAG interface selection process may be employed instead of the static priority-based LAG interface selection process discussed above. With the dynamic priority-based LAG interface selection process, a user or another entity does not have to pre-assign static priorities to LAG interfaces. Assigning static priorities to LAG interfaces may be associated with overhead (in terms of time spent or processing resources used) because a user or another entity may have to track which LAG interfaces of peer electronic devices are connected together so that the user or another entity can assign consistent static priorities to LAG interfaces in peer electronic devices. Any misconfiguration or incorrect mapping of LAG interfaces of peer electronic devices may result in time synchronization asymmetry and inaccurate time offsets between the calculated clock source and the clock sink.

[0064] Using the dynamic priority-based LAG selection process, the priority-based LAG interface selection engine can assign an initial priority to a LAG interface of a given LAG based on information associated with the LAG interface. The information associated with the LAG interface can include an interface index of the LAG interface. The initial priority is dynamically modified based on timing messages exchanged in the time synchronization process.

[0065] Figure 3 is a flow chart of a dynamic synchronization process employing a dynamic priority-based LAG selection process according to some examples. Figure 3 The synchronization process may be performed by the boundary clock 124 in the electronic device 104. Another clock in another electronic device may perform a similar synchronization process.

[0066] In an example using a dynamic priority-based LAG selection process, a clock source (e.g., Figure 1 The upstream clock 122 does not have to support dynamic priority-based LAG selection. Instead, the clock source can simply employ a LAG hashing algorithm (such as according to PTP) to select a LAG interface through which to send a timing message. The priority-based LAG interface selection engine can apply a dynamic priority-based LAG selection process to modify which LAG interface is selected as the designated LAG interface based on which LAG interface a timing message (such as a synchronization message (e.g., PTP Sync)) is received.

[0067] In other examples, both the clock source and the clock sink may employ a dynamic priority-based LAG selection process according to some implementations of the present disclosure.

[0068] Initially, the priority-based LAG interface selection engine 144 in the boundary clock 124 selects (at 302) a designated LAG interface from among the LAG interfaces based on the interface index of the LAG interface of the given LAG. The designated LAG interface selected based on the interface index is referred to as the "initial designated LAG interface". In some examples, the interface index indicates an initial priority associated with the LAG interface. For example, a LAG interface with a lower (or higher) interface index has a higher priority relative to a LAG interface with a higher (or lower) interface index. The priority-based LAG interface selection engine 144 compares the interface indexes of the LAG interfaces of the given LAG, and the priority-based LAG interface selection engine 144 selects the available LAG interface with the lowest (or highest) interface index as the initial designated LAG interface. The remaining LAG interfaces of the given LAG are set in a non-designated standby mode.

[0069] In other examples, other information associated with the LAG interfaces of a given LAG may be used to indicate the relative priority of the LAG interfaces. For example, the priority-based LAG interface selection engine 144 may generate a random number (e.g., from a pseudo-random generator) or other value to assign the LAG interface, and the priority-based LAG interface selection engine 144 may derive the relative priority of the LAG interface based on the random number or other value.

[0070] The synchronization engine 134 in the boundary clock 124 may send (at 304) a timing message using the initially designated LAG interface. The timing message sent may include, for example, an announcement message sent by the boundary clock 124 to the upstream clock 122.

[0071] The synchronization engine 134 may also receive (at 306) an announce message from the upstream clock 122. Note that the announce message from the upstream clock 122 may be received at a non-designated LAG interface (a LAG interface in non-designated standby mode) of a given LAG. If the announce message from the upstream clock 122 is received at the non-designated LAG interface, the synchronization engine 134 may remap the received announce message to the initial designated LAG interface (selected at 302) so that the synchronization engine 134 may compare the quality information of the announce message. Remapping the received announce message from the upstream clock 122 to the initial designated LAG interface refers to providing that the received announce message is to be analyzed relative to the announce message sent (or to be sent) by the boundary clock 124 from the initial designated LAG interface.

[0072] Based on comparing the quality attributes of the notification messages sent by the boundary clock 124 with the quality attributes of the notification messages received from the upstream clock 122, the synchronization engine 134 determines (at 308) whether the boundary clock 124 is a clock source or a clock sink on the initially designated LAG interface. If the boundary clock 124 is a clock source, then the upstream clock 122 is a clock sink, and if the boundary clock 124 is a clock sink, then the upstream clock 122 is a clock source. Note that the designated LAG interface has a synchronization interface state (e.g., a PTP port state) associated with the initially designated LAG interface. The synchronization interface state can be a clock source state or a clock sink state. Therefore, the determination at 308 is to determine whether the initially designated LAG interface has a clock source state or a clock sink state.

[0073] If the synchronization engine 134 determines (at 308) that the initially designated LAG interface has the clock source state, no dynamic modification is necessary with respect to the initially designated LAG interface being in the clock source state, and tasks 316 and 318 are skipped. The synchronization engine 134 continues (at 310) with the remainder of the time synchronization process. For example, the remainder of the time synchronization process may include the exchange of synchronization messages, follow-up messages (if a two-step clock is used), delay request messages, and delay response messages.

[0074] However, if the synchronization engine 134 determines (at 308) that the initially designated LAG interface has a clock sink state, then tasks 312, 314, 316, and 318 are performed. In the following discussion, it is assumed that the synchronization engine 134 determines that the initially designated LAG interface has a clock sink state, which means that the upstream clock 122 is the clock source on the initially designated LAG interface.

[0075] Based on the initial designated LAG interface being in the clock sink state (as determined at 308), dynamic modification may have to be made relative to the initial designated LAG interface being in the clock sink state because a synchronization message may be received from the clock source (upstream clock 122) at a non-designated LAG interface. Note that the upstream clock 122 may have selected a different LAG interface as the designated LAG interface at the electronic device 102, such as due to application of a LAG hashing algorithm at the upstream clock 122. As a result, time synchronization asymmetry may occur between the upstream clock 122 and the boundary clock 124.

[0076] To address time synchronization asymmetry, the priority-based LAG interface selection engine 144 of the boundary clock 124 can update the priority of the LAG interface of a given LAG based on which LAG interface a synchronization message (e.g., PTY Sync) is received. For example, the priority-based LAG interface selection engine 144 may have selected LAG interface 1 ( LAG 1 ) based on the interface indexes of LAG interfaces 1, 2, and 3 of the electronic device 104. Figure 1 ) as the initial designated LAG interface.

[0077] However, the synchronization engine 132 of the upstream clock 122 in the electronic device 102 may have selected LAG interface B (which is coupled to LAG interface 2 of the electronic device 104) to send the synchronization message through the network link 108-2 of the LAG 108 (such as based on the LAG hash algorithm). Because the hash function of the LAG hash algorithm is applied to specific fields of the header of the synchronization message from the upstream clock 122 to the boundary clock 124, the hash function will produce the same hash value for each such synchronization message. As a result, for each synchronization message sent by the upstream clock 122 to the boundary clock 124, the upstream clock 122 will select the same LAG interface (e.g., select LAG interface B) based on the hash value.

[0078] In view of this predictable behavior regarding the LAG interface for synchronization messages, the priority-based LAG interface selection engine 144 of the boundary clock 124 may modify its initial designated LAG interface selection (e.g., LAG interface 1 in the example given above). The boundary clock 124 receives (at 312) a synchronization message from the upstream clock 122. The priority-based LAG interface selection engine 144 determines (at 314) whether the synchronization message was received at the initial designated LAG interface (e.g., LAG interface 1) or at a non-designated LAG interface (different from the initial designated LAG interface).

[0079] In response to determining that the synchronization message is received at the initially designated LAG interface (e.g., LAG interface 1), the priority-based LAG interface selection engine 144 does not perform modifications to the initially designated LAG interface, and the priority-based LAG interface selection engine 144 may continue to perform (at 310) the remainder of the time synchronization process with the upstream clock 122 using the initially designated LAG interface. For example, the remainder of the time synchronization process may include the exchange of follow-up messages (if a two-step clock is used), delay request messages, and delay response messages.

[0080] However, in response to determining that a synchronization message is received at a non-designated LAG interface (e.g., LAG interface B), the priority-based LAG interface selection engine 144 promotes (at 316) the non-designated LAG interface (e.g., LAG interface B) to be a new designated LAG interface. Promoting the non-designated LAG interface to be a new designated LAG interface dynamically changes the priority of the non-designated LAG interface to be higher than the priority of the initial designated LAG interface. The priority-based LAG interface selection engine 144 may continue (at 318) the remainder of the time synchronization process with the upstream clock 122 using the new designated LAG interface. In this manner, time synchronization symmetry may be achieved between the upstream clock 122 and the boundary clock 124. For example, the remainder of the time synchronization process may include the exchange of follow-up messages (if two-step clocks are used), delay request messages, and delay response messages.

[0081] Later, the priority-based LAG interface selection engine 144 may receive (at 320) an indication that the current designated LAG interface has become unavailable (such as due to a failure or for any other reason). If the flow including task 310 is followed, the “current” designated LAG interface is the initial designated LAG interface, while if the flow including tasks 316 and 318 is followed, the “current” designated LAG interface is the new designated LAG interface.

[0082] In response to an indication that the current designated LAG interface has become unavailable, the priority-based LAG interface selection engine 144 performs (at 322) a LAG interface failover by selecting an available LAG interface having a next highest priority (e.g., next highest interface index) to serve as a new initial designated LAG interface. This new initial designated LAG interface is modified based on receiving a synchronization message from the upstream clock 122 at a non-designated LAG interface that is different from the new initial designated LAG interface.

[0083] In some examples, a dynamic priority-based LAG interface selection process may have the following benefits. Since a user or another entity does not have to pre-assign priorities to electronic devices, configuration overhead may be reduced. A dynamic priority-based LAG interface selection process is able to dynamically change the priority of a LAG interface based on timing messages of a timing synchronization process, such as a PTP process. A dynamic priority-based LAG interface selection process does not rely on adding additional messages or information elements to support dynamic adjustment of LAG interface priorities. As a result, some electronic devices, such as the electronic device 102 having an upstream clock 122, do not have to be modified to support a dynamic priority-based LAG interface selection process.

[0084] In some examples of the present disclosure, the dynamic priority-based LAG interface selection process is non-preemptive, meaning that if a LAG interface with a lower interface index becomes available after the current designated LAG interface has been selected, the current designated LAG interface will not change based on the LAG interface with the lower interface index becoming available as long as the current designated LAG interface remains available (i.e., the current designated LAG interface becoming unavailable will trigger the failover process as described above).

[0085] As described above, a LAG interface in non-designated standby mode is able to receive timing messages, but cannot send timing messages. If a designated LAG interface becomes unavailable, the non-designated LAG interface can be selected as the next designated LAG interface simply by unblocking the transmission capability of the non-designated LAG interface. As a result, the time synchronization process (e.g., PTP process) does not have to be restarted when the designated LAG interface changes. Therefore, failover can be performed in an efficient and seamless manner without affecting clock functionality and accuracy.

[0086] More Examples

[0087] Figure 4 is a block diagram of a first electronic device 400 according to some examples. The first electronic device 400 is Figure 1 An example of any one of the electronic devices 102, 104 and 106.

[0088] The electronic device 400 includes a plurality of interfaces 402 to a network link that is part of a LAG. The plurality of interfaces 402 are LAG interfaces.

[0089] The electronic device 400 includes a first clock 404 for providing time information. The first clock 404 is Figure 1 The first clock 404 is used to perform various tasks. These tasks can be performed by the hardware processing circuit of the first clock 404, or by the machine-readable instructions executed by the first clock 404.

[0090] The tasks of the first clock 404 include a priority-based designated interface selection task 406 for selecting a designated interface from the plurality of interfaces 402 for a time synchronization process based on the priorities associated with the plurality of interfaces 402. The priorities include a first priority assigned to the first interface, a second priority assigned to the second interface, a third priority assigned to the third interface, etc. The priorities may be static priorities or initial priorities (the initial priorities may change).

[0091] The task of the first clock 404 includes a timing message sending task 408, which is used to use a specified interface to send a timing message of a time synchronization process to a second electronic device including a second clock, and the first clock of the first electronic device will be synchronized with the second clock according to the time synchronization process.

[0092] In examples where the priority is a static priority, the static priority may be obtained from a remote command interface (e.g., Figure 1 's UI 116) or received from another entity.

[0093] In examples where the priority is an initial priority that may change, the priority may be based on an interface index assigned to the plurality of interfaces 402. For example, a lower (or higher) interface index may indicate a higher priority relative to a higher (or lower) interface index.

[0094] In some examples, the timing message includes a notification message (sent from the first clock 404), the notification message including information for selecting which of the first clock 404 and the second clock is the clock source and the other of the first clock 404 and the second clock is the clock sink. The notification message may include, for example, clock quality information indicating the quality of the first clock 404.

[0095] In some examples, the first clock 404 determines that the first clock 404 is a clock sink (and the second clock is a clock source) based on the announcement message. Based on determining that the first clock 404 is a clock sink, the first clock 404 detects that a synchronization message of a time synchronization process is received at a second interface among the multiple interfaces, the second interface being different from the designated interface.

[0096] In some examples, based on detecting receipt of the synchronization message at the second interface, the first clock 404 changes the designated interface selection by selecting the second interface as the new designated interface. This change in designated interface selection changes the priority of the plurality of interfaces 402 to allow selection of the new designated interface.

[0097] In some examples, the first clock 404 sends another timing message of the time synchronization process to the second electronic device using the new designated interface. The other timing message is a delay message (eg, a delay request message) for calculating the delay in the network link between the first electronic device and the second electronic device.

[0098] In some examples, the plurality of interfaces 402 include designated interfaces and remaining interfaces that are non-designated interfaces. The first clock 404 is capable of receiving timing messages of a time synchronization process at the non-designated interfaces.

[0099] In some examples, the non-designated interface is in a standby mode capable of receiving timing messages for the time synchronization process, but the non-designated interface is blocked from sending any timing messages for the time synchronization process.

[0100] In some examples, the first clock 404 detects that the designated interface has become unavailable, and in response to detecting that the designated interface has become unavailable, another interface is selected from the non-designated interfaces as a new designated interface based on the priority assigned to the non-designated interface. The first clock 404 uses the new designated interface to send a timing message of the time synchronization process to the second electronic device.

[0101] Figure 5 is a block diagram of a non-transitory machine-readable or computer-readable storage medium 500 storing machine-readable instructions that, when executed, cause a first clock to perform various tasks. The first clock may be Figure 1 boundary clock 124, or another boundary clock.

[0102] The machine-readable instructions include initial designated interface selection instructions 502 for selecting an initial designated interface from a plurality of interfaces for use in a time synchronization process based on priorities associated with the plurality of interfaces. For example, the priorities may be based on interface indexes of the plurality of interfaces.

[0103] The machine-readable instructions include a first timing message sending instruction 504 for sending a first timing message of a time synchronization process to the second clock using an initial designated interface, and the first clock will synchronize with the second clock according to the time synchronization process. For example, the first timing message is a notification message.

[0104] The machine-readable instructions include designated interface change instructions 508 for changing the designated interface selection by selecting the non-designated interface as a new designated interface based on receiving a second timing message from a second clock at a non-designated interface of the first clock, wherein the non-designated interface is different from the initial designated interface. For example, the second timing message is a synchronization message.

[0105] Figure 6 600 according to some examples of the present disclosure. The process 600 may be performed by a first clock (such as Figure 1 Executed by any one of clocks 122, 124 and 126 in the example.

[0106] The process 600 includes selecting (at 602), by a first clock, from a plurality of LAG interfaces of a first electronic device, an initially designated LAG interface for use in a time synchronization process between the first clock and a second clock in a second electronic device based on a priority associated with the plurality of LAG interfaces. For example, the priority may be based on an interface index of the plurality of LAG interfaces.

[0107] Process 600 includes sending (at 604) a first announcement message of a time synchronization process from a first clock to a second clock using an initially designated LAG interface. Process 600 includes receiving (at 606) a second announcement message of the time synchronization process at the first clock from the second clock. The first announcement message and the second announcement message contain clock quality information to enable the first clock and the second clock to select a clock source.

[0108] Process 600 includes determining (at 608) whether the first clock is a clock sink on the initially designated LAG interface based on the first announcement message and the second announcement message. The first announcement message and the second announcement message may indicate that the second clock is a higher quality clock and therefore the second clock should be used as a clock source to be synchronized with the first clock.

[0109] Process 600 includes performing tasks 610, 612, and 614 based on determining that the first clock is a clock sink on the initially designated LAG interface. In other words, the initially designated LAG interface has a clock sink status.

[0110] Task 610 includes determining, by the first clock, whether a synchronization message is received from the second clock at an initially designated LAG interface.

[0111] Task 612 includes changing, by the first clock, the designated LAG interface selection by selecting the non-designated LAG interface as a new designated LAG interface based on determining that a synchronization message from the second clock is received at a non-designated LAG interface that is different from the initial designated LAG interface.

[0112] Task 614 includes performing the remainder of the time synchronization process by the first clock using the new designated LAG interface.

[0113] Storage media (e.g. Figure 5500) may include any one of the following or some combination thereof: a semiconductor memory device such as DRAM or SRAM, an erasable and programmable read-only memory (EPROM), an electrically erasable and programmable read-only memory (EEPROM), and flash memory; a disk such as a fixed disk, a floppy disk, and a removable disk; another magnetic medium including a tape; an optical medium such as a compact disk (CD) or a digital video disk (DVD); or another type of storage device. Note that the instructions discussed above may be provided on one computer-readable or machine-readable storage medium, or may be provided on multiple computer-readable or machine-readable storage media distributed in a large system that may have multiple nodes. Such one or more computer-readable or machine-readable storage media are considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. One or more storage media may be located in a machine that runs machine-readable instructions, or at a remote site from which machine-readable instructions may be downloaded over a network for execution.

[0114] In the present disclosure, the use of the terms "a", "an" or "the" is also intended to include plural forms, unless the context clearly indicates otherwise. In addition, the terms "comprises", "comprising", "including", "having", "having" when used in the present disclosure specify the presence of the elements described, but do not exclude the presence or addition of other elements.

[0115] In the foregoing description, many details are set forth to provide an understanding of the subject matter disclosed herein. However, implementations may be practiced without some of these details. Other implementations may include modifications and variations to the details discussed above. The appended claims are intended to cover these modifications and variations.

Claims

1. A first electronic device, comprising: a plurality of interfaces to a network link, the network link being part of a link aggregation group; as well as A first clock for providing time information, wherein the first clock is used to: selecting a designated interface from the plurality of interfaces for use in a time synchronization process based on priorities associated with the plurality of interfaces, wherein the priorities include a first priority assigned to a first interface, a second priority assigned to a second interface, and a third priority assigned to a third interface; as well as The designated interface is used to send a timing message of the time synchronization process to a second electronic device including a second clock, and the first clock of the first electronic device will be synchronized to the second clock according to the time synchronization process. 2 . The first electronic device according to claim 1 , wherein the priority level comprises a static priority level. 3 . The first electronic device according to claim 2 , wherein the first electronic device is configured to receive the static priority through a remote command interface. The first electronic device of claim 1 , wherein the priority is based on an interface index assigned to the plurality of interfaces.

5. The first electronic device according to claim 4, wherein the timing message comprises a notification message, the notification message comprising information for selecting which one of the first clock and the second clock is a clock source and the other one of the first clock and the second clock is a clock sink.

6. The first electronic device according to claim 5, wherein the first clock is used to: Determining, based on the notification message, that the first clock is the clock sink; Based on determining that the first clock is the clock sink, a synchronization message for the time synchronization process is detected to be received at another interface of the plurality of interfaces, the another interface being different from the designated interface.

7. The first electronic device according to claim 6, wherein the first clock is used to: Based on detecting that the synchronization message is received at the other interface, the designated interface selection is changed by selecting the other interface as a new designated interface.

8. The first electronic device according to claim 7, wherein the first clock is used to: Another timing message of the time synchronization process is sent to the second electronic device using the new designated interface. 9 . The first electronic device of claim 8 , wherein the another timing message is a delay message for calculating a delay in a network link between the first electronic device and the second electronic device.

10. The first electronic device according to claim 1, wherein the plurality of interfaces include the designated interface and remaining interfaces as a plurality of non-designated interfaces, and wherein the first clock is used to: A timing message of the time synchronization process is received at a non-designated interface of the plurality of non-designated interfaces.

11. The first electronic device according to claim 10, wherein the plurality of non-designated interfaces are in a standby mode capable of receiving timing messages of the time synchronization process, and the plurality of non-designated interfaces are blocked from sending any timing messages of the time synchronization process.

12. The first electronic device according to claim 10, wherein the first clock is used to: detecting that the designated interface has become unavailable; In response to detecting that the designated interface has become unavailable, selecting another interface from among the plurality of non-designated interfaces as a new designated interface based on priorities assigned to the plurality of non-designated interfaces; and The timing message of the time synchronization process is sent to the second electronic device using the new designated interface.

13. The first electronic device of claim 1, wherein the first electronic device comprises a network switch, and the first clock is part of the network switch.

14. The first electronic device according to claim 1, wherein the first clock is a boundary clock.

15. A non-transitory machine-readable storage medium comprising instructions that, when executed, cause a first clock to: selecting an initial designated interface for a time synchronization process from a plurality of interfaces based on priorities associated with the plurality of interfaces; Sending a first timing message of the time synchronization process to a second clock using the initial designated interface, and the first clock will be synchronized to the second clock according to the time synchronization process; as well as Based on receiving a second timing message from the second clock at a non-designated interface of the first clock, wherein the non-designated interface is different from the initial designated interface, changing the designated interface selection by selecting the non-designated interface as a new designated interface.

16. The non-transitory machine-readable storage medium of claim 15, wherein the instructions, when executed, cause the first clock to: determining, based on the first timing message, that the first clock is a clock sink and the second clock is a clock source on the initially designated interface, Wherein the change in the designated interface selection is responsive to a determination that the first clock is the clock sink. 17 . The non-transitory machine-readable storage medium of claim 16 , wherein the first timing message is an announce message and the second timing message is a sync message.

18. The non-transitory machine-readable storage medium of claim 15, wherein the priorities associated with the plurality of interfaces are based on interface indexes of the plurality of interfaces.

19. A method comprising: Selecting, by a first clock, an initial designated LAG interface from a plurality of logical aggregation group LAG interfaces of a first electronic device based on priorities associated with the plurality of LAG interfaces for use in a time synchronization process between the first clock and a second clock in a second electronic device; Sending a first notification message of the time synchronization process from the first clock to the second clock using the initial designated LAG interface; receiving, at the first clock, a second notification message of the time synchronization process from the second clock; Determine whether the first clock is a clock sink on the initially designated LAG interface based on the first notification message and the second notification message; as well as Based on determining that the first clock is the clock sink on the initially designated LAG interface: determining, by the first clock, whether a synchronization message from the second clock is received at the initially designated LAG interface, changing, by the first clock, designated LAG interface selection by selecting the non-designated LAG interface as a new designated LAG interface based on determining that the synchronization message from the second clock is received at a non-designated LAG interface different from the initial designated LAG interface, and The remainder of the time synchronization process is performed by the first clock using the new designated LAG interface.

20. The method of claim 19, wherein the time synchronization process is a Precision Time Protocol (PTP) process.

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