Semiconductor memory device

Abstract

The semiconductor device includes a first substrate, and a first memory block and a second memory block spaced apart in a first direction on the first substrate, the first memory block includes first bit lines spaced apart in a second direction, first semiconductor patterns in contact with side surfaces of the first bit lines and extending in one direction, and first capacitors electrically connected to ends of the first semiconductor patterns; the second memory block includes second bit lines spaced apart in the second direction, second semiconductor patterns in contact with side surfaces of the second bit lines and extending in the first direction, and second capacitors electrically connected to ends of the second semiconductor patterns. The first capacitors each include a first dielectric layer having one of silicon oxide or a metal oxide, and the second capacitors each include a second dielectric layer having one of a ferroelectric material or an antiferroelectric material.

Description

[0001] This patent application claims the priority of Korean Patent Application No. 10-2023-0126569 filed in the Korean Intellectual Property Office on September 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a semiconductor memory device. Background Art

[0003] Semiconductor devices may be attractive in the electronics industry due to their relatively small size, multifunctional properties, and / or relatively low manufacturing costs. As electronic devices become more highly integrated, semiconductor devices are also becoming more highly integrated. The line width of semiconductor devices has been gradually reduced to increase the integration density of semiconductor devices. However, there may be some limitations in increasing the integration density of semiconductor devices, for example, in order to further reduce the line width, new exposure techniques and / or high costs for new exposure techniques may be required. Summary of the invention

[0004] Embodiments of the inventive concept provide a highly integrated semiconductor memory device having both volatile and nonvolatile characteristics.

[0005] According to some embodiments of the present invention, a semiconductor memory device includes: a first substrate; and a first memory block and a second memory block, which are on the upper surface of the first substrate and spaced apart from each other in a first direction, wherein the first memory block includes: a first bit line extending perpendicularly to the upper surface of the first substrate, the first bit lines being spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern contacting a side surface of the first bit line, the first semiconductor pattern extending along the first direction; and a first capacitor electrically connected to an end of the first semiconductor pattern, wherein the second memory block includes: a second bit line extending perpendicularly to the upper surface of the first substrate, the second bit lines being spaced apart from each other in a second direction; a second semiconductor pattern contacting a side surface of the second bit line, the second semiconductor pattern extending along the first direction; and a second capacitor electrically connected to an end of the second semiconductor pattern, wherein the first capacitors respectively include a first dielectric layer having at least one of silicon oxide or metal oxide, and wherein the second capacitors respectively include a second dielectric layer having at least one of ferroelectric material or antiferroelectric material.

[0006] According to some embodiments of the present invention, a semiconductor memory device includes: a first substrate; a first memory block and a second memory block, which are on the upper surface of the first substrate and spaced apart from each other in a first direction; and a transfer transistor, which is on the first substrate and electrically connects the first memory block to the second memory block, wherein the first memory block includes: a first bit line, which extends perpendicularly to the upper surface of the first substrate, and the first bit lines are spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern, which contacts the side surface of the first bit line, and the first semiconductor pattern extends along the first direction; and a first capacitor, which is electrically connected to an end of the first semiconductor pattern, wherein the second memory block includes: a second bit line, which extends perpendicularly to the upper surface of the first substrate, and the second bit lines are spaced apart from each other in a second direction; a second semiconductor pattern, which contacts the side surface of the second bit line, and the second semiconductor pattern extends along the first direction; and a second capacitor, which is electrically connected to an end of the second semiconductor pattern, wherein the first capacitors respectively include a first dielectric layer having at least one of silicon oxide or metal oxide, and the second capacitors respectively include a second dielectric layer having at least one of ferroelectric material or antiferroelectric material.

[0007] A semiconductor memory device according to some embodiments of the present invention includes: a first substrate; a first memory block and a second memory block, which are on an upper surface of the first substrate and spaced apart from each other in a first direction; a transfer transistor, which is on the first substrate and electrically connects the first memory block to the second memory block; a second substrate, which is on the first memory block and the second memory block; and a bit line selection transistor, which is on the second substrate and electrically connected to a first bit line, wherein the first memory block includes: a first bit line, which extends perpendicularly to an upper surface of the first substrate, and the first bit lines are spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern, which contacts a side surface of the first bit line, and the first semiconductor pattern extends along the first direction; a first word line, which is adjacent to an upper surface of the first semiconductor pattern; a first gate insulating layer, between the first semiconductor pattern and the first word line; and a first capacitor electrically connected to the end of the first semiconductor pattern, wherein the second storage block includes: a second bit line extending perpendicularly to the upper surface of the first substrate, the second bit lines being spaced apart from each other in the second direction; a second semiconductor pattern contacting the side surface of the second bit line, the second semiconductor pattern extending along the first direction; a second word line adjacent to the upper surface of the second semiconductor pattern; a second gate insulating layer between the second semiconductor pattern and the second word line; and a second capacitor electrically connected to the end of the second semiconductor pattern, wherein the first capacitors respectively include a first dielectric layer having at least one of silicon oxide or metal oxide, and the second capacitors respectively include a second dielectric layer having at least one of ferroelectric material or antiferroelectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which illustrate non-limiting example embodiments described herein.

[0009] Figure 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the inventive concept.

[0010] Figure 2 is a perspective view of a semiconductor memory device according to an embodiment of the inventive concept.

[0011] Figure 3 According to the embodiment of the present invention, Figure 2 A cross-sectional view taken along line AA'.

[0012] Figure 4 yes Figure 3 An enlarged view of portion 'P1'.

[0013] Figure 5A and Figure 5B yes Figure 3 An enlarged view of portion 'P2'.

[0014] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E and Fig. 6F The sequence shows the manufacturing Figure 3 The process of semiconductor memory devices.

[0015] Figure 7 is a cross-sectional view of a semiconductor memory device according to an embodiment of the inventive concept.

[0016] Figure 8 is a cross-sectional view of a semiconductor memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0017] Hereinafter, in order to explain the inventive concept in detail, embodiments according to the inventive concept will be described in detail with reference to the accompanying drawings. In this specification, "word line" may be referred to as "first conductor", and "bit line" may be referred to as "second conductor". The terms "first", "second", etc. may be used only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. in this article. When used in this article, the terms "include", "comprise", "have", and / or "contain in" specify the presence of the stated elements, but do not exclude the presence of other elements. The term "and / or" includes any and all combinations of one or more items listed in association. The term "connection" may be used to refer to physical and / or electrical connections in this article. When a component or layer is referred to as "directly" on, or "directly in contact" or "directly connected" in this article, there is no intermediate component or layer. Similarly, when components are "directly" adjacent to each other, there may be no intermediate component.

[0018] Figure 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the inventive concept.

[0019] refer to Figure 1 , the semiconductor memory device according to the present embodiment may be, for example, a hybrid random access memory (HRAM), which is a combination of a dynamic random access memory (DRAM) and a ferroelectric random access memory (FeRAM). Specifically, the semiconductor memory device includes a first memory block MB1 and a second memory block MB2 disposed on a first substrate 1 and spaced apart from each other in a first direction D1. The first direction D1 may be parallel to the upper surface of the first substrate 1.

[0020] The first memory block MB1 may be a DRAM cell block. The first memory block MB1 includes first sub-blocks SB1 that are symmetrical to each other about the first common electrode PP1. The first sub-block SB1 includes first memory cells MC1 arranged along a second direction D2 and a third direction D3. The second direction D2 may be parallel to the upper surface of the first substrate 1 and may intersect the first direction D1. The third direction D3 may be perpendicular to the upper surface of the first substrate 1. The first memory cell MC1 may be a DRAM cell. One first memory cell MC1 may include one first storage transistor MTR1 and a first capacitor CAP1 connected to one end thereof. The first capacitor CAP1 may have a first dielectric layer DL1 ( Figure 2 ), the first dielectric layer DL1 has a single layer or multilayer structure of at least one of silicon oxide and metal oxide. The gate of the first storage transistor MTR1 is connected to the first word line WL1. The first bit line BL1 is connected to the other terminal of the first storage transistor MTR1. The first storage block MB1 may include a DRAM cell and may have a volatile memory storage characteristic to achieve fast data processing and have excellent durability.

[0021] The second storage block MB2 may be a FeRAM cell block. The second storage block MB2 includes second sub-blocks SB2 that are symmetrical to each other about the second common electrode PP2. The second sub-block SB2 includes second storage cells MC2 arranged along the second direction D2 and the third direction D3. The second storage cell MC2 may be a FeRAM cell. One second storage cell MC2 may include one second storage transistor MTR2 and a second capacitor CAP2 connected to one end thereof. The second capacitor CAP2 may have a second dielectric layer DL2 ( Figure 2 ), the second dielectric layer DL2 has a single layer or multilayer structure of at least one of a ferroelectric material or an antiferroelectric material. The gate of the second storage transistor MTR2 is connected to the second word line WL2. The second bit line BL2 is connected to the other terminal of the second storage transistor MTR2. The ferroelectric or antiferroelectric material can change its polarization direction by an electric field. Since the polarization direction fixed to one side does not change even when the voltage is cut off, the FeRAM cell can have non-volatile memory storage characteristics. In addition, the FeRAM cell also has excellent power gain characteristics.

[0022] The first memory block MB1 may be connected to the second memory block MB2 through the transfer transistor TTR. That is, the first bit line BL1 belonging to one first sub-block SB1 may be connected to the second bit line BL2 belonging to the second sub-block SB2 adjacent to the first sub-block SB1 through the transfer transistor TTR.

[0023] although Figure 1 Although not shown, the first bit line BL1 of the first memory block MB1 and / or the second bit line BL2 of the second memory block MB2 may be connected to a sense amplifier circuit or a bit line selection circuit. The first word line WL1 of the first memory block MB1 and the second word line WL2 of the second memory block MB2 may be connected to a sub-word line driver circuit or a row decoder circuit.

[0024] According to an example, the first bit line BL1 of the first memory block MB1 may be connected to the sense amplifier circuit or the bit line selection circuit, but the second bit line BL2 of the second memory block MB2 may not be connected to the sense amplifier circuit or the bit line selection circuit. In this case, when a program / read operation is performed on the first memory block MB1, the transfer transistor TTR may be turned off. When a program / read operation is performed on the second memory block MB2, the transfer transistor TTR may be turned on, and a cut-off voltage may be applied to the first word line WL1 of the first memory block MB1.

[0025] The semiconductor memory device according to the present embodiment may include both a first memory block MB1 having DRAM cells and a second memory block MB2 having FeRAM cells, thereby having advantages of both DRAM and FeRAM. Figure 1The semiconductor memory device of the circuit diagram may be implemented as follows.

[0026] Figure 2 is a perspective view of a semiconductor memory device according to an embodiment of the inventive concept. Figure 3 According to the embodiment of the present invention, Figure 2 A cross-sectional view taken along line AA'. Figure 4 yes Figure 3 An enlarged view of portion 'P1'. Figure 5A and Figure 5B yes Figure 3 An enlarged view of portion 'P2'.

[0027] refer to Figure 2 and Figure 3 , the semiconductor memory device 100 according to the present embodiment includes a first semiconductor chip CIP1 and a second semiconductor chip CIP2 bonded on the first semiconductor chip CIP1. The first semiconductor chip CIP1 includes a first substrate 1, a first memory block MB1 and a second memory block MB2 disposed on the first substrate 1, and first to fourth interlayer insulating layers IL1, IL2, IL3 and IL4. The first memory block MB1 and the second memory block MB2 may have the same structure except that the materials of the first dielectric layer DL1 and the second dielectric layer DL2 are different. The first memory block MB1 and the second memory block MB2 may have a symmetrical structure with respect to the second interlayer insulating layer IL2 interposed therebetween.

[0028] The first substrate 1 may include a semiconductor material. The transfer transistor TTR may be disposed on the first substrate 1. The transfer transistor TTR may include a transfer gate and source / drain regions disposed on both sides (e.g., opposite sides) of the transfer gate. The transfer transistor TTR and the first substrate 1 may be covered by a first interlayer insulating layer IL1. Each of the first to fourth interlayer insulating layers IL1 to IL4 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, SiCN, and a low-k porous insulator.

[0029] The first contact CT1 and the second contact CT2 are disposed in the first interlayer insulating layer IL1. The first contact CT1 may connect one terminal (one of the source / drain regions) of the transfer transistor TTR to the first bit line BL1 of the first memory block MB1. The second contact CT2 may connect the other terminal (the other of the source / drain regions) of the transfer transistor TTR to the second bit line BL2 of the second memory block MB2.

[0030] refer to Figure 2 , Figure 3 and Figure 4, the first memory block MB1 and the second memory block MB2 are disposed on the first interlayer insulating layer IL1. The second interlayer insulating layer IL2 is disposed between the first memory block MB1 and the second memory block MB2. The first memory block MB1 includes first memory cells MC1 arranged three-dimensionally from the first direction D1 to the third direction D3. The second memory block MB2 includes second memory cells MC2 arranged three-dimensionally from the first direction D1 to the third direction D3.

[0031] The first memory block MB1 includes first sub-blocks SB1 that are symmetrical to each other about the first common electrode PP1. The first memory block MB1 includes first semiconductor patterns SP1 stacked on the first interlayer insulating layer IL1. Each of the first semiconductor patterns SP1 may have a bar shape elongated in the first direction D1. The first semiconductor pattern SP1 may include at least one of single crystal silicon, polycrystalline silicon, an oxide semiconductor, and a two-dimensional material. The oxide semiconductor may be, for example, indium gallium zinc oxide (IGZO). The two-dimensional material may be MoS 2 , WS 2 、MoSe 2 or WSe 2 The first semiconductor pattern SP1 may include a first channel region CH1 at a center or central region thereof and first and second source / drain regions SD1 and SD2 on both sides (eg, opposite sides) thereof. The first and second source / drain regions SD1 and SD2 may be doped with impurities of the first conductivity type.

[0032] Each of the first semiconductor patterns SP1 has a first end EP1 and a second end EP2 opposite to each other. The first end EP1 of the first semiconductor pattern SP1 may be an end of the first source / drain region SD1. The first end EP1 of the first semiconductor pattern SP1 may contact the first bit line BL1. The first bit line BL1 may contact the upper surface of the first interlayer insulating layer IL1 and may extend from the upper surface of the first interlayer insulating layer IL1 in a vertical third direction D3.

[0033] The second end portion EP2 of the first semiconductor pattern SP1 may be an end portion of the second source / drain region SD2 .

[0034] The second end portion EP2 of the first semiconductor pattern SP1 may be in contact with the first capacitor CAP1 .

[0035] The first capacitor CAP1 may include a first unit electrode BE1, a first dielectric layer DL1, and a first common electrode PP1. The first unit electrode BE1 and the first common electrode PP1 may include metals such as tungsten, aluminum, titanium, tantalum, and ruthenium, respectively. The first dielectric layer DL1 may have a single-layer or multi-layer structure of at least one of silicon oxide and metal oxide. The metal oxide may include at least one of aluminum oxide, hafnium oxide, and zirconium oxide. The first unit electrode BE1 may have a hollow cup shape or a cylindrical shape with one end closed. A portion of the first dielectric layer DL1 and the first common electrode PP1 may be inserted into the first unit electrode BE1 or may extend into the first unit electrode BE1 in other ways.

[0036] The first word line WL1 may be disposed on the first channel region CH1 of the first semiconductor pattern SP1. The first word line WL1 may extend in the second direction D2. The first word line WL1 may be stacked in the third direction D3. Although not shown, an end of the first word line WL1 may have a stepped shape. A gate insulating layer Gox may be interposed between the first semiconductor pattern SP1 and the first word line WL1.

[0037] A first semiconductor pattern SP1 and a portion of a first word line WL1 passing therethrough may constitute Figure 1 The first memory transistor MTR1 connected to the first semiconductor pattern SP1 and the first capacitor CAP1 may constitute one first memory cell MC1.

[0038] The first back gate line BG1 may be disposed below the first channel region CH1 of the first semiconductor pattern SP1. The first back gate line BG1 may extend along the second direction D2. The first back gate line BG1 may be stacked along the third direction D3. Although not shown, an end of the first back gate line BG1 may have a stepped shape. A gate insulating layer Gox may be inserted between the first semiconductor pattern SP1 and the first back gate line BG1. The first back gate line BG1 may adjust a threshold voltage of the first storage transistor MTR1.

[0039] refer to Figure 2 , Figure 3 , Figure 5A and Figure 5B, the second memory block MB2 includes second sub-blocks SB2 that are symmetrical to each other about the second common electrode PP2. The second memory block MB2 includes second semiconductor patterns SP2 stacked on the first interlayer insulating layer IL1. Each of the second semiconductor patterns SP2 may have a bar shape elongated in the first direction D1. The second semiconductor pattern SP2 may include at least one of single crystal silicon, polycrystalline silicon, an oxide semiconductor, and a two-dimensional material. The second semiconductor pattern SP2 may include a second channel region CH2 at its center or central region and a third source / drain region SD3 and a fourth source / drain region SD4 on both sides (e.g., opposite sides) of the second channel region CH2. The third source / drain region SD3 and the fourth source / drain region SD4 may be doped with impurities of the first conductivity type.

[0040] Each of the second semiconductor patterns SP2 has a third end EP3 and a fourth end EP4 opposite to each other. The third end EP3 of the second semiconductor pattern SP2 may be an end of the third source / drain region SD3. The third end EP3 of the second semiconductor pattern SP2 may be in contact with the second bit line BL2. The second bit line BL2 may be in contact with the upper surface of the first interlayer insulating layer IL1, and may extend from the upper surface in a third direction D3 perpendicular to the upper surface of the first interlayer insulating layer IL1. The fourth end EP4 of the second semiconductor pattern SP2 may be an end of the fourth source / drain region SD4. The fourth end EP4 of the second semiconductor pattern SP2 may be in contact with the second capacitor CAP2.

[0041] refer to Figure 5A , the second capacitor CAP2 may include a second unit electrode BE2, a second dielectric layer DL2, and a second common electrode PP2. The second unit electrode BE2 and the second common electrode PP2 may include metals such as tungsten, aluminum, titanium, tantalum, and ruthenium, respectively. The second dielectric layer DL2 may include a single layer or a multilayer structure having at least one of a ferroelectric material and an antiferroelectric material. The ferroelectric material may be HfO 2 、ZrO 2 , Hf x Zr 1-x O 2 、BaTiO 3 、SrTiO 3 and Sr x Ba 1-x TiO 3 At least one of the antiferroelectric materials may be ZrO 2 , Hf y Zr 1-y O 2 、PbZrO 3 and AgNbO 3At least one of , wherein 'x' is 0.5 or more, and 'y' is less than 0.5. The second dielectric layer DL2 may have a thickness of 30 to The second unit electrode BE2 may have a hollow cup shape. A portion of the second dielectric layer DL2 and the second common electrode PP2 may be inserted into the second unit electrode BE2 or may otherwise extend into the second unit electrode BE2.

[0042] refer to Figure 5B , the end of the second unit electrode BE2 may include a leakage material portion LKM. The leakage material portion LKM may include a leakage material. The resistance of the leakage material may be greater than the resistance of the conductive material constituting the second unit electrode BE2, and may be less than the resistance of the ferroelectric material or the antiferroelectric material. When charge accumulates in the second capacitor CAP2, the leakage material portion LKM may prevent the second capacitor CAP2 from being overloaded.

[0043] The second word line WL2 may be disposed on the second channel region CH2 of the second semiconductor pattern SP2. The second word line WL2 may extend along the second direction D2. The second word line WL2 may be stacked along the third direction D3. Although not shown, an end of the second word line WL2 may have a stepped shape. A gate insulating layer Gox may be interposed between the second semiconductor pattern SP2 and the second word line WL2.

[0044] A second semiconductor pattern SP2 and a portion of a second word line WL2 passing therethrough may constitute Figure 1 The second storage transistor MTR2 connected to the second semiconductor pattern SP2 and the second capacitor CAP2 may constitute one second memory cell MC2.

[0045] The second back gate line BG2 may be disposed below the second channel region CH2 of the second semiconductor pattern SP2. The second back gate line BG2 may extend along the second direction D2. The second back gate line BG2 may be stacked along the third direction D3. Although not shown, an end of the second back gate line BG2 may have a stepped shape. A gate insulating layer Gox may be inserted between the second semiconductor pattern SP2 and the second back gate line BG2. The second back gate line BG2 may adjust the threshold voltage of the second storage transistor MTR2.

[0046] refer to Figure 4 , Figure 5A and Figure 5B, the first insulating pattern 3 may be inserted between the first word line WL1 and the second word line WL2 and the first bit line BL1 and the second bit line BL2, and between the first back gate line BG1 and the second back gate line BG2 and the first bit line BL1 and the second bit line BL2. The second insulating pattern 5 may be inserted between the first word line WL1 and the second word line WL2 and the first unit electrode BE1 and the second unit electrode BE2, and between the first back gate line BG1 and the second back gate line BG2 and the first unit electrode BE1 and the second unit electrode BE2. The third insulating pattern 7 may be inserted between the first unit electrode BE1 and the second unit electrode BE2. The first to third insulating patterns 3, 5 and 7 may each independently have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride and silicon oxynitride. The gate insulating layer Gox may cover the side surfaces of the first word line WL1 and the second word line WL2, and may cover the upper and lower surfaces of the first word line WL1 and the second word line WL2 and the first insulating pattern 3. The third insulating pattern 7 may cover the upper surface of the gate insulating layer Gox. The terms “covering” or “surrounding” or “filling” as may be used herein may not require completely covering or surrounding or filling the described elements or layers, but may, for example, mean partially surrounding or covering or filling the described elements or layers, for example, with gaps or other spaces.

[0047] The third interlayer insulating layer IL3 and the fourth interlayer insulating layer IL4 are sequentially stacked on the first memory block MB1 and the second memory block MB2 and the second interlayer insulating layer IL2. The first via VA1 may be disposed in the third interlayer insulating layer IL3. The first wiring WR1 is disposed between the third interlayer insulating layer IL3 and the fourth interlayer insulating layer IL4. The second via VA2 is disposed in the fourth interlayer insulating layer IL4. The first conductive pad CP1 is disposed on the fourth interlayer insulating layer IL4. Each of the first via VA1, the first wiring WR1, the second via VA2, and the first conductive pad CP1 may include a metal such as tungsten, copper, aluminum, ruthenium, tantalum, and titanium.

[0048] The second semiconductor chip CIP2 includes a second substrate 10 and a bit line selection transistor BTR disposed on the lower surface of the second substrate 10. The bit line selection transistor BTR may constitute a sense amplifier circuit or a bit line selection circuit. The lower surface of the second substrate 10 may be sequentially covered by a fifth interlayer insulating layer IL5 and a sixth interlayer insulating layer IL6. Each of the fifth interlayer insulating layer IL5 and the sixth interlayer insulating layer IL6 may have a single layer or multilayer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, SiCN, and a low-k porous insulator.

[0049] The third contact CT3 is disposed in the fifth interlayer insulating layer IL5. The second wiring WR2 is disposed between the fifth interlayer insulating layer IL5 and the sixth interlayer insulating layer IL6. The third via VA3 is disposed in the sixth interlayer insulating layer IL6. The second conductive pad CP2 is disposed at the bottom of the sixth interlayer insulating layer IL6. Each of the third contact CT3, the second wiring WR2, the third via VA3 and the second conductive pad CP2 may include a metal such as tungsten, copper, aluminum, ruthenium, tantalum and titanium.

[0050] The fourth interlayer insulating layer IL4 of the first semiconductor chip CIP1 may contact the sixth interlayer insulating layer IL6 of the second semiconductor chip CIP2. The second conductive pads CP2 of the second semiconductor chip CIP2 may contact the first conductive pads CP1 of the first semiconductor chip CIP1, respectively. A lower portion of one of the first bit lines BL1 may contact the first contact CT1, and an upper portion of one of the first bit lines BL1 may be connected to one terminal of the bit line selection transistor BTR through the first via VA1, the first wiring WR1, the second via VA2, the first conductive pad CP1, the second conductive pad CP2, the third via VA3, the second wiring WR2, and the third contact CT3.

[0051] The semiconductor memory device 100 according to the inventive concept has a three-dimensional structure, which is highly integrated and easy to manufacture.

[0052] In the semiconductor memory device, the first back gate line BG1 and the second back gate line BG2 may be omitted. Alternatively, the first back gate line BG1 and the second back gate line BG2 may be combined with the first word line WL1 and the second word line WL2, respectively, to provide the first word line WL1 and the second word line WL2 of the all-around gate (GAA) structure surrounding the first channel region CH1 and the second channel region CH2.

[0053] 6A to 6F The sequence shows the manufacturing Figure 3 The process of semiconductor memory devices.

[0054] refer to Fig. 6A, prepare a first substrate 1. The first substrate 1 includes a first memory block region MB1R and a second memory block region MB2R. A transfer transistor TTR is formed on the first substrate 1. The transfer transistor TTR may be disposed between the first memory block region MB1R and the second memory block region MB2R. A first interlayer insulating layer IL1 is formed to cover the transfer transistor TTR. First semiconductor patterns SP1 and second semiconductor patterns SP2, first word lines WL1 and WL2, and first back gate lines BG1 and BG2, a gate insulating layer Gox, first to third insulating patterns 3, 5, and 7, first unit electrodes BE1 and BE2, first bit lines BL1 and BL2, and a second interlayer insulating layer IL2 are formed on the first interlayer insulating layer IL1. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed simultaneously at the same height from the same material. The first word lines WL1 and WL2 and the first back gate lines BG1 and BG2 may have the same material and may be formed simultaneously. The first bit line BL1 and the second bit line BL2 may be formed of the same material and may be formed at the same time. The first unit electrode BE1 and the second unit electrode BE2 may be formed of the same material at the same height at the same time. The term "height" used herein may refer to a distance from the underlying substrate 1 in a vertical direction (e.g., D3).

[0055] Two first unit electrodes BE1 located at one height may be formed to face each other. A first empty space 11 may be formed between the first unit electrode BE1 and the third insulating pattern 7 in the first memory block region MB1R. A second empty space 13 may be formed between the second unit electrode BE2 and the third insulating pattern 7 in the second memory block region MB2R. The first empty space 11 is filled with a first sacrificial pattern SCL1. The second empty space 13 is filled with a second sacrificial pattern SCL2. The first sacrificial pattern SCL1 and the second sacrificial pattern SCL2 may be formed of, for example, a spin-on hard mask (SOH) or an amorphous carbon layer (ACL).

[0056] refer to Fig. 6A and Figure 6B , a first mask pattern MK1 is formed on the first memory block region MB1R to cover the first sacrificial pattern SCL1 and the second interlayer insulating layer IL2. The first mask pattern MK1 exposes the second sacrificial pattern SCL2 on the second memory block region MB2R. The second sacrificial pattern SCL2 is removed to expose the second empty space 13. As a result, the inner surface and end of the second unit electrode BE2 and the side surface of the third insulating pattern 7 adjacent thereto may be exposed. The upper surface of the first interlayer insulating layer IL1 may be exposed at the bottom of the second empty space 13.

[0057] refer to Figure 6B and Figure 6C, the second dielectric layer DL2 is conformally covered on the front surface of the first substrate 1 to conformally cover the inner surface and the bottom surface of the second empty space 13. Therefore, the second dielectric layer DL2 can be conformally formed on the inner surface and the end of the second unit electrode BE2, the side surface of the third insulating pattern 7 adjacent thereto, and the upper surface of the first interlayer insulating layer IL1. The second dielectric layer DL2 can be formed of a ferroelectric material or an antiferroelectric material. The second common electrode layer is deposited on the front surface of the first substrate 1 to fill the second empty space 13. Then, an anisotropic etching process can be performed on the second common electrode layer and the second dielectric layer DL2 to remove the second common electrode layer and the second dielectric layer DL2 on the top third insulating pattern 7, the second interlayer insulating layer IL2 and the first mask pattern MK1, while retaining the second dielectric layer DL2 in the second empty space 13 to form a second common electrode PP2.

[0058] refer to Figure 6C and Fig.6D , the first mask pattern MK1 is removed. The second mask pattern MK2 is formed to cover the second memory block region MB2R. The second mask pattern MK2 exposes the first sacrificial pattern SCL1 on the first memory block region MB1R. The first sacrificial pattern SCL1 is removed to expose the first empty space 11. As a result, the inner surface and end of the first unit electrode BE1 and the side surface of the third insulating pattern 7 adjacent thereto may be exposed. The upper surface of the first interlayer insulating layer IL1 may be exposed at the bottom of the first empty space 11.

[0059] refer to Fig.6D and Fig. 6E , the first dielectric layer DL1 conformally covers the front surface of the first substrate 1 to conformally cover the inner surface and the bottom surface of the first empty space 11. Therefore, the first dielectric layer DL1 can be conformally formed on the inner surface and the end of the first unit electrode BE1, the side surface of the third insulating pattern 7 adjacent thereto, and the upper surface of the first interlayer insulating layer IL1. The first dielectric layer DL1 can be formed as a single-layer or multi-layer structure of at least one of silicon oxide and / or metal oxide. The first common electrode layer is deposited on the front surface of the first substrate 1 to fill the first empty space 11. Then, an anisotropic etching process can be performed on the first common electrode layer and the first dielectric layer DL1 to remove the first common electrode layer and the first dielectric layer DL1 on the uppermost third insulating pattern 7, the second interlayer insulating layer IL2 and the second mask pattern MK2, while retaining the first dielectric layer DL1 in the first empty space 11 to form the first common electrode PP1. As a result, a reference electrode PP1 can be formed. Figure 3 A first memory block MB1 and a second memory block MB2 are described.

[0060] refer to Fig. 6F, a third interlayer insulating layer IL3 is formed on the first memory block MB1 and the second memory block MB2 and the second interlayer insulating layer IL2. A first via VA1 is formed in the third interlayer insulating layer IL3. A first wiring WR1 is formed on the third interlayer insulating layer IL3. A second via VA2 and a first conductive pad CP1 are formed in the third interlayer insulating layer IL3. Thus, a first semiconductor chip CIP1 is formed.

[0061] In addition, refer to Fig. 6F , forming a second semiconductor chip CIP2. The second semiconductor chip CIP2 may have a reference Figure 3 The second semiconductor chip CIP2 is flipped and placed on the first semiconductor chip CIP1 so that the second conductive pad CP2 contacts the first conductive pad CP1. Then, a hot pressing process may be performed to manufacture Figure 3 semiconductor memory devices.

[0062] In a semiconductor memory device according to the present invention, Fig. 6A As shown, processes of manufacturing the first unit electrode BE1 and the second unit electrode BE2 on the first substrate 1 in the first memory block region MB1R and the second memory block region MB2R may be identical to each other and may be formed simultaneously, thereby simplifying the process.

[0063] Figure 7 is a cross-sectional view of a semiconductor memory device according to an embodiment of the inventive concept.

[0064] refer to Figure 7 In the semiconductor memory device 101 according to the present embodiment, the first semiconductor chip CIP1 may have a Figure 3 The structure is the same as the structure described above. In the second semiconductor chip CIP2, the bit line selection transistor BTR is arranged on the second substrate 10. The fifth interlayer insulating film IL5 and the sixth interlayer insulating film IL6 are sequentially stacked on the second substrate 10 and cover the bit line selection transistor BTR. The third contact CT3 can be arranged in the fifth interlayer insulating film IL5. The second wiring WR2 is arranged between the fifth interlayer insulating film IL5 and the sixth interlayer insulating film IL6. The lower surface of the second substrate 10 is covered by the protective layer PL. The protective layer PL contacts the fourth interlayer insulating layer IL4 of the first semiconductor chip CIP1. The second conductive pad CP2 is arranged in the protective layer PL. The second conductive pad CP2 can contact the first conductive pad CP1 of the first semiconductor chip CIP1, respectively. The through hole TV penetrates the second substrate 10 and the fifth interlayer insulating layer IL5 to connect the second wiring WR2 to the second conductive pad CP2. The through hole insulating layer TL is inserted between the through hole TV and the second substrate 10. Other structures can be the same as those of reference Figure 3 The structures described are the same / similar.

[0065] Figure 8 is a cross-sectional view of a semiconductor memory device according to an embodiment of the inventive concept.

[0066] refer to Figure 8 , in the semiconductor memory device 102 according to the present embodiment, the first semiconductor chip CIP1 may include a bit line selection transistor BTR, and the second semiconductor chip CIP2 includes a transfer transistor TTR. Specifically, the bit line selection transistor BTR is disposed on the first substrate 1. The first interlayer insulating layer IL1 and the seventh interlayer insulating film IL7 are sequentially stacked on the first substrate 1 to cover the bit line selection transistor BTR. The third contact CT3 is disposed in the first interlayer insulating layer IL1 to be connected to the source / drain region of the bit line selection transistor BTR. The third wiring WR3 is disposed between the first interlayer insulating layer IL1 and the seventh interlayer insulating layer IL7. The fourth via VA4 is disposed in the seventh interlayer insulating layer IL7. One of the first bit lines BL1 is connected to one of the third contacts CT3 through one of the fourth vias VA4 and one of the third wirings WR3.

[0067] The first memory block MB1 and the second memory block MB2 and the second interlayer insulating layer IL2 are disposed on the seventh interlayer insulating layer IL7. The third interlayer insulating layer IL3 and the fourth interlayer insulating layer IL4 are sequentially stacked on the first memory block MB1 and the second memory block MB2 and the second interlayer insulating layer IL2. The first via VA1 may be disposed in the third interlayer insulating layer IL3. The first wiring WR1 is disposed between the third interlayer insulating layer IL3 and the fourth interlayer insulating layer IL4. The second via VA2 is disposed in the fourth interlayer insulating layer IL4. The first conductive pad CP1 is disposed on the fourth interlayer insulating layer IL4. Each of the first via VA1, the first wiring WR1, the second via VA2 and the first conductive pad CP1 may include a metal such as tungsten, copper, aluminum, ruthenium, tantalum and titanium.

[0068] The second semiconductor chip CIP2 includes a second substrate 10 and a transfer transistor TTR arranged on the lower surface of the second substrate 10. The lower surface of the second substrate 10 may be sequentially covered by a fifth interlayer insulating layer IL5 and a sixth interlayer insulating layer IL6. The first contact CT1 and the second contact CT2 are arranged in the fifth interlayer insulating layer IL5. The second wiring WR2 is arranged between the fifth interlayer insulating layer IL5 and the sixth interlayer insulating layer IL6. The third via VA3 is arranged in the sixth interlayer insulating layer IL6. The second conductive pad CP2 is arranged at the lower end of the sixth interlayer insulating layer IL6. Each of the third contact CT3, the second wiring WR2, the third via VA3 and the second conductive pad CP2 may include a metal such as tungsten, copper, aluminum, ruthenium, tantalum and titanium. Other structures may be the same as Figure 3 Same or similar.

[0069] The semiconductor memory device according to the present invention may include a first memory block having a DRAM cell and a second memory block having a FeRAM cell, and may have both volatile memory storage characteristics and non-volatile memory storage characteristics. In addition, the semiconductor memory device is capable of fast data processing, has excellent durability, and has excellent power gain characteristics. In addition, since the first memory block and the second memory block have the same three-dimensional structure, a highly integrated semiconductor memory device can be provided and the highly integrated semiconductor memory device can be manufactured more easily.

[0070] It will be understood that spatially relative terms such as "top," "above," "upper," "upper portion," "upper surface," "bottom," "below," "lower," "lower portion," "lower surface," "side surface," and the like may be represented by reference numerals and with reference to the accompanying drawings, unless otherwise indicated. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the term "below" may include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0071] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the scope of the inventive concept defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept are to be considered in all respects as illustrative and not restrictive, and the scope of the inventive concept is indicated by the appended claims.

Claims

1. A semiconductor memory device, comprising: a first substrate; as well as a first memory block and a second memory block spaced apart from each other on an upper surface of the first substrate and in a first direction, Wherein, the first storage block includes: a first bit line extending perpendicularly to the upper surface of the first substrate, the first bit lines being spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern contacting a side surface of the first bit line, the first semiconductor pattern extending along the first direction; and a first capacitor electrically connected to an end of the first semiconductor pattern, Wherein, the second storage block includes: second bit lines extending perpendicularly to the upper surface of the first substrate, the second bit lines being spaced apart from each other in the second direction; a second semiconductor pattern contacting a side surface of the second bit line, the second semiconductor pattern extending along the first direction; and a second capacitor electrically connected to an end portion of the second semiconductor pattern, wherein the first capacitors each include a first dielectric layer having at least one of silicon oxide or metal oxide, and The second capacitors each include a second dielectric layer having at least one of a ferroelectric material or an antiferroelectric material.

2. The semiconductor memory device according to claim 1, further comprising: a transfer transistor on the first substrate; a first interlayer insulating layer on the first substrate and the transfer transistor, and between the first substrate and the first memory block and the second memory block; first contacts in the first interlayer insulating layer and electrically connecting first source / drain regions of the transfer transistors to the first bit lines, respectively; as well as Second contacts are in the first interlayer insulating layer and electrically connect the second source / drain regions of the transfer transistors to the second bit lines, respectively.

3. The semiconductor memory device according to claim 2, further comprising: a first conductive pad adjacent to an upper surface of the first interlayer insulating layer and contacting the first contact and the second contact, respectively; a second interlayer insulating layer between the first interlayer insulating layer and the first memory block and the second memory block; second conductive pads, adjacent to the lower surface of the second interlayer insulating layer and respectively contacting the first conductive pads; third contacts in the second interlayer insulating layer and electrically connected to the first bit lines, respectively; as well as Fourth contacts are in the second interlayer insulating layer and are electrically connected to the second bit lines, respectively.

4. The semiconductor memory device according to claim 1, further comprising: a second substrate, on the first storage block and the second storage block; as well as A bit line selection transistor is on the second substrate and electrically connected to the first bit line.

5. The semiconductor memory device according to claim 4, further comprising: a first interlayer insulating layer on the first memory block and the second memory block; first conductive pads, adjacent to an upper surface of the first interlayer insulating layer and electrically connected to the first bit lines, respectively; second conductive pads, between the second substrate and the first interlayer insulating layer, wherein the second conductive pads are in contact with the first conductive pads respectively; as well as A through hole electrically connects the second conductive pad to the first source / drain region of the bit line selection transistor.

6. The semiconductor memory device according to claim 1, further comprising: a second substrate, on the first storage block and the second storage block; A bit line selection transistor on the first substrate; as well as a transmission transistor, between the second substrate and the first storage block and the second storage block, The transfer transistor electrically connects the first bit line to the second bit line.

7. The semiconductor memory device according to claim 1, wherein: The first memory block further includes first word lines adjacent to upper surfaces of the first semiconductor patterns, respectively. Wherein, the second storage block further includes second word lines respectively adjacent to the upper surface of the second semiconductor pattern, and The first word line and the second word line extend along the second direction.

8. The semiconductor memory device according to claim 7, wherein: The first storage block further includes first back gate lines respectively adjacent to lower surfaces of the first semiconductor patterns, Wherein, the second storage block further includes second back gate lines respectively adjacent to the lower surface of the second semiconductor pattern, and Wherein, the first back gate line and the second back gate line extend along the second direction.

9. The semiconductor memory device according to claim 1, wherein: The first storage block includes a first left sub-block and a first right sub-block that are symmetrical to each other, wherein each of the first left sub-block and the first right sub-block includes the first bit line, the first semiconductor pattern, and the first capacitor, The second storage block includes a second left sub-block and a second right sub-block that are symmetrical to each other. Each of the second left sub-block and the second right sub-block includes the second bit line, the second semiconductor pattern, and the second capacitor.

10. The semiconductor memory device according to claim 1, wherein The first capacitor further includes a first unit electrode and a first common electrode, respectively, the first unit electrode and the first common electrode being spaced apart from each other by the first dielectric layer between the first unit electrode and the first common electrode, The second capacitor further comprises a second unit electrode and a second common electrode, respectively, and the second unit electrode and the second common electrode are separated from each other by the second dielectric layer between the second unit electrode and the second common electrode. The first unit electrode and the second unit electrode each have a hollow cup shape. The first unit electrode and the second unit electrode respectively include a first conductive material. wherein an end portion of the second unit electrode adjacent to the second common electrode comprises a leakage material portion, wherein the leakage material portion comprises a leakage material, The resistance of the leakage material is greater than the resistance of the first conductive material and less than the resistance of the ferroelectric material or the antiferroelectric material.

11. A semiconductor memory device, comprising: a first substrate; A first memory block and a second memory block spaced apart from each other on an upper surface of the first substrate and in a first direction; as well as a transfer transistor on the first substrate and electrically connecting the first storage block to the second storage block, Wherein, the first storage block includes: a first bit line extending perpendicularly to the upper surface of the first substrate, the first bit lines being spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern contacting a side surface of the first bit line, the first semiconductor pattern extending along the first direction; and a first capacitor electrically connected to an end of the first semiconductor pattern, Wherein, the second storage block includes: second bit lines extending perpendicularly to the upper surface of the first substrate, the second bit lines being spaced apart from each other in the second direction; a second semiconductor pattern contacting a side surface of the second bit line, the second semiconductor pattern extending along the first direction; and a second capacitor electrically connected to an end portion of the second semiconductor pattern, wherein the first capacitors each include a first dielectric layer having at least one of silicon oxide or metal oxide, and The second capacitors each include a second dielectric layer having at least one of a ferroelectric material or an antiferroelectric material.

12. The semiconductor memory device according to claim 11, further comprising: a first interlayer insulating layer on the first substrate and the transfer transistor, and between the first substrate and the first memory block and the second memory block; first contacts in the first interlayer insulating layer and electrically connecting first source / drain regions of the transfer transistors to the first bit lines, respectively; as well as Second contacts are in the first interlayer insulating layer and electrically connect the second source / drain regions of the transfer transistors to the second bit lines, respectively.

13. The semiconductor memory device according to claim 12, further comprising: a first conductive pad adjacent to an upper surface of the first interlayer insulating layer and contacting the first contact and the second contact, respectively; a second interlayer insulating layer between the first interlayer insulating layer and the first memory block and the second memory block; second conductive pads, adjacent to the lower surface of the second interlayer insulating layer and respectively contacting the first conductive pads; third contacts in the second interlayer insulating layer and electrically connected to the first bit lines, respectively; as well as Fourth contacts are in the second interlayer insulating layer and are electrically connected to the second bit lines, respectively.

14. The semiconductor memory device according to claim 11, further comprising: a second substrate, on the first storage block and the second storage block; as well as A bit line selection transistor is on the second substrate and electrically connected to the first bit line.

15. The semiconductor memory device according to claim 14, further comprising: a first interlayer insulating layer on the first memory block and the second memory block; a first conductive pad adjacent to an upper surface of the first interlayer insulating layer and electrically connected to the first bit line; second conductive pads, between the second substrate and the first interlayer insulating layer, wherein the second conductive pads are in contact with the first conductive pads respectively; as well as A through hole electrically connects the second conductive pad to the first source / drain region of the bit line selection transistor.

16. The semiconductor memory device according to claim 11, wherein The first memory block further includes a first word line adjacent to an upper surface of the first semiconductor pattern, Wherein, the second storage block further includes a second word line adjacent to the upper surface of the second semiconductor pattern, and The first word line and the second word line extend along the second direction.

17. The semiconductor memory device according to claim 16, wherein: The first storage block further includes a first back gate line adjacent to a lower surface of the first semiconductor pattern, Wherein, the second storage block further includes a second back gate line adjacent to the lower surface of the second semiconductor pattern, and Wherein, the first back gate line and the second back gate line extend along the second direction.

18. A semiconductor memory device comprising: a first substrate; A first memory block and a second memory block spaced apart from each other on an upper surface of the first substrate and in a first direction; a transfer transistor, on the first substrate, and electrically connecting the first storage block to the second storage block; a second substrate, on the first storage block and the second storage block; as well as A bit line selection transistor, on the second substrate, Wherein, the first storage block includes: a first bit line extending perpendicularly to the upper surface of the first substrate and electrically connected to the bit line selection transistor, the first bit lines being spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern contacting a side surface of the first bit line, the first semiconductor pattern extending along the first direction; a first word line adjacent to an upper surface of the first semiconductor pattern; first gate insulating layers respectively between the first semiconductor patterns and the first word lines; and a first capacitor electrically connected to an end of the first semiconductor pattern, Wherein, the second storage block includes: second bit lines extending perpendicularly to the upper surface of the first substrate, the second bit lines being spaced apart from each other in the second direction; a second semiconductor pattern contacting a side surface of the second bit line, the second semiconductor pattern extending along the first direction; a second word line adjacent to an upper surface of the second semiconductor pattern; a second gate insulating layer, respectively between the second semiconductor pattern and the second word line; and a second capacitor electrically connected to an end portion of the second semiconductor pattern, wherein the first capacitors each include a first dielectric layer having at least one of silicon oxide or metal oxide, and The second capacitors each include a second dielectric layer having at least one of a ferroelectric material or an antiferroelectric material.

19. The semiconductor memory device according to claim 18, wherein: The first storage block further includes a first back gate line adjacent to a lower surface of the first semiconductor pattern, Wherein, the second storage block further includes a second back gate line adjacent to the lower surface of the second semiconductor pattern, and Wherein, the first back gate line and the second back gate line extend along the second direction.

20. The semiconductor memory device according to claim 18, wherein The first capacitor further includes a first unit electrode and a first common electrode, respectively, the first unit electrode and the first common electrode being spaced apart from each other by the first dielectric layer between the first unit electrode and the first common electrode, The second capacitor further comprises a second unit electrode and a second common electrode, respectively, and the second unit electrode and the second common electrode are separated from each other by the second dielectric layer between the second unit electrode and the second common electrode. The first unit electrode and the second unit electrode each have a hollow cup shape. The first unit electrode and the second unit electrode respectively include a first conductive material. wherein an end portion of the second unit electrode adjacent to the second common electrode comprises a leakage material portion, wherein the leakage material portion comprises a leakage material, The resistance of the leakage material is greater than the resistance of the first conductive material and less than the resistance of the ferroelectric material or the antiferroelectric material.

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