Integrated circuit and preparation method thereof, memory and electronic equipment

Abstract

The invention discloses an integrated circuit and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and aims to improve the data retention capability of a device. The integrated circuit can be, for example, a memory array with semi-floating gate transistors as memory cells. Each semi-floating gate transistor comprises a substrate, a first gate dielectric layer, a floating gate and a control gate, the substrate comprises a lower surface and an upper surface which are opposite in the thickness direction of the substrate, the first gate dielectric layer is arranged on the upper surface of the substrate, and a via hole is formed in the first gate dielectric layer. The floating gates are arranged on the first gate dielectric layer, and each floating gate is electrically connected with the substrate through a via hole in the first gate dielectric layer. The control gate is arranged on the floating gate, the floating gate comprises an end part far away from the lower surface of the substrate, and the end part of the floating gate is embedded into the control gate on the section cutting plane of the semi-floating gate transistor. The integrated circuit can be applied to a memory to realize data reading and writing.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an integrated circuit and a method for manufacturing the same, a memory, and an electronic device. Background Art

[0002] A semi-floating gate transistor (SFGT) is a microelectronic device that can replace a storage unit in a dynamic random access memory (DRAM) to prepare a semi-floating gate transistor memory.

[0003] Different from the traditional floating gate transistor, in the semi-floating gate transistor, a via is opened on the gate dielectric layer between the floating gate and the substrate, and the via can be used as a transmission window for the charge between the floating gate and the substrate. The floating gate is used to store the charge, and a coupling capacitor is generated between the control gate and the floating gate to store the data in the coupling capacitor. The capacitance value of the coupling capacitor directly affects its data retention capability.

[0004] Usually, the control gate and the floating gate are facing each other in one direction (the surfaces facing the control gate and the floating gate extend along the plane direction), but as the planar size of the device shrinks, the facing area between the control gate and the floating gate is reduced, resulting in a decrease in the capacitance value of the coupling capacitor, which in turn leads to a decrease in data retention capability. Summary of the invention

[0005] The present application provides an integrated circuit and a method for manufacturing the same, a memory, and an electronic device, aiming to improve the data retention capability of the device.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, an integrated circuit is provided, which includes semi-floating gate transistors arranged at intervals, and the integrated circuit can be a storage array with semi-floating gate transistors as storage units. Each semi-floating gate transistor includes a substrate, a first gate dielectric layer, a floating gate and a control gate, the substrate includes a lower surface and an upper surface opposite to each other along its thickness direction, the first gate dielectric layer is arranged on the upper surface of the substrate, and a via is provided on the first gate dielectric layer. The floating gate is arranged on the first gate dielectric layer, and each floating gate is electrically connected to the substrate through the via on the first gate dielectric layer. The control gate is arranged on the floating gate, and the floating gate includes an end away from the lower surface of the substrate, and on the cross-sectional surface of the semi-floating gate transistor, the end of the floating gate is embedded in the control gate.

[0008] In the integrated circuit provided by the present application, the integrated circuit includes a plurality of semi-floating gate transistors arranged at intervals, in each of which the floating gate is arranged on the first gate dielectric layer, and the floating gate is electrically connected to the substrate through a via on the first gate dielectric layer. The control gate stack is arranged on the floating gate, and on the cross-sectional surface of the semi-floating gate transistor, the end of the floating gate away from the lower surface of the substrate is embedded in the control gate, and the control gate and the floating gate are not only facing each other in the stacking direction, but also facing each other in the spacing arrangement direction of the plurality of semi-floating gate transistors, so that the control gate and the floating gate are facing each other in multiple directions, and the effective facing area between the control gate and the floating gate is increased, which is conducive to increasing the coupling capacitance value between the control gate and the floating gate, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0009] In a possible implementation, the integrated circuit further includes a plurality of shallow trench isolation structures disposed on the substrate, each shallow trench isolation structure being located between the floating gates of two adjacent semi-floating gate transistors. With the lower surface of the substrate as a reference plane, the shallow trench isolation structure includes a first surface away from the reference plane, and the floating gate includes a second surface away from the reference plane, and relative to the reference plane, the first surface is lower than the second surface. The shallow trench isolation structure forms a groove with the two floating gates located on both sides, and at least a portion of the control gate is embedded in the groove.

[0010] The first surface of the shallow trench isolation structure is the top surface of the shallow trench isolation structure, and the second surface of the floating gate is the top surface of the floating gate. By setting the top surface of the shallow trench isolation structure lower than the top surface of the floating gate, the shallow trench isolation structure can form a groove with the floating gates located on both sides thereof, and a portion of the control gate can be embedded in the groove. Along the spacing arrangement direction of the plurality of semi-floating gate transistors, the portion of the control gate embedded in the groove faces the surface of the floating gate, which is beneficial to increase the effective facing area between the control gate and the floating gate, and increase the coupling capacitance value between the control gate and the floating gate.

[0011] In a possible implementation manner, the portion of the control gate embedded in the groove includes a third surface close to the reference plane, and the third surface contacts the first surface.

[0012] It can be understood that, with the surface of the substrate close to the control gate as the upper surface of the substrate, when part of the shallow trench isolation structure is located in the substrate, and relative to the reference plane, the top surface of the shallow trench isolation structure is higher than the upper surface of the substrate, the part of the control gate embedded in the groove can be in direct contact with the shallow trench isolation structure, and there will be no electrical contact between the control gate and the substrate to generate a short circuit.

[0013] In another possible implementation, the integrated circuit also includes a second gate dielectric layer, the portion of the control gate embedded in the groove includes a third surface close to the reference plane, the third surface is lower than the second surface relative to the reference plane, and a portion of the second gate dielectric layer is located between the third surface and the first surface.

[0014] It is understandable that if the shallow trench isolation structure is located in the substrate, the first surface of the shallow trench isolation structure is flush with the upper surface of the substrate, and the portion of the control gate embedded in the groove is in direct contact with the shallow trench isolation structure, there is a possibility that the control gate is in electrical contact with the substrate. By providing a second gate dielectric layer between the third surface of the control gate and the first surface of the shallow trench isolation structure, the vertical distance between the control gate and the shallow trench isolation structure can be increased, and the distance between the control gate and the upper surface of the substrate can be further increased, thereby reducing the risk of short circuit caused by electrical contact between the control gate and the substrate.

[0015] In a possible implementation, part of the first gate dielectric layer is located between the second gate dielectric layer and the first surface. A second gate dielectric layer is disposed between the third surface of the control gate and the first surface of the shallow trench isolation structure. In this case, the first gate dielectric layer is added between the second gate dielectric layer and the first surface, which can further increase the vertical distance between the control gate and the shallow trench isolation structure, further increase the distance between the control gate and the upper surface of the substrate, and reduce the risk of short circuit caused by electrical contact between the control gate and the substrate.

[0016] In a possible implementation manner, the integrated circuit further includes an insulating layer, and the insulating layer is located between the third surface and the second gate dielectric layer.

[0017] On the basis of setting the first gate dielectric layer and the second gate dielectric layer between the third surface of the control gate and the first surface of the shallow trench isolation structure, an insulating layer is added between the third surface of the control gate and the second gate dielectric layer, which can further increase the vertical distance between the control gate and the shallow trench isolation structure, increase the distance between the control gate and the upper surface of the substrate, and reduce the risk of short circuit due to electrical contact between the control gate and the substrate.

[0018] In a possible implementation, the first gate dielectric layer is located between the floating gate and the shallow trench isolation structure, and the first gate dielectric layer extends into the control gate. Along the arrangement direction of the plurality of floating gates, the first gate dielectric layer is also located between the floating gate and the control gate. The second gate dielectric layer is located on a side of the floating gate away from the reference plane, and the second gate dielectric layer is also located between the floating gate and the control gate.

[0019] The insulation between the floating gate and the control gate is achieved by the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer can serve as dielectrics of the coupling capacitor formed by the floating gate and the control gate. The first gate dielectric layer and the second gate dielectric layer can both be made of materials with high dielectric constants, for example, at least one of hafnium oxide, zirconium oxide or hafnium zirconium oxide compounds can be used, which is beneficial to increase the coupling capacitance value between the control gate and the floating gate.

[0020] In another possible implementation, the second gate dielectric layer extends into the control gate, and the second gate dielectric layer includes a first portion and a second portion. Along the arrangement direction of the plurality of floating gates, the first portion is located between the floating gate and the control gate. The second portion is located on the side of the floating gate away from the reference plane, and the second portion is also located between the floating gate and the control gate. That is, the second gate dielectric layer covers the top surface of the floating gate and the portion of the side wall adjacent to the top surface, thereby achieving insulation between the floating gate and the control gate, and the second gate dielectric layer can serve as a medium for the coupling capacitor formed by the floating gate and the control gate. The second gate dielectric layer can be made of a material with a high dielectric constant, for example, at least one of hafnium oxide, zirconium oxide, or hafnium zirconium oxide, which is beneficial to increase the coupling capacitance value between the control gate and the floating gate.

[0021] In a possible implementation, the dielectric constant of the material of the first gate dielectric layer is in the range of 4-100, and the dielectric constant of the material of the second gate dielectric layer is in the range of 4-100.

[0022] In a possible implementation, the material of the control gate includes at least one of tungsten, aluminum, titanium nitride, or tantalum nitride. These materials have low resistance and can reduce the resistance of the control gate.

[0023] One end of the control gate receives a voltage signal at two opposite ends along its extension direction, and this end of the control gate can also be called the "proximal end", and the other end is called the "distal end". The voltage signal is transmitted from the proximal end to the distal end of the control gate. By reducing the resistance of the control gate, the voltage drop caused by the transmission of the voltage signal on the control gate can be reduced. In this way, on the premise that the actual operating voltage received by the distal end of the control gate reaches the rated operating voltage, it is beneficial to increase the number of semi-floating gate transistors corresponding to the same control gate, thereby helping to improve the storage density of the storage array.

[0024] In a second aspect, a method for preparing an integrated circuit is provided, wherein the integrated circuit includes semi-floating gate transistors arranged at intervals, and the method includes: forming a first gate dielectric layer on the upper surface of a substrate, and a via is provided on the first gate dielectric layer, and the via exposes the upper surface of the substrate. A floating gate is formed on the first gate dielectric layer, and the floating gate is electrically connected to the substrate through the hole. A control gate is formed on the floating gate, and the floating gate includes an end away from a reference plane, and on a cross-sectional surface of the semi-floating gate transistor, the end of the floating gate is embedded in the control gate.

[0025] The preparation method provided in the present application forms a floating gate on a first gate dielectric layer, and the floating gate is electrically connected to a substrate through a via hole on the first gate dielectric layer. A control gate is formed on the floating gate, and on a cross-sectional surface of a semi-floating gate transistor, an end of the floating gate away from a reference surface is embedded in the control gate, so that the control gate and the floating gate are not only facing each other in the stacking direction of the two, but also facing each other in the spacing direction of multiple semi-floating gate transistors, so that the control gate and the floating gate are facing each other in multiple directions, and the effective facing area between the control gate and the floating gate is increased, which is conducive to increasing the coupling capacitance value between the control gate and the floating gate, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0026] In a possible implementation, before forming the first gate dielectric layer, a shallow trench isolation structure is formed on the substrate, part of the shallow trench isolation structure is located in the substrate, and the first surface of the shallow trench isolation structure is higher than the upper surface of the substrate. After forming a plurality of floating gates arranged at intervals, the shallow trench isolation structure is located between two adjacent floating gates, and the shallow trench isolation structure is etched to make the first surface lower than the second surface and higher than the upper surface of the substrate relative to the reference plane, and the shallow trench isolation structure and the two floating gates located on both sides form a groove, and finally, a control gate is formed in the groove.

[0027] A shallow trench isolation structure is first formed, and then a floating gate is formed on both sides of the shallow trench isolation structure, and the shallow trench isolation structure is etched so that the top surface of the shallow trench isolation structure is lower than the top surface of the floating gate, and the shallow trench isolation structure and the floating gate form a groove. Finally, a control gate material is filled in the groove so that the control gate is embedded in the groove, and the portion of the control gate embedded in the groove faces the surface of the floating gate, which is beneficial to increase the effective facing area between the control gate and the floating gate, and increase the coupling capacitance value between the control gate and the floating gate, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0028] In a possible implementation, the first gate dielectric layer covers the shallow trench isolation structure, and during the etching of the shallow trench isolation structure, the first gate dielectric layer is also etched to expose the floating gate. Then, a second gate dielectric layer covering the floating gate is formed to insulate the floating gate from the control gate.

[0029] The first gate dielectric layer and the shallow trench isolation structure are made of the same material. By selectively etching the first gate dielectric layer and the shallow trench isolation structure, the portion of the side wall of the floating gate adjacent to the top surface can be exposed, so that the top surface of the shallow trench isolation structure is lower than the top surface of the floating gate. The top surface of the shallow trench isolation structure can form a groove with the floating gates on both adjacent sides.

[0030] In another possible implementation, the first gate dielectric layer includes a third portion and a fourth portion, the third portion covers the first surface of the shallow trench isolation structure, and the fourth portion covers the sidewall of the shallow trench isolation structure. In the process of etching the shallow trench isolation structure, the third portion is also etched, and the fourth portion is retained, and the fourth portion covers the sidewall of the floating gate, exposing the second surface of the floating gate. Then, a second gate dielectric layer covering the second surface of the floating gate is formed. The fourth portion of the first gate dielectric layer and the second gate dielectric layer are used to achieve insulation between the floating gate and the control gate, and when the material of the floating gate includes polysilicon, a thermal oxidation process can be used to form an oxide layer on the second surface of the floating gate, and the oxide layer is used as the second gate dielectric layer, avoiding the use of a thin film deposition process to form the second gate dielectric layer, thereby simplifying the preparation process.

[0031] In a possible implementation, before forming the first gate dielectric layer, a shallow trench isolation structure is formed on the substrate, the shallow trench isolation structure is located in the substrate, and the first surface of the shallow trench isolation structure is flush with the upper surface of the substrate. Then, a floating gate layer is formed, the floating gate layer is located on the substrate and the shallow trench isolation structure, and the portion of the floating gate layer located on the shallow trench isolation structure is removed to obtain a plurality of floating gates arranged at intervals. The shallow trench isolation structure is located between two adjacent floating gates, and relative to the reference plane, the first surface is lower than the second surface, the shallow trench isolation structure and the two floating gates located on both sides form a groove, and finally, a control gate is formed in the groove.

[0032] By forming a floating gate layer covering the shallow trench isolation structure, the top surface of the floating gate layer is higher than the top surface of the shallow trench isolation structure. The portion of the floating gate layer located on the shallow trench isolation structure is removed by etching to form a groove on the floating gate layer. Finally, a control gate material is filled in the groove so that the control gate is embedded in the groove. The portion of the control gate embedded in the groove faces the surface of the floating gate, which is beneficial to increase the effective facing area between the control gate and the floating gate, and increase the coupling capacitance value between the control gate and the floating gate, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0033] In a possible implementation, before forming the control gate, a second gate dielectric layer covering the floating gate is formed. An insulating layer is formed on the first surface of the shallow trench isolation structure, and relative to the reference plane, the surface of the insulating layer away from the reference plane is lower than the second surface of the floating gate to prevent the insulating layer from filling the groove. The insulating layer can increase the vertical distance between the control gate and the shallow trench isolation structure, increase the distance between the control gate and the upper surface of the substrate, and reduce the risk of short circuit caused by electrical contact between the control gate and the substrate.

[0034] In a third aspect, a memory is provided, which includes a controller and the above-mentioned integrated circuit, and the integrated circuit is electrically connected to the controller.

[0035] In a fourth aspect, an electronic device is provided. The electronic device includes a circuit board and the above-mentioned memory, and the memory is electrically connected to the circuit board.

[0036] It can be understood that the beneficial effects that can be achieved by the memory and electronic device provided in the present application can refer to the beneficial effects of the integrated circuit mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structure of the server provided for this application;

[0038] Figure 2 The architecture diagram of the memory provided for this application;

[0039] Figure 3 A partial structural diagram of a storage array provided in this application;

[0040] Figure 4 A schematic diagram of a write operation for a semi-floating gate transistor;

[0041] Figure 5 A schematic diagram of an erase operation for a semi-floating gate transistor;

[0042] Figure 6 for Figure 3 A local enlarged view of the storage array at position M;

[0043] Figure 7A to Figure 7K A diagram of each step of preparing a storage array provided in this application;

[0044] Figure 8 A partial structural diagram of another storage array provided by the present application;

[0045] Figure 9A to Figure 9K A diagram of each step of preparing a storage array provided in this application;

[0046] Fig.10 A partial structural diagram of another storage array provided by the present application;

[0047] Figures 11A to 11J A diagram of each step of preparing a storage array provided in this application;

[0048] Fig.12 A partial structural diagram of another storage array provided by the present application;

[0049] Figures 13A to 13L A diagram of the steps for preparing a storage array provided in this application. DETAILED DESCRIPTION

[0050] In order to solve the problem in the prior art that as the planar size of the semi-floating gate transistor is miniaturized, the area facing the control gate and the floating gate is reduced, resulting in a decrease in the coupling capacitance value and a decrease in the data retention ability of the device, the present application proposes a semi-floating gate transistor, which adopts a design method of embedding the control gate on the top of the floating gate, thereby increasing the effective facing area between the control gate and the floating gate, which is beneficial to increase the coupling capacitance value between the control gate and the floating gate, thereby improving the data retention ability of the device and reducing the refresh power consumption of the device.

[0051] The present application provides an electronic device, which may be, for example, a server, a mobile phone, a tablet computer, a personal computer (PC), a vehicle-mounted electronic product, etc. The present application does not impose any special restrictions on the specific type of the electronic device.

[0052] Figure 1 A schematic diagram of the structure of the server provided for this application.

[0053] See also Figure 1 The server 1 includes a cabinet 11, a circuit board 12 disposed in the cabinet 11, and a chip 13 disposed on the circuit board 12, wherein the chip 13 is electrically connected to the circuit board 12. The circuit board 12 includes but is not limited to a printed circuit board (PCB).

[0054] The chip 13 may be a memory chip, and the memory may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. In terms of packaging form, the memory may include a registered dual in-line memory module (RDIMM), a small outline dual in-line memory module (SO-DIMM), a high bandwidth memory (HBM), etc.

[0055] Take DRAM as an example for explanation. Figure 2 The architecture diagram of the memory provided for this application.

[0056] See also Figure 2 The memory 2 includes a storage array 21 , a row decoder 22 , a column decoder 23 , a controller 24 , a read / write control circuit 25 , and a sense amplifier 26 .

[0057] The memory array 21 includes a plurality of memory cells 210 arranged in an array, and the plurality of memory cells 210 include a plurality of rows arranged along a first direction X and a plurality of columns arranged along a second direction Y. The first direction X intersects with the second direction Y, for example, the two are perpendicular to each other.

[0058] The controller 24 is electrically connected to the row decoder 22 , the column decoder 23 , the storage array 21 , the read / write control circuit 25 , and the sense amplifier 26 , respectively, and is configured to control each circuit.

[0059] The row decoder 22 is electrically connected to the memory array 21 , and is configured to select the memory cells 210 of the corresponding row according to the row address, so as to address the memory cells 210 of the corresponding row.

[0060] The column decoder 23 is electrically connected to the memory array 21. After the memory cells 210 of the corresponding row are selected, the column decoder 23 is configured to select the memory cells 210 of the corresponding column according to the column address, thereby selecting the memory cells 210 that need to be read or written.

[0061] The read / write control circuit 25 is electrically connected to the memory array 21 , and the read / write control circuit 25 is configured to control the selected memory cell 210 to perform a read operation or a write operation.

[0062] The sense amplifier 26 is electrically connected to the storage array 21 and is configured to read, amplify and output the data information stored in the selected storage cell 210 to implement a data read operation; or to input a data signal to the selected storage cell 210 to implement a data write operation.

[0063] In traditional DRAM, the storage unit 210 is based on the architecture of transistors and storage capacitors. As the size of the device decreases, the architecture faces many problems, such as the decrease in the driving current of the transistor, the increase in the leakage current, the smaller and smaller the capacity of the storage capacitor, resulting in a decrease in data retention capability and an increase in power consumption; the device process is complex, and the cost rises sharply, etc. Therefore, a new type of memory is urgently needed to replace DRAM.

[0064] A semi-floating gate transistor (SFGT) is a microelectronic device that can replace the storage unit 210 in a DRAM to prepare a semi-floating gate transistor memory. The semi-floating gate transistor memory can achieve compatibility with the controller 24 and control instructions of the DRAM, that is, the read and write operations of the semi-floating gate transistor memory can be implemented using the controller 24 and control instructions of the DRAM, so as to avoid the use of the semi-floating gate transistor memory to replace the DRAM. The original function or structure of other hardware circuits related to the DRAM is affected as much as possible, thereby reducing the cost and complexity of replacing the DRAM.

[0065] The difference from DRAM is that in the semi-floating gate transistor memory, the storage unit includes a semi-floating gate transistor, and the storage unit does not carry a storage capacitor. The semi-floating gate transistor memory has the characteristics of low operating (read / write) voltage, fast operating speed, unlimited erasable times, small device size and high storage density. In addition, the preparation process of the semi-floating gate transistor is compatible with the currently mature complementary metal oxide semiconductor (CMOS) process, making the preparation process of the semi-floating gate transistor memory simple and low-cost.

[0066] The present application provides a memory array using a semi-floating gate transistor as a memory cell. Figure 3 A partial structural diagram of a storage array provided in this application, Figure 3 The left side is the main view of the storage array, and the right side is a cross-sectional view of the left main view along the section line AA', which shows the "cross-sectional view of multiple half-floating gate transistors".

[0067] See also Figure 3 In the partial structure diagram of the storage array 3, 2 rows×5 columns of half-floating gate transistors T are shown, each row of half-floating gate transistors T is arranged along a first direction X, and each column of half-floating gate transistors T is arranged along a second direction Y, and the present application does not impose any limitation on this.

[0068] Continue to see Figure 3 The memory array 3 includes a substrate 30 , and a source S, a drain D, a floating gate (Semi-Floating Gate, SFG) 31 and a control gate (Controlling Gate, CG) 32 arranged on the substrate 30 .

[0069] Exemplarily, the thickness direction of the substrate 30 may be along the third direction Z, and the substrate 30 includes a lower surface R1 and an upper surface R2 that are opposite to each other along the third direction Z. The substrate 30 includes a p-well 30a and an n-well 30b disposed on the p-well 30a, the material of the p-well 30a includes a p-type semiconductor material, the material of the n-well 30b includes an n-type semiconductor material, and the source S and the drain D are located in the n-well 30b.

[0070] See also Figure 3 The storage array 3 further includes a first gate dielectric layer 33 disposed on the upper surface R2 of the substrate 30, and a via h is provided on the first gate dielectric layer 33. Along the first direction X, a plurality of floating gates 31 are arranged on the first gate dielectric layer 33 at intervals, and each floating gate 31 is electrically connected to the substrate 30 via the via h on the first gate dielectric layer 33, and the via h can be used as a "window" for charge transfer between the floating gate 31 and the substrate 30.

[0071] Exemplarily, the projection of the via h on the plane XY may be in the shape of a circle or a rectangle. When the shape of the via h is a circle, the diameter of the via h is in the range of 10 nm to 20 nm. When the shape of the via h is a rectangle, the length of the via h is in the range of 10 nm to 20 nm, and the width is in the range of 10 nm to 20 nm.

[0072] Continue to see Figure 3 Each control gate 32 corresponds to a plurality of floating gates 31, and the control gate 32 is disposed on the corresponding plurality of floating gates 31. The floating gate 31 includes an end portion A away from the lower surface R1 of the substrate 30. On the cross-sectional surface of the semi-floating gate transistor T, the end portion A of the floating gate 31 is embedded in the control gate 32. In other words, part of the control gate 32 is embedded between two adjacent floating gates 31.

[0073] It can be understood that the “cross-section plane of the semi-floating gate transistor T” is perpendicular to the lower surface R1 of the substrate 30 and parallel to the direction in which the plurality of floating gates 31 are arranged at intervals. Figure 3 From a sectional view, the cross-section plane of the semi-floating gate transistor T is perpendicular to the plane XY and parallel to the first direction X.

[0074] The source S and the drain D are arranged along the second direction Y, and the floating gate 31 is located between the source S and the drain D. Each floating gate 31 and the corresponding source S, drain D and control gate 32 constitute a semi-floating gate transistor T. Since the floating gate 31 and the control gate 32 are stacked along the third direction Z, this structure of the semi-floating gate transistor T can be called a "vertical stacked gate structure".

[0075] Furthermore, along the first direction X, in each row of half-floating gate transistors T, a plurality of half-floating gate transistors T share a source S, a drain D and a control gate 32 , and in the second direction Y, every two adjacent half-floating gate transistors T share a source S.

[0076] Exemplarily, the memory array 3 further includes a second gate dielectric layer 34 . The second gate dielectric layer 34 is located between the floating gate 31 and the control gate 32 and is used for insulating the floating gate 31 from the control gate 32 .

[0077] Exemplarily, part of the floating gate 31 may be embedded in the substrate 30, and part of it may be located on the surface of the substrate 30. By increasing the size of the floating gate 31 along the third direction Z, the area of ​​the floating gate 31 along the plane XY can be reduced while ensuring that the performance of the floating gate 31 in storing charges remains unchanged, which is beneficial to the miniaturization of the device.

[0078] See also Figure 3 The semi-floating gate transistor T further includes a spacer layer 35. Along the second direction Y, the spacer layer 35 is located between two adjacent semi-floating gate transistors T to separate the floating gates 31 and the control gates 32 of the two adjacent semi-floating gate transistors T to achieve insulation between the devices.

[0079] Figure 4 A schematic diagram of a write operation for a semi-floating gate transistor; Figure 5 Schematic diagram of the erase operation of a semi-floating gate transistor.

[0080] See also Figure 4 , a write operation voltage is applied to the control gate 32, source S and drain D of the semi-floating gate transistor T. For example, the operation voltage received by the control gate 32 is -1.5V, the source S is connected to the ground terminal GND, and the operation voltage of the drain D is 3V. Under the action of the electric field, positive charges enter the floating gate 31 from the drain D and the n-well 30b through the hole h. The positive charge in the floating gate 31 increases, causing the threshold voltage of the semi-floating gate transistor T to decrease, thereby realizing data writing (writing data "1").

[0081] Based on this, by applying a fixed read operation voltage to the control gate 32, source S and drain D of the semi-floating gate transistor T, the threshold voltage of the semi-floating gate transistor T is low, so that the semi-floating gate transistor T is fully turned on, and a large drain-source current I is generated between the drain D and the source S. ds , at this time the data "1" can be read.

[0082] See also Figure 5 , an operating voltage is applied to the control gate 32, source S and drain D of the semi-floating gate transistor T. For example, the operating voltage received by the control gate 32 is 1.2V, the source S is connected to the ground terminal GND, and the operating voltage of the drain D is 0.6V. Under the action of the electric field, the positive charge enters the n-well 30b and the drain D from the floating gate 31 through the hole h, and the positive charge in the floating gate 31 is reduced, so that the threshold voltage of the semi-floating gate transistor T is increased, thereby realizing data erasure (also known as: writing data "0").

[0083] Based on this, by applying the same read operation voltage to the control gate 32, source S and drain D of the semi-floating gate transistor T, due to the high threshold voltage of the semi-floating gate transistor T, the semi-floating gate transistor T is not fully turned on, and a small drain-source current I is generated between the drain D and the source S. ds , at this time the data "0" can be read.

[0084] During the data writing process of the semi-floating gate transistor T, more positive charges are stored in the floating gate 31, and a coupling capacitor can be generated between the control gate 32 and the floating gate 31. It can be understood that the data is stored in the coupling capacitor, and the capacitance value of the coupling capacitor directly affects its data retention capability.

[0085] In the present application, the control gate 32 of the semi-floating gate transistor T is stacked on the floating gate 31, and on the cross-section of the semi-floating gate transistor T, the end A of the floating gate 31 away from the lower surface R1 of the substrate 30 is embedded in the control gate 32. Compared with the prior art in which the control gate and the floating gate are only facing each other on the upper surface in the third direction Z, in the present application, the control gate 32 and the floating gate 31 are not only facing each other on the upper surface in the third direction Z, but also facing each other on the upper surface in the first direction X, so that the control gate 32 and the floating gate 31 are facing each other on the surface in multiple directions, and the effective facing area between the control gate 32 and the floating gate 31 is increased, which is conducive to increasing the coupling capacitance value between the control gate 32 and the floating gate 31, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0086] In addition, the source S and the drain D are arranged along the second direction Y, the floating gate 31 also includes a side wall close to the drain D, and the control gate 32 can also cover the side wall of the floating gate 31 close to the drain D, so that the control gate 32 and the floating gate 31 are directly opposite to each other on the upper surface in the second direction Y, and the effective facing area between the control gate 32 and the floating gate 31 is increased, which is beneficial to increase the coupling capacitance value between the control gate 32 and the floating gate 31.

[0087] For convenience of introduction Figure 3 The local structural features of the storage array are shown in Figure 6 exhibit Figure 3 A partial enlarged view of the storage array at M in FIG.

[0088] See also Figure 6 The memory array 3 further includes a shallow trench isolation structure (STI) 34 disposed on the substrate 30 , and a plurality of shallow trench isolation structures 36 are arranged at intervals along the first direction X. The shallow trench isolation structures 36 and the floating gates 31 are alternately disposed along the first direction X, and each shallow trench isolation structure 36 is located between two adjacent floating gates 31 , and the shallow trench isolation structure 36 is used to isolate two adjacent floating gates 31 .

[0089] For the sake of convenience of explanation, taking the lower surface R1 of the substrate 30 as the reference plane R1, the shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1, and the floating gate 31 includes a second surface P2 away from the reference plane R1. Relative to the reference plane R1, the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate 31. In other words, the top surface of the shallow trench isolation structure 36 is lower than the top surface of the floating gate 31.

[0090] By setting the top surface of the shallow trench isolation structure 36 lower than the top surface of the floating gate 31, the shallow trench isolation structure 36 can form a groove C with the floating gates 31 located on both sides thereof, and at least a portion of the control gate 32 can be embedded in the groove C. Along the first direction X, the portion of the control gate 32 embedded in the groove C is opposite to the surface of the floating gate 31, which is beneficial to increase the effective facing area between the control gate 32 and the floating gate 31, and increase the coupling capacitance value between the control gate 32 and the floating gate 31.

[0091] See also Figure 6 , the second gate dielectric layer 34 extends into the control gate 32, and the second gate dielectric layer 34 can be disassembled into a first portion 34a and a second portion 34b. Along the first direction X, the first portion 34a is located between the floating gate 31 and the control gate 32. Along the third direction Z, the second portion 34b is located between the floating gate 31 and the control gate 32. It can also be said that the second gate dielectric layer 34 covers the top surface of the floating gate 31 and the part of the side wall adjacent to the top surface, thereby achieving insulation between the floating gate 31 and the control gate 32. The second gate dielectric layer 34 can serve as a medium for the coupling capacitor formed by the floating gate 31 and the control gate 32.

[0092] Exemplarily, the second gate dielectric layer 34 serves as a dielectric of the coupling capacitor, and the dielectric constant of the material thereof may range from 4 to 100, for example, the dielectric constant of the material thereof is 4, 20, 50, 80 or 100, etc. The second gate dielectric layer 34 may be made of a material with a high dielectric constant, for example, at least one of hafnium oxide, zirconium oxide or hafnium zirconium oxide, which is beneficial to increase the coupling capacitance value between the control gate 32 and the floating gate 31.

[0093] See also Figure 6 The portion of the control gate 32 embedded in the groove C includes a third surface P3 close to the reference plane R1. Relative to the reference plane R1, the third surface P3 of the control gate 32 is lower than the second surface P2 of the floating gate 31. Part of the second gate dielectric layer 34 is also located between the third surface P3 and the first surface P1.

[0094] Exemplarily, the substrate 30 also includes an upper surface R2 close to the control gate 32, a portion of the shallow trench isolation structure 36 is located within the substrate 30, and relative to the reference plane R1, a first surface P1 of the shallow trench isolation structure 36 is higher than the upper surface R2 of the substrate 30, which is equivalent to that a portion of the shallow trench isolation structure 36 is embedded in the substrate 30 and a portion extends out of the substrate 30.

[0095] It is understandable that if the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30 , the portion of the control gate 32 embedded in the groove C may be in direct contact with the shallow trench isolation structure 36 , and there is a possibility that the control gate 32 is in electrical contact with the substrate 30 .

[0096] By setting a second gate dielectric layer 34 between the third surface P3 of the control gate 32 and the first surface P1 of the shallow trench isolation structure 36, the distance between the control gate 32 and the shallow trench isolation structure 36 along the third direction Z can be increased, and the distance between the control gate 32 and the upper surface R2 of the substrate 30 can be further increased, thereby reducing the risk of short circuit due to electrical contact between the control gate 32 and the substrate 30.

[0097] See also Figure 6 , the control gate 32 extends along the first direction X, and in each row of half-floating gate transistors T, a plurality of half-floating gate transistors T share one control gate 32. Generally, one end of the control gate 32 receives a voltage signal at two opposite ends along the first direction X, and this end of the control gate 32 may be referred to as a "near end", and the other end may be referred to as a "far end", and the voltage signal is transmitted from the near end to the far end of the control gate 32.

[0098] At present, the material of the control gate is mostly polysilicon, which has a large resistance. A voltage drop (IR drop) will occur during the transmission of the voltage signal on the control gate, causing the actual operating voltage received by the far end of the control gate to be lower than the rated operating voltage, which will affect the read / write operation of the semi-floating gate transistor for data.

[0099] In the present application, the control gate 32 is made of metal or metal nitride. For example, the material of the control gate 32 includes at least one of tungsten, aluminum, titanium nitride or tantalum nitride, which can reduce the resistance of the control gate 32 and reduce the voltage drop caused by the voltage signal transmitted on the control gate 32. In this way, on the premise that the actual operating voltage received by the far end of the control gate 32 reaches the rated operating voltage, it is beneficial to increase the number of semi-floating gate transistors T corresponding to the same control gate 32, thereby facilitating the improvement of the storage density of the storage array 3.

[0100] Combination of the above Figure 3 to Figure 6 The structural features of the memory array provided by the present application and the working principle of the semi-floating gate transistor in the memory array are introduced. Next, Figure 7A to Figure 7K Further Introduction Figure 3 The method for preparing the memory array is shown.

[0101] The method for preparing the storage array comprises the following steps:

[0102] See also Fig. 7AA plurality of first trenches 40 are formed on the substrate 30 , and the plurality of first trenches 40 are arranged along the first direction X. The depth of the first trenches 40 is greater than the depth of the n-well 30 b , and the bottom of the first trenches 40 is located in the p-well 30 a .

[0103] For example, a thin film deposition process may be used to sequentially form a first mask layer 41 and a second mask layer 42 on the substrate 30. The material of the first mask layer 41 may include silicon oxide, and the material of the second mask layer 42 may include silicon nitride. Then, a photolithography process is used to etch the first mask layer 41 and the second mask layer 42 to form vias, so that the first mask layer 41 and the second mask layer 42 are patterned. Finally, the substrate 30 is etched using the first mask layer 41 and the second mask layer 42 as masks to form a plurality of first trenches 40 on the substrate 30.

[0104] See also Figure 7B , depositing a dielectric material, which may include silicon dioxide, so that the dielectric material fills a plurality of first trenches 40 to form a shallow trench isolation structure 36 in the first trench 40, wherein the shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1. The area between two adjacent shallow trench isolation structures 36 in the substrate 30 may be defined as an active area AA, and the active area AA of the substrate 30 may be used as a channel for charge migration of the semi-floating gate transistor T.

[0105] It can be understood that before removing the first mask layer 41 and the second mask layer 42, the dielectric material is deposited, and the dielectric material also fills the vias on the first mask layer 41 and the second mask layer 42, so that the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface of the second mask layer 42. Therefore, the first surface P1 of the shallow trench isolation structure 36 is higher than the upper surface R2 of the substrate 30, so that the shallow trench isolation structure 36 is partially embedded in the substrate 30 and partially extends out of the substrate 30.

[0106] See also Figure 7B and Figure 7C , remove the first mask layer 41 and the second mask layer 42, and then, use a photolithography process to etch the substrate 30 to form a second trench 43. The depth of the second trench 43 is greater than the depth of the n-well 30b and less than the depth of the shallow trench isolation structure 36, and the bottom of the second trench 43 is located in the p-well 30a.

[0107] See also Figure 7C and Fig.7D , a first gate dielectric layer 33 is formed on the substrate 30 , a plurality of via holes h are opened on the first gate dielectric layer 33 , and the via holes h expose the substrate 30 .

[0108] For example, a thin film deposition process may be used to form the first gate dielectric layer 33, the first gate dielectric layer 33 covers the upper surface R2 of the substrate 30, the surface of the second trench 43 and the shallow trench isolation structure 36, and the thickness of the first gate dielectric layer 33 does not exceed half of the width of the second trench 43, so that the first gate dielectric layer 33 does not fill the second trench 43. Then, a photolithography process is used to etch the first gate dielectric layer 33 to form a via h exposing the substrate 30.

[0109] The material of the first gate dielectric layer 33 may include at least one of silicon dioxide, silicon nitride or silicon oxynitride.

[0110] Alternatively, when the material of the substrate 30 includes silicon, a thermal oxidation process can be used to form an oxide layer on the upper surface R2 of the substrate 30 and the surface of the second trench 43. The oxide layer can serve as the first gate dielectric layer 33, that is, the material of the first gate dielectric layer 33 includes silicon dioxide.

[0111] See also Fig.7D and Fig. 7E , a thin film deposition process is used to form a floating gate material layer, the floating gate material may include polysilicon doped with P-type ions, for example, the floating gate material layer fills the second trench 43 and covers the first gate dielectric layer 33. Then, a chemical mechanical polishing (CMP) process is used to grind the upper surface of the floating gate material layer to make the upper surface of the floating gate material layer flat. Finally, a photolithography process is used to etch the floating gate material layer, so that the floating gate material layer is disconnected along the second direction Y to form a floating gate layer 310, and the floating gate layer 310 includes a second surface P2.

[0112] The floating gate layer 310 is formed on the first gate dielectric layer 33, and the floating gate layer 310 is electrically connected to the substrate 30 through the via h on the first gate dielectric layer 33. Part of the floating gate layer 310 fills the second trench 43, and part of the floating gate layer 310 is located on the upper surface R2 of the substrate 30. By increasing the size of the floating gate layer 310 along the third direction Z, it is beneficial to improve the performance of the floating gate layer 310 in storing charges, or to reduce the area of ​​the floating gate layer 310 along the plane XY, which is beneficial to the miniaturization of the device.

[0113] See also Figure 7F In the case where the materials of the first gate dielectric layer 33 and the shallow trench isolation structure 36 are both silicon dioxide and the material of the floating gate layer 310 is polysilicon, silicon dioxide and polysilicon have an etching selectivity ratio. Based on this, the first gate dielectric layer 33 and the shallow trench isolation structure 36 can be selectively etched to expose the portion of the sidewall adjacent to the top surface of the floating gate layer 310, so that the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate layer 310 and higher than the upper surface R2 of the substrate 30, and the top of the shallow trench isolation structure 36 can form a groove C with the floating gate layer 310.

[0114] See also Figure 7G A second gate dielectric layer 34 is formed by a thin film deposition process. The second gate dielectric layer 34 covers the upper surface and the portion of the sidewall adjacent to the top surface of the floating gate layer 310, the upper surface R2 of the substrate 30, and the first surface P1 of the shallow trench isolation structure 36.

[0115] The material of the second gate dielectric layer 34 may include at least one of silicon dioxide, silicon nitride, or silicon oxynitride.

[0116] See also Figure 7H , a control gate material layer is deposited by a thin film deposition process. The control gate material may include at least one of tungsten, aluminum, titanium nitride or tantalum nitride. The control gate material layer fills the groove C and covers the second gate dielectric layer 34. Then, a chemical mechanical polishing process is used to grind the upper surface of the control gate material layer to make the upper surface of the control gate material layer flat. Finally, a photolithography process is used to etch the control gate material layer so that the control gate material layer is disconnected along the second direction Y to form a control gate layer 320.

[0117] See also Fig.7I , the control gate layer 320, the second gate dielectric layer 34, the floating gate layer 310 and the first gate dielectric layer 33 are etched to form a third trench 44 along the second direction Y to disconnect two adjacent rows of half-floating gate transistors T.

[0118] See also Figure 7J A spacer 35 is formed on the sidewall of the third trench 44, and the bottom of the spacer 35 exposes the substrate 30. The spacer 35 can separate two adjacent rows of half-floating gate transistors T, thereby achieving insulation between the two adjacent rows of half-floating gate transistors T.

[0119] See also Figure 7K Using the spacer layer 35 as a mask, an ion implantation process is used to implant n-type ions into the n-well 30 b of the substrate 30 , and an annealing treatment is performed to form a source S and a drain D in the substrate 30 . Two adjacent rows of half-floating gate transistors T share a source S.

[0120] In the present application, the n-well 30b of the substrate 30 is disposed on the p-well 30a, and by injecting n-type ions into the n-well 30b, a source S and a drain D are formed in the n-well 30b, and the formed semi-floating-gate transistor T is an N-type transistor. In other examples, the p-well of the substrate 30 may also be disposed on the n-well, and by injecting p-type ions into the p-well, a source S and a drain D are formed in the p-well, and the formed semi-floating-gate transistor T is a P-type transistor.

[0121] The above-mentioned preparation method provided by the present application first forms a plurality of shallow trench isolation structures 36 arranged at intervals along the first direction X, then forms a floating gate layer 310 between two adjacent shallow trench isolation structures 36, and etches the shallow trench isolation structure 36 so that the top surface of the shallow trench isolation structure 36 is lower than the top surface of the floating gate layer 310, and the shallow trench isolation structure 36 and the floating gate layer 310 form a groove C. Finally, the control gate material is filled in the groove C, so that the control gate layer 320 is embedded in the groove C. Along the first direction X, the portion of the control gate layer 320 embedded in the groove C faces the surface of the floating gate layer 310, which is beneficial to increase the effective facing area between the control gate layer 320 and the floating gate layer 310. After the semi-floating gate transistor T is prepared, the coupling capacitance value between the control gate 32 and the floating gate 31 can be increased, thereby improving the data retention capability of the device and reducing the refresh power consumption of the device.

[0122] Figure 8 A partial structural diagram of another storage array provided in this application, Figure 3 The difference between the storage array in FIG. 1 and FIG. 2 is that the portion of the sidewall of the floating gate 31 adjacent to the top surface covers the first gate dielectric layer 33 , and the portion of the control gate 32 embedded in the groove C is in direct contact with the shallow trench isolation structure 36 .

[0123] See also Figure 8 , along the first direction X, the first gate dielectric layer 33 is located between the floating gate 31 and the shallow trench isolation structure 36, and the first gate dielectric layer 33 extends into the control gate 32, and the first gate dielectric layer 33 is also located between the floating gate 31 and the control gate 32. Along the third direction Z, the second gate dielectric layer 34 is located between the floating gate 31 and the control gate 32, and the first gate dielectric layer 33 and the second gate dielectric layer 34 are used to achieve insulation between the floating gate 31 and the control gate 32. The first gate dielectric layer 33 and the second gate dielectric layer 34 can serve as the medium of the coupling capacitor formed by the floating gate 31 and the control gate 32.

[0124] Exemplarily, the first gate dielectric layer 33 and the second gate dielectric layer 34 serve as dielectrics of the coupling capacitor, and the dielectric constant of the material of the first gate dielectric layer 33 may range from 4 to 100, for example, the dielectric constant of the material of the first gate dielectric layer 33 is 4, 20, 50, 80 or 100, etc.; the dielectric constant of the material of the second gate dielectric layer 34 may range from 4 to 100, for example, the dielectric constant of the material of the second gate dielectric layer 34 is 4, 20, 50, 80 or 100, etc. The first gate dielectric layer 33 and the second gate dielectric layer 34 may both be made of materials with high dielectric constants, for example, the first gate dielectric layer 33 and the second gate dielectric layer 34 may both be made of at least one of hafnium oxide, zirconium oxide or hafnium zirconium oxide, which is beneficial to increase the coupling capacitance value between the control gate 32 and the floating gate 31.

[0125] Continue to see Figure 8The portion of the control gate 32 embedded in the groove C contacts the shallow trench isolation structure 36 , and the third surface P3 of the control gate 32 contacts the first surface P1 of the shallow trench isolation structure 36 .

[0126] Exemplarily, the substrate 30 further includes an upper surface R2 close to the control gate 32 , and the first surface P1 of the shallow trench isolation structure 36 is higher than the upper surface R2 of the substrate 30 , that is, part of the shallow trench isolation structure 36 is embedded in the substrate 30 and part of it extends out of the substrate 30 .

[0127] By setting the first surface P1 of the shallow trench isolation structure 36 higher than the upper surface R2 of the substrate 30 , the distance between the control gate 32 and the upper surface R2 of the substrate 30 can be increased, thereby reducing the risk of short circuit caused by electrical contact between the control gate 32 and the substrate 30 .

[0128] This application also provides Figure 8 A method for preparing a storage array, Figure 9A to Figure 9K The steps of preparing the storage array provided in this application are as follows Figure 7A to Figure 7K The preparation method of the storage array is similar, the difference is Fig.9F and Figure 9G These two steps: during the etching of the shallow trench isolation structure 36, only the portion of the first gate dielectric layer 33 covering the top surface of the shallow trench isolation structure 36 is etched, and the portion of the first gate dielectric layer 33 covering the side wall of the shallow trench isolation structure 36 is retained. The retained portion of the first gate dielectric layer 33 will cover the side wall of the floating gate layer 310, exposing the top surface of the floating gate layer 310. When the material of the floating gate layer 310 includes polysilicon, a thermal oxidation process can be used to form an oxide layer on the top surface of the floating gate layer 310, and the oxide layer is used as the second gate dielectric layer 34.

[0129] The method for preparing the storage array comprises the following steps:

[0130] See also Fig. 9A A plurality of first trenches 40 are formed on the substrate 30 , and the plurality of first trenches 40 are arranged along the first direction X. The depth of the first trenches 40 is greater than the depth of the n-well 30 b , and the bottom of the first trenches 40 is located in the p-well 30 a .

[0131] See also Fig. 9B , depositing a dielectric material, which may include silicon dioxide, so that the dielectric material fills the plurality of first trenches 40 to form a shallow trench isolation structure 36 in the first trenches 40, wherein the shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1, and the first surface P1 of the shallow trench isolation structure 36 is higher than the upper surface R2 of the substrate 30, thereby achieving a state in which a portion of the shallow trench isolation structure 36 is embedded in the substrate 30 and a portion thereof extends out of the substrate 30.

[0132] See also Fig. 9B and Fig. 9C , remove the first mask layer 41 and the second mask layer 42, and then, use a photolithography process to etch the substrate 30 to form a second trench 43. The depth of the second trench 43 is greater than the depth of the n-well 30b and less than the depth of the shallow trench isolation structure 36, and the bottom of the second trench 43 is located in the p-well 30a.

[0133] See also Fig.9D A first gate dielectric layer 33 is formed on the substrate 30, and a plurality of via holes h are formed on the first gate dielectric layer 33, and the via holes h expose the substrate 30. The first gate dielectric layer 33 includes a third portion 33a and a fourth portion 33b, wherein the third portion 33a covers the first surface P1 of the shallow trench isolation structure 36, and the fourth portion 33b covers the sidewall of the shallow trench isolation structure 36.

[0134] See also Fig.9D and Fig.9E , a thin film deposition process is used to form a floating gate material layer, the floating gate material may include polysilicon doped with P-type ions, for example, the floating gate material layer fills the second trench 43 and covers the first gate dielectric layer 33. Then, a chemical mechanical polishing (CMP) process is used to grind the upper surface of the floating gate material layer to make the upper surface of the floating gate material layer flat. Finally, a photolithography process is used to etch the floating gate material layer, so that the floating gate material layer is disconnected along the second direction Y to form a floating gate layer 310, and the floating gate layer 310 includes a second surface P2.

[0135] See also Fig.9F , using a photolithography process, the third portion 33a of the first gate dielectric layer 33 and the shallow trench isolation structure 36 are etched, and the fourth portion 33b of the first gate dielectric layer 33 is retained. The fourth portion 33b covers the sidewall of the floating gate layer 310 and exposes the second surface P2 of the floating gate layer 310.

[0136] By etching the shallow trench isolation structure 36 , the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate layer 310 and higher than the upper surface R2 of the substrate 30 . The top of the shallow trench isolation structure 36 can form a groove C with the floating gate layer 310 .

[0137] See also Fig.9F and Figure 9G When the material of the floating gate layer 310 includes polysilicon, a thermal oxidation process can be used to form an oxide layer on the second surface P2 of the floating gate layer 310, and the oxide layer can be used as the second gate dielectric layer 34, that is, the material of the second gate dielectric layer 34 includes silicon dioxide.

[0138] See also Figure 9H, a control gate material layer is deposited by a thin film deposition process. The control gate material may include, for example, at least one of tungsten, aluminum, titanium nitride or tantalum nitride. The control gate material layer fills the groove C and covers the fourth portion 33b of the first gate dielectric layer 33 and the second gate dielectric layer 34. Then, a chemical mechanical polishing process is used to grind the upper surface of the control gate material layer to make the upper surface of the control gate material layer flat. Finally, a photolithography process is used to etch the control gate material layer to disconnect the control gate material layer along the second direction Y to form a control gate layer 320.

[0139] See also Fig.9I , the control gate layer 320, the second gate dielectric layer 34, the floating gate layer 310 and the first gate dielectric layer 33 are etched to form a third trench 44 along the second direction Y to disconnect two adjacent rows of half-floating gate transistors T.

[0140] See also Figure 9J A spacer 35 is formed on the sidewall of the third trench 44, and the bottom of the spacer 35 exposes the substrate 30. The spacer 35 can separate two adjacent rows of half-floating gate transistors T, thereby achieving insulation between the two adjacent rows of half-floating gate transistors T.

[0141] See also Figure 9K Using the spacer layer 35 as a mask, an ion implantation process is used to implant n-type ions into the n-well 30 b of the substrate 30 , and an annealing treatment is performed to form a source S and a drain D in the substrate 30 . Two adjacent rows of half-floating gate transistors T share a source S.

[0142] The above-mentioned preparation method provided by the present application, during the process of etching the shallow trench isolation structure 36, only the portion of the first gate dielectric layer 33 covering the top surface of the shallow trench isolation structure 36 is etched, and the portion of the first gate dielectric layer 33 covering the side wall of the shallow trench isolation structure 36 is retained. The retained portion of the first gate dielectric layer 33 will cover the side wall of the floating gate layer 310, exposing the top surface of the floating gate layer 310. In the case where the material of the floating gate layer 310 includes polysilicon, a thermal oxidation process can be used to form an oxide layer on the top surface of the floating gate layer 310, and the oxide layer is used as the second gate dielectric layer 34, thereby avoiding the use of a thin film deposition process to form the second gate dielectric layer 34, thereby simplifying the preparation process.

[0143] Fig.10 A partial structural diagram of another storage array provided in this application, Figure 3 The difference between the storage array and the control gate 32 is that the top surface of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30, and the first gate dielectric layer 33 also covers the top surface of the shallow trench isolation structure 36, so that the first gate dielectric layer 33 is added between the control gate 32 and the shallow trench isolation structure 36.

[0144] See also Fig.10The shallow trench isolation structure 36 is located in the substrate 30 , and the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30 .

[0145] The third surface P3 of the control gate 32 is lower than the second surface P2 of the floating gate 31 and higher than the first surface P1 of the shallow trench isolation structure 36 . Parts of the first gate dielectric layer 33 and the second gate dielectric layer 34 are also located between the third surface P3 and the first surface P1 .

[0146] It is understandable that the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30 . If the portion of the control gate 32 embedded in the groove C is in direct contact with the shallow trench isolation structure 36 , the control gate 32 may be in electrical contact with the substrate 30 .

[0147] Based on this, a first gate dielectric layer 33 and a second gate dielectric layer 34 are arranged between the third surface P3 of the control gate 32 and the first surface P1 of the shallow trench isolation structure 36, which can increase the distance between the control gate 32 and the shallow trench isolation structure 36 along the third direction Z, and further increase the distance between the control gate 32 and the upper surface R2 of the substrate 30, thereby reducing the risk of short circuit due to electrical contact between the control gate 32 and the substrate 30.

[0148] This application also provides Fig.10 A method for preparing a storage array, Figures 11A to 11J The steps of preparing the storage array provided in this application are as follows Figure 3 The preparation method of the storage array is similar, the difference is Fig.11A , Fig. 11B and Fig.11E These two steps: forming a shallow trench isolation structure 36, the top surface of the shallow trench isolation structure 36 is roughly flush with the upper surface R2 of the substrate 30, and then forming a floating gate layer 310 covering the shallow trench isolation structure 36, the top surface of the floating gate layer 310 is higher than the top surface of the shallow trench isolation structure 36, and removing the portion of the floating gate layer 310 located on the shallow trench isolation structure 36 by etching to form a groove C on the floating gate layer 310.

[0149] The method for preparing the storage array comprises the following steps:

[0150] See also Fig.11A A plurality of first trenches 40 are formed on the substrate 30 , and the plurality of first trenches 40 are arranged along the first direction X. The depth of the first trenches 40 is greater than the depth of the n-well 30 b , and the bottom of the first trenches 40 is located in the p-well 30 a .

[0151] For example, a thin film deposition process may be used to sequentially form a first mask layer 41 and a second mask layer 42 on the substrate 30. The material of the first mask layer 41 may include silicon oxide, and the material of the second mask layer 42 may include silicon nitride. Then, a photolithography process is used to etch the first mask layer 41 and the second mask layer 42 to form vias, so that the first mask layer 41 and the second mask layer 42 are patterned. Finally, the substrate 30 is etched using the first mask layer 41 and the second mask layer 42 as masks to form a plurality of first trenches 40 on the substrate 30.

[0152] See also Fig.11A and Fig. 11B , depositing a dielectric material, which may include silicon dioxide, so that the dielectric material fills the plurality of first trenches 40 to form a shallow trench isolation structure 36 in the first trenches 40, wherein the shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1, the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30, and the entire shallow trench isolation structure 36 is embedded in the substrate 30.

[0153] It can be understood that the thickness of the first mask layer 41 and the second mask layer 42 is set to be relatively thin, and the dielectric material is deposited to fill the first trench 40 to form a shallow trench isolation structure 36 in the first trench 40. Then, in the process of etching away the first mask layer 41 and the second mask layer 42, the top of the shallow trench isolation structure 36 is also etched, so that the first surface P1 of the shallow trench isolation structure 36 is substantially flush with the upper surface R2 of the substrate 30, so that the shallow trench isolation structure 36 is completely embedded in the substrate 30.

[0154] See also Fig. 11C , the substrate 30 is etched by photolithography to form a second trench 43. The depth of the second trench 43 is greater than the depth of the n-well 30b and less than the depth of the shallow trench isolation structure 36, and the bottom of the second trench 43 is located in the p-well 30a.

[0155] See also Fig. 11C and Fig.11D A first gate dielectric layer 33 is formed on the substrate 30. A plurality of via holes h are formed on the first gate dielectric layer 33, and the via holes h expose the substrate 30. The first gate dielectric layer 33 covers the upper surface R2 of the substrate 30, the surface of the second trench 43 and the shallow trench isolation structure 36.

[0156] See also Fig.11D and Fig.11E, a thin film deposition process is used to form a floating gate material layer. The floating gate material may include polysilicon doped with P-type ions, for example. The floating gate material layer fills the second trench 43 and covers the first gate dielectric layer 33. Then, a chemical mechanical polishing process is used to grind the upper surface of the floating gate material layer to make the upper surface of the floating gate material layer flat. Finally, a photolithography process is used to etch the floating gate material layer so that the floating gate material layer is disconnected along the second direction Y, and the portion of the floating gate material layer located on the shallow trench isolation structure 36 is removed to form a floating gate layer 310. The floating gate layer 310 includes a second surface P2.

[0157] Since the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate layer 310 , a groove C may be formed between the top of the shallow trench isolation structure 36 and the floating gate layer 310 by removing the portion of the floating gate material layer located on the shallow trench isolation structure 36 .

[0158] See also Fig.11F A second gate dielectric layer 34 is formed by a thin film deposition process. The second gate dielectric layer 34 covers the upper surface and the portion of the sidewall adjacent to the top surface of the floating gate layer 310 , and covers the first gate dielectric layer 33 .

[0159] See also Fig.11G , a control gate material layer is deposited by a thin film deposition process. The control gate material may include at least one of tungsten, aluminum, titanium nitride or tantalum nitride. The control gate material layer fills the groove C and covers the second gate dielectric layer 34. Then, a chemical mechanical polishing process is used to grind the upper surface of the control gate material layer to make the upper surface of the control gate material layer flat. Finally, a photolithography process is used to etch the control gate material layer so that the control gate material layer is disconnected along the second direction Y to form a control gate layer 320.

[0160] See also Fig.11H , the control gate layer 320, the second gate dielectric layer 34, the floating gate layer 310 and the first gate dielectric layer 33 are etched to form a third trench 44 along the second direction Y to disconnect two adjacent rows of half-floating gate transistors T.

[0161] See also Fig.11I A spacer 35 is formed on the sidewall of the third trench 44, and the bottom of the spacer 35 exposes the substrate 30. The spacer 35 can separate two adjacent rows of half-floating gate transistors T, thereby achieving insulation between the two adjacent rows of half-floating gate transistors T.

[0162] See also Fig.11J Using the spacer layer 35 as a mask, an ion implantation process is used to implant n-type ions into the n-well 30 b of the substrate 30 , and an annealing treatment is performed to form a source S and a drain D in the substrate 30 . Two adjacent rows of half-floating gate transistors T share a source S.

[0163] The above-mentioned preparation method provided by the present application forms a floating gate layer 310 covering a plurality of shallow trench isolation structures 36, and the top surface of the floating gate layer 310 is higher than the top surface of the shallow trench isolation structure 36. The portion of the floating gate layer 310 located on the shallow trench isolation structure 36 is removed by etching to form a groove C on the floating gate layer 310.

[0164] Fig.12 A partial structural diagram of another storage array provided in this application, Fig.10 The difference between the memory array and the memory array is that an insulating layer 37 is provided between the control gate 32 and the shallow trench isolation structure 36 .

[0165] See also Fig.12 The memory array 3 further includes an insulating layer 37 , a portion of the first gate dielectric layer 33 and the second gate dielectric layer 34 , and the insulating layer 37 is located between the third surface P3 of the control gate 32 and the first surface P1 of the shallow trench isolation structure 36 .

[0166] It is understandable that the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30 . If the portion of the control gate 32 embedded in the groove C is in direct contact with the shallow trench isolation structure 36 , the control gate 32 may be in electrical contact with the substrate 30 .

[0167] On the basis of setting the first gate dielectric layer 33 and the second gate dielectric layer 34 between the third surface P3 of the control gate 32 and the first surface P1 of the shallow trench isolation structure 36, an insulating layer 37 is added between the third surface P3 of the control gate 32 and the second gate dielectric layer 34, which can further increase the distance between the control gate 32 and the shallow trench isolation structure 36 along the third direction Z, increase the distance between the control gate 32 and the upper surface R2 of the substrate 30, and reduce the risk of short circuit due to electrical contact between the control gate 32 and the substrate 30.

[0168] This application also provides Fig.12 A method for preparing a storage array, Figures 13A to 13L The steps of preparing the storage array provided in this application are as follows Fig.10 The preparation method of the storage array is similar, the difference is Figure 13G and Fig.13H These two steps: using a thin film deposition process to form an insulating material layer 370 covering the groove C. Then, etching the insulating material layer 370 to form an insulating layer 37, the surface P4 of the insulating layer 37 away from the reference plane R1 is lower than the second surface P2 of the floating gate layer 310, so as to prevent the insulating layer 37 from filling the groove C.

[0169] The method for preparing the storage array comprises the following steps:

[0170] See also Fig.13AA plurality of first trenches 40 are formed on the substrate 30 , and the plurality of first trenches 40 are arranged along the first direction X. The depth of the first trenches 40 is greater than the depth of the n-well 30 b , and the bottom of the first trenches 40 is located in the p-well 30 a .

[0171] See also Fig. 13B , depositing a dielectric material, which may include silicon dioxide, so that the dielectric material fills the plurality of first trenches 40 to form a shallow trench isolation structure 36 in the first trenches 40, wherein the shallow trench isolation structure 36 includes a first surface P1 away from the reference plane R1, the first surface P1 of the shallow trench isolation structure 36 is flush with the upper surface R2 of the substrate 30, and the entire shallow trench isolation structure 36 is embedded in the substrate 30.

[0172] See also Fig. 13C , the substrate 30 is etched by photolithography to form a second trench 43. The depth of the second trench 43 is greater than the depth of the n-well 30b and less than the depth of the shallow trench isolation structure 36, and the bottom of the second trench 43 is located in the p-well 30a.

[0173] See also Fig. 13C and Fig.13D A first gate dielectric layer 33 is formed on the substrate 30. A plurality of via holes h are formed on the first gate dielectric layer 33, and the via holes h expose the substrate 30. The first gate dielectric layer 33 covers the upper surface R2 of the substrate 30, the surface of the second trench 43 and the shallow trench isolation structure 36.

[0174] See also Fig.13D and Fig.13E , a thin film deposition process is used to form a floating gate material layer. The floating gate material may include polysilicon doped with P-type ions, for example. The floating gate material layer fills the second trench 43 and covers the first gate dielectric layer 33. Then, a chemical mechanical polishing process is used to grind the upper surface of the floating gate material layer to make the upper surface of the floating gate material layer flat. Finally, a photolithography process is used to etch the floating gate material layer so that the floating gate material layer is disconnected along the second direction Y, and the portion of the floating gate material layer located on the shallow trench isolation structure 36 is removed to form a floating gate layer 310. The floating gate layer 310 includes a second surface P2.

[0175] Since the first surface P1 of the shallow trench isolation structure 36 is lower than the second surface P2 of the floating gate layer 310 , a groove C may be formed between the top of the shallow trench isolation structure 36 and the floating gate layer 310 by removing the portion of the floating gate material layer located on the shallow trench isolation structure 36 .

[0176] See also Fig.13F A second gate dielectric layer 34 is formed by a thin film deposition process. The second gate dielectric layer 34 covers the upper surface and the portion of the sidewall adjacent to the top surface of the floating gate layer 310 , and covers the first gate dielectric layer 33 .

[0177] See also Figure 13G , a thin film deposition process is used to form an insulating material layer 370 covering the groove C, and the material of the insulating material layer 370 is different from that of the second gate dielectric layer 34 .

[0178] See also Fig.13H The material of the insulating material layer 370 is different from that of the second gate dielectric layer 34, and the two have an etching selectivity ratio. Based on this, the insulating material layer 370 can be selectively etched to form an insulating layer 37. The surface P4 of the insulating layer 37 away from the reference plane R1 is lower than the second surface P2 of the floating gate layer 310 to prevent the insulating layer 37 from filling the groove C.

[0179] See also Fig.13I , a control gate material layer is deposited by a thin film deposition process. The control gate material may include at least one of tungsten, aluminum, titanium nitride or tantalum nitride. The control gate material layer fills the groove C and covers the second gate dielectric layer 34. Then, a chemical mechanical polishing process is used to grind the upper surface of the control gate material layer to make the upper surface of the control gate material layer flat. Finally, a photolithography process is used to etch the control gate material layer so that the control gate material layer is disconnected along the second direction Y to form a control gate layer 320.

[0180] See also Fig.13J , the control gate layer 320, the second gate dielectric layer 34, the floating gate layer 310 and the first gate dielectric layer 33 are etched to form a third trench 44 along the second direction Y to disconnect two adjacent rows of half-floating gate transistors T.

[0181] See also Figure 13K A spacer 35 is formed on the sidewall of the third trench 44, and the bottom of the spacer 35 exposes the substrate 30. The spacer 35 can separate two adjacent rows of half-floating gate transistors T, thereby achieving insulation between the two adjacent rows of half-floating gate transistors T.

[0182] See also Figure 13L Using the spacer layer 35 as a mask, an ion implantation process is used to implant n-type ions into the n-well 30 b of the substrate 30 , and an annealing treatment is performed to form a source S and a drain D in the substrate 30 . Two adjacent rows of half-floating gate transistors T share a source S.

[0183] The above-mentioned preparation method provided by the present application adopts a thin film deposition process to form an insulating material layer 370 covering the groove C. The material of the insulating material layer 370 is different from the material of the second gate dielectric layer 34, and the two have an etching selectivity. Based on this, the insulating material layer 370 can be selectively etched to form an insulating layer 37. The surface P4 of the insulating layer 37 away from the reference plane R1 is lower than the second surface P2 of the floating gate layer 310 to prevent the insulating layer 37 from filling the groove C. The insulating layer 37 can increase the distance between the control gate 32 and the shallow trench isolation structure 36 along the third direction Z, increase the distance between the control gate 32 and the upper surface R2 of the substrate 30, and reduce the risk of short circuit caused by electrical contact between the control gate 32 and the substrate 30.

[0184] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An integrated circuit, characterized in that: The integrated circuit comprises half-floating gate transistors arranged at intervals; the half-floating gate transistors comprise: A substrate, comprising a lower surface and an upper surface opposite to each other along a thickness direction thereof; A first gate dielectric layer is disposed on the upper surface of the substrate, and a via hole is formed in the first gate dielectric layer; A floating gate is disposed on the first gate dielectric layer, and the floating gate is electrically connected to the substrate through the via hole; A control gate, disposed on the floating gate; The floating gate includes an end portion away from the lower surface of the substrate, and on a cross-sectional plane of the semi-floating gate transistor, the end portion of the floating gate is embedded in the control gate.

2. The integrated circuit according to claim 1, characterized in that The integrated circuit further comprises a shallow trench isolation structure, which is arranged on the substrate, and the shallow trench isolation structure is located between the floating gates of two adjacent semi-floating gate transistors; Taking the lower surface of the substrate as a reference plane, the shallow trench isolation structure includes a first surface away from the reference plane, the floating gate includes a second surface away from the reference plane, and relative to the reference plane, the first surface is lower than the second surface; The shallow trench isolation structure and the two floating gates located on both sides form a groove, and a portion of the control gate is embedded in the groove.

3. The integrated circuit according to claim 2, characterized in that The portion of the control gate embedded in the groove includes a third surface close to the reference plane, and the third surface is in contact with the first surface.

4. The integrated circuit according to claim 2, characterized in that The integrated circuit further includes a second gate dielectric layer; The portion of the control gate embedded in the groove includes a third surface close to the reference plane. Relative to the reference plane, the third surface is lower than the second surface. Part of the second gate dielectric layer is located between the third surface and the first surface.

5. The integrated circuit according to claim 4, characterized in that A portion of the first gate dielectric layer is located between the second gate dielectric layer and the first surface.

6. The integrated circuit according to claim 4 or 5, characterized in that: The integrated circuit further includes an insulating layer, and the insulating layer is located between the third surface and the second gate dielectric layer.

7. The integrated circuit according to any one of claims 2 to 6, characterized in that: The first gate dielectric layer is located between the floating gate and the shallow trench isolation structure, and the first gate dielectric layer extends into the control gate; along the arrangement direction of the plurality of floating gates, the first gate dielectric layer is also located between the floating gate and the control gate; The integrated circuit further comprises a second gate dielectric layer, wherein the second gate dielectric layer is located on a side of the floating gate away from the reference plane, and the second gate dielectric layer is also located between the floating gate and the control gate.

8. The integrated circuit according to any one of claims 2 to 6, characterized in that: The integrated circuit further includes a second gate dielectric layer, and the second gate dielectric layer extends into the control gate; The second gate dielectric layer includes a first portion and a second portion, and along the arrangement direction of the plurality of floating gates, the first portion is located between the floating gate and the control gate; The second portion is located on a side of the floating gate away from the reference plane, and the second portion is also located between the floating gate and the control gate.

9. The integrated circuit according to claim 7 or 8, characterized in that: The dielectric constant of the material of the first gate dielectric layer is in the range of 4-100; the dielectric constant of the material of the second gate dielectric layer is in the range of 4-100.

10. The integrated circuit according to any one of claims 1 to 9, characterized in that: The material of the control gate includes at least one of tungsten, aluminum, titanium nitride or tantalum nitride.

11. A method for preparing an integrated circuit, characterized in that: The integrated circuit includes half-floating gate transistors arranged at intervals; The preparation method comprises: A first gate dielectric layer is formed on a substrate, wherein a via is provided on the first gate dielectric layer; the substrate comprises a lower surface and an upper surface opposite to each other along a thickness direction thereof, the first gate dielectric layer is located on the upper surface of the substrate, and the via exposes the upper surface of the substrate; forming a floating gate on the first gate dielectric layer, wherein the floating gate is electrically connected to the substrate through the via hole; forming a control gate on the floating gate; The floating gate includes an end portion away from the lower surface of the substrate, and on a cross-sectional plane of the semi-floating gate transistor, the end portion of the floating gate is embedded in the control gate.

12. The preparation method according to claim 11, characterized in that: Before forming the first gate dielectric layer, the preparation method further includes: A shallow trench isolation structure is formed on the substrate, wherein a portion of the shallow trench isolation structure is located in the substrate; taking the lower surface of the substrate as a reference surface, the shallow trench isolation structure includes a first surface away from the reference surface, and relative to the reference surface, the first surface is higher than the upper surface of the substrate; The floating gate includes a second surface away from the reference plane, and after the floating gates are formed and arranged at intervals, the shallow trench isolation structure is located between two adjacent floating gates, and the preparation method further includes: Etching the shallow trench isolation structure so that the first surface is lower than the second surface and higher than the upper surface of the substrate relative to the reference surface; Forming the control gate includes: The control gate is formed on the first surface of the shallow trench isolation structure and the second surface of the floating gate.

13. The preparation method according to claim 11, characterized in that: Before forming the first gate dielectric layer, the preparation method further includes: A shallow trench isolation structure is formed on the substrate, wherein the shallow trench isolation structure is located in the substrate; taking the lower surface of the substrate as a reference surface, the shallow trench isolation structure includes a first surface away from the reference surface, and the first surface is flush with the upper surface of the substrate; Forming the floating gate includes: forming a floating gate layer, wherein the floating gate layer is located on the substrate and the shallow trench isolation structure; Removing a portion of the floating gate layer located on the shallow trench isolation structure to obtain the floating gates arranged at intervals, wherein the floating gates include a second surface away from the reference plane; the shallow trench isolation structure is located between two adjacent floating gates, and relative to the reference plane, the first surface is lower than the second surface; Forming the control gate includes: The control gate is formed on the first surface of the shallow trench isolation structure and the second surface of the floating gate.

14. A memory, characterized in that: include: An integrated circuit as claimed in any one of claims 1 to 10; A controller, wherein the integrated circuit is electrically connected to the controller.

15. An electronic device, characterized in that: include: The memory as claimed in claim 14; A circuit board, wherein the memory is electrically connected to the circuit board.

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