Semiconductor device, memory system, and manufacturing method of semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device, a memory system, and a manufacturing method of a semiconductor device. The semiconductor device includes a first stack structure, a second stack structure located on one side of the first stack structure, wherein the first stack structure and the second stack structure each include a plurality of first dielectric layers and a plurality of material layers arranged alternately, and the material layers include insulating portions and conductive portions, and a contact structure including an inner core portion penetrating through the first stack structure and the second stack structure and connected to the conductive portion of one of the material layers in the first stack structure, and an outer ring portion penetrating through the second stack structure and sleeved on the inner core portion and connected to the conductive portion of one of the material layers in the second stack structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Technology

[0002] As the number of stacked layers in 3D memory (e.g., 3D NAND memory) increases, its storage density continues to improve. However, this leads to an increase in the area required for the step regions in 3D memory, thereby increasing the area and manufacturing cost of 3D memory. Summary of the Invention

[0003] This application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above-mentioned problems in related technologies or other problems in the art.

[0004] In a first aspect, some embodiments of this application provide a semiconductor device. The semiconductor device includes: a first stacked structure; a second stacked structure located on one side of the first stacked structure, wherein both the first and second stacked structures include alternating first dielectric layers and multiple material layers, and the material layers include insulating portions and conductive portions; and a contact structure including: an inner core extending through the first and second stacked structures and connected to the conductive portion of one material layer in the first stacked structure; and an outer ring extending through the second stacked structure and sleeved on the inner core, connected to the conductive portion of one material layer in the second stacked structure.

[0005] In some embodiments, the contact structure further includes an insulating layer located between the inner core and the outer ring.

[0006] In some embodiments, the inner core includes a first part and a second part, the first part penetrating through a first stacked structure and the second part penetrating through a second stacked structure. On a plane perpendicular to the stacking direction, the size of the second part is smaller than the size of the first part. An insulating layer is sleeved on the outer wall of the second part and contacts the inner wall of the outer ring and the end face of the first part near the second stacked structure.

[0007] In some embodiments, the first stacked structure has multiple first steps, the second stacked structure has multiple second steps, and the top layer of both the first and second steps is a material layer; the inner core passes through the first and second steps and is connected to the conductive portion of the top material layer in the first step, and the outer ring is connected to the conductive portion of the top material layer in the second step.

[0008] In some embodiments, the semiconductor device further includes: a first insulating structure covering the top side of a plurality of first steps; and a second insulating structure covering the top side of a plurality of second steps; wherein the inner core portion also passes through the second insulating structure and the first insulating structure, and the outer ring portion also passes through the second insulating structure.

[0009] In some embodiments, the semiconductor device further includes: a first gate line gap structure that penetrates the second stacked structure and the first stacked structure and extends along a first direction perpendicular to the stacking direction; wherein the first stacked structure and the second stacked structure are located between adjacent first gate line gap structures.

[0010] In some embodiments, in the top layer of material in the first step and the second step, the conductive portion includes: a first conductive portion located on one side of the insulating portion in a first direction; and a second conductive portion located on both sides of the insulating portion along the first direction; wherein the second conductive portion is in contact with an adjacent first gate wire slot structure.

[0011] In some implementations, the thickness of the first conductive portion is greater than the thickness of the second conductive portion in the stacking direction.

[0012] In some embodiments, the first stacked structure and the second stacked structure have at least two partitions in the second direction, a first dielectric layer and a material layer constitute a stack pair, the first stacked structures in adjacent partitions differ by one stack pair, and the second stacked structures in adjacent partitions differ by one stack pair; within the same partition, the number of stack pairs between adjacent first steps is equal to the number of partitions, and the number of stack pairs between adjacent second steps is equal to the number of partitions; the second direction is perpendicular to the first direction and the stacking direction.

[0013] In some embodiments, the semiconductor device further includes a second gate gap structure that extends through the second stacked structure and the first stacked structure and along a first direction, for dividing the first stacked structure and the second stacked structure into at least two partitions.

[0014] In some embodiments, in the material layers of the first and second steps other than the top material layer, the conductive portion is located on both sides of the insulating portion along the first direction and is in contact with the second gate slot structure and / or the first gate slot structure.

[0015] In some embodiments, the semiconductor device has a step region and a core region, with a first stacked structure and a second stacked structure located in the step region and extending to the core region. The portions of the first stacked structure and the second stacked structure located in the core region include a plurality of alternately arranged second dielectric layers and a plurality of gate layers. The plurality of first dielectric layers are respectively connected to the plurality of second dielectric layers, and the plurality of gate layers are respectively connected to each conductive portion in the plurality of material layers. The semiconductor device further includes a plurality of channel structures that penetrate the portions of the first stacked structure and the second stacked structure located in the core region.

[0016] Secondly, some embodiments of this application provide a memory system. The memory system includes: a three-dimensional memory, including at least one semiconductor device as mentioned in any of the embodiments described above; and a controller coupled to the three-dimensional memory for controlling the storage of data in the three-dimensional memory.

[0017] Thirdly, some embodiments of this application provide a method for manufacturing a semiconductor device. The method includes: forming a first contact hole penetrating a first initial stacked structure; forming a second initial stacked structure on one side of the first initial stacked structure, both the first and second initial stacked structures including alternating dielectric layers and multiple sacrificial layers; forming a second contact hole penetrating the second initial stacked structure to the first contact hole; replacing a portion of each sacrificial layer with a conductive portion to form a material layer, wherein the remaining portion of the sacrificial layer serves as an insulating portion of the material layer; and forming an outer ring portion in the second contact hole connected to a conductive portion in one of the material layers, and forming an inner core portion in the first and second contact holes connected to a conductive portion in one of the material layers.

[0018] In some embodiments, the manufacturing method further includes: forming a first filler sacrificial layer in a first contact hole; and forming a second filler sacrificial layer in a second contact hole; wherein forming an outer ring portion connected to a conductive portion in a material layer in the second contact hole, and forming an inner core portion connected to a conductive portion in a material layer in the first and second contact holes includes: removing the second filler sacrificial layer to the first filler sacrificial layer; sequentially forming a conductive layer and a first insulating layer on the inner wall of the second contact hole and the surface of the first filler sacrificial layer; removing portions of the first insulating layer and the conductive layer located on the surface of the first filler sacrificial layer, and removing the end of the conductive layer near the first filler sacrificial layer to form an outer ring portion; forming a second insulating layer on the inner wall of the first insulating layer and the end face of the outer ring portion near the first filler sacrificial layer; and removing the first filler sacrificial layer and forming an inner core portion inside the second insulating layer and in the first contact hole.

[0019] In some implementations, the materials of the first filling sacrificial layer and the second filling sacrificial layer are different from each other.

[0020] In some embodiments, a first initial stacked structure is formed on one side of the substrate, a first contact hole extends into the substrate, and the substrate is made of the same material as the first filling sacrificial layer. The manufacturing method further includes oxidizing the substrate exposed to the first contact hole.

[0021] In some embodiments, the manufacturing method further includes: etching a first initial stack structure to form a plurality of first steps; forming a first step sacrificial layer covering the top surface of the plurality of first steps; etching a second initial stack structure to form a plurality of second steps; forming a second step sacrificial layer covering the top surface of the plurality of second steps; and forming a first gate wire gap penetrating the second step sacrificial layer, the second initial stack structure, the first step sacrificial layer, and the first initial stack structure; wherein replacing a portion of each sacrificial layer with a conductive portion to form a material layer includes: using the first gate wire gap, replacing the edge portion of the sacrificial layer near the first gate wire gap, the first step sacrificial layer and the second step sacrificial layer, and the portion of the sacrificial layer covered by the first step sacrificial layer and the second step sacrificial layer, respectively, with a conductive portion.

[0022] In some embodiments, the first step sacrificial layer and the second step sacrificial layer exposed on the sidewall of the first gate wire gap have an oxide layer; wherein, using the first gate wire gap, replacing the edge portion of the sacrificial layer near the first gate wire gap, the first step sacrificial layer and the second step sacrificial layer, and the portion of the sacrificial layer respectively covered by the first step sacrificial layer and the second step sacrificial layer with a conductive portion includes: using the first gate wire gap, removing a first sub-portion of the sacrificial layer near the first gate wire gap and exposing the first step sacrificial layer and the second step sacrificial layer; removing the first step sacrificial layer and the second step sacrificial layer; removing a second sub-portion of the sacrificial layer near the first gate wire gap and the portion of the sacrificial layer respectively covered by the first step sacrificial layer and the second step sacrificial layer to form a sacrificial gap; and forming a conductive portion in the sacrificial gap; wherein, in the extension direction perpendicular to the first gate wire gap, the total thickness of the first sub-portion and the second sub-portion is equal to the thickness of the edge portion.

[0023] In some embodiments, the manufacturing method further includes: forming a second gate wire gap penetrating the second step sacrificial layer, the second initial stack structure, the first step sacrificial layer, and the first initial stack structure, wherein the second gate wire gap extends along a first direction and divides the first initial stack structure and the second initial stack structure into at least two partitions arranged in a second direction, the first direction and the second direction being perpendicular to each other with the stacking direction; and wherein replacing a portion of each sacrificial layer with a conductive portion to form a material layer includes: using the second gate wire gap, replacing the edge portion of the sacrificial layer near the second gate wire gap, the first step sacrificial layer and the second step sacrificial layer, and the portions of the sacrificial layer covered by the first step sacrificial layer and the second step sacrificial layer, respectively, with conductive portions.

[0024] According to at least one embodiment of this application, the semiconductor device, memory system, and semiconductor device manufacturing method provided by this application connect the inner core of the contact structure to the conductive portion of a material layer in the first stacked structure, and connect the outer ring of the contact structure to the conductive portion of a material layer in the second stacked structure. This allows the conductive portions of two vertically arranged stacked structures to be led out using a single contact structure, thereby reducing the number of contact structures and the area occupied by the contact structures and semiconductor devices. This is beneficial for reducing manufacturing costs and improving economic efficiency. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0026] Figure 1A This is a top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0027] Figure 1B It is along Figure 1A The diagram shows a cross-section taken by line A-A';

[0028] Figure 1C yes Figure 1B A magnified view of a portion of region D is shown;

[0029] Figure 1D It is along Figure 1A The diagram shows a cross-section taken by line B-B'.

[0030] Figure 1E and Figure 1F They are along Figure 1D The diagram shows cross-sections taken by lines E-E' and F-F'.

[0031] Figure 1G It is along Figure 1A The diagram shows a cross-section taken by line C-C';

[0032] Figure 1H This is a partial cross-sectional schematic diagram of a channel structure provided in an embodiment of this application;

[0033] Figure 2A This is a top view schematic diagram of a semiconductor device provided in another embodiment of this application;

[0034] Figure 2B It is along Figure 2A The diagram shows a cross-section taken by line A-A';

[0035] Figure 2C It is along Figure 2AThe diagram shows a cross-section taken by line B-B'.

[0036] Figure 2D and Figure 2E They are along Figure 2C The diagram shows cross-sections taken by lines E-E' and F-F'.

[0037] Figure 3 This is a block diagram of a system with a memory system provided in an embodiment of this application;

[0038] Figure 4A and Figure 4B This is a schematic diagram of the memory system provided in an embodiment of this application;

[0039] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; and

[0040] Figures 6 to 13G This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the manufacturing process. Detailed Implementation

[0041] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first stacking structure discussed herein may also be referred to as the second stacking structure, and vice versa.

[0043] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0044] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0045] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0046] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0047] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0048] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] This application provides a semiconductor device. Figures 1A to 1H This is a schematic diagram of the structure of the semiconductor device provided in an embodiment of this application. Wherein, Figure 1A This is a top view schematic diagram of the semiconductor device provided in the embodiments of this application. Figure 1B It is along Figure 1A The diagram shows a cross-section taken by line A-A'. Figure 1C yes Figure 1B A magnified schematic diagram of a portion of region D is shown. Figure 1D It is along Figure 1A The diagram shows a cross-section taken by line B-B'. Figure 1E and Figure 1F They are along Figure 1D The diagram shows cross-sections taken by lines E-E' and F-F'. Figure 1GIt is along Figure 1A The diagram shows a cross-section taken by line C-C'. Figure 1H This is a partial cross-sectional schematic diagram showing a portion of the channel structure provided in an embodiment of this application. The semiconductor device may be a three-dimensional memory or a portion thereof. For example, the three-dimensional memory may be a 3D NAND flash memory.

[0050] It should be noted that, in the following figures, directions D1, D2, and D3 illustrate the spatial relationships of components in a semiconductor device. For example, direction D3 is the stacking direction of the first stacked structure and / or the second stacked structure, and directions D1 and D2 are two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the stacking direction. The same concepts will be used throughout this application to describe the spatial relationships of components in a semiconductor device.

[0051] like Figure 1A and Figure 1D As shown, the semiconductor device 100 includes a first stacked structure 111 and a second stacked structure 112. The second stacked structure 112 is located on one side of the first stacked structure 111. Both the first stacked structure 111 and the second stacked structure 112 include alternatingly arranged first dielectric layers (e.g., 1131a, 1132a) and multiple material layers (e.g., 1141a, 1142a). For example, the first stacked structure 111 may include alternatingly arranged first dielectric layers (e.g., 1131a) and multiple material layers (e.g., 1141a). The second stacked structure 112 may include alternatingly arranged first dielectric layers (e.g., 1132a) and multiple material layers (e.g., 1142a). The material layers (e.g., 1141a, 1142a) may include insulating portions (e.g., 1151a, 1152a) and conductive portions (e.g., 1161a, 1162a). For example, material layer 1141a in the first stacked structure 111 may include insulating portion 1151a and conductive portion 1161a. Material layer 1142a in the second stacked structure 112 may include insulating portion 1152a and conductive portion 1162a.

[0052] Exemplarily, the material of the first dielectric layer (e.g., 1131a, 1132a) may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y One or more of silicon oxide (SiO2) or any other suitable insulating material. The insulating portions (e.g., 1151a, 1152a) in the material layers (e.g., 1141a, 1142a) may contain silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N yThe material may be one or more of tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable insulating material, and may differ from the material of the first dielectric layer (e.g., 1131a, 1132a). For example, the material of the first dielectric layer (e.g., 1131a, 1132a) may be silicon oxide (SiO2), and the material of the insulating portion (e.g., 1151a, 1152a) may be silicon nitride (Si3N4). Additionally, the material of the conductive portion (e.g., 1161a, 1162a) in the material layer (e.g., 1141a, 1142a) may include one or more of tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material. For example, the material of the conductive portion (e.g., 1161a, 1162a) may be tungsten (W).

[0053] The semiconductor device 100 also includes a contact structure 117a. The contact structure 117a includes an inner core 118a and an outer ring 119a. The inner core 118a extends through the first stacked structure 111 and the second stacked structure 112 and is connected (e.g., contacted) to a conductive portion 1161a of a material layer 1141a in the first stacked structure 111. The outer ring 119a extends through the second stacked structure 112 and is fitted over the inner core 118a, and is connected (e.g., contacted) to a conductive portion 1162a of a material layer 1142a in the second stacked structure 112. Exemplarily, the material of the contact structure 117a may include one or more of tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material.

[0054] The semiconductor device provided in the above embodiments of this application is connected to a conductive portion of a material layer in a first stacked structure through an inner core in a contact structure, and to a conductive portion of a material layer in a second stacked structure through an outer ring in a contact structure. This allows the conductive portions of two vertically arranged stacked structures to be led out using a single contact structure, thereby reducing the number of contact structures and the area occupied by the contact structures and the semiconductor device. This is beneficial for reducing manufacturing costs and improving economic efficiency.

[0055] To further illustrate the spatial relationships of the components in the semiconductor device 100, the following section combines... Figures 1A to 1H An example of semiconductor device 100 is provided.

[0056] In some implementations, such as Figure 1AAs shown, the semiconductor device 100 may include a stepped region 101 and a core region 102. Exemplarily, viewed from the D3 direction, the semiconductor device 100 is divided into a core region 102 and a stepped region 101 along the D1 direction. For example, the core region 102 may be located on both sides of the stepped region 101, or the stepped region 101 may be located on both sides of the core region 102. This application does not limit the specific arrangement of the core region 102 and the stepped region 101.

[0057] In some implementations, such as Figure 1A , Figure 1B as well as Figure 1D As shown, the first stacked structure 111 and the second stacked structure 112 may be located in the step region 101. In other words, the first stacked structure 111 and the second stacked structure 112 may extend laterally (e.g., along the D1 direction and / or the D2 direction) within the step region 101. For example, the first stacked structure 111 may be located on one side of the semiconductor layer 123, and the second stacked structure 112 may be located on the side of the first stacked structure 111 away from the semiconductor layer 123. In other words, the first stacked structure 111 and the second stacked structure 112 are sequentially disposed on one side of the semiconductor layer 123. For example, the material of the semiconductor layer 123 may include polysilicon (poly-Si) or any other suitable semiconductor material.

[0058] In some implementations, such as Figure 1D As shown, the first stacked structure 111 may have multiple first steps 124. In the first stacked structure 111, a first dielectric layer (e.g., 1131a) and a material layer (e.g., 1141a) may form a stack pair. For example, the first dielectric layer 1131a and the material layer 1141a in this stack pair may have the same lateral extension dimension. For two adjacent stack pairs, the lateral extension dimension of the upper stack pair (e.g., the one farther from the semiconductor layer 123) may be smaller than the lateral extension dimension of the lower stack pair (e.g., the one closer to the semiconductor layer 123). More specifically, for two adjacent stack pairs, both have the same extension dimension in the D2 direction, while the extension dimension of the upper stack pair in the D1 direction is smaller than the extension dimension of the lower stack pair in the D1 direction. As described above, the two horizontally extending surfaces in two adjacent stack pairs and the vertically extending surface in the upper stack pair may form the first step 124. Similarly, the second stacked structure 112 may have multiple second steps 125. The top layers of the first step 124 and the second step 125 are both material layers (e.g., 1141a and 1142a). In other words, the top surfaces of the first step 124 and the second step 125 are the surfaces of material layers (e.g., 1141a and 1142a).

[0059] It should be noted that the thickness and number of the first dielectric layer (e.g., 1131a, 1132a) and material layer (e.g., 1141a, 1142a) are not specifically limited in this application. For example, each first dielectric layer (e.g., 1131a, 1132a) may have the same or different thicknesses, and each material layer (e.g., 1141a, 1142a) may also have the same or different thicknesses. Furthermore, the number of multiple first dielectric layers (e.g., 1131a) and multiple material layers (e.g., 1141a) included in the first stacked structure 111, and the number of multiple first dielectric layers (e.g., 1132a) and multiple material layers (e.g., 1142a) included in the second stacked structure 112, can be designed according to actual storage requirements. Generally speaking, the more first dielectric layers (e.g., 1131a, 1132a) and material layers (e.g., 1141a, 1142a) there are, the higher the integration and the higher the storage density. Furthermore, there is a one-to-one correspondence between the multiple first steps 124 and the multiple second steps 125. For example, the number of multiple first steps 124 is the same as the number of multiple second steps 125, and from the D3 direction, the top surface of the first step 124 and the top surface of the second step 125 at least partially overlap.

[0060] In some implementations, reference continues. Figure 1D The semiconductor device 100 may further include a first insulating structure 126 and a second insulating structure 127. The first insulating structure 126 may cover the top side of a plurality of first steps 124. The second insulating structure 127 may cover the top side of a plurality of second steps 125. Exemplarily, the materials of the first insulating structure 126 and / or the second insulating structure 127 may include silicon oxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2). x N y One or more of tetraethyl orthosilicate (TEOS) or any other suitable insulating material.

[0061] In some implementations, such as Figure 1A and Figure 1BAs shown, the semiconductor device 100 may further include a first gate line gap structure 128. The first gate line gap structure 128 may penetrate the second stacked structure 112 and the first stacked structure 111, and extend along the D1 direction (e.g., continuously). For example, the first gate line gap structure 128 may extend within the step region 101 and the core region 102. The first stacked structure 111 and the second stacked structure 112 may be located between adjacent first gate line gap structures 128. For example, two adjacent first gate line gap structures 128 in the D2 direction may be used to define a memory block and provide electrical isolation between adjacent memory blocks. Exemplarily, the first gate line gap structure 128 may be made of a single material or a composite material. The material of the first gate line gap structure 128 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y ), polycrystalline silicon (poly-Si) or any other suitable material.

[0062] As mentioned above, Figure 1D As shown, the material layers (e.g., 1141a, 1142a) may include insulating portions (e.g., 1151a, 1152a) and conductive portions (e.g., 1161a, 1162a). The following illustration uses material layers 1142a and 1142b in the second stacked structure 112 as examples. Since the second step 125 is composed of a stacked pair, material layers 1142a and 1142b are both the top layers of the second step 125. Figure 1E As shown, in material layer 1142a, conductive portions 1162a surround insulating portions 1152a on both sides along the D1 direction and on one side along the D1 direction (e.g., the side away from the core region 102). Conductive portions 1162a may include first conductive portions 11621a and second conductive portions 11622a. The first conductive portion 11621a is located on one side of the insulating portion 1152a along the D1 direction, and the second conductive portions 11622a are located on both sides of the insulating portion 1152a along the D1 direction. The second conductive portions 11622a may contact the first gate line slot structure 128 respectively. The first conductive portion 11621a may be exposed to the upper second step 125 (reference). Figure 1D Furthermore, the thickness of the first conductive portion 11621a in the D3 direction may be greater than the thickness of the second conductive portion 11622a in the D3 direction. It should be noted that in the material layer 1142a, besides the first conductive portion 11621a being exposed to the upper second step 125, a portion of the insulating portion 1152a near the first conductive portion 11621a is also exposed to the upper second step 125. In other words, the first conductive portion 11621a may have a gap between it and the side of the upper second step 125.

[0063] Similarly, such as Figure 1F As shown, in material layer 1142b, the first conductive portion 11621b may be located on one side of the insulating portion 1152b in the D1 direction, and the second conductive portion 11622b is located on both sides of the insulating portion 1152b along the D1 direction. It should be noted that, compared to... Figure 1E The material layer 1142a shown has an insulating portion 1152b in the lower material layer 1142b that has a larger extension dimension in the D1 direction. Viewed from the D3 direction, the projection of the first conductive portion 11621a in the upper material layer 1142a lies within the projection of the insulating portion 1152b in the lower material layer 1142b.

[0064] In some implementations, such as Figures 1D to 1F As shown, the inner core 118a of the contact structure 117a can sequentially pass through the second insulating structure 127, the second stacked structure 112, the first insulating structure 126, and the first stacked structure 111. Specifically, the inner core 118a passes through the second stacked structure 112 and the first stacked structure 111 on the top surface of a second step 125 and the top surface of the corresponding first step 124. The outer ring 119a sequentially passes through the second insulating structure 127 and the second stacked structure 112. In this structure, the inner core 118a can be connected (e.g., in contact) to the conductive portion 1161a in the material layer 1141a of the first step 124 it passes through, and also connected (e.g., in contact) to the insulating portion of the material layer below the first step 124 it passes through. Similarly, the outer ring 119a can connect (e.g., contact) with the conductive portion 1162a (e.g., the first conductive portion 11621a) in the material layer 1142a of the second step 125 through which it passes, and with the insulating portion (e.g., 1152b) in the material layer below the second step 125 (e.g., 1142b) through which it passes. In this embodiment, by having the contact structure pass through the first and second steps, the landing area of ​​the contact structure provided by the plurality of first and second steps arranged in the vertical direction can be fully utilized, further reducing the radial dimension of the contact structure and further reducing the area occupied by the contact structure and the semiconductor device.

[0065] In some implementations, such as Figure 1CAs shown, the contact structure 117a may further include an insulating layer 120a. The insulating layer 120a may be located between the inner core portion 118a and the outer ring portion 119a to provide electrical isolation. Exemplarily, the inner core portion 118a may include a first portion 1181a and a second portion 1182a. The first portion 1181a may penetrate the first stacked structure 111, and the second portion 1182a may penetrate the second stacked structure 112. In a plane perpendicular to the D3 direction, the size of the second portion 1182a is smaller than the size of the first portion 1181a. For example, the first portion 1181a and the second portion 1182a may be generally cylindrical, and the diameter of the second portion 1182a may be smaller than the diameter of the first portion 1181a. The insulating layer 120a is sleeved on the outer wall of the second portion 1182a and contacts the inner wall of the outer ring portion 119a and the end face of the first portion 1181a near the second stacked structure 112.

[0066] In some implementations, such as Figure 1A and Figure 1G As shown above, the semiconductor device 100 may include a step region 101 and a core region 102. The first stacked structure 111 and the second stacked structure 112 extend beyond the step region 101 to the core region 102. The portions of the first stacked structure 111 and the second stacked structure 112 located in the core region 102 may include alternatingly arranged multiple second dielectric layers 1301 and 1302 and multiple gate layers 1311 and 1312. For example, the portion of the first stacked structure 111 located in the core region 102 may include alternatingly arranged multiple second dielectric layers 1301 and multiple gate layers 1311, and the portion of the second stacked structure 112 located in the core region 102 may include alternatingly arranged multiple second dielectric layers 1302 and multiple gate layers 1312. In the first stacked structure 111, the multiple second dielectric layers 1301 may be respectively connected to multiple first dielectric layers (e.g., 1131a, see reference 1131a). Figure 1D The plurality of gate layers 1311 can be connected to respective conductive portions (e.g., 1161a, reference 1141a) in the plurality of material layers (e.g., 1141a). Figure 1D In the second stacked structure 112, multiple second dielectric layers 1302 can be connected to multiple first dielectric layers (e.g., 1132a, see reference 1132a). Figure 1D The multiple gate layers 1312 can be connected to respective conductive portions (e.g., 1162a, reference 1142a) in the multiple material layers (e.g., 1142a). Figure 1D (Connection). Exemplarily, the material of the second dielectric layers 1301 and 1302 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N yThe materials used for the second dielectric layers 1301 and 1302 may be one or more of the following: tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material. For example, the second dielectric layers 1301 and 1302 may be made of a composite material (e.g., tungsten (W) on the inside and titanium nitride (TiN) on the outside, and surrounded by a gate barrier layer (not shown).

[0067] In some implementations, reference continues to be made to 1A and Figure 1G The semiconductor device 100 may further include a plurality of channel structures 129. For example, the plurality of channel structures 129 may be arranged in an array within the core region 102. For one channel structure 129, it may penetrate the portion of the first stacked structure 111 and the second stacked structure 112 located in the core region 102. In some embodiments, such as Figure 1H As shown, the channel structure 129 may include a barrier layer 1291, a charge trapping layer 1292, a tunneling layer 1293, and a channel layer 1294, arranged sequentially from the outside to the inside. The barrier layer 1291, charge trapping layer 1292, and tunneling layer 1293 may be referred to as functional layers 1295. For example, the materials of the barrier layer 1291, charge trapping layer 1292, and tunneling layer 1293 may sequentially include silicon oxide (SiO2), silicon nitride (Si3O4), and silicon oxide (SiO2). The material of the channel layer 1294 may include amorphous silicon (α-Si), polycrystalline silicon (poly-Si), or any other suitable semiconductor material.

[0068] In some embodiments, a portion of the channel structure 129 surrounded by a gate layer 1311, 1312, and a portion of the gate layer 1311, 1312, constitute a memory cell MC. Multiple memory cells MC are arranged in series along the extension direction of the channel structure 129 (e.g., the D3 direction) to form a memory string and share the channel layer 1294. The remaining portions of the gate layers 1311, 1312 can serve as word lines connecting multiple memory cells MC at the same height in different memory strings. For example, by applying a voltage to the gate layers 1311, 1312, the memory cell MC can cause charge in the channel layer 1294 to enter the charge trapping layer 1292, or cause charge in the charge trapping layer 1292 to retreat back into the channel layer 1294, thereby placing the memory cell MC in a programmed state or an erased state (unprogrammed state).

[0069] Figures 2A to 2E This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application. Wherein, Figure 2A This is a top view schematic diagram of a semiconductor device provided in another embodiment of this application. Figure 2B It is along Figure 2A The diagram shows a cross-section taken by line A-A'. Figure 2C It is along Figure 2A The diagram shows a cross-section taken by line B-B'. Figure 2D and Figure 2E They are along Figure 2C The diagram shows cross-sectional views taken along lines E-E' and F-F'. For the sake of brevity, content identical to that in the previous embodiment will not be repeated in this embodiment.

[0070] like Figures 2A to 2C As shown, the first stacking structure 211 and the second stacking structure 212 have at least two partitions in the D2 direction. The following description uses the example of the first stacking structure 211 and the second stacking structure 212 having three partitions 203a, 203b, and 203c in the D2 direction. It is understood that the first stacking structure 211 and the second stacking structure 212 may have other numbers of partitions in the D2 direction, and this application does not impose specific limitations on this.

[0071] In some implementations, such as Figure 2C As shown, in the first stacked structure 211, a first dielectric layer (e.g., 2131a) and a material layer (e.g., 2141a) may constitute a stack pair. The first dielectric layers 2131a, 2131b, 2131c and the material layers 2141a, 2141b, 2141c in the three stack pairs (hereinafter referred to as a set of stack pairs) may have the same lateral extension dimension. For two adjacent sets of stack pairs, the lateral extension dimension of the upper set of stack pairs (e.g., the set farther from semiconductor layer 223) may be smaller than the lateral extension dimension of the lower set of stack pairs (e.g., the set closer to semiconductor layer 223). As described above, the two horizontally extending surfaces in two adjacent sets of stack pairs and the vertically extending surface in the upper set of stack pairs may constitute a first step 224. Within the same partition (e.g., 203c), the number of stack pairs between adjacent first steps 224 is 3, which is equal to the number of partitions. Similarly, the second stack structure 212 may have multiple second steps 225. Within the same partition (e.g., 203c), the number of stack pairs between adjacent second steps 225 is also 3, equal to the number of partitions. The top layers of both the first step 224 and the second step 225 are material layers (e.g., 2141a and 2142a). In other words, the top surfaces of the first step 224 and the second step 225 are the surfaces of material layers (e.g., 2141a and 2142a).

[0072] like Figure 2BAs shown, the first stacked structures 211 located in adjacent partitions (e.g., 203a and 203b, 203b and 203c) differ by one stack pair. Similarly, the second stacked structures 212 located in adjacent partitions (e.g., 203a and 203b, 203b and 203c) also differ by one stack pair. For example, the first stacked structures 211 have multiple first steps 224 with gradient descent in the D1 direction (see reference). Figure 2C The first stack structure 211 also has steps in the D2 direction. In other words, for example, the plurality of first steps 224 in partition 203c differ from the plurality of first steps 224 in partition 203b by a stack pair. Similarly, the second stack structure 212 also has a similar structure in different partitions.

[0073] It should be noted that there is a one-to-one correspondence between the multiple first steps 224 and the multiple second steps 225. For example, the number of multiple first steps 224 is the same as the number of multiple second steps 225, and from the D3 direction, the top surface of the first step 224 and the top surface of the second step 225 at least partially overlap.

[0074] In some implementations, such as Figure 2A and Figure 2B As shown, the semiconductor device 200 may further include a second gate line gap structure 232. The second gate line gap structure 232 may penetrate the second stacked structure 212 and the first stacked structure 211 and extend along the D1 direction (e.g., continuously). For example, the second gate line gap structure 232 may extend within the step region 201. The second gate line gap structure 232 can be used to divide the first stacked structure 211 and the second stacked structure 212 into partitions 203a, 203b, and 203c. Exemplarily, the second gate line gap structure 232 may be made of a single material or a composite material. The material of the second gate line gap structure 232 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y ), polycrystalline silicon (poly-Si) or any other suitable material.

[0075] The following is based on Figure 2C The material layers 2142a and 2142b in the second stacked structure 212 shown are illustrated as examples. Since the second step 225 consists of three stacked pairs, and adjacent partitions (e.g., 203a and 203b, 203b and 203c) differ by one stacked pair, for a material layer (e.g., 2142a) in the same D3 direction, it can serve as the top material layer of the second step 225 within partition 203c, while within partitions 203a and 203b, it serves as a non-top material layer of the second step 225. Figure 2DAs shown, in the portion of material layer 2142a located within partition 203c, the first conductive portion 21621a is located on one side of the insulating portion 2152a in the D1 direction, and the second conductive portion 21622a is located on both sides of the insulating portion 2152a along the D1 direction. The second conductive portion 21622a can contact the first gate line slot structure 228 and the second gate line slot structure 232, respectively. In the portion of material layer 2142a located within partition 203b, it does not have the first conductive portion, and the second conductive portion 21622a is located on both sides of the insulating portion 2152a along the D1 direction. The second conductive portion 21622a can contact the second gate line slot structure 232, respectively. In the portion of material layer 2142a located within partition 203a, it does not have the first conductive portion, and the second conductive portion 21622a is located on both sides of the insulating portion 2152a along the D1 direction. The second conductive portion 21622a can contact the first gate line slot structure 228 and the second gate line slot structure 232 respectively.

[0076] Similarly, such as Figure 2E As shown, in the portion of material layer 2142b located within partition 203c, the first conductive portion 21621b is located on one side of the insulating portion 2152b in the D1 direction, and the second conductive portion 21622b is located on both sides of the insulating portion 2152b along the D1 direction. In the portion of material layer 2142b located within partition 203b, it does not have the first conductive portion, and the second conductive portion 21622b is located on both sides of the insulating portion 2152b along the D1 direction. In the portion of material layer 2142b located within partition 203a, it does not have the first conductive portion, and the second conductive portion 21622b is located on both sides of the insulating portion 2152b along the D1 direction.

[0077] It should be pointed out that, compared to Figure 2D In the material layer 2142a shown, within partition 203c, the insulating portion 2152b in the lower material layer 2142b has a larger extension dimension in the D1 direction. Viewed from the D3 direction, the projection of the first conductive portion 21621a in the upper material layer 2142a lies within the projection of the insulating portion 2152b in the lower material layer 2142b.

[0078] In some implementations, such as Figures 2D to 2EAs shown, the inner core 218a of the contact structure 217a can pass through the second stacked structure 212 and the first stacked structure 211. Specifically, the inner core 218a passes through the top surface of a second step 225 and the top surface of the corresponding first step 224 of the second step 225, respectively. The outer ring 219a passes through the second stacked structure 212. In this structure, the inner core 218a can be connected (e.g., contacted) to the conductive portion of the top layer 2141a of the first step 224 it passes through, and to the insulating portion of the material layer below the first step 224 (including the non-top layer of the first step 224 and the material layer of the lower first step). Similarly, the outer ring 219a can be connected (e.g., in contact) to the conductive portion 2162a (e.g., the first conductive portion 21621a) in the top layer 2142a of the second step 225 through which it passes, and to the insulating portion (e.g., 2152b) in the lower layer (e.g., 2142b) of the second step 225 through which it passes. In this embodiment, by providing steps in both the D1 and D2 directions for the first and second stacked structures, the area occupied by the step region can be reduced while maintaining the same number of stacked layers.

[0079] It should be noted that although the above description uses the example of a first stacking structure and a second stacking structure having multiple first steps and multiple second steps respectively, in other embodiments, the first stacking structure and the second stacking structure may not have steps, and this application does not impose specific limitations.

[0080] This application also provides a memory system. Figure 3 This is a block diagram of a system with a memory system provided in an embodiment of this application. Figure 4A and Figure 4B This is a schematic diagram of a memory system provided in an embodiment of this application.

[0081] like Figure 3 As shown, system 11 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 12 located therein). Figure 3As shown, system 11 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0082] The three-dimensional memory 14 may include the semiconductor devices described in any embodiment of this application, for example, Figures 1A to 1H The semiconductor device 100 shown is or Figures 2A to 2EThe semiconductor device 200 is shown. According to some embodiments, a controller 16 is coupled to the 3D memory 14 and the host 18 and is configured to control the 3D memory 14. The controller 16 can manage data stored in the 3D memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. The controller 16 can be configured to control the operation of the 3D memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0083] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 4AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 3 The host 18) is coupled to the memory card connector 24. In such a way... Figure 4B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 3 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0084] This application also provides a method for manufacturing a semiconductor device. Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 5 As shown, the semiconductor device manufacturing method 300 (hereinafter referred to as manufacturing method 300) includes the following steps.

[0085] S310, forming a first contact hole that penetrates the first initial stacked structure.

[0086] S320, a second initial stacking structure is formed on one side of the first initial stacking structure. Both the first and second initial stacking structures include multiple dielectric layers and multiple sacrificial layers arranged alternately.

[0087] S330, forming a second contact hole that extends through the second initial stacked structure to the first contact hole.

[0088] S340, a portion of each sacrificial layer is replaced with a conductive portion to form a material layer, wherein the remaining portion of the sacrificial layer serves as an insulating portion of the material layer.

[0089] S350, an outer ring portion connected to a conductive portion in a material layer is formed in the second contact hole, and an inner core portion connected to a conductive portion in a material layer is formed in the first contact hole and the second contact hole.

[0090] According to the semiconductor device manufacturing method provided in the embodiments of this application, the inner core of the contact structure is connected to the conductive portion of a material layer in the first stacked structure, and the outer ring of the contact structure is connected to the conductive portion of a material layer in the second stacked structure. The conductive portions of the two stacked structures arranged in the vertical direction can be led out using a single contact structure, which can reduce the number of contact structures, thereby reducing the area occupied by the contact structures and the semiconductor device, which is beneficial to reducing manufacturing costs and improving economic efficiency.

[0091] Figures 6 to 13G This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the manufacturing process. For example, Figures 6 to 13G Can be based on Figure 5 The intermediate structure formed by the manufacturing method 300 shown is used to form, for example, Figures 1A to 1H The semiconductor device 100 is shown below. (The following is in conjunction with...) Figures 6 to 13G right Figure 5 The manufacturing method 300 shown is further explained.

[0092] S310, forming a first contact hole that penetrates the first initial stacked structure.

[0093] Figure 6 A cross-sectional schematic diagram of an intermediate structure 400a is shown after the formation of a first initial stacked structure, a first contact hole, a first filling sacrificial layer, and a second initial stacked structure.

[0094] In step S310, as Figure 6 As shown, the first initial stack structure 411' includes a plurality of dielectric layers 4341 and a plurality of sacrificial layers 4351 alternately disposed. For example, the plurality of dielectric layers 4341 and the plurality of sacrificial layers 4351 may be formed alternately using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The materials of the dielectric layers 4341 and the sacrificial layers 4351 may be different from each other, thereby giving them different etch selectivity ratios relative to the same etch material. For example, the material of the dielectric layer 4341 may include silicon oxide (SiO2), and the material of the sacrificial layer 4351 may include silicon nitride (Si3N4). In some embodiments, the first initial stack structure 411' may be formed on one side of a substrate 433. For example, the substrate 433 may be a semiconductor substrate. The material of the semiconductor substrate may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). For example, the semiconductor substrate can be silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrates.

[0095] It should be pointed out that, Figure 6 This could be in step area 101 (reference) Figure 1A A cross-sectional schematic diagram of the intermediate structure 400a taken along the D1 direction within the core region 102. In some embodiments, the dielectric layer 4341 and the sacrificial layer 4351 may extend laterally to the core region 102 (see reference). Figure 1A Within the core region 102, the portion of dielectric layer 4341 located within the step region 101 can be referred to as the "first dielectric layer", and the portion of dielectric layer 4341 located within the core region 102 can be referred to as the "second dielectric layer".

[0096] In some embodiments, the manufacturing method 300 may further include the step of forming a plurality of first steps 424 before forming the first contact hole 437. For example, a trimming-etching process may be used to etch the first initial stacked structure 411' to form the plurality of first steps 424. Adjacent first steps 424 are separated by a dielectric layer 4341 and a sacrificial layer 4351, and the top layer of the first steps 424 is the sacrificial layer 4351. In other words, the surface of the sacrificial layer 4351 may serve as the top surface of the first steps 424. Next, a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, may be used to form a first step sacrificial layer 436 covering at least a portion of the top surface of the plurality of first steps 424. For example, the material of the first step sacrificial layer 436 may include polysilicon (poly-Si). As another example, the thickness of the first step sacrificial layer 436 may be less than the thickness of the dielectric layer 4341 located above it.

[0097] In some embodiments, a first insulating structure 426 covering the top side of the plurality of first steps 424 may be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The surface of the first insulating structure 426 away from the substrate 433 may be substantially flush (e.g., with an error within ±10%).

[0098] In step S310, as Figure 6 As shown, an etching process (e.g., dry etching and / or wet etching) can be used to form a first contact hole 437 penetrating the first initial stacked structure 411'. In some embodiments, where multiple first steps 424 are formed, the first contact hole 437 can pass through the top surface of the first step 424 and extend, for example, into the substrate 433. Further, a first filling sacrificial layer 438 can be formed in the first contact hole 437 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the first filling sacrificial layer 438 may include polysilicon (poly-Si), carbon (C), or other easily removable sacrificial materials. For example, the material of the first filling sacrificial layer 438 may be the same as the material of the substrate 433. Specifically, the substrate 433 may be a silicon substrate, and the material of the first filling sacrificial layer 438 may be polysilicon (poly-Si).

[0099] In some embodiments, after the first contact hole 437 is formed, the substrate 433 exposed to the first contact hole 437 may be oxidized using dry oxidation and / or wet oxidation to form an oxide barrier layer 439. When the material of the first filler sacrificial layer 438 is the same as the material of the substrate 433, the oxide barrier layer 439 can be used to protect the substrate 433 during the subsequent removal of the first filler sacrificial layer 438, preventing damage to the substrate 433.

[0100] S320, a second initial stacking structure is formed on one side of the first initial stacking structure.

[0101] In step S320, continue to refer to Figure 6 The second initial stacked structure 412' may be formed on the side of the first initial stacked structure 411' away from the substrate 433. The second initial stacked structure 412' includes a plurality of alternating dielectric layers 4342 and a plurality of sacrificial layers 4352. For example, the plurality of dielectric layers 4342 and the plurality of sacrificial layers 4352 may be formed alternately using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, dielectric layers 4342 and 4341 may be made of the same material, and sacrificial layers 4352 and 4351 may be made of the same material.

[0102] It should be noted that the dielectric layer 4342 and the sacrificial layer 4352 can extend laterally to the core region 102 (see reference). Figure 1A Within the core region 102, the portion of dielectric layer 4342 located within the step region 101 can be referred to as the "first dielectric layer", and the portion of dielectric layer 4342 located within the core region 102 can be referred to as the "second dielectric layer".

[0103] In some embodiments, a trim-etch process can be used to etch the second initial stack structure 412' to form a plurality of second steps 425. Adjacent second steps 425 are separated by a dielectric layer 4342 and a sacrificial layer 4352, with the sacrificial layer 4352 being the top layer of each second step 425. In other words, the surface of the sacrificial layer 4352 can serve as the top surface of the second step 425. Next, a thin-film deposition process, such as CVD, PVD, ALD, or any combination thereof, can be used to form a second step sacrificial layer 440 covering at least a portion of the top surface of the plurality of second steps 425. For example, the material of the second step sacrificial layer 440 may include polysilicon (poly-Si). As another example, the thickness of the second step sacrificial layer 440 may be less than the thickness of the dielectric layer 4342 located above it. Furthermore, the plurality of first steps 424 and the plurality of second steps 425 may correspond one-to-one. For example, the number of multiple first steps 424 may be the same as the number of multiple second steps 425, and from the D3 direction, the top surface of the first step 424 and the top surface of the second step 425 at least partially overlap.

[0104] In some embodiments, a second insulating structure 427 covering the top sides of the plurality of second steps 425 may be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The surface of the second insulating structure 427 away from the substrate 433 may be substantially flush (e.g., with an error within ±10%).

[0105] S330, forming a second contact hole that extends through the second initial stacked structure to the first contact hole. .

[0106] Figure 7 A cross-sectional schematic diagram of the intermediate structure 400b after the formation of the second contact hole is shown. Figure 8 A cross-sectional schematic diagram of the intermediate structure 400c after the formation of the second filling sacrificial layer is shown.

[0107] In step S330, as Figure 7 As shown, an etching process (e.g., dry etching and / or wet etching) can be used to form a second contact hole 441 extending through the second initial stack structure 412' to the first contact hole 437. For example, the second contact hole 441 exposes the first filling sacrificial layer 438. When the first contact hole 437 and the second contact hole 441 are columnar, the axis of the first contact hole 437 and the axis of the second contact hole 441 can be substantially coincident (e.g., with an error within ±10%). In some embodiments, when multiple second steps 425 are formed, the second contact hole 441 can pass through the top surface of the second step 425 and extend to the first contact hole 437. For example, by rationally designing the number and relative position of the first steps 424 and the second steps 425, multiple first steps 424 and multiple second steps 425 can be made to correspond one-to-one, such that the first contact hole 437 passes through the top surface of the first step 424 and the second contact hole 441 passes through the top surface of the second step 425, while the first contact hole 437 and the second contact hole 441 are aligned with each other.

[0108] In some implementations, such as Figure 8 As shown, in forming the second contact hole 441 (reference) Figure 7 Following this, a second filler sacrificial layer 442 can be formed in the second contact hole 441 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the second filler sacrificial layer 442 may include polysilicon (poly-Si), carbon (C), or other easily removable sacrificial materials. The material of the second filler sacrificial layer 442 may differ from the material of the first filler sacrificial layer 438, thereby allowing them to have different etching selectivity ratios relative to the same etch material. For example, if the material of the first filler sacrificial layer 438 is polysilicon (poly-Si), the material of the second filler sacrificial layer may be carbon (C).

[0109] In some embodiments, manufacturing method 300 may further include the step of forming a channel hole (not shown) through the first initial stacked structure and the second initial stacked structure within the core region, and using the channel hole to form such as Figure 1H The steps of the channel structure are shown. For example, the channel holes can be formed in the etching process that forms the first contact hole 437 and the second contact hole 441, respectively.

[0110] S340, a portion of each sacrificial layer is replaced with a conductive portion to form a material layer, wherein the sacrificial layer contains The remaining portion serves as the insulating part of the material layer. .

[0111] Figure 9A A top view schematic diagram of the intermediate structure 400d after the formation of the first grid line slot is shown. Figure 9B It is along Figure 9A The diagram shows a cross-sectional view of the intermediate structure 400d taken by line A-A'. Figure 10A yes Figure 9B A magnified schematic diagram of a portion of region G is shown. Figures 10B to 10D A schematic diagram of the structure of region G during the formation of the sacrificial gap is shown. Figure 11 It shows that it contains Figure 10D The diagram shows a cross-sectional view of the intermediate structure 400e in region G. Figure 12 A cross-sectional schematic diagram of the intermediate structure 400f after the material layer is formed is shown.

[0112] In step S340, in some embodiments, such as Figure 9A and Figure 9B As shown, an etching process (e.g., dry etching and / or wet etching) can be used to form a first gate line slot 428' that penetrates the second step sacrificial layer 440, the second initial stacked structure 412', the first step sacrificial layer 436, and the first initial stacked structure 411'. For example, the first gate line slot 428' extends into the substrate 433 in the D3 direction and into the core region 402 in the D1 direction. Further, as... Figure 9B and Figure 12 As shown, the first grid line gap 428' can be used to... Figure 9B The sacrificial layers shown (e.g., 4351b and 4352b) near the edge of the first gate line slot 428' are replaced with Figure 12The conductive portions shown (e.g., 4161b and 4162b) are formed by replacing the portion of the first step sacrificial layer 436 and sacrificial layer 4351a covered by the first step sacrificial layer 436 with conductive portion 4161a, and replacing the portion of the second step sacrificial layer 440 and sacrificial layer 4352a covered by the second step sacrificial layer 440 with conductive portion 4162a. The sacrificial layers (e.g., 4351a, 4351b, 4352a, 4352b) can be partially replaced to form material layers (e.g., 4141a, 4141b, 4142a, 4142b), while the remaining unreplaced portions of the sacrificial layers (e.g., 4351b, 4352b) can serve as insulating portions (e.g., 4151b, 4152b). The distribution and positional relationship of the conductive and insulating portions in the material layers have been described in detail above and will not be repeated here. After this step, the first initial stacking structure 411' can be converted into the first stacking structure 411, and the second initial stacking structure 412' can be converted into the second stacking structure 412.

[0113] In some implementations, refer again Figure 9B After the first gate line gap 428' is formed, during, for example, a natural oxidation process, an oxide layer 443 can be formed on the sidewall of the first gate line gap 428' exposed to the first step sacrificial layer 436 and the second step sacrificial layer 440, as shown below. Figure 10A As shown. For example, oxide layer 443 may extend along the D1 direction and have the same extension dimension as the first gate gap 428'. When the material of the first step sacrificial layer 436 and / or the second step sacrificial layer 440 is polysilicon (poly-Si), oxide layer 443 may be silicon oxide (SiO2). In some exemplary embodiments, when the first step sacrificial layer and the second step sacrificial layer are exposed to oxide layers on the sidewalls of the first gate gap, it is difficult to perform "partial replacement" of the sacrificial layer. The following embodiments of this application can at least partially solve the above problems.

[0114] First, such as Figure 10A and Figure 10BAs shown, the first sub-portion of the sacrificial layer (e.g., 4351a, 4351b) near the first gate gap 428' can be removed using, for example, a wet etching process, to expose the first step sacrificial layer 436. For example, in the D2 direction, the size of the first sub-portion is larger than the size of the oxide layer 443, and the bottom surface of the first step sacrificial layer 436 is exposed in the D3 direction. Exemplarily, when the material of the sacrificial layer (e.g., 4351a, 4351b) is silicon nitride (Si3N4) and the material of the dielectric layer 4342 is silicon oxide (SiO2), phosphoric acid (H3PO4) can be selected as the etchant, for example, and the first sub-portions of the sacrificial layer (e.g., 4351a, 4351b) on both sides of the first gate gap 428' in the D2 direction can be etched by controlling etching parameters (e.g., etching time and / or etching rate). Similarly, in the same wet etching process, the first sub-part of the sacrificial layer in the second initial stacked structure near the first gate gap can be removed, and the second step sacrificial layer (not shown) can be exposed.

[0115] Then, as Figure 10B and Figure 10C As shown, the first step sacrificial layer 436 can be removed, for example, using a wet etching process. Exemplarily, when the material of the first step sacrificial layer 436 is polysilicon (poly-Si), an etchant with a high etch selectivity relative to polysilicon (poly-Si) and a low etch selectivity relative to silicon oxide (SiO2) and silicon nitride (Si3N4) can be used to etch the first step sacrificial layer 436. Similarly, the second step sacrificial layer (not shown) can be removed in the same wet etching process.

[0116] Next, as Figure 10C and Figure 10D As shown, a wet etching process can be used, for example, to remove the second sub-portion of the sacrificial layer (e.g., 4351a, 4351b) near the first gate gap 428' and the sacrificial layer (e.g., 4351a) by the first step sacrificial layer 436 (see reference). Figure 10B The portion covered by the first gate gap 428' is used to form a sacrificial gap 444. Exemplarily, phosphoric acid (H3PO4) can be used as the etchant, and the second sub-portions of the sacrificial layer (e.g., 4351b) on both sides of the first gate gap 428' in the D2 direction can be further etched, for example, by controlling etching parameters (e.g., etching time and / or etching rate). Additionally, due to the first step sacrificial layer 436 in... Figure 10CThe space corresponding to the first step sacrificial layer 436, which has already been removed in the illustrated steps, is unfilled. During the removal of the second sub-part, the etchant enters the space corresponding to the first step sacrificial layer 436, thereby etching the sacrificial layer 4351a below the space, thus forming the sacrificial gap 444. Similarly, in the same wet etching process, the second sub-part of the sacrificial layer in the second initial stacked structure near the first gate line gap and the portion of the sacrificial layer in the second initial stacked structure covered by the second step sacrificial layer can be removed to form the sacrificial gap 444, as shown. Figure 11 As shown. It should be noted that the total thickness of the sacrificial layer (e.g., 4351b) in the D2 direction via the first and second sub-parts that are removed twice is equal to that of the edge portion 4151b (reference). Figure 12 Thickness in the D2 direction.

[0117] Subsequently, as Figure 11 and Figure 12 As shown, conductive portions (e.g., 4162a, 4162b, 4161a, 4161b) can be formed in the sacrificial gaps 444 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof.

[0118] In this embodiment, by removing the first sub-part of the sacrificial layer to remove the first step sacrificial layer and the second step sacrificial layer, and then removing the second sub-part of the sacrificial layer again to form a sacrificial gap with a designed thickness in the D2 direction, the problem of difficulty in "partially replacing" the sacrificial layer when the first step sacrificial layer and the second step sacrificial layer are exposed to the sidewall of the first gate line gap having an oxide layer can be addressed.

[0119] In some embodiments, when forming the step region 401 (reference) Figure 9A After the sacrificial gap 444 is filled, sacrificial material can be filled into the sacrificial gap 444, and the material located in the core region 402 (see reference) can be removed. Figure 9A The sacrificial layer within the core region 402 allows the sacrificial gap 444 to extend laterally into the core region 402. Furthermore, during the formation of conductive portions (e.g., 4162a, 4162b, 4161a, 4161b), gate layers 1311 and 1312 (see reference) can be formed on the portion of the sacrificial gap 444 located within the core region 402. Figure 1G For example, gate layers 1311, 1312 (reference) Figure 1G The conductive parts (e.g., 4162a, 4162b, 4161a, 4161b) can be formed simultaneously.

[0120] In some implementations, such as Figure 12As shown, the manufacturing method 300 may further include the step of forming a first gate gap structure 428. Exemplarily, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof may be used to fill the first gate gap 428' with materials such as silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y At least one of polysilicon (poly-Si) or any other suitable material is used to form the first gate gap structure 428.

[0121] S350, an outer ring portion is formed in the second contact hole to connect with a conductive portion in a material layer, in the first contact hole. An inner core is formed in the contact hole and the second contact hole, which is connected to a conductive portion in a material layer.

[0122] Figures 13A to 13G A structural schematic diagram is shown illustrating the process of forming the outer ring and inner core. Among them, Figures 13A to 13G Can be Figure 12 A partially enlarged schematic diagram of region D is shown. In step S350, as... Figure 13G As shown, an outer ring portion 419 connected to a conductive portion 4162a in a material layer 4142a can be formed in the second contact hole 441, and an inner core portion 418 connected to a conductive portion 4161a in a material layer 4141a can be formed in the first contact hole 437 and the second contact hole 441.

[0123] The following is combined with Figures 13A to 13G The steps for forming the outer ring portion 419 and the inner core portion 418 are illustrated with examples.

[0124] like Figure 13A As shown, the second filler sacrificial layer 442 in the second contact hole 441 can be removed up to the first filler sacrificial layer 438 using an etching process (e.g., wet etching and / or dry etching). When the material of the second filler sacrificial layer 442 differs from that of the first filler sacrificial layer 438, the second filler sacrificial layer 442 can serve as an etching stop layer for removing the first filler sacrificial layer 438, reducing the difficulty of process control. Alternatively, the etching of the second filler sacrificial layer 442 can be stopped at the first filler sacrificial layer 438 by controlling etching parameters (e.g., etching time and / or etching rate). After removing the second filler sacrificial layer 442, the second contact hole 441 can again be in an unfilled state.

[0125] like Figure 13BAs shown, a conductive layer 445 and a first insulating layer 446 can be sequentially formed on the inner wall of the second contact hole 441 and the surface of the first filling sacrificial layer 438 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, the conductive layer 445 and the first insulating layer 446 can cover the surface of the second insulating structure 427. Exemplarily, the material of the conductive layer 445 may include one or more of tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (poly-Si), or any other suitable conductive material. The material of the first insulating layer 446 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), or silicon oxynitride (SiO2). x N y (or at least one of any other suitable insulating material).

[0126] like Figure 13C As shown, an etching process (e.g., punching etching) can be used to remove portions of the first insulating layer 446 and conductive layer 445 located on the surface of the first filling sacrificial layer 438 to form an opening 448 exposing the conductive layer 445. Further, as... Figure 13D As shown, etching (e.g., wet etching and / or dry etching) can be used to remove the end of the conductive layer 445 near the first filling sacrificial layer 438, for example, so that the conductive layer 445 and the first insulating layer 446 after the end is removed are substantially flush with the end face of the first filling sacrificial layer 438 (e.g., with an error within ±10%). The conductive layer 445 after the end is removed can serve as an outer ring portion 419.

[0127] like Figure 13E As shown, a second insulating layer 447 can be formed on the inner wall of the first insulating layer 446 and the end face of the outer ring 419 near the first filled sacrificial layer 438 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, the material of the second insulating layer 447 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y At least one of the following: first insulating layer 446 or any other suitable insulating material. When the materials of the first insulating layer 446 and the second insulating layer 447 are the same, there is no distinct boundary between them (which may be referred to as insulating layer 420). For example, the portion of the second insulating layer 447 adjacent to the first filling sacrificial layer 438 may be removed by etching (e.g., punching etching) to expose the first filling sacrificial layer 438 (not shown).

[0128] like Figure 13E and 13FAs shown, the first filling sacrificial layer 438 in the first contact hole 437 can be removed using an etching process (e.g., dry etching and / or wet etching). When the material of the first filling sacrificial layer 438 is the same as the material of the substrate 433, the oxide barrier layer 439 can be used to protect the substrate 433 and prevent damage to the substrate 433. Further, as... Figure 13G As shown, conductive material can be filled into the inner side of the second insulating layer 447 and the first contact hole 437 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof to form the inner core 418. Optionally, chemical mechanical polishing (CMP) can be used to remove the outer ring 419 and the insulating layer 420 located above the second insulating structure 427, such as... Figure 1C As shown. Alternatively, the step of removing the outer ring 419 and the insulating layer 420 located above the second insulating structure 427 can be omitted. For example, the outer ring 419 located above the second insulating structure 427 can be used to connect to a lead-out structure (not shown).

[0129] In another embodiment, reference Figure 2A Multiple first steps and multiple second steps with partitions (e.g., 203a, 203b, 203c) in the D2 direction can be formed using a "trimming-etching" process. Subsequently, refer to... Figure 9A and Figure 9B A second gate line slot (not shown) can be formed through the second step sacrificial layer 440, the second initial stacked structure 412', the first step sacrificial layer 436, and the first initial stacked structure 411' using an etching process (e.g., dry etching and / or wet etching). For example, the second gate line slot can correspond to... Figure 2A and Figure 2B The outer contour of the second gate line slot structure 232 is shown. The second gate line slot can extend along the D1 direction and divide the first initial stacked structure 411' and the second initial stacked structure 412' into at least two partitions (e.g., three partitions) arranged in the D2 direction. Further, during the execution of step S340, the second gate line slot can be used to replace the edge portion of the sacrificial layer near the second gate line slot, the first step sacrificial layer and the second step sacrificial layer, and the portions of the sacrificial layer covered by the first step sacrificial layer and the second step sacrificial layer, respectively, with conductive portions, thereby forming a structure as shown in the figure. Figures 2B to 2E The material layer shown.

[0130] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that, include: First stacking structure; A second stacked structure is located on one side of the first stacked structure. Both the first and second stacked structures include alternating first dielectric layers and multiple material layers, and each material layer includes insulating and conductive portions. Contact structure, including: The inner core extends through the first stacked structure and the second stacked structure and is connected to the conductive portion of one of the material layers in the first stacked structure; The outer ring penetrates the second stacked structure and is fitted onto the inner core, and is connected to the conductive portion of one of the material layers in the second stacked structure.

2. The semiconductor device according to claim 1, wherein, The contact structure further includes an insulating layer located between the inner core and the outer ring.

3. The semiconductor device according to claim 2, wherein, The inner core includes a first part and a second part. The first part penetrates the first stacked structure, and the second part penetrates the second stacked structure. On a plane perpendicular to the stacking direction, the size of the second part is smaller than the size of the first part. The insulating layer is sleeved on the outer wall of the second part and contacts the inner wall of the outer ring and the end face of the first part near the second stacked structure.

4. The semiconductor device according to claim 2, wherein, The first stacked structure has multiple first steps, and the second stacked structure has multiple second steps, wherein the top layer of both the first and second steps is the material layer. The inner core passes through the first step and the second step and is connected to the conductive portion of the material layer at the top of the first step, and the outer ring is connected to the conductive portion of the material layer at the top of the second step.

5. The semiconductor device according to claim 4, wherein, Also includes: A first insulating structure covers the top side of the plurality of first steps; as well as A second insulating structure covers the top side of the plurality of second steps; The inner core portion also passes through the second insulation structure and the first insulation structure, and the outer ring portion also passes through the second insulation structure.

6. The semiconductor device according to claim 4, wherein, Also includes: A first gate line slot structure penetrates the second stack structure and the first stack structure, and extends along a first direction perpendicular to the stacking direction; The first stacked structure and the second stacked structure are located between adjacent first gate line slot structures.

7. The semiconductor device according to claim 6, wherein, In the top layer of the material in the first step and the second step, the conductive portion includes: A first conductive portion is located on one side of the insulating portion in the first direction; and The second conductive portion is located on both sides of the insulating portion along the first direction; The second conductive portion is in contact with the adjacent first gate wire slot structure.

8. The semiconductor device according to claim 7, wherein, In the stacking direction, the thickness of the first conductive portion is greater than the thickness of the second conductive portion.

9. The semiconductor device according to claim 7, wherein, The first stacked structure and the second stacked structure have at least two partitions in a second direction, a first dielectric layer and a material layer constitute a stack pair, the first stacked structures located in adjacent partitions differ by one stack pair, and the second stacked structures located in adjacent partitions differ by one stack pair; Within the same partition, the number of stacked pairs between adjacent first steps is equal to the number of partitions, and the number of stacked pairs between adjacent second steps is equal to the number of partitions; The second direction is perpendicular to the first direction and the stacking direction.

10. The semiconductor device according to claim 9, wherein, Also includes: A second gate slot structure, penetrating the second stack structure and the first stack structure and extending along the first direction, is used to divide the first stack structure and the second stack structure into the at least two partitions.

11. The semiconductor device according to claim 10, wherein, In the material layers of the first and second steps, excluding the top material layer, the conductive portion is located on both sides of the insulating portion along the first direction and is in contact with the second gate slot structure and / or the first gate slot structure.

12. The semiconductor device according to claim 1, wherein, The semiconductor device has a stepped region and a core region. The first stacked structure and the second stacked structure are located in the stepped region and extend to the core region. The portions of the first stacked structure and the second stacked structure located in the core region include a plurality of alternately arranged second dielectric layers and a plurality of gate layers. The plurality of first dielectric layers are respectively connected to the plurality of second dielectric layers, and the plurality of gate layers are respectively connected to each of the conductive portions in the plurality of material layers. The semiconductor device further includes: Multiple channel structures penetrate the portions of the first stacked structure and the second stacked structure located in the core region.

13. A memory system, characterized in that, include: A three-dimensional memory, comprising at least one semiconductor device as described in any one of claims 1 to 12; as well as A controller, coupled to the three-dimensional memory, is used to control the storage of data in the three-dimensional memory.

14. A method for manufacturing a semiconductor device, characterized in that, include: Forming a first contact hole that penetrates the first initial stacked structure; A second initial stack structure is formed on one side of the first initial stack structure. Both the first initial stack structure and the second initial stack structure include multiple dielectric layers and multiple sacrificial layers that are alternately arranged. A second contact hole is formed, penetrating the second initial stacked structure to the first contact hole; A portion of each of the sacrificial layers is replaced with a conductive portion to form a material layer, wherein the remaining portion of the sacrificial layer serves as an insulating portion of the material layer; as well as An outer ring portion connected to the conductive portion of one of the material layers is formed in the second contact hole, and an inner core portion connected to the conductive portion of one of the material layers is formed in the first contact hole and the second contact hole.

15. The manufacturing method according to claim 14, wherein, The method further includes: A first filling sacrificial layer is formed in the first contact hole; and A second filling sacrificial layer is formed in the second contact hole; The method comprising forming an outer ring portion in the second contact hole that is connected to a conductive portion in one of the material layers, and forming an inner core portion in the first contact hole and the second contact hole that is connected to a conductive portion in one of the material layers, comprising: Remove the second filler sacrificial layer down to the first filler sacrificial layer; A conductive layer and a first insulating layer are sequentially formed on the inner wall of the second contact hole and on the surface of the first filling sacrificial layer. Remove the portions of the first insulating layer and the conductive layer located on the surface of the first filling sacrificial layer, and remove the end of the conductive layer near the first filling sacrificial layer to form the outer ring portion; A second insulating layer is formed on the inner wall of the first insulating layer and on the end face of the outer ring portion near the first filling sacrificial layer; and The first filler sacrificial layer is removed, and the inner core is formed inside the second insulating layer and in the first contact hole.

16. The manufacturing method according to claim 15, wherein, The materials of the first filling sacrificial layer and the second filling sacrificial layer are different from each other.

17. The manufacturing method according to claim 15, wherein, The first initial stacked structure is formed on one side of the substrate, the first contact hole extends into the substrate, the substrate is made of the same material as the first filling sacrificial layer, and the method further includes: The substrate exposed to the first contact hole is subjected to an oxidation treatment.

18. The manufacturing method according to claim 14, wherein, Also includes: The first initial stacked structure is etched to form multiple first steps; A first step sacrificial layer is formed covering the top surface of the plurality of first steps; The second initial stacked structure is etched to form multiple second steps; A second step sacrificial layer is formed covering the top surface of the plurality of second steps; as well as A first gate line gap is formed that penetrates the second step sacrificial layer, the second initial stack structure, the first step sacrificial layer, and the first initial stack structure; The method of replacing a portion of each of the sacrificial layers with a conductive portion to form a material layer includes: Using the first gate line gap, the edge portion of the sacrificial layer near the first gate line gap, the first step sacrificial layer and the second step sacrificial layer, and the portion of the sacrificial layer covered by the first step sacrificial layer and the second step sacrificial layer, respectively, are replaced with the conductive portion.

19. The manufacturing method according to claim 18, wherein, The first step sacrificial layer and the second step sacrificial layer have oxide layers on the sidewalls exposed to the first gate wire gap; Specifically, replacing the edge portion of the sacrificial layer near the first gate line gap, the first step sacrificial layer, the second step sacrificial layer, and the portions of the sacrificial layer respectively covered by the first step sacrificial layer and the second step sacrificial layer with the conductive portion using the first gate line gap includes: Using the first grid line gap, the first sub-part of the sacrificial layer near the first grid line gap is removed, and the first step sacrificial layer and the second step sacrificial layer are exposed; Remove the first step sacrificial layer and the second step sacrificial layer; Remove the second sub-portion of the sacrificial layer near the first gate gap and the portions of the sacrificial layer covered by the first step sacrificial layer and the second step sacrificial layer, respectively, to form a sacrificial gap; and The conductive portion is formed in the sacrificial gap; Wherein, in the extension direction perpendicular to the first grid line slot, the total thickness of the first sub-part and the second sub-part is equal to the thickness of the edge portion.

20. The manufacturing method according to claim 18, wherein, The method further includes: A second gate wire slot is formed, penetrating the second step sacrificial layer, the second initial stack structure, the first step sacrificial layer, and the first initial stack structure. The second gate wire slot extends along a first direction and divides the first and second initial stack structures into at least two partitions arranged in a second direction. The first and second directions are perpendicular to each other with respect to the stacking direction. The method of replacing a portion of each of the sacrificial layers with a conductive portion to form a material layer includes: Using the second gate line gap, the edge portion of the sacrificial layer near the second gate line gap, the first step sacrificial layer and the second step sacrificial layer, and the portion of the sacrificial layer covered by the first step sacrificial layer and the second step sacrificial layer, respectively, are replaced with the conductive portion.

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