Silicon carbide-based electrostatic induction thyristor and preparation method thereof

Abstract

The invention relates to a silicon carbide-based electrostatic induction thyristor, which comprises an N + rectangular channel region close to an N-type drift region and an N + curved channel region positioned on the N + rectangular channel region, the P + type gate region is of a three-section type gate structure and specifically comprises a P + type rectangular gate region close to the N type drift region, a P type bent gate region located on the P + type rectangular gate region and a gate region adjacent aluminum contact electrode part located on the P type bent gate region. And the bottom of the trench structure cathode is also provided with a cathode bottom P + region opposite to the P-type bent gate region. By introducing a new structural design, stronger grid control capability, higher breakdown voltage and better current uniform distribution are realized.

Description

Technical Field

[0001] The invention relates to the field of power semiconductor devices, and in particular to a silicon carbide-based electrostatic induction thyristor and a preparation method thereof. Background Art

[0002] In the power electronics industry, thyristors are widely used semiconductor devices, mainly used in medium-high voltage and high current control applications. Traditional thyristors are made of silicon materials, but this material has performance limitations in high temperature, high voltage and high frequency environments. For example, the thermal conductivity of silicon materials is 1.56 W / (cm*K), which is lower than the 4.9 W / (cm*K) of silicon carbide materials; and the breakdown voltage of silicon devices (2.5 e 5 V / cm) also limits its application in high voltage applications. Compared to silicon, silicon carbide has unique electrical properties, such as wide bandgap, high thermal conductivity, high critical electric field strength, and higher critical electric field strength, thermal conductivity, and electron mobility. These properties enable semiconductor devices based on silicon carbide to withstand higher voltages at the same size, while having faster switching speeds and better thermal stability. Compared to the pioneering exploration of power devices such as VDMOS in materials such as silicon carbide and gallium nitride, thyristors lag behind in using third-generation semiconductor materials such as silicon carbide as device substrates.

[0003] However, due to the large input capacitance, output capacitance, and feedback capacitance, the switching speed of traditional thyristors is relatively slow, which limits their performance in high-frequency applications. In circuits that require fast switching, this switching speed limitation may lead to insufficient device performance. In addition, traditional thyristor devices often face a series of trade-offs and compromises during design. For example, increasing the current carrying capacity of the device is usually accompanied by an increase in the on-resistance, while reducing the on-resistance may affect the switching performance and control sensitivity of the device. These factors limit the performance of the device in high-efficiency and high-power density applications. Summary of the invention

[0004] In view of the problems existing in the above-mentioned prior art, the present invention aims to solve the defects of traditional silicon-based thyristors in terms of control accuracy, voltage tolerance, gate conductivity, high-frequency characteristics and high-temperature stability. By introducing a new structural design, a stronger gate control capability, a higher breakdown voltage and better current uniformity distribution are achieved, thereby providing an innovative solution for the field of high-performance power electronic devices.

[0005] The silicon carbide-based electrostatic induction thyristor of the present invention comprises an anode P+ region, an N-type drift region located on the anode P+ region, an N+ channel region located on the N-type drift region, a P+ gate region, and a trench structure cathode; The N+ channel region includes an N+ rectangular channel region close to the N-type drift region and an N+ curved channel region located on the N+ rectangular channel region; The P+ type gate region is a three-segment gate structure, specifically including a P+ type rectangular gate region close to the N type drift region, a P type curved gate region located on the P+ type rectangular gate region, and a gate region located on the P type curved gate region adjacent to an aluminum contact electrode portion; The bottom of the trench structure cathode is also provided with a cathode bottom P+ region opposite to the P-type curved gate region.

[0006] Furthermore, the P-type curved gate region of the silicon carbide-based electrostatic induction thyristor described in the present invention is a concave structure.

[0007] Furthermore, the cathode bottom P+ region of the silicon carbide-based electrostatic induction thyristor described in the present invention is a convex structure corresponding to the P-type curved gate region.

[0008] Furthermore, the N+ curved channel region of the silicon carbide-based electrostatic induction thyristor described in the present invention is realized by a P-type curved gate region with an inner concave structure and a cathode bottom P+ region with an outer convex structure.

[0009] Furthermore, the thickness of the anode P+ region of the silicon carbide-based electrostatic induction thyristor of the present invention is 150-200 μm, and the doping concentration is 5e 19 ~3e 20 / cm 3 The doping concentration of the P+ type rectangular gate region and the P type curved gate region is 3e 18 ~7e 18 / cm 3 The doping concentration of the gate region adjacent to the aluminum contact electrode is 3.5e 19 ~8e 19 / cm 3 ; The doping concentration of the P+ region at the bottom of the cathode is 2e 19 ~5e 19 / cm 3 If the doping concentration of the P+ region at the bottom of the cathode is too high, the saddle surface barrier is difficult to establish, and the modulation effect of the gate on the saddle surface peak is reduced; if the concentration is too low, the device body resistance is too large, and the on-state voltage drop is too large, which can easily cause the device to burn out.

[0010] Furthermore, the lateral spacing between the cathode in the P+ region trench structure at the bottom of the cathode and the aluminum contact electrode portion adjacent to the gate region is 3-5 μm, and the epitaxial doping concentration of the N+ curved channel region is 1.1-4 times the doping concentration of the N+ curved channel region.

[0011] On the other hand, the present invention further provides a method for preparing a silicon carbide-based electrostatic induction thyristor based on any of the above, which specifically comprises the following steps: 1) Using a doping concentration of 5e 19 ~3e 20 / cm 3 The P-type silicon carbide wafer is used as the anode P+ region and also as the device substrate, and an N-type doped region is epitaxially grown on its surface as the device region; 2) Step-by-step epitaxy and step-by-step implantation are used to form an N+ rectangular channel region and a P+ rectangular gate region, and a deposited nitride layer is used to block ion implantation, wherein each step of implantation uses the same dose, the same temperature but different energies, and the injection energies are implanted in sequence from large to small; the step-by-step implantation uses an incident angle of 45° toward the cathode region; the step-by-step epitaxy uses a doping concentration of 5e 12 ~1e 13 / cm 3 N-type epitaxy; 3) Perform ion implantation of the P-type curved gate region at an angle perpendicular to the wafer, and make the width of the P-type curved gate region smaller than the width of the P+ type rectangular gate region; 4) Also adopting step-by-step epitaxy and step-by-step implantation to form a P+ region at the bottom of the cathode, thereby forming an N+ curved channel region realized by a P-type curved gate region with an inner concave structure and a P+ region at the bottom of the cathode with an outer convex structure; 5) Using a doping concentration of 2e 13 ~1e 14 / cm 3 N-type epitaxy is performed, and ion implantation is performed at an incident angle of 45° toward the cathode region to form an aluminum contact electrode portion adjacent to a gate region having the same width as the P+ type rectangular gate region.

[0012] In step 1), in order to take into account the withstand voltage characteristics in the off state and the low on-state voltage drop, a doping concentration of 1e 13 ~5e 13 / cm 3 N-type silicon carbide wafer is used as the device substrate.

[0013] In step 5), the anode and cathode electric fields are longitudinal and have no component in the lateral direction. To reduce the channel body resistance, ion implantation is used to form a gate region with the same width as the P+ type rectangular gate region adjacent to the aluminum contact electrode portion, and at the same time, the breakdown voltage can be increased when the gate is reverse biased.

[0014] In the preparation method, the P+ rectangular gate region, the P-type curved gate region, and the P+ region at the bottom of the cathode are all epitaxially grown in steps using high-temperature and high-energy ion implantation to form high-quality high-doping concentration gates. During ion implantation, nitride is used as a protective layer to prevent damage to the surface lattice of the non-implanted area during high-energy particle implantation. After the implantation, high-temperature annealing is performed to restore the damaged valence bonds.

[0015] The P+ rectangular gate region is formed by forming a 45° angle between the wafer and the ion implantation direction, and the wafer is rotated 90° four times each time through high-temperature and high-energy ion implantation to form a rectangular P+ gate region slightly larger than the aperture of the mask. This region uses a superjunction structure to achieve preliminary regulation of the channel region barrier, increase the withstand voltage range, and also increase the conductive area perpendicular to the structural plane direction, thereby increasing the conductivity.

[0016] Furthermore, the preparation method of the present invention also includes a thermal diffusion process, and the thermal diffusion process is specifically kept at a temperature of 1400~1600K for 30~50min.

[0017] Furthermore, the preparation method of the present invention also includes depositing a protective layer to prevent the gate from contacting the cathode, etching the cathode groove, depositing aluminum, and leading out the metal electrode.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects: The silicon carbide-based electrostatic induction thyristor described in the present invention adopts a three-section gate structure, in which the concave P-type curved gate region of the middle section and the convex P+ region at the bottom of the cathode form an N+ curved channel region. This design makes the channel region include a "turning structure", which increases the contact area between the metallurgical junction and the region under the same controlled area, thereby significantly enhancing the gate's control over the channel. On the other hand, the convex P+ region at the bottom of the cathode can also prevent the current from going directly from the anode to the cathode, but conducts through the N+ curved channel regions on both sides of the P+ region at the bottom of the cathode, avoiding the current concentration effect.

[0019] The design of the trench structure cathode of the silicon carbide-based electrostatic induction thyristor described in the present invention increases the contact area between the cathode and the device, improves the conductivity, increases the distance between the aluminum contact electrode portion adjacent to the gate area in the lateral direction, increases the gate-to-cathode breakdown voltage, and thus enhances the stability of the device in high voltage applications.

[0020] The design of the P+ region at the bottom of the cathode of the silicon carbide-based electrostatic induction thyristor of the present invention can further improve the gate-to-positive breakdown voltage, increase the robustness of gate control, reduce the breakdown risk, and make the device more reliable in a high-voltage environment. The distance between the aluminum contact electrode portion adjacent to the gate region is increased in the lateral direction, so that there is a larger contact area and the conductivity is increased. At the same time, by increasing the doping concentration in the middle region and reducing the width of the space charge region, the effect of increasing the gate-to-negative breakdown voltage is finally achieved.

[0021] The superjunction structure design of the silicon carbide-based electrostatic induction thyristor described in the present invention is: that is, a P+-type rectangular gate region. In the electrostatic induction thyristor, the gate current is relatively large, which may easily lead to the gate being mistakenly turned on or partially unable to be turned off during large-scale integration. This design can enhance the gate conductivity on the one hand, and ensure that the gate potential is at the same height under a large integration area. At the same time, the shape change of the depletion region when it expands outward during blocking is controlled. This shape determines the withstand voltage area of ​​the device in the off state. This design ensures that the channel depletion region can expand outward synchronously when it is turned off.

[0022] The anode P+ region and the aluminum metal layer deposited at the anode realize ohmic contact; the cathode is a Schottky contact. Since the current inside the device can only flow from the anode to the cathode, the Schottky contact provides more electrons for the device, increases the electron current, and reduces the current crowding effect.

[0023] In addition, the preparation method of the present invention uses a submicron process mask to form a high-quality gate by step-by-step epitaxial implantation through high-temperature and high-energy ion implantation. At the same time, in order to reduce the damage to the surface lattice caused by high-energy particle implantation, the non-implantation area is protected by a generated nitride layer during each ion implantation, combining the advantages of the surface gate and buried gate structure, and optimizing its potential distribution by precisely controlling the depth and width of the gate adjacent to the barrier control area. This design enhances the control of the potential on the carriers, while increasing the switching speed of the device and reducing power loss.

[0024] The silicon carbide-based electrostatic induction thyristor described in the present invention has an operating range of 50MHz~400MHz; a blocking gain G=900, and has the characteristics of small static loss in the blocking state, high operating frequency compared to other high-power devices, small off-state and on-state gate current, and large-scale integration.

[0025] The device can withstand a blocking voltage of 2000~3000V and is not easy to break down. The on-state voltage drop is 0.8, the threshold voltage is 3V, and the on-state resistance is less than 0.5mΩ / cm 2 , the input capacitance is 9.2*10 -11 F / cm 2 , the output capacitance is 2.1*10 -11 F / cm 2 , the feedback capacitor is 1.3*10 -11 F / cm 2. The new electrostatic induction thyristor uses 4H-SiC as the substrate, and uses its wide bandgap characteristics to significantly improve the device's voltage resistance. Due to the extensive application of lithium batteries (3.7V) and lead-acid batteries (12V) in industry and life, this invention uses a lower gate voltage control (3~5V), which has a larger application scenario compared to the traditional silicon carbide VDMOS control voltage (15~20V); compared to the VDMOS conductive channel, which must be formed through weak inversion and strong inversion, it is affected by the inversion carrier generation rate and cannot achieve high frequency. The device controls conduction and shutdown through barrier control and can be used in ultra-high frequency circuits. It can be mainly used in radar, aviation, base stations and other scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is an equivalent schematic diagram of the traditional surface gate electrostatic induction thyristor structure; Figure 2 It is an equivalent schematic diagram of the traditional buried-gate electrostatic induction thyristor structure; Figure 3 Schematic diagram of the structural equivalent of the silicon carbide-based electrostatic induction thyristor of the present invention; Figure 4 It is an equivalent schematic diagram of the P-type anode region of anode deposition; Figure 5 It is an equivalent schematic diagram of forming a super junction structure by step-by-step epitaxy and implantation; Figure 6 It is an equivalent schematic diagram of epitaxy and ion implantation into a strong gate region; Figure 7 This is an equivalent schematic diagram of the P-type region at the bottom of the cathode formed by injection; Figure 8 This is an equivalent schematic diagram of epitaxy and ion implantation to increase the gate height; Fig. 9 It is an equivalent schematic diagram of forming an oxide layer between electrodes, etching cathode grooves and depositing and etching aluminum; Fig.10 yes Figure 3 Stereoscopic diagram: Among them: 1. Anode P+ region, 2. P+ rectangular gate region, 3. P-type curved gate region, 4. P+ region at the bottom of cathode, 5. N+ curved channel region, 6. Gate region adjacent to aluminum contact electrode portion, 7. Trench structure cathode, 8. Maintenance layer, 9. N-type drift region, 10. N+ rectangular channel region. DETAILED DESCRIPTION

[0027] In order to make the technical content and implementation effects of the present invention more deeply and clearly understood, the detailed implementation mode of the present invention will be described with reference to the accompanying drawings. It should be pointed out that the embodiment only represents one of the possible implementation forms of the present invention and is not limited to all possible implementation forms. Under the guidance of the present invention, practitioners with conventional technical level can derive all alternative implementation modes without involving creative work, and these alternative implementation modes also belong to the scope of protection covered by the present invention. For the part where the conditions are not specifically specified in the deductive implementation mode, the operation should be carried out according to the conventional conditions in the industry or the conditions recommended by the manufacturer.

[0028] In the following description, unless otherwise specified, the same figure numbers generally refer to the same or similar elements. The embodiments provided herein do not reflect all implementations of the present invention, but are only intended to illustrate exemplary embodiments of devices and methods consistent with certain aspects described in the claims of the present invention. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Specific implementation method one:

[0029] A silicon carbide-based electrostatic induction thyristor, comprising an anode P+ region, an N-type drift region located on the anode P+ region, an N+ channel region located on the N-type drift region, a P+ gate region, and a trench structure cathode; The N+ channel region includes an N+ rectangular channel region close to the N-type drift region and an N+ curved channel region located on the N+ rectangular channel region; The P+ type gate region is a three-segment gate structure, specifically including a P+ type rectangular gate region close to the N type drift region, a P type curved gate region located on the P+ type rectangular gate region, and a gate region located on the P type curved gate region adjacent to an aluminum contact electrode portion; The bottom of the trench structure cathode is also provided with a cathode bottom P+ region opposite to the P-type curved gate region.

[0030] In some other embodiments, the P-type bent gate region of the silicon carbide-based electrostatic induction thyristor is a concave structure.

[0031] In some other embodiments, the P+ region at the bottom of the cathode of the silicon carbide-based electrostatic induction thyristor is a convex structure corresponding to the P-type curved gate region.

[0032] In some other embodiments, the N+ curved channel region of the silicon carbide-based electrostatic induction thyristor is realized by a P-type curved gate region with an inner concave structure and a cathode bottom P+ region with an outer convex structure.

[0033] In some other embodiments, the thickness of the anode P+ region of the silicon carbide-based electrostatic induction thyristor is 150-200 μm, and the doping concentration is 5e19 ~3e 20 / cm 3 The doping concentration of the P+ type rectangular gate region and the P type curved gate region is 3e 18 ~7e 18 / cm 3 The doping concentration of the gate region adjacent to the aluminum contact electrode is 3.5e 19 ~8e 19 / cm 3 ; The doping concentration of the P+ region at the bottom of the cathode is 2e 19 ~5e 19 / cm 3 .

[0034] In some other embodiments, the lateral spacing between the cathode in the P+ region trench structure at the bottom of the cathode and the aluminum contact electrode portion adjacent to the gate region is 3-5 μm, and the epitaxial doping concentration of the N+ curved channel region is 1.1-4 times the doping concentration of the N+ curved channel region. Specific implementation method 2:

[0035] A method for preparing a silicon carbide-based electrostatic induction thyristor according to any of the above specific embodiments comprises the following steps: 1) Using a doping concentration of 5e 19 ~3e 20 / cm 3 The P-type heavily doped silicon carbide wafer is used as the anode P+ region, and then the epitaxial N-type doped layer is used as the substrate; 2) Step-by-step epitaxy and step-by-step implantation are used to form an N+ rectangular channel region and a P+ rectangular gate region, and a deposited nitride layer is used to block ion implantation, wherein each step of implantation uses the same dose, the same temperature but different energies, and the injection energies are implanted in sequence from large to small; the step-by-step implantation uses an incident angle of 45° toward the cathode region; the step-by-step epitaxy uses a doping concentration of 5e 12 ~1e 13 / cm 3 N-type epitaxy; 3) Perform ion implantation of the P-type curved gate region at an angle perpendicular to the wafer, and make the width of the P-type curved gate region smaller than the width of the P+ type rectangular gate region; 4) Also adopting step-by-step epitaxy and step-by-step implantation to form a P+ region at the bottom of the cathode, thereby forming an N+ curved channel region realized by a P-type curved gate region with an inner concave structure and a P+ region at the bottom of the cathode with an outer convex structure; 5) Using a doping concentration of 2e 13 ~1e 14 / cm 3N-type epitaxy is performed, and ion implantation is performed at an incident angle of 45° toward the cathode region to form an aluminum contact electrode portion adjacent to a gate region having the same width as the P+ type rectangular gate region.

[0036] In some other embodiments, the preparation method further includes a thermal diffusion process, and the thermal diffusion process is specifically heat preservation at a temperature of 1400-1600K for 30-50 minutes.

[0037] In some other embodiments, the preparation method further comprises depositing a protective layer to prevent the gate from contacting the cathode, etching the cathode groove, depositing aluminum, and leading out the metal electrode. Embodiment 1:

[0038] In a silicon carbide-based electrostatic induction thyristor of the present invention, in a crystal material, since atoms are arranged in a regular lattice form, the atomic arrangement gaps in certain specific crystal directions are larger. When ions are injected along these crystal directions, they encounter the least collisions and penetrate deeper. Therefore, the {0 0 0 1} crystal direction is selected and the tilt angle is set to 4 degrees.

[0039] See attached Figure 3 and Fig.10 , which is a global structural image of the present invention. Due to regional limitations, the regional annotations are detailed in the subsequent figures.

[0040] See attached Figure 4 The present invention uses a P-type heavily doped silicon carbide wafer with a doping concentration of 5e19~3e20 / cm3 as the anode P+ region 1, and then epitaxially grows an N-type doped layer as a substrate.

[0041] See attached Figure 5 In the figure, the P+ rectangular gate region 2 is adopted. In order to ensure uniform doping concentration and fit the actual process conditions, six times of distributed epitaxy and injection are selected to form the gate region. The step-by-step epitaxy and distributed injection are adopted to ensure the uniformity of doping in the entire region, and to accurately shape the regional appearance and the uniformity of regional conductivity. For the doping concentration of each layer, a doping concentration of 5e 12 ~1e 13 / cm 3 N-type epitaxy with high doping concentration. To achieve high-temperature and high-energy ion implantation, a deposited nitride layer is used to block ion implantation instead of photoresist. To ensure the uniformity of implantation, the same dose is used after each deposition: 3e 16 / cm 2 Concentration, the same temperature of 500K, but multiple injections with different energies of 700KeV, 500KeV, 360KeV, 240KeV, 120KeV, and 30KeV respectively, to ensure the continuity of doping in the multi-layer injection area, and the injection energy is injected in sequence from large to small.

[0042] See attached Figure 6 In the figure, the P-type curved gate region 3 uses a different ion implantation angle compared to the P+ type rectangular gate region 2. The P+ type rectangular gate region 2 uses an incident angle of 45° toward the cathode region for ion implantation. The wafer is rotated 90° each time, divided into four times, that is, the implantation is completed after one rotation, so that the area is slightly larger than the nitride aperture after the mask is etched. The P-type curved gate region 3 uses an implantation angle perpendicular to the wafer for ion implantation, forming a P-type curved gate region 3 with a width slightly smaller than the P+ type rectangular gate region 2, so as to achieve better control of the channel region by the overall gate region.

[0043] See attached Figure 7 In order to reduce the current gathering effect at the bottom of the cathode and change the current flow path, that is, to force it to flow to the cathode through the N+ curved channel region 5 to enhance the control over the current, a P+ region 4 is added to the bottom of the cathode by ion implantation. This region uses the same implantation method and related parameters as the gate region to form the structure shown in the figure.

[0044] See attached Figure 8 , using a doping concentration of 2e 13 ~1e 14 / cm 3 N-type epitaxy with a doping concentration of 1. Ion implantation is also performed at an incident angle of 45° toward the cathode region to form a gate region adjacent to an aluminum contact electrode portion 6 with the same width as the P+ type rectangular gate region 2.

[0045] See attached Fig. 9 , by depositing a protective layer 8 to prevent the gate from contacting the cathode, while etching the cathode groove, depositing aluminum, and leading out the metal electrode.

[0046] In this embodiment 1, the lateral spacing between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is Lμm, and L is 3.7μm, and the epitaxial doping concentration of the N+ curved channel region 5 is N times the doping concentration of the N+ curved channel region 5, and N is 2. Embodiment 2:

[0047] The difference between the second embodiment and the first embodiment is that the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is 3 μm. Embodiment 3:

[0048] The only difference between the present embodiment 3 and the embodiment 1 is that the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is 5 μm. Embodiment 4:

[0049] The difference between this embodiment 4 and embodiment 1 is that the epitaxial doping concentration of the N+ curved channel region 5 is 1.1 times the doping concentration of the N+ curved channel region 5 . Embodiment 5:

[0050] The difference between this embodiment 5 and embodiment 1 is that the epitaxial doping concentration of the N+ curved channel region 5 is 4 times the doping concentration of the N+ curved channel region 5 .

[0051] Comparative Example 1 like Figure 1 As shown, comparative example 1 is a traditional surface gate thyristor. Since the device structure adopts single diffusion, the junction depth is shallow, and a higher gate voltage is required to control the saddle surface barrier at the bottom of the cathode, which makes the device more easily broken down, and the device blocking voltage drop is low.

[0052] Comparative Example 2 like Figure 2 As shown, this comparative example 2 is a traditional buried gate thyristor. Since the device adopts a buried gate structure, the high-frequency characteristics of the device are relatively weak. At the same time, the thyristor gate current is large, and in high-power application scenarios, the device cannot be in the same conduction state globally, and partial opening, partial closing or weak opening can be achieved.

[0053] Comparative Example 3: The difference between the comparative example 3 and the embodiment 1 is that the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is 2 μm.

[0054] Comparative Example 4: The difference between the comparative example 4 and the embodiment 1 is that the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is 7 μm.

[0055] Comparative Example 5: The difference between this comparative example 5 and the embodiment 1 is that the epitaxial doping concentration of the N+ curved channel region 5 is 0.5 times the doping concentration of the N+ curved channel region 5 .

[0056] Comparative Example 6: The difference between this comparative example 6 and the embodiment 1 is that the epitaxial doping concentration of the N+ curved channel region 5 is 6 times the doping concentration of the N+ curved channel region 5 .

[0057] Table 1 Device parameter performance table in Examples 1 to 5 and Comparative Examples 3 to 6

[0058] The present invention has been described in the above embodiments and examples, and it should be understood by those skilled in the relevant art that the present invention can be subjected to various modifications and equivalent substitutions without departing from its protection scope. The parts not specifically described in this specification belong to the technical knowledge known to those skilled in the art. In addition, the present invention may be modified accordingly according to the specific implementation scenario, which will not depart from the scope of the present invention. Therefore, the protection scope of the present invention shall be based on the scope defined in the claims, including all various implementation forms within the scope covered by the claims of the present invention.

Claims

1. A silicon carbide based electrostatic induction thyristor, characterized in that: It comprises an anode P+ region (1), an N-type drift region (9) located on the anode P+ region (1), an N+ channel region located on the N-type drift region (9), a P+ gate region, and a trench structure cathode (7); The N+ channel region comprises an N+ rectangular channel region (10) close to the N-type drift region (9) and an N+ curved channel region (5) located on the N+ rectangular channel region (10); The P+ type gate region is a three-segment gate structure, specifically comprising a P+ type rectangular gate region (2) close to the N type drift region (9), a P type curved gate region (3) located on the P+ type rectangular gate region (2), and a gate region adjacent to an aluminum contact electrode portion (6) located on the P type curved gate region (3); A cathode bottom P+ region (4) is also provided at the bottom of the trench structure cathode (7) opposite to the P-type curved gate region (3).

2. The silicon carbide based electrostatic induction thyristor according to claim 1, characterized in that: The P-type curved gate region (3) is a concave structure.

3. The silicon carbide based electrostatic induction thyristor according to claim 2, characterized in that: The cathode bottom P+ region (4) is an outward convex structure corresponding to the P-type curved gate region (3).

4. The silicon carbide based electrostatic induction thyristor according to claim 3, characterized in that: The N+ curved channel region (5) is realized by a P-type curved gate region (3) with an inner concave structure and a cathode bottom P+ region (4) with an outer convex structure.

5. The silicon carbide based electrostatic induction thyristor according to claim 1, characterized in that: The thickness of the anode P+ region (1) is 150-200 μm, and the doping concentration is 5e 19 ~3e 20 / cm 3 The doping concentrations of the P+ type rectangular gate region (2) and the P type curved gate region (3) are both 3e 18 ~7e 18 / cm 3 The doping concentration of the gate region adjacent to the aluminum contact electrode portion (6) is 3.5e 19 ~8e 19 / cm 3 The doping concentration of the cathode bottom P+ region (4) is 2e 19 ~5e 19 / cm 3 .

6. The silicon carbide based electrostatic induction thyristor according to claim 1, characterized in that: The lateral spacing between the trench structure cathode (7) and the aluminum contact electrode portion (6) adjacent to the gate region is 3-5 μm, and the epitaxial doping concentration of the N+ curved channel region (5) is 1.1-4 times the doping concentration of the N+ curved channel region (5).

7. A method for preparing a silicon carbide-based electrostatic induction thyristor according to any one of claims 1 to 6, characterized in that: The specific steps include: 1) Using a doping concentration of 5e 19 ~3e 20 / cm 3 A P-type heavily doped silicon carbide wafer is used as an anode P+ region (1), and then an epitaxial N-type doped layer is used as a substrate; 2) using step-by-step epitaxy and step-by-step implantation to form an N+ rectangular channel region (10) and a P+ rectangular gate region (2), and using a deposited nitride layer to block ion implantation, wherein each step of implantation uses the same dose, the same temperature but different energies, and the injection energies are sequentially implanted from large to small; the step-by-step implantation uses an incident angle of 45° toward the cathode region; the step-by-step epitaxy uses a doping concentration of 5e 12 ~1e 13 / cm 3 N-type epitaxy; 3) performing ion implantation of the P-type curved gate region (3) at an angle perpendicular to the wafer, and making the width of the P-type curved gate region (3) smaller than the width of the P+ type rectangular gate region (2); 4) Similarly, a cathode bottom P+ region (4) is formed by step-by-step epitaxy and step-by-step implantation, thereby forming an N+ curved channel region (5) realized by a P-type curved gate region (3) with an inner concave structure and a cathode bottom P+ region (4) with an outer convex structure; 5) Using a doping concentration of 2e 13 ~1e 14 / cm 3 N-type epitaxy is performed, and ion implantation is performed at an incident angle of 45° toward the cathode region to form an aluminum contact electrode portion (6) adjacent to a gate region having the same width as the P+ type rectangular gate region (2).

8. The preparation method according to claim 7, characterized in that: The preparation method includes a thermal diffusion process after step epitaxy and ion implantation to form a gate region, wherein the thermal diffusion process is specifically carried out at a temperature of 1400-1600 K for 30-50 minutes.

9. The preparation method according to claim 8, characterized in that: The method also includes depositing a protective layer (8) to prevent the gate from contacting the cathode, etching the cathode groove, depositing aluminum, and leading out a metal electrode.

Images