Transistor device with reduced on-resistance

Abstract

The invention relates to a transistor device with reduced on resistance. A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a semiconductor body; first trenches, each first trench extending into the semiconductor body from the first surface of the semiconductor body; second trenches, each second trench extending from the first surface into the semiconductor body; a drift region adjacent to each of the second trenches; source regions, each source region being separated from the drift region by a respective body region; and a gate electrode. Each of the gate electrodes is disposed in one of the first trenches, adjacent to at least one of the body regions, and dielectrically insulated from the at least one of the body regions by a gate dielectric. Each of the second trenches is configured to induce a strain in a region of the drift region adjoining the respective second trench.

Description

Technical Field

[0001] The present disclosure generally relates to a transistor device. Background Art

[0002] In various electronic applications (such as, for example, power conversion circuits, motor drive circuits, etc.), transistor devices (such as, vertical transistor devices) are widely used as electronic switches. In the vertical transistor device, the current path essentially extends in the vertical direction of the semiconductor body in which the transistor device is integrated. Therefore, when the vertical transistor device is in the on state (conducting state), the current flows through the semiconductor body in the vertical direction between the first load path node and the second load path node. In a MOSFET (metal oxide semiconductor field effect transistor), for example, the first load path node is the drain node and the second load path node is the source node.

[0003] The on-resistance of the transistor device is the resistance between the first load path node and the second load path node in the on-state of the transistor device.

[0004] It would be desirable to provide a vertical transistor device having reduced on-resistance. Summary of the invention

[0005] One example relates to a transistor device. The transistor device includes: a semiconductor body; first trenches, each of which extends from a first surface of the semiconductor body into the semiconductor body; second trenches, each of which extends from the first surface into the semiconductor body; a drift region adjacent to each of the second trenches; a source region, each of which is separated from the drift region by a corresponding body region; and a gate electrode. Each of the gate electrodes is arranged in one of the first trenches, adjacent to at least one of the body regions, and is dielectrically insulated from the at least one of the body regions by a gate dielectric, and each of the second trenches is configured to induce strain in a region of the drift region adjacent to the corresponding second trench.

[0006] Another example relates to a method. The method includes: forming a first trench and a second trench in a semiconductor body, each trench extending from a first surface of the semiconductor body into the semiconductor body; forming a drift region adjacent to each of the second trenches; forming a source region, each source region separated from the drift region by a corresponding body region; and forming a gate electrode. Each of the gate electrodes is formed in one of the first trenches, adjacent to at least one of the body regions, and dielectrically insulated from the at least one of the body regions by a gate dielectric. Forming the second trench includes: forming the second trench so that each of the second trenches is configured to induce strain in a region of the drift region adjacent to the corresponding second trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles, and thus only illustrate aspects necessary for understanding these principles. The accompanying drawings are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals indicate similar features.

[0008] Figure 1 illustrating a vertical cross-sectional view of a transistor device having a plurality of first trenches and a plurality of second trenches, each first trench including a gate electrode, each second trench being adjacent to a drift region and configured to induce strain in the adjacent drift region;

[0009] Figure 2 Graphics based on Figure 1 A variation of a transistor device;

[0010] Figure 3 showing a detailed view of a section of the transistor device according to claim 1 to illustrate certain dimensions in the transistor device;

[0011] Figure 4-6 illustrating various examples of top views of semiconductor bodies;

[0012] Figure 7A-7B schematically illustrates one example of a method for forming a second trench including a strain inducing material;

[0013] Figure 8-11 illustrating different examples of second trenches, each second trench comprising a strain inducing material;

[0014] Fig.12 The second trench is shown, and in addition to the strain inducing material, the second trench also includes a contact electrode for contacting the adjacent source region and the body region;

[0015] Fig.13 The diagram is used to Fig.12 An example of a contact electrode connected to a source electrode of a transistor device;

[0016] Fig.14 illustrates a top view of a transistor device according to an example; and

[0017] Fig.15 An example for connecting a field electrode arranged below the gate electrode in the first trench to the source electrode is illustrated. DETAILED DESCRIPTION

[0018] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form part of this description and show examples of how the invention may be used and implemented for the purpose of illustration. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically noted.

[0019] Figure 1 A transistor device according to one example is shown. More particularly, Figure 1 A vertical cross-sectional view of a portion of a transistor arrangement is shown. The transistor arrangement comprises a semiconductor body 100. The semiconductor body 100 comprises a first surface 101 and a second surface 102. The second surface 102 is opposite to the first surface 101 and is spaced apart from the first surface 101 in a vertical direction z of the semiconductor body 100.

[0020] According to an example, the semiconductor body 100 is a single crystalline semiconductor body. According to an example, the semiconductor body 100 includes single crystalline silicon (Si) or single crystalline silicon carbide (SiC), but may also include any type of single crystalline III-V or II-VI semiconductor material.

[0021] Reference Figure 1 , the transistor device further comprises: a plurality of first trenches 2, each of which extends from a first surface 101 of the semiconductor body 100 into the semiconductor body 100; a plurality of second trenches 4, each of which extends from the first surface 101 into the semiconductor body 100; and a drift region 11, adjacent to each of the first trenches 2 and the second trenches 4. In addition, the transistor device comprises a plurality of source regions 13, wherein each source region 13 is separated from the drift region 11 by a respective body region 12. Each of the first trenches 2 comprises a gate electrode, which is arranged adjacent to at least one of the body regions 12 and is dielectrically insulated from the body region 12 by a gate dielectric 22. The first trenches 2 are also referred to as gate trenches in the following.

[0022] The gate electrode 21 is connected to the gate node G, the source region 13 and the body region 12 are connected to the source node S, and the drift region 11 is connected to the drain node D. The connections between the gate electrode 21 and the gate node G, between the source region 13 and the body region 12 on one side and the source node S on the other side, and between the drift region 11 and the drain node D are only schematically illustrated. Figure 1 These connections can be formed using conventional wiring techniques. One example for connecting the source region 13 and the body region 12 to the source node S and for connecting the gate electrode 21 to the gate node G is further explained herein below. The gate electrode 21 includes a conductive material, such as metal or doped polysilicon.

[0023] The transistor device may further comprise a drain region 15 adjacent to the drift region 11, such that the drift region 11 is arranged between the drain region and the body region 12. Figure 1As shown by the dotted line in FIG. 1 , the drain region 15 may be adjacent to the second surface 102 and connected to the drain node D at the second surface 102. However, this is only an example. It is also possible to form the drain region 15 separated from the second surface 102 and connect the drain region 15 to the drain electrode via a sinker, which is arranged on top of the first surface 101 at a position separated from the first trench 2 and the second trench 4. This example is not shown in FIG. Figure 1 middle.

[0024] Each of the drift region 11, the source region 13 and the body region 12 is a doped region in the semiconductor body 100. The drift region 11 and the source region 13 are doped regions of a first doping type (conductivity type), and the body region 12 is a doped region of a second doping type complementary to the first doping type. The drain region (not shown) is a region of the first doping type.

[0025] The transistor device can be implemented as an N-type transistor device or as a P-type transistor device. In an N-type transistor device, the doped regions of the first doping type (drift region 11 and source region 13) are N-type regions, and the doped regions of the second doping type (body region 12) are P-type regions. In a P-type transistor device, the drift region 11 and source region 13 are P-type regions, and the body region 12 is an N-type region.

[0026] In addition, the transistor device can be implemented as an enhancement mode device or as a depletion mode device. In an enhancement mode device, each body region 12 is adjacent to a corresponding gate dielectric 22 (e.g., Figure 1 ). In a depletion mode device, there is a channel region of the same doping type as the source region 13, which is arranged between each body region 12 and the gate dielectric 22. However, such a channel region is not shown in FIG. Figure 1 middle.

[0027] By applying a driving voltage (gate-source voltage) between the gate node G and the source node S, according to Figure 1 The transistor device can be operated in a conventional manner. When the voltage level of the driving voltage applied between the gate node G and the source node S is such that a conductive channel is generated in each body region 12 along the corresponding gate dielectric 22 between the source region 13 and the drift region 11, the transistor device is in an on state (conductive state). For example, when a positive driving voltage higher than the threshold voltage is applied between the gate node G and the source node S, the N-type transistor device is in an on state. In the on state, current can flow from the source node S to the drain node D via the source region 13, the conductive channel in the body region 12, and the drift region 11.

[0028] In the following, the body region 12, the source region 13, the drift region 11 and the drain region are referred to as "active device regions". According to one example, the doping concentration of the active device regions in the silicon semiconductor body 100 is selected from the following ranges: the drift region 11: at 1E15 cm -3 and 3E17 cm -3 Between; Main area 12: 1E16 cm -3 and 5E18 cm -3 Source region 13: higher than 1E19 cm -3 ; Drain region 15: higher than 1E19 cm -3 .

[0029] At least in those sections where the second trench 4 adjoins the drift region 11, the second trench 4 comprises a material that induces strain in the drift region 11 at least at the interface between the trench 4 and the drift region 11. The second trench 4 is also referred to below as a strain-inducing trench. The strain generated by the second trench 4 causes it to reduce the resistivity of the drift region 11 or increase the conductivity of the drift region 11 in those sections adjoining the second trench 4. In this way, the on-resistance (which is the resistance in the on-state) of the transistor device is reduced compared to a conventional transistor device without a strain-inducing trench 4. A more detailed example of a strain-inducing trench 2 is further explained herein below.

[0030] The first trench 2 and the second trench 4 are separated from each other in a lateral direction of the semiconductor body 100. A "lateral direction" is a direction that is substantially parallel to the first surface 101 and perpendicular to the vertical direction z. Figure 1 In the example illustrated in FIG. 4 , the first groove 2 and the second groove 4 are spaced apart from each other in a first lateral direction x.

[0031] In order to distribute the current more evenly in the drift region 11 when the transistor device is in the on-state, the drift region 11 may include a current extension region 14. The current extension region 14 is optional and is therefore illustrated in dashed lines in FIG. Figure 1 The current extension region 14 is part of the drift region 11 and has a higher doping concentration than the rest of the drift region 11. According to an example, the doping concentration of the current extension region 14 is between 2 times and 100 times, in particular between 2 times and 10 times, the doping concentration of the rest of the drift region 11. The current extension region 14 may be adjacent to the body region 12 and extend between the first trench 2 and the second trench 4. Therefore, in the on state, charge carriers injected into the drift region 11 from the source region 12 through the conductive channel in the body region 12 along the gate dielectric 22 can flow within the higher doped current extension region 14 to the second trench 4, and further flow along the second trench 4 in the strain region in the vertical direction z.

[0032] Reference Figure 1 The transistor device may further include a plurality of field electrodes 31, which are dielectrically insulated from the drift region 11 by a field electrode dielectric 32. Each of the field electrodes 31 is arranged below a respective gate electrode 21 in a respective one of the gate trenches 2. The field electrodes 31 include a conductive material, such as metal or doped polysilicon.

[0033] According to one example, the field electrodes 31 are connected to the source node S. In this example, each field electrode 31 is separated from the gate electrode 21 arranged in the same gate trench 2 and is dielectrically insulated from the gate electrode 21. This is illustrated in Figure 1 middle.

[0034] according to Figure 2 In another example illustrated in FIG. 3 , each field electrode 31 adjoins a gate electrode 21 arranged in the same trench. In this example, the field electrode 31 is connected to the gate node G.

[0035] In each case, in the blocking state of the transistor device, the field electrode 31 compensates the charge in the drift region 11 and thus helps to increase the voltage blocking capability or reduce the on-resistance of the transistor device compared to a transistor device without such a field electrode. This is generally known so that no further explanation is provided in this regard.

[0036] Figure 3 Show Figure 1 Detailed view of a section of a semiconductor body 100 is shown in FIG. 1 to illustrate the dimensions of certain features of a transistor device. Figure 3 , the first trench 2 has a first trench depth d2 and a first trench width w2, and the second trench 4 has a second trench depth d4 and a second trench width w4. The “trench depth” is the dimension of the respective trench in the vertical direction z of the semiconductor body 100, and the “trench width” is the (shortest) dimension of the respective trench in the lateral direction of the semiconductor body 100. The gate electrode depth d21 is the dimension of the gate electrode 21 in the vertical direction z.

[0037] According to one example, the second trench 4 extends deeper in the semiconductor body than the gate electrode 21, so that the second trench depth d4 is greater than the gate electrode depth d21, d4>d21. Compared to the first trench 2, the second trench 4 may extend deeper in the semiconductor body 100, so that d4>d2, wherein the second trench depth d4 is less than 1.5 times the first trench depth d2 or less than 1.2 times the first trench depth d2.

[0038] The drift region 11 has a length which is the shortest distance of the drift region 11 between the body region 12 and the drain region 15. The length of the drift region 11 particularly depends on the voltage blocking capability of the transistor device. The "voltage blocking capability" of the transistor device is the maximum voltage that the transistor device can withstand between the drain node and the source node in the blocking state. In a transistor device including a silicon (Si) semiconductor body, the drift region length is approximately 10 micrometers (μm) per 100 V of voltage blocking capability. In a semiconductor device having a voltage blocking capability of 150 V, for example, the drift region length is, for example, between 10 micrometers and 15 micrometers.

[0039] In a transistor device including a SiC semiconductor body, the drift region length is approximately 1 micrometer (μm) per 100 V of voltage blocking capability.

[0040] For example, the absolute depths d2, d4 of the first trench 2 and the second trench 4 depend on the length of the drift region 11. According to one example, the depth d2 of the first trench 2 is between 30% and 60% of the length of the drift region 11. In a transistor device having a silicon semiconductor body 100 and a voltage blocking capability of 15 V, for example, the depth of the first trench 2 can be selected from between 500 nanometers (nm) and 650 nanometers. In a transistor device having a silicon semiconductor body 100 and a voltage blocking capability of 150 V, for example, the depth d2 of the first trench 2 can be selected from between 5 micrometers and 7 micrometers.

[0041] According to one example, the second trench 4 is narrower than the first trench 2, such that w4 < w2. According to another example, the second trench 4 is wider than the first trench 2, such that w4 > w2. According to one example, the ratio of the first trench width to the second trench width w2:w4 is between 0.5:1 and 1:0.5, and in particular, between 0.7:1 and 1:0.7.

[0042] For example, the absolute values of the trench widths w2, w4 depend on the voltage blocking capability of the transistor device. According to one example, in a silicon-based transistor device having a voltage blocking capability of 15 V, the width w2 of the first trench 2 is selected from between 250 nanometers and 400 nanometers. For example, in a silicon-based transistor device having a voltage blocking capability of 150 V, the width w2 of the first trench 2 is selected from between 1.2 micrometers and 2 micrometers.

[0043] In Figure 3, w110 indicates the (shortest) distance between two adjacent first trenches 2. This distance is equal to the width of the mesa region 110 defined by the two adjacent trenches, so that w110 can also be referred to as the mesa width. According to an example, the second trench 4 is essentially located in the middle between the adjacent first trenches 2 defining the mesa region 110. For example, the second trench width w4 is between 0.2 times and 0.7 times, in particular, between 0.4 times and 0.6 times, of the mesa width w110.

[0044] For example, the pitch p of the device structure including the first and second trenches 2 , 4 and the mesa region 110 is given by the mesa width w110 plus the first trench width w2 , p=w110+w2 .

[0045] Figure 1 1 shows a vertical cross-sectional view of the semiconductor body 100. In a horizontal plane (which is a plane essentially parallel to the first surface 101), the first trench 2 and the second trench 4 can be implemented in various ways. Different examples are illustrated in FIG. Figure 4-6 , wherein each of the figures shows a top view of a first surface 101 of a section of a semiconductor body 100 .

[0046] according to Figure 4 In one example shown in FIG. 1 , the first trench 2 and the second trench 4 are elongated trenches substantially parallel to each other. Each of the second trenches is arranged between two adjacent first trenches, wherein the two adjacent first trenches 2 define a mesa region 110, and the second trench 4 is arranged in the mesa region 110. Figure 4 In the example illustrated in , the first grooves 2 and the second grooves 4 are spaced apart from each other in a first lateral direction x and are elongated in a second lateral direction y.

[0047] Figure 5 Show Figure 4 A variation of the example illustrated in . Figure 5 In the example illustrated in , the first trench 2 is an elongated trench, and the second trench 4 is a needle-shaped trench, wherein a plurality of second trenches 4 are formed in each mesa region 110 and are spaced apart from each other in the second lateral direction y.

[0048] according to Figure 6 In another example illustrated in , the first trenches 2 form a grid, wherein the mesa regions 110 are located in the openings of the grid formed by the first trenches 2. In this example, the second trenches 4 are needle-shaped trenches, wherein at least one second trench 4 is arranged in each mesa region 110.

[0049] For illustration purposes only, Figure 6 The grid illustrated in FIG. 1 is a hexagonal grid. However, this is only an example. Other types of grids (such as a square grid or an octagonal grid) may also be implemented.

[0050] In order to induce strain in the drift zone 11 of the semiconductor body 100, the strain inducing trench 4 is at least partially filled with a strain inducing material 41 (see, for example, Figure 7B ), the strain-inducing material 41 has a lower thermal expansion coefficient than the semiconductor material of the drift region 11. For example, silicon has a thermal expansion coefficient of 2.6E-6K -1 (2.6·10 -6 / K). “At least partially filled” may include: at least the sidewalls and the bottom of the strain inducing trench 4 are covered by the strain inducing material, so that an interface between the drift region 11 and the strain inducing material 41 is formed.

[0051] Forming the strain inducing material 41 includes a high temperature process in which the semiconductor body 100 is heated up to a temperature between 600° C. and 1200° C. After the high temperature process strain is induced in the drift region 11 due to the different thermal expansion coefficients of the semiconductor material of the drift region 11 on one side and the strain inducing material 41 on the other side, when the semiconductor body 100 cools down.

[0052] Figure 7A-7B One example of a method for forming a strain inducing trench 4 is illustrated, which is partially filled with a strain inducing material 41 . Figure 7A-7B A section of a semiconductor body 100 comprising one strain-inducing trench is shown. The first trench 2 or further strain-inducing trenches are not illustrated in this figure.

[0053] Fig. 7A The semiconductor body 100 is shown after forming a trench 40 extending from the first surface 101 into the semiconductor body 100. Forming the trench 40 may include a conventional etching process, such as an anisotropic etching process. In addition, a body region 12 and a source region 13 are formed in the drift region 11 (at Figure 7A-7B The trench 40 may be formed before or after the body region 12 and the source region 13 are formed (illustrated as dashed lines in FIG. 1 ). Forming the body region 12 and the source region 13 may include at least one of an implantation and a diffusion process. The process for forming the body region 12 and the source region 13 is generally known, so that no further explanation is provided in this regard.

[0054] Figure 7B The trench 40 is shown after being partially filled with a strain inducing material 41 , which covers the sidewalls and the bottom of the trench 40 to form a strain inducing trench 4 .

[0055] The strain inducing material 41 may be implemented and formed in various ways. According to one example, the strain inducing material 41 is a semiconductor oxide, such as silicon oxide. Forming the strain inducing oxide material 41 may include a deposition process in which the material is deposited on the sidewalls and bottom of the trench 40. According to another example, forming the strain inducing oxide material includes a thermal oxidation process in which the sidewalls and bottom of the trench 40 are oxidized to form the strain inducing oxide material. According to another example, forming the strain inducing oxide material 41 includes forming a first layer by a thermal oxidation process, and forming a second layer on top of the first layer by a deposition process.

[0056] According to another example, the strain inducing material 41 includes a carbon-containing material, such as, for example, silicon oxycarbide (SiOC). SiOC may be formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 600° C. Other examples of the strain inducing material 41 include, but are not limited to, silicon carbide (SiC), glass (such as silicon dioxide (SiO2)), or diamond. These materials may be formed during a deposition process. For example, SiC may be formed using a PECVD process, and diamond may be formed using a chemical vapor deposition (CVD) process.

[0057] Referring to above, the strain inducing material 41 at least partially fills the trench 40. Figure 8 In one example illustrated in FIG. 4 , the trenches 40 are completely filled with the same strain inducing material 41 , wherein the strain inducing material is selected from one of the strain inducing materials previously explained in this document.

[0058] according to Fig. 9 , the strain inducing trench 4 includes: a first strain inducing material 41 covering the sidewalls and the bottom of the trench; and a second strain inducing material 42, which is different from the first strain inducing material 41. The second strain inducing material 42 is formed on top of the first strain inducing material 41 and fills the residual trench remaining after forming the first strain inducing material 41. Each of the first strain inducing material 41 and the second strain inducing material 42 is selected from the strain inducing materials previously explained herein.

[0059] according to Fig.10 , in addition to the strain inducing material 41, the strain inducing trench 4 further includes a conductive material 43, which is formed on top of the strain inducing material 41 and fills the residual trench remaining after forming the strain inducing material 41. The conductive material 43 may include metal or doped polysilicon.

[0060] According to one example, the conductive material 43 is floating, that is, the conductive material is neither connected to the source node S, the gate node G nor the drain node D. In this example, the conductive material 42 is simply used as a filling material.

[0061] According to another example explained further herein below, the conductive material 43 is connected to the source node S. However, in this example, the strain inducing material 41 disposed between the conductive material 43 and the drift region 11 is thicker than the field dielectric 33, so that the conductive material 43 has little effect (if any effect) on the formation of the electric field in the drift region 11. According to one example, the thickness d41 of the strain inducing material 41 is the thickness d32 of the field dielectric 32 (see Figure 3 ) is at least 1.2 times greater than the

[0062] According to one example, the thickness of the field dielectric 32 depends on the voltage blocking capability of the transistor device. In a transistor device with a voltage blocking capability of 15 V, for example, the thickness of the field dielectric 32 is selected from, for example, between 30 nanometers and 50 nanometers. In a transistor device with a voltage blocking capability of 150 V, for example, the thickness of the field dielectric 32 is selected from, for example, between 600 nanometers and 800 nanometers.

[0063] according to Fig.11 In another example illustrated in FIG. 4 , the strain inducing material 41 forms a gap 44 in the strain inducing trench 4 .

[0064] Referring to the above, the body region 12 and the source region 13 are connected to the source node S. Fig.12 In one example illustrated in FIG. 4 , the contact electrode 5 is formed in the strain-inducing trench 4 and is adjacent to the source region 13 and the body region 12. The contact electrode 5 (which includes a conductive material such as metal or doped polysilicon) is connected to the source node S1. Fig.10 As explained, the conductive material 43 may be formed on top of the strain inducing material 41 in the strain inducing trenches 4. The conductive material 43 (in the strain inducing trenches 4) disposed in each of the strain inducing trenches 4 may be formed on top of the strain inducing material 41 in the strain inducing trenches 4. Fig.12 The MOSFET 5 may be adjacent to the corresponding contact electrode 5 and thus connected to the source node S.

[0065] Fig.13 An example for connecting the contact electrode 5 to the source node S is shown in the figure. Fig.13In the example illustrated in , the transistor device comprises a source electrode (source metallization) 71, which is formed on top of an insulating layer 6, which is formed on top of a first surface 101 of the semiconductor body 100. A conductive via 72 extends from the source electrode 71 through the insulating layer 6 down to the contact electrode 5, and connects the contact electrode 5 to the source electrode 71. The source electrode 71 forms a source node S, or is connected to a source node S of the transistor device.

[0066] The connection between the gate electrode 21 and the gate node G is not shown in the figure. Fig.13 An example for connecting the gate electrode 21 to the gate node G is illustrated in FIG. Fig.14 middle. Fig.14 A top view of a transistor device is shown. More particularly, Fig.14 1 shows a top view of a semiconductor body 100 with a source metallization 71. An example of a gate trench 2 and its location below the source metallization 71 is illustrated in dashed lines in FIG. Fig.14 In this example, below the source metallization 71, the gate trench 2 extends beyond the source metallization 71 and is connected to a gate runner 82. The gate runner 82 is formed on top of the insulating layer 6 and is connected to a gate pad 81. The gate pad 81 is connected to a gate node G, or forms a gate node G of the transistor device.

[0067] according to Fig.14 The transistor device may include only one source metallization 71. However, this is only an example. According to another example, the transistor device includes several source metallizations 71, each source metallization 71 is connected to the source node S, and the transistor device includes two or more gate tracks 82, each gate track 82 is connected to the gate pad 51. Each of the gate tracks 82 is arranged between adjacent source metallizations and is separated from the source metallization 71. Such additional gate tracks 82 are illustrated in dashed lines in FIG. Fig.14 middle.

[0068] Further gate tracks 82 and several source metallizations 71 may be implemented in a transistor arrangement comprising a field electrode 31 connected to the source node S. Fig.15 To explain this.

[0069] Fig.15 A vertical cross-sectional view of one gate trench 2 is shown, the gate trench 2 comprising a gate electrode 21 and a field electrode 31 connected to a source node S. Fig.15 A vertical cross-sectional view of the gate trench 2 is shown in a cross-sectional plane extending along the longitudinal direction of the gate trench 2. Fig.15, the field electrode 31 comprises a contact section 33, which extends to the first surface 101 and is connected to the source metallization 71 through a conductive via 73. The contact section 33 is dielectrically insulated from the adjacent gate electrode 21 arranged in the same trench 2. Each of the gate electrodes 21 is connected to a source track 82 through a corresponding conductive via 83. The gate track 82 and the source metallization are formed on top of the insulating layer 6.

[0070] Some of the aspects explained above are briefly summarized below with reference to numbered examples.

[0071] Example 1. A transistor device comprises: a semiconductor body; first trenches, each of the first trenches extending from a first surface of the semiconductor body into the semiconductor body; second trenches, each of the second trenches extending from the first surface into the semiconductor body; a drift region adjacent to each of the second trenches; a source region, each of the source regions being separated from the drift region by a respective body region; and a gate electrode, wherein each of the gate electrodes is arranged in one of the first trenches, adjacent to at least one of the body regions, and dielectrically insulated from the at least one of the body regions by a gate dielectric, wherein each of the second trenches is configured to induce strain in a region of the drift region adjacent to the respective second trench.

[0072] Example 2. The transistor device of Example 1, wherein the second trench is at least partially filled with a strain inducing material.

[0073] Example 3. The transistor device of Example 1 or 2, wherein the strain inducing material has a lower coefficient of thermal expansion than a semiconductor material of the semiconductor body.

[0074] Example 4. The transistor device of Example 3, wherein the strain inducing material comprises at least one of a semiconductor oxide, silicon carbide, carbon, or glass.

[0075] Example 5. The transistor device of any of Examples 1 to 4, wherein the first trench defines a plurality of mesa regions in the semiconductor body, and wherein at least one second trench is arranged in each of the mesa regions.

[0076] Example 6. The transistor device of any of Examples 1 to 5, wherein the first trenches are substantially parallel to each other, and wherein each mesa region is formed between a corresponding pair of adjacent ones of the first trenches.

[0077] Example 7. The transistor device of Examples 1 to 5, wherein the first trenches form a grid, and wherein each mesa region is formed in an opening of the grid.

[0078] Example 8. The transistor device of any of Examples 5 to 7, wherein each mesa region includes at least one of a source region and a corresponding body region.

[0079] Example 9. The transistor arrangement of any of the preceding examples, further comprising: a field electrode arranged in the first trench adjacent to the drift region and dielectrically insulated from the drift region by a field electrode dielectric.

[0080] Example 10. The transistor device of Example 9, wherein the strain inducing material is thicker than the field electrode dielectric.

[0081] Example 11. The transistor device of any one of Examples 2 to 10, wherein the strain inducing material completely fills the second trench.

[0082] Example 12. The transistor device of any one of Examples 2 to 10, wherein the strain inducing material comprises: a first strain inducing material covering the sidewalls and the bottom of the second trench; and a second strain inducing material different from the first strain inducing material and formed on top of the first strain inducing material.

[0083] Example 13. The transistor device of any of Examples 2 to 10, wherein the second trench further comprises a conductive material formed on top of the strain inducing material.

[0084] Example 14. The transistor device of any of Examples 2 to 10, wherein each second trench further comprises a gap surrounded by the strain inducing material.

[0085] Example 15. The transistor device of any one of Examples 1 to 14 further comprises: contact electrodes arranged in the second trench, wherein each of the contact electrodes is adjacent to at least one source region and at least one body region and is connected to a source node of the transistor device.

[0086] Example 16. A method for forming a transistor device, wherein the method includes: forming a first trench and a second trench in a semiconductor body, each trench extending from a first surface of the semiconductor body into the semiconductor body; forming a drift region adjacent to each of the second trenches; forming source regions, each source region separated from the drift region by a corresponding body region; and forming a gate electrode, wherein each of the gate electrodes is formed in one of the first trenches, adjacent to at least one of the body regions, and dielectrically insulated from the at least one of the body regions by a gate dielectric, and wherein forming the second trench includes: forming the second trenches so that each of the second trenches is configured to induce strain in a region of the drift region adjacent to the corresponding second trench.

[0087] Example 17. The method of Example 16, wherein forming the second trench comprises at least partially filling the second trench with a strain inducing material.

[0088] Example 18. The method of Example 17, wherein at least partially filling the second trench with the strain inducing material comprises a high temperature process, and wherein the strain inducing material has a lower coefficient of thermal expansion than a semiconductor material of the semiconductor body.

Claims

1. A transistor device comprising: A semiconductor body (100); first trenches (2), each first trench (2) extending from a first surface (101) of the semiconductor body (100) into the semiconductor body (100); second trenches (4), each second trench (4) extending from the first surface (101) into the semiconductor body (100); A drift region (11) adjacent to each of the second trenches (4); source regions (13), each source region (13) being separated from the drift region (11) by a corresponding body region (12); and a gate electrode (21), wherein each of the gate electrodes (21) is arranged in one of the first trenches (2), adjacent to at least one of the body regions (12), and dielectrically insulated from the at least one of the body regions (12) by a gate dielectric (22), wherein each of the second trenches (4) is configured to induce strain in a region of the drift region (11) adjacent to the respective second trench (4), The second trenches (4) are at least partially filled with the strain-inducing material (41), since at least the sidewalls and the bottom of each of the second trenches (4) are covered by the strain-inducing material (41).

2. The transistor device according to claim 1, The strain-inducing material (41) has a lower thermal expansion coefficient than the semiconductor material of the semiconductor body (100).

3. The transistor device according to claim 2, The strain inducing material (41) comprises at least one of the following materials: Semiconductor oxides, Silicon Carbide, Carbon, or Glass.

4. A transistor device as claimed in any one of claims 1 to 3, wherein the first trench (2) defines a plurality of mesa regions (110) in the semiconductor body (100), and At least one second trench (4) is arranged in each of the mesa regions (110).

5. A transistor device as claimed in any one of claims 1 to 4, wherein the first grooves (2) are substantially parallel to each other, and Each mesa region (110) is formed between a corresponding pair of adjacent first trenches (2) in the first trenches (2).

6. A transistor arrangement as claimed in claims 1 to 4, wherein the first grooves (2) form a grid, and Each mesa region (110) is formed in a grid opening.

7. A transistor arrangement as claimed in any one of claims 4 to 6, Each mesa region (110) includes at least one of the source region (13) and a corresponding body region (12).

8. A transistor arrangement as claimed in any one of the preceding claims, further comprising: A field electrode (31) is arranged in the first trench (2) adjacent to the drift region (11) and is dielectrically insulated from the drift region by a field electrode dielectric (32).

9. The transistor device as claimed in claim 8, The strain inducing material (41) is thicker than the field electrode dielectric (32).

10. A transistor device as claimed in any one of claims 1 to 9, The strain inducing material (41) completely fills the second trench (4).

11. A transistor device as claimed in any one of claims 1 to 9, The strain inducing material (41) comprises: A first strain-inducing material (41) covering the sidewalls and bottom of the second groove (4); and A second strain inducing material (42) is different from the first strain inducing material (41) and is formed on top of the first strain inducing material (42).

12. The transistor device according to claim 11, The second strain inducing material (42) fills the residual trench formed by the first strain inducing material (41).

13. A transistor device as claimed in any one of claims 1 to 9, The second trench (4) further comprises a conductive material (43) formed on top of the strain inducing material (41).

14. A transistor device as claimed in any one of claims 1 to 9, Each of the second trenches (4) further comprises a gap (44) surrounded by the strain-inducing material (41).

15. The transistor device according to any one of claims 1 to 14, further comprising: A contact electrode (5) is arranged in the second groove (4). Each of the contact electrodes (5) adjoins at least one source region (13) and at least one body region (12) and is connected to a source node (S) of the transistor device.

16. A method for forming a transistor device, wherein the method comprises: forming a first trench (2) and a second trench (4) in a semiconductor body (100), each trench extending from a first surface (101) of the semiconductor body (100) into the semiconductor body (100); forming a drift region (11) adjacent to each of the second trenches (4); forming source regions (13), each source region (13) being separated from the drift region (11) by a corresponding body region (12); and forming a gate electrode (21), wherein each of the gate electrodes (21) is formed in one of the first trenches (2), adjacent to at least one of the body regions (12), and dielectrically insulated from the at least one of the body regions (12) by a gate dielectric (22), and Wherein forming the second trenches (4) includes forming the second trenches (4) such that each of the second trenches (4) is configured to induce strain in a region of the drift region (11) adjacent to the corresponding second trench (4). The forming of the second trenches (4) comprises at least partially filling the second trenches (4) with a strain inducing material (41), so that at least the sidewalls and the bottom of each of the second trenches (4) are covered by the strain inducing material (41).

17. The method of claim 16, wherein at least partially filling the second trench (4) with the strain inducing material (41) comprises a high temperature process, and The strain-inducing material (41) has a lower thermal expansion coefficient than the semiconductor material of the semiconductor body (100).

Images