Systems and methods for testing integrated circuit packages

Abstract

The invention provides a test system and a test method. In some embodiments, a system for testing an integrated circuit package includes a device tester. The device tester comprises a socket, an air pressure cylinder cover unit capable of being connected with the socket, and a pressure regulator. The receptacle includes a first pressure cylinder configured to engage a first region of the integrated circuit package and a second pressure cylinder configured to engage a second region of the integrated circuit package. The pressure regulator is configured to provide a gas at a first pressure to the first pressure cylinder and a gas at a second pressure different from the first pressure to the second pressure cylinder.

Description

Technical Field

[0001] Embodiments of the present invention relate to a system and method for testing an integrated circuit package. Background Art

[0002] A semiconductor device such as a semiconductor wafer includes a plurality of circuit devices such as integrated circuits. The integrated circuits are separated by scribe lines. A separation process, such as a wafer sawing process, is performed along the scribe lines to separate and isolate the integrated circuits from each other. One or more semiconductor dies are packaged in an integrated circuit package to provide a three-dimensional integrated circuit package (3DIC) with stacked dies, a system on integrated circuit (SoIC) package, an integrated fan-out (InFO) package, a chip on wafer on substrate (CoWoS) package, or some other type of integrated circuit package. Finally, a tester system is connected to contacts on the integrated circuit package, such as solder balls, contact pads, etc., to test the functionality of the integrated circuits in the integrated circuit package. Summary of the invention

[0003] An embodiment of the present invention provides a system for testing an integrated circuit package. The system includes a device tester. The device tester includes a socket, a pneumatic cylinder cover unit that can be engaged with the socket, and a pressure regulator. The socket includes a first pressure cylinder configured to engage a first area of ​​the integrated circuit package and a second pressure cylinder configured to engage a second area of ​​the integrated circuit package. The pressure regulator is configured to provide a gas of a first pressure to the first pressure cylinder and provide a gas of a second pressure different from the first pressure to the second pressure cylinder.

[0004] Embodiments of the present invention provide a method for testing an integrated circuit package. The method includes connecting the integrated circuit package to a socket of a device tester. Using a first pressure cylinder, a first force is applied to a first area of ​​the integrated circuit package. Using a second pressure cylinder, a second force different from the first force is applied to a second area of ​​the integrated circuit package. Using the device tester, a first test of the integrated circuit package is performed.

[0005] An embodiment of the present invention provides a system. The system includes a socket, a pneumatic cylinder cover unit engageable with the socket, and a pressure regulator. The pneumatic cylinder cover unit includes a first pressure cylinder configured to engage a first area of ​​an integrated circuit package, a second pressure cylinder configured to engage a second area of ​​the integrated circuit package, and a third pressure cylinder configured to engage a third area of ​​the integrated circuit package. A first pressure chamber fluidly connected to the first pressure cylinder, and a second pressure chamber fluidly connected to the second pressure cylinder and the third pressure cylinder. The pressure regulator is configured to provide a first pressure to the first pressure chamber, and to provide a second pressure different from the first pressure to the second pressure chamber. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram of a system for integrated circuit package testing according to some embodiments.

[0008] Figure 2 A cross-sectional view of a device tester is shown in accordance with some embodiments.

[0009] Figure 3 The pneumatic cylinder head unit is shown fully engaged with the socket and applying preliminary pressure, according to some embodiments.

[0010] Figure 4 The pneumatic cylinder head unit is shown fully engaged with the socket and with the test pressure applied, according to some embodiments.

[0011] Figure 5 and Figure 6 is a top view of a pressure cylinder array according to some embodiments.

[0012] Figure 7 is a top view of a pressure cylinder above a mold according to some embodiments.

[0013] Figure 8 is an expanded view showing sizes and spacing according to some embodiments.

[0014] Fig. 9 is an illustration of an example computer-readable medium according to some embodiments, which may include processor-executable instructions configured to embody one or more provisions set forth herein.

[0015] Fig.10 is a diagram of a computing environment for implementing one or more of the specified embodiments set forth herein, according to some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature is formed on or on a second feature, which may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] The present application relates to an integrated circuit package tester and a method for testing an integrated circuit package. In semiconductor processing, dies or chips are formed in groups on a wafer, allowing batch processing of the dies. The dies are segmented and packaged. Multiple dies of various types can be packaged together in a stacked arrangement, a side-by-side arrangement, or both. The integrated circuit package is tested using a device tester having probes that can contact contact pads (or metal bumps, solder balls, etc.) of a device under test (DUT). The integrated circuit package may exhibit a certain degree of warping, such as warping caused by high temperature. Testing of the integrated circuit package addresses this warping by using spring-loaded probes and applying force to the DUT to engage the probe pins. If some contact pads of the DUT fail to contact some probe pins during the probing process, the DUT may be incorrectly identified as a faulty device. Increasing the force to ensure contact may damage the integrated circuit package or the device tester.

[0019] According to some embodiments, a device tester includes pressure cylinders that can be individually controlled to affect the force applied to an integrated circuit package. The pressure cylinders can be pressurized individually or as a group using a shared pressure chamber. For example, a first pressure can be applied to a first cylinder to apply a first force to the integrated circuit package, and a second pressure can be applied to a second cylinder to apply a second force different from the first force to the integrated circuit package. Using different applied pressures allows appropriate forces to be applied to the semiconductor die in the integrated circuit package associated with the pressure cylinder based on the pin count of the semiconductor die to account for reaction forces from conductive pins in the device tester. Using a force that depends on the pin count reduces the possibility of damage to the integrated circuit package, damage to the semiconductor die in the integrated circuit package, or damage to the device tester.

[0020] Figure 1 1 is a block diagram of a system 100 for integrated circuit package testing according to some embodiments. In some embodiments, the system 100 includes a test side 102 and a probe side 104. The test side 102 manages and controls one or more groups of devices on the probe side 104. The test side 102 includes a tester 106, an analyzer 108, and a data storage module 110. The probe side 104 processes the integrated circuit package, physically manipulates the probes, and performs the actual testing of the integrated circuit package. The probe side 104 includes a handler 112, a probe 114, and a device tester 116.

[0021] The tester 106 sends instructions to the probe 114 and the processor 112 on the probe side 104. The tester 106 also receives test data from the probe 114. In some embodiments, the tester 106 retrieves test and probe parameters from the data storage module 110 on the test side and transmits the data to the probe 114 to test the integrated circuit package and the probe contact quality. In some embodiments, the analyzer 108 analyzes the test results received by the tester 106 to determine whether the integrated circuit package passes the functional test and generates probe or test parameters based on at least one of the benchmark parameters or the previous test data. In some embodiments, the analyzer 108 also determines whether the integrated circuit package that failed the test should be retested with the modified probe contact parameters, and whether the basic parameters for testing the integrated circuit package should be modified. The probe 114 controls the device tester 116 so that the probe on the device tester 116 contacts the integrated circuit package for testing. When the integrated circuit package is tested with the device tester 116, the processor 112 retrieves the integrated circuit package and engages with the device tester 116. After the test, the processor 112 removes the integrated circuit package and replaces the integrated circuit package with a different integrated circuit package for testing. In some embodiments, multiple integrated circuit packages are tested in parallel.

[0022] In some embodiments, the tester 106 includes a computer system having instructions stored on a non-transitory computer readable medium for generating probe and test instructions determined at least in part based on the type of integrated circuit package being tested and the test parameters, generated from a previous test of the integrated circuit package or a previous test of the same integrated circuit package. The tester 106 includes a processor for executing the instructions. In some embodiments, the data storage module 110 is a database, archive, cloud storage system, or other data storage system that stores data on a non-transitory computer readable medium (e.g., a hard disk, a solid state disk drive, a computer memory). For example, a random access memory (RAM), a synchronous dynamic random access memory (SDRAM), a flash memory, etc.

[0023] In some embodiments, the analyzer 108 is in signal communication with the data storage module 110 and the tester 106. In addition, in some embodiments, the analyzer 108 is integrated into the tester 106, and in other embodiments, the analyzer 108 is a computer system analyzer 108 separate from the tester 106 but connected to the tester 106. The analyzer 108 determines the probe parameters and the device test parameters and stores the parameters in the data storage module 110 or transmits the parameters directly to the tester 106. The tester 106 uses the probe parameters and the device test parameters to generate instructions for controlling the probe 114. The analyzer 108 obtains historical test data from the data storage module 110 and optimizes the testing of the integrated circuit package to improve performance by ensuring that the probe parameters result in good contact with the device for testing. The processor 112 is a computer system or control system that, in some embodiments, receives instructions from the tester 106 to load a specific integrated circuit package to engage with the device tester 116. The processor 112 may include a robotic arm or manipulator.

[0024] Figure 2 FIG. 1 shows a cross-sectional view of a device tester 116 according to some embodiments. Figure 2, the device tester 116 is configured to test the integrated circuit package 200. In some embodiments, the device tester 116 is configured to perform a final test (FT) or a system level test (SLT) on the integrated circuit package 200, but the present disclosure is not limited thereto. The integrated circuit package 200 has a plurality of electrical terminals 202 set on a contact surface 204 of the integrated circuit package 200. In some embodiments, the integrated circuit package 200 includes a 3DIC package, a SoIC package, an InFO package, a CoWoS package, or some other package type. In some embodiments, the size of the integrated circuit package 200 may exceed 45 mm×45 mm. Due to the different coefficients of thermal expansion (CTE) between different materials in the integrated circuit package 200, the integrated circuit package 200 may be prone to warping at elevated temperatures. Therefore, the contact surface 204 of the integrated circuit package 200 may not be a flat surface, but may also be a curved surface or any form of uneven surface.

[0025] In some embodiments, the device tester 116 includes a base 206, a socket 208, and a conductive pin 210. In some embodiments, the base 206 includes an electrical contact 212 connected to the conductive pin 210. The socket 208 is located on the base 206 and includes through holes 214 distributed in the socket 208. The through holes 214 can be evenly distributed in the socket 208, and additional through holes 214 and conductive pins 210 can be provided. Figure 2 2. The socket 208 may be located within or outside the page of the integrated circuit package 200. The outline of the socket 208 corresponds to the outline of the integrated circuit package 200. The conductive pin 210 is movably disposed in the through hole 214 and electrically connected to the electrical contact 212. In some embodiments, a passivation layer may be formed on the top surface of each electrical contact 212. The passivation layer may be formed, for example, by a chemical plating process and include gold (Au) or any other suitable material. The passivation layer reduces oxidation of the electrical contact 212 at high temperatures caused by high currents.

[0026] In some embodiments, the conductive pins 210 are temporarily electrically connected to the electrical contacts 212 for the device tester 116 to perform a test on the integrated circuit package 200. In some embodiments, the device tester 116 is configured and implemented to perform an electrical test on the integrated circuit package 200, so that a current or voltage can be applied to or received by the electrical contacts 212. In some embodiments, the conductive pins 210 are spring-loaded, also known as pogo pins, for establishing an electrical connection between the electrical contacts 212 of the base 206 and the electrical terminals 202 of the integrated circuit package 200.

[0027] In some embodiments, the socket 208 is connected to the base 206. The base 206 can be fixed to the printed circuit board, for example, by connecting the frame of the base 206 to the printed circuit board. In some embodiments, the conductive pins 210 include signal pins and at least one ground pin for probing the integrated circuit package 200. In addition, the conductive pins 210 include power pins, which can have the same structure as the signal pins or the ground pins. The base 206 can include at least one of an active or passive device ( Figure 2 206). A variety of devices such as controllers, processors, transistors, capacitors, resistors, any combination thereof, etc. may be used to generate the structural and functional requirements of the design of the device tester 116. The active or passive devices may be formed using any suitable method and may be embedded in the base 206 or mounted on the base 206 via surface mount technology, but the present disclosure is not limited thereto.

[0028] The device tester 116 includes a pneumatic cylinder head unit 216 for holding the integrated circuit package 200 and connecting the integrated circuit package 200 to the socket 208. The pneumatic cylinder head unit 216 includes a body 217 having a suction cup 218 (e.g., a vacuum nozzle) for holding the integrated circuit package 200. A guide hole 220 defined in the body 217 of the pneumatic cylinder head unit 216 engages a post 222 defined in the socket 208 to align the pneumatic cylinder head unit 216 and the socket 208. Figure 2 The pneumatic cylinder head unit 216 is shown partially engaged with the socket 208.

[0029] The pneumatic cylinder cover unit 216 includes pressure cylinders 224, 226 for applying force to the integrated circuit package 200 so that the electrical terminals 202 of the integrated circuit package 200 engage with the conductive pins 210. The pneumatic cylinder cover unit 216 includes a cover body 228, and the cover body 228 engages the integrated circuit package 200. A seal 230 is provided on the main body 217 to define pressure chambers 232, 234 between the main body 217 and the cover body 228. A seal 236 such as an O-ring can be provided between the main body 217 and the pressure cylinders 224, 226. The pressure chamber 232 can be in fluid communication with the pressure cylinder 224, and the pressure chamber 234 can be in fluid communication with the pressure cylinder 226. The number of pressure chambers and the number of pressure cylinders in each pressure chamber can vary. Additional pressure chambers and pressure cylinders can be provided in Figure 2 Location within or outside the page.

[0030] In some embodiments, the pressure regulator 229, such as a digital pressure regulator, is configured to provide different gas supplies to the pressure chambers 232, 234 at the gas inlets 229A, 229B at different pressures to affect the force applied by the pressure cylinder 224. The pressure parameters of the pressure regulator 229 can be controlled by the probe 114 so that the force applied by the pressure cylinder 224 can be different from the force applied by the pressure cylinder 226. In some embodiments, the pressure of the pressure regulator 229 is about 0.18 MPa. The gas provided by the pressure regulator 229 at the gas inlet can be air, an inert gas, such as nitrogen or argon, or some other supply gas. The pressure regulator 229 can receive gas from the ambient atmosphere, for example through a filter, or the gas can be provided to the pressure regulator 229 through a gas reservoir.

[0031] In some embodiments, the pressure provided by the pressure regulator 229 and the corresponding force applied by the specific pressure cylinder 224, 226 are proportional to the number of pins of the components of the integrated circuit package 200 positioned under the pressure cylinder 224, 226. For example, the integrated circuit package 200 may include one or more central processing unit (CPU) tube cores, one or more memory tube cores, digital signal processor tube cores, graphics tube cores, input / output (I / O) controller tube cores, bus controller tube cores, or other tube cores for some other functional units. Each tube core in the integrated circuit package 200 may have a different pin density. The force applied to the integrated circuit package 200 by the pressure cylinder 224, 226 is offset by the spring force of the conductive pin 210. As the applied force increases, the conductive pin 210 is compressed until the maximum stroke of the conductive pin 210 is reached. Applying additional force after the conductive pin 210 has exhausted its range of motion may damage the conductive pin 210.

[0032] The probe 114 may retrieve probe parameters from the data storage module 110 for configuring the pressure regulator 229 to provide different pressures to different pressure cylinders 224, 226. For example, the probe 114 may access a lookup table that matches specific pressure chambers 232, 234 and their associated pressure cylinders 224, 226 to pressure values. In some embodiments, one pressure cylinder disposed in one pressure chamber applies a force to a single component of the integrated circuit package 200. In some embodiments, more than one pressure cylinder in a pressure chamber applies a force to a single component of the integrated circuit package 200. The force applied by a group of pressure cylinders (which may include one or more pressure cylinders) is based on the pressure provided by the pressure regulator 229 and the surface area A of the pressure cylinders in the group. x Although the pressure cylinders 224 and 226 are Figure 2224, 226, but the size and corresponding surface area between the pressure cylinders 224, 226 may be different. In some embodiments, the maximum force parameter associated with a set of pressure cylinders is based on the number of pins P of the components of the integrated circuit package 200 positioned under the pressure cylinders 224, 226. C and the pin force P of the conductive pin 210 F The test of the integrated circuit package 200 produced by the applied pressure P1 is limited based on the following equation:

[0033] Applied force (test): Σ(A1…A N )×P1<=Maximum force: P F *P C (1)

[0034] Figure 3 A pneumatic cylinder cover unit 216 is shown fully engaged with the socket 208 and a preliminary pressure is applied by a pressure regulator 229 to engage the electrical terminals 202 disposed on the contact surface 204 of the integrated circuit package 200 with the conductive pins 210. According to some embodiments. Due to the warpage of the integrated circuit package 200, not all of the electrical terminals 202 can be engaged by the conductive pins 210 during the preliminary engagement between the integrated circuit package 200 and the socket 208. The engagement of the conductive pins 210 during the preliminary engagement using the preliminary pressure can be an indication of the degree of warpage. The preliminary engagement can be used to verify the alignment between the integrated circuit package 200 and the socket 208. In some embodiments, the preliminary pressure corresponds to a force of about one third of the force applied by the test of the integrated circuit package 200 in the equation.

[0035] Applied force (preliminary): Σ(A1…A N )×P1<=Maximum force: (P F *P C ) / 3. (2)

[0036] Figure 4 The pneumatic cylinder head unit 216 is shown fully engaged with the socket 208 and a test pressure is applied by the pressure regulator 229 to engage the electrical terminal 202 disposed on the contact surface 204 of the integrated circuit package 200 with the conductive pin 210. According to some embodiments, the test pressure causes the conductive pin 210 to deflect to facilitate full engagement between the electrical terminal 202 and the conductive pin 210. The contact quality between the conductive pin 210 and the electrical terminal 202 disposed on the contact surface 204 of the integrated circuit package 200 affects the accuracy of the test results of the integrated circuit package 200. Insufficient contact between the conductive pin 210 and the electrical terminal 202 may cause a test result of the integrated circuit package 200 that is actually working properly to fail.

[0037] The applied pressure P1 for a particular pressure chamber 232, 234 can be selected so that the applied force is a fractional multiplier of the maximum force, such as 95%. The probe 114 can dynamically adjust the fraction used for a particular integrated circuit package 200. For example, when a particular integrated circuit package 200 receives a failed test result in a functional test using a nominal fraction, the probe 114 can repeat the test using a higher nominal fraction, such as 98%. The increased risk of causing damage to an integrated circuit package 200 that failed the initial test by repeating the test using a higher pressure can be mitigated by the chance of achieving a passing result for the integrated circuit package 200. The initial use of a higher pressure for the integrated circuit package 200 only risks additional failures of the integrated circuit package 200 that would otherwise be damaged by the greater force, which would otherwise result in the integrated circuit package 200 being scrapped.

[0038] The degree of warpage determined based on the bond existing using the initial pressure can also be used to determine the fractional multiplier. An integrated circuit package 200 with less warpage can use a reduced fractional multiplier, such as 93%, to reduce the risk of breakage while still obtaining a passing test result. Prior to testing the integrated circuit package 200, the test pressure applied to the pressure cylinders 224, 226 can be modified from a baseline value.

[0039] refer to Figure 5 , provides a top view of an array 500 of pressure cylinders 502, 504, 506 according to some embodiments. In some embodiments, the configuration of the pressure cylinders 502, 504, 506 corresponds to the die area of ​​the integrated circuit package 200. For example, the pressure cylinder 502 can be positioned above the CPU die area, the pressure cylinder 504 can be positioned above the memory die area, and the pressure cylinder 506 can be positioned above a portion of the sealing ring provided in the integrated circuit package 200 to surround the CPU and memory dies. The pressure value of the pressure cylinder 502 can be determined based on the number of pins of the CPU die, the pressure value of the pressure cylinder 504 can be determined based on the number of pins of the memory die, and the pressure value of the pressure cylinder 506 can be determined according to the number of pins of the sealing ring portion. In some embodiments, when the number of pins is the same, the pressure cylinder 502 can be served by a shared pressure cavity, and the pressure cylinder 504 can be grouped into an upper seat and a lower seat, where each group shares a pressure cavity. The pressure cylinder 506 can be served by a separate pressure cavity.

[0040] refer to Figure 6, according to some embodiments, a top view of an array 600 of pressure cylinders 602, 604, 606 is provided. In some embodiments, the arrangement of the pressure cylinders 602, 604, 606 corresponds to the arrangement of the tube cores in the integrated circuit package 200. For example, the pressure cylinders 602 are arranged in groups, where each group is positioned to cover the CPU tube core. Multiple groups of pressure cylinders 602 can share a pressure cavity or provide a pressure cavity for each group. The pressure cylinder 604 can be a separate pressure cylinder positioned above the memory tube core. The pressure cylinder 604 can be divided into an upper seat and a lower seat, and each group shares a pressure cavity. The pressure cylinder 606 can be arranged in a group and positioned above a portion of the sealing ring provided in the integrated circuit package 200 to surround the CPU and memory tube cores. Each group of pressure cylinders 606 can be served by a separate pressure cavity.

[0041] refer to Figure 7 , according to some embodiments, a top view of a pressure cylinder 700 above a tube core 702 is provided. In the integrated circuit package 200, a tube core such as a tube core 702 may be surrounded by a protective material such as an epoxy resin material. The protective material is softer than the tube core 702. In order to reduce the pressure on the edge of the tube core 702 or the protective material and potentially cause the tube core 702 to crack, the size of the pressure cylinder 700 can be designed so that the contact area of ​​the pressure of the pressure cylinder 700 is smaller than the tube core 702. For example, an edge X in the x direction and an edge Y in the y direction can be provided. In some embodiments, X≥0.2mm and Y≥0.2mm.

[0042] refer to Figure 8 , provides an expanded view showing dimensions and spacings associated with the body 217, the pressure cylinder 224, the cover 228, and the seal 236 according to some embodiments. When the pressure cylinder 224 is fully displaced, the upper dimension H2 ≥ the extended dimension H1 ≥ 0.1 mm to account for package warping. The thickness H4 of the body 217 ≥ the distance H3 between the head 224H of the pressure cylinder 224 and the bottom of the seal 236 to ensure overlap with the axis 224S of the pressure cylinder 224 and the seal 236. The width W1 of the head 224H> the width W2 of the seal 236> the width W3 of the axis 224S of the pressure cylinder 224 to ensure the functionality of the seal 236. The spacing W4 between the pressure cylinders 224 defined by the body 217 is approximately ≥ 0.5 mm.

[0043] Another embodiment involves a computer-readable medium comprising processor-executable instructions configured to implement one or more of the techniques presented herein. Fig. 9, wherein embodiment 900 includes a computer-readable medium 908, such as a recordable compact disk (CD-R), a recordable digital video disk (DVD-R), a flash drive, a hard disk platter, etc., on which computer-readable data 906 is encoded. This computer-readable data 906 includes, for example, binary data such as Fig. 9 The plurality of 0s and 1s shown further include a set of processor executable computer instructions 904 configured to operate according to one or more principles set forth herein. In one such embodiment 900, the processor executable computer instructions 904 are configured to perform the method 902, such as at least some of the steps described above for controlling the device tester 116. In another embodiment, the processor executable computer instructions 904 are configured to implement a system, such as Figure 1 Many such computer-readable media are designed by those of ordinary skill in the art that are configured to operate in accordance with the techniques presented herein.

[0044] Fig.10 The following discussion provides a brief, general description of a suitable computing environment for implementing one or more specified embodiments set forth herein. Fig.10 The operating environments are only examples of suitable operating environments and are not intended to imply any limitation as to the scope of use or functionality of the operating environments. Example computing devices include, but are not limited to, personal computers, server computers, handheld or laptop devices, mobile devices (e.g., mobile phones, personal digital assistants (PDAs), media players, etc.), multiprocessor systems, consumer electronic devices, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like.

[0045] In general, embodiments are described in the general context of "computer-readable instructions" being executed by one or more computing devices. The computer-readable instructions are distributed via computer-readable media, as discussed below. The computer-readable instructions are implemented as program modules that perform specific tasks or implement specific abstract data types, such as functions, objects, application programming interfaces (APIs), data structures, etc. Typically, the functionality of the computer-readable instructions will be combined or distributed in various environments as needed.

[0046] Fig.10 An example of a system 1000 is shown, which includes a computing device 1012, and the computing device 1012 is configured to implement one or more embodiments provided herein, such as Figure 1106, analyzer 108, or probe 114 shown in FIG. In one configuration, computing device 1012 includes at least one processing unit 1016 and memory 1018. Depending on the specific configuration and type of computing device, memory 1018 may be volatile, such as RAM, non-volatile, such as read-only memory (ROM), flash memory, or some combination of the two. Fig.10 1014. The processing unit 1016 may include general and special computing devices, such as a CPU cluster and a hardware accelerator cluster that allow task optimization and parallel processing. The memory 1018 and storage device 1020 may be a global memory and storage device shared by the cluster.

[0047] In other embodiments, the device 1012 includes additional features or functions. For example, the device 1012 also includes an additional storage device, such as a removable storage device or a non-removable storage device, including but not limited to a magnetic storage device, an optical storage device, etc. Such an additional storage device is Fig.10 1018 is shown by storage device 1020. In one embodiment, computer readable instructions for implementing one or more embodiments provided herein are located in storage device 1020. Storage device 1020 also stores other computer readable instructions for implementing an operating system, application programs, etc. For example, computer readable instructions are loaded into memory 1018 for execution by processing unit 1016.

[0048] As used herein, the term "computer-readable media" includes computer storage media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions or other data. Memory 1018 and storage device 1020 are examples of computer storage media. Computer storage media include, but are not limited to, RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technology, compact disk read-only memory (CD-ROM), DVD or other fiber optic storage devices, audio cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other media that can be used to store the desired information and can be accessed by device 1012. Any such computer storage media is part of device 1012.

[0049] The term "computer-readable media" includes communication media. Communication media typically embodies computer-readable instructions or other data in a "modulated data signal" such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" includes a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal.

[0050] The device 1012 includes an input device 1024, such as a keyboard, a mouse, a pen, a voice input device, a touch input device, an infrared camera, a video input device, or any other input device. The device 1012 also includes an output device 1022, such as one or more displays, speakers, a printer, or any other output device. The input device 1024 and the output device 1022 are connected to the device 1012 via a wired connection, a wireless connection, or any combination thereof. In one embodiment, an input device or an output device from another computing device is used as an input device 1024 or an output device 1022 of the computing device 1012. The device 1012 also includes a communication connection 1026 to facilitate communication between one or more other devices and the computing device 1012.

[0051] The use of pressure cylinders 224, 226 with different applied pressures allows the semiconductor die associated with the pressure cylinders 224, 226 to be applied with appropriate force based on the number of pins to account for the reaction force from the conductive pins 210. The magnitude of the force depending on the number of pins reduces the possibility of damage to the integrated circuit package 200, damage to the semiconductor die in the integrated circuit package 200, or damage to the device tester 116. During the initial engagement with the device tester 116, for example, an initial pressure corresponding to a reduced force can be applied to verify the alignment between the integrated circuit package 200 and the socket 208 of the device tester 116. In some embodiments, the use of the initial pressure allows the degree of warpage to be determined. During testing, a pressure is applied to the pressure cylinders 224, 226, the force applied by the pressure being less than the maximum force determined based on the number of pins and the pin force. The pressure applied during testing can be adjusted based on the estimated degree of warpage or the test results of the integrated circuit package 200.

[0052] According to some embodiments, a system for testing an integrated circuit package is provided. The system includes a device tester. The device tester includes a socket, a pneumatic cylinder cover unit engageable with the socket, and a pressure regulator. The socket includes a first pressure cylinder configured to engage a first area of ​​the integrated circuit package and a second pressure cylinder configured to engage a second area of ​​the integrated circuit package. The pressure regulator is configured to provide a gas of a first pressure to the first pressure cylinder and to provide a gas of a second pressure different from the first pressure to the second pressure cylinder.

[0053] In some embodiments, the pneumatic cylinder head unit includes: a third pressure cylinder; and a pressure chamber in fluid communication with the first pressure cylinder and the third pressure cylinder.

[0054] In some embodiments, wherein: the first pressure is based on a pin count of a first semiconductor die of the integrated circuit package in the first region, and the second pressure is based on a pin count of a second semiconductor die of the integrated circuit package in the second region.

[0055] In some embodiments, wherein: the socket includes conductive pins having associated pin forces for deflecting the conductive pins, and the first pressure is based on the number of pins and associated pin forces of a first semiconductor die of the integrated circuit package in the first region.

[0056] In some embodiments, wherein: the first pressure corresponds to a first force, the first force being a fraction of a maximum force defined by the number of pins and the associated pin forces.

[0057] In some embodiments, the system includes: a first gas inlet connected between the pressure regulator and the pneumatic cylinder head unit; and a second gas inlet connected between the pressure regulator and the pneumatic cylinder head unit, wherein the gas includes at least one of air or an inert gas.

[0058] In some embodiments, the system includes: a probe for configuring the first pressure and the second pressure in the device tester, wherein: the first pressure and the second pressure are used by the device tester during testing of the integrated circuit package, the probe is configured to provide a third pressure and a fourth pressure for preliminary bonding between the integrated circuit package and the device tester, the pressure regulator is configured to provide gas of the third pressure to the first pressure cylinder and gas of the fourth pressure to the second pressure cylinder during the preliminary bonding, the third pressure is less than the first pressure, and the fourth pressure is less than the second pressure.

[0059] In some embodiments, the system includes: a probe for configuring the first pressure and the second pressure in the device tester, wherein: during a first test of the integrated circuit package, the device tester adopts the first pressure and the second pressure, the probe is configured to provide a third pressure and a fourth pressure for a second test of the integrated circuit package in response to a failure result of the first test, and the pressure regulator is configured to provide gas of the third pressure to the first pressure cylinder and gas of the fourth pressure to the second pressure cylinder during the second test, the third pressure is greater than the first pressure, and the fourth pressure is greater than the second pressure.

[0060] According to some embodiments, a method for testing an integrated circuit package is provided. The method includes connecting the integrated circuit package to a socket of a device tester. Using a first pressure cylinder, a first force is applied to a first area of ​​the integrated circuit package. Using a second pressure cylinder, a second force different from the first force is applied to a second area of ​​the integrated circuit package. A first test of the integrated circuit package is performed using the device tester.

[0061] In some embodiments, the method includes: providing a first pressure to the first pressure cylinder to apply the first force; and providing a second pressure to the second pressure cylinder to apply the second force.

[0062] In some embodiments, the method includes providing the first pressure to a third pressure cylinder to apply a third force to a third region of the integrated circuit package.

[0063] In some embodiments, the method includes configuring the first pressure based on a pin count of a first semiconductor die of the integrated circuit package in the first region, and configuring the second pressure based on a pin count of a second semiconductor die of the integrated circuit package in the second region.

[0064] In some embodiments, wherein: the socket includes a conductive pin having an associated pin force for deflecting the conductive pin, and the method includes configuring the first pressure based on the number of pins of the first semiconductor die of the integrated circuit package in the first region and the associated pin force.

[0065] In some embodiments, configuring the first pressure includes configuring the first pressure to provide the first force as a fraction of a maximum force defined by the number of pins and the associated pin forces.

[0066] In some embodiments, configuring the first pressure includes configuring the first pressure based on a surface area of ​​the first pressure cylinder.

[0067] In some embodiments, the method includes: providing a third pressure less than the first pressure to the first pressure cylinder to apply a third force to the first area of ​​the integrated circuit package during preliminary bonding between the socket and the integrated circuit package; and providing a fourth pressure less than the second pressure to the first pressure cylinder to apply a fourth force to the second area of ​​the integrated circuit package during preliminary bonding.

[0068] In some embodiments, the method includes modifying the first pressure and the second pressure prior to performing the first test based on the preliminary engagement.

[0069] In some embodiments, the method includes: in response to a failure result of the first test: using the first pressure cylinder to apply a third force greater than the first force to the first area of ​​the integrated circuit package; using the second pressure cylinder to apply a fourth force greater than the second force to the second area of ​​the integrated circuit package; and using the device tester to perform a second test of the integrated circuit package.

[0070] According to some embodiments, a system is provided. The system includes a socket, a pneumatic cylinder cover unit engageable with the socket, and a pressure regulator. The pneumatic cylinder cover unit includes a first pressure cylinder configured to engage a first area of ​​an integrated circuit package, a second pressure cylinder configured to engage a second area of ​​the integrated circuit package, and a third pressure cylinder configured to engage a third area of ​​the integrated circuit package. A first pressure chamber is fluidly connected to the first pressure cylinder, and a second pressure chamber is fluidly connected to the second pressure cylinder and the third pressure cylinder. The pressure regulator is configured to provide a first pressure to the first pressure chamber, and to provide a second pressure different from the first pressure to the second pressure chamber.

[0071] In some embodiments, wherein: the first pressure is based on a pin count of a first semiconductor die of the integrated circuit package in the first region, and the second pressure is based on a pin count of a second semiconductor die of the integrated circuit package in the second region.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should know that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and modifications to them without departing from the spirit and scope of the present disclosure.

[0073] Although the subject matter has been described in language specific to structural features or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

[0074] Various operations of the embodiments are provided herein. The order of some or all of the operations described should not be interpreted as implying that these operations are necessarily dependent on the order. It should be understood that the alternative order has the rights and interests of this specification. In addition, it should be understood that not all operations are necessarily present in each embodiment provided herein. In addition, it should be understood that not all operations are necessarily in some embodiments.

[0075] It should be understood that the layers, features, components, etc. depicted herein are shown with specific dimensions (e.g., structural dimensions or orientations) relative to each other, for example, for the purpose of simplicity and ease of understanding, and in some embodiments, their actual dimensions are substantially different from the dimensions shown herein. In addition, there are various techniques, such as etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or at least one of deposition techniques such as CVD, for example, for forming the layers, regions, features, components, etc. mentioned herein.

[0076] In addition, "exemplary" is used herein to mean serving as an example, situation, explanation, etc., and is not necessarily advantageous. As used herein, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, unless otherwise specified or clearly pointed to the singular form from the context, "a and an" as used in the present application and the attached claims are generally interpreted as meaning "one or more". In addition, at least one of A and B and / or the like generally means A or B, or both A and B. In addition, with respect to the use of "including", "having / has / with" or its variants, such terms are intended to be inclusive in a manner similar to the term "including". In addition, unless otherwise specified, "first", "second" or the like are not intended to imply time, space, order, etc. On the contrary, these terms are only used as identifiers, names, etc. of features, components, articles, etc. For example, the first component and the second component generally correspond to component A and component B or two different or two identical components or the same component.

[0077] In addition, although the present disclosure has been illustrated and described with respect to one or more embodiments, those with ordinary knowledge in the art should expect equivalent changes and modifications based on reading and understanding this specification and the accompanying drawings. The present disclosure includes all these modifications and changes, and is only limited to the scope of the attached claims. In particular, for various functions performed by the above-mentioned components (such as components, resources, etc.), unless otherwise indicated, the terms used to describe these components are intended to correspond to any components that perform the specified functions (such as functionally equivalent) of the described components, even if the structure is not equivalent to the disclosed structure. In addition, although the specific features of the present disclosure may have been disclosed with respect to only one of several embodiments, these features may be combined with one or more other features of other embodiments, which may be desirable and advantageous for any given or specific application.

Claims

1. A system for testing integrated circuit packaging, characterized in that: include: Device tester, comprising: socket; A pneumatic cylinder head unit, engageable with the socket, comprising: a first pressure cylinder configured to engage a first region of the integrated circuit package; and a second pressure cylinder configured to engage a second region of the integrated circuit package; and The pressure regulator is configured to supply gas at a first pressure to the first pressure cylinder and supply gas at a second pressure different from the first pressure to the second pressure cylinder.

2. The system according to claim 1, characterized in that The first pressure is based on a pin count of a first semiconductor die of the integrated circuit package in the first region, and The second pressure is based on a pin count of a second semiconductor die of the integrated circuit package in the second region.

3. The system according to claim 1, characterized in that Also includes: a first gas inlet connected between the pressure regulator and the pneumatic cylinder head unit; as well as A second gas inlet is connected between the pressure regulator and the pneumatic cylinder head unit, wherein the gas comprises at least one of air or an inert gas.

4. The system according to claim 3, characterized in that Also includes: a probe for configuring the first pressure and the second pressure in the device tester, wherein: the first pressure and the second pressure are used by the device tester during testing of the integrated circuit package, The probe is configured to provide a third pressure and a fourth pressure for preliminary bonding between the integrated circuit package and the device tester, The pressure regulator is configured to supply the gas at the third pressure to the first pressure cylinder and supply the gas at the fourth pressure to the second pressure cylinder during the preliminary engagement, The third pressure is less than the first pressure, and The fourth pressure is lower than the second pressure.

5. The system according to claim 3, characterized in that Also includes: a probe for configuring the first pressure and the second pressure in the device tester, wherein: During a first test of the integrated circuit package, the device tester applies the first pressure and the second pressure, The probe is configured to provide a third pressure and a fourth pressure for a second test of the integrated circuit package in response to a failure result of the first test, the pressure regulator being configured to supply the gas at the third pressure to the first pressure cylinder and to supply the gas at the fourth pressure to the second pressure cylinder during the second test, The third pressure is greater than the first pressure, and The fourth pressure is greater than the second pressure.

6. A method for testing an integrated circuit package, characterized in that: include: connecting the integrated circuit package to a socket of a device tester; applying a first force to a first region of the integrated circuit package using a first pressure cylinder; applying a second force different from the first force to a second area of ​​the integrated circuit package using a second pressure cylinder; and A first test of the integrated circuit package is performed using a device tester.

7. The method according to claim 6, characterized in that Also includes: providing a first pressure to the first pressure cylinder to apply the first force; as well as A second pressure is provided to the second pressure cylinder to apply the second force.

8. The method according to claim 7, characterized in that The socket includes a conductive pin having an associated pin force for deflecting the conductive pin, and The method includes configuring the first pressure based on a pin count of a first semiconductor die of the integrated circuit package in the first region and the associated pin forces.

9. The method according to claim 7, characterized in that: Also includes: providing a third pressure, less than the first pressure, to the first pressure cylinder to apply a third force to the first region of the integrated circuit package during initial engagement between the socket and the integrated circuit package; as well as A fourth pressure less than the second pressure is provided to the first pressure cylinder to apply a fourth force to the second region of the integrated circuit package during preliminary bonding.

10. A system, characterized in that: include: socket; A pneumatic cylinder head unit, engageable with the socket, comprising: a first pressure cylinder configured to engage a first region of an integrated circuit package; a second pressure cylinder configured to engage a second region of the integrated circuit package; a third pressure cylinder configured to engage a third region of the integrated circuit package; a first pressure chamber in fluid communication with the first pressure cylinder; and a second pressure chamber in fluid communication with the second pressure cylinder and the third pressure cylinder; and The pressure regulator is configured to provide a first pressure to the first pressure chamber and to provide a second pressure different from the first pressure to the second pressure chamber.

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