Low dropout linear regulator without off-chip capacitor, power supply circuit and electronic system

Abstract

The application provides a low-dropout linear voltage regulator without external capacitor, which comprises a power tube, a feedback resistance network, an error amplifier, a load switching module, a switching frequency detection module and a power consumption / response control module, wherein the load switching module is connected to the second end of the power tube and is used for switching control of the access load according to a switching control signal; the switching frequency detection module is used for detecting the switching frequency of the access load according to the switching control signal and generating a first power control signal according to the fast or slow of the switching frequency; and the power consumption / response control module is connected to the output end of the error amplifier and the switching frequency detection module and is used for adjusting the working current size of the power consumption / response control module according to the first power control signal and adjusting the output through the control of the power tube under different working currents. The low-dropout linear voltage regulator without external capacitor provided by the application solves the problems of output disturbance and large power consumption of the existing low-dropout linear voltage regulator without external capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, in particular to a low-dropout linear regulator without off-chip capacitor, a power supply circuit and an electronic system. BACKGROUND

[0002] The integration of a system on chip (SOC) including analog, digital and radio frequency circuits in a portable communication device is increasingly high, but the SOC is susceptible to noise interference from high-frequency digital switches, radio frequency modules, etc., and the use of a low-dropout linear regulator (LDO) can reduce the impact of environmental noise on the performance of sensitive circuits in the SOC.

[0003] The main pole of a conventional LDO is generally set at the output, which requires a micro-farad off-chip capacitor to be connected to the output and an equivalent series resistance to compensate for the power tube gate pole, in order to improve the transient response speed of the LDO and the stability of the circuit. If there is no off-chip capacitor at the output or the ESR parameter of the off-chip capacitor does not meet the requirements, the LDO may not respond normally or even be locked up; moreover, the use of an off-chip capacitor not only requires an additional circuit pin, but also increases the component cost of the application scheme.

[0004] Some LDO schemes without off-chip capacitors cannot respond in time to the output disturbance caused by the transient change of the output voltage due to the limited loop bandwidth of the regulated output voltage; especially for a multi-carrier modulation system, when the multi-carrier modulation signal to be transmitted has a high peak average power ratio (PAPR), this problem is more prominent. In order to achieve fast response and improve the load regulation rate, the LDO scheme without off-chip capacitors uses a higher operating current at the error amplifier and the drive stage, but this results in high power consumption, which is not conducive to reducing the energy consumption of the portable product when it is working.

[0005] In view of the above, it is an urgent technical problem for those skilled in the art to design an LDO without off-chip capacitors that has high energy efficiency and low disturbance. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a low-dropout linear regulator without off-chip capacitor, a power supply circuit and an electronic system, which solves the problems of output disturbance and high power consumption in the existing LDO scheme without off-chip capacitor.

[0007] To achieve the above-mentioned objects and other related objects, the present application provides a low-dropout linear regulator without off-chip capacitor, which comprises:

[0008] The power tube, the feedback resistance network, the error amplifier, the load switching module, the switching frequency detection module and the power consumption / response control module, wherein:

[0009] The control end of the power tube is connected to the output end of the power consumption / response control module, the first end is connected to the input power supply, and the second end is connected to the ground through the feedback resistance network and generates an output voltage, wherein the feedback resistance network divides the output voltage to generate a feedback voltage;

[0010] The first input end of the error amplifier is connected to a reference voltage, and the second input end is connected to the feedback voltage;

[0011] The load switching module is connected to the second end of the power tube and is used for switching control of the access load according to a switching control signal;

[0012] The switching frequency detection module receives the switching control signal and is used for detecting the switching frequency of the access load according to the switching control signal and generating a first power control signal according to the fast / slow of the switching frequency;

[0013] The power consumption / response control module is connected to the output ends of the error amplifier and the switching frequency detection module and is used for adjusting the working current size of the power consumption / response control module according to the first power control signal and adjusting the output through the control of the power tube under different working currents.

[0014] Optionally, the load switching module comprises a multi-channel selection switch and at least two load units; the control end of the multi-channel selection switch is connected to the switching control signal, the common end is connected to the second end of the power tube, and each selection end is connected to the first end of each load unit; and the second end of each load unit is connected to the ground.

[0015] Optionally, the switching frequency detection module comprises a first pulse shaping unit and a signal generation unit, wherein:

[0016] The first pulse shaping unit is used for pulse broadening processing of the pulse in the switching control signal to obtain a first rectangular pulse;

[0017] The signal generation unit is connected to the output end of the first pulse shaping unit and is used for converting the first rectangular pulse into a first analog voltage quantity as the first power control signal through a capacitor charging method.

[0018] Optionally, the first pulse shaping unit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a discharge tube, a first comparator, a second comparator, an RS flip-flop, a NAND gate and an inverter; the first resistor and the first capacitor are connected in series between a working voltage and ground; the second resistor, the third resistor and the fourth resistor are connected in series between the working voltage and ground; a non-inverting input terminal of the first comparator is grounded through the second capacitor and connected to a connection node of the second resistor and the third resistor, an inverting input terminal is connected to a connection node of the first resistor and the first capacitor, and an output terminal is connected to a reset terminal of the RS flip-flop; a non-inverting input terminal of the second comparator is connected to the switching control signal, an inverting input terminal is connected to a connection node of the third resistor and the fourth resistor, and an output terminal is connected to a set terminal of the RS flip-flop; a clear terminal of the RS flip-flop is connected to an inverting signal of the clear signal, and an output terminal is connected to a first input terminal of the NAND gate; a second input terminal of the NAND gate is connected to the inverting signal of the clear signal, and an output terminal is connected to an input terminal of the inverter and connected to a gate of the discharge tube through the fifth resistor; an output terminal of the inverter serves as an output terminal of the first pulse shaping unit; a drain of the discharge tube is connected to the connection node of the first resistor and the first capacitor, and a source is grounded.

[0019] Optionally, the signal generating unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third capacitor; the first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube and the second NMOS tube are connected in series between a working voltage and ground, a gate terminal of each of the first PMOS tube, the second PMOS tube, the third PMOS tube and the second NMOS tube is connected to a respective drain terminal, a gate terminal of the first NMOS tube is connected to an output terminal of the first pulse shaping unit, and a source terminal of the first NMOS tube is grounded through the third capacitor and serves as an output terminal of the signal generating unit.

[0020] Optionally, the power consumption / response control module comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first operational amplifier and a sixth resistor; the gate of the fourth PMOS transistor is connected to the output of the error amplifier, the source is connected to the output voltage, and the drain is connected to the drain of the third NMOS transistor and the source of the sixth NMOS transistor; the gates of the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are connected to each other and to the inverting input of the first operational amplifier, the sources are grounded, the drain of the fourth NMOS transistor is connected to the gate, the drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor; the gate of the sixth NMOS transistor is connected to a bias voltage, the drain is connected to the drain of the sixth PMOS transistor and serves as the output of the power consumption / response control module; the gate of the fifth PMOS transistor is connected to the drain and to the gate of the sixth PMOS transistor, and the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the input power supply; the non-inverting input of the first operational amplifier is connected to the output of the load switching module, and the output is connected to the inverting input through the sixth resistor.

[0021] Optionally, the power consumption / response control module further comprises a fourth capacitor and a seventh resistor; the fourth capacitor and the seventh resistor are connected in series between the gate and the drain of the fourth PMOS transistor.

[0022] Optionally, the low-dropout linear regulator further comprises a peak-to-average ratio detection module and a comprehensive control module, wherein:

[0023] The peak-to-average ratio detection module is configured to detect the peak-to-average ratio of the multi-carrier modulation signal and generate a second power control signal according to a set number of times of the peak-to-average ratio;

[0024] The comprehensive control module is connected to the outputs of the switching frequency detection module and the peak-to-average ratio detection module and is configured to generate a total power control signal according to the first power control signal and the second power control signal;

[0025] The power consumption / response control module is configured to adjust the working current according to the total power control signal and to adjust the output by controlling the power transistor under different working currents.

[0026] Optionally, the peak-to-average ratio detection module comprises a comparison unit, a second pulse shaping unit and a low-pass filter unit, wherein:

[0027] The comparison unit is configured to compare the peak voltage of the multi-carrier modulation signal with a set voltage and generate a comparison pulse when the peak voltage is greater than the set voltage.

[0028] The second pulse shaping unit is connected to the output of the comparison unit, and is configured to perform pulse stretching processing on the comparison pulse to generate a second rectangular pulse.

[0029] The low-pass filter unit is connected to the output of the second pulse shaping unit, and is configured to convert the second rectangular pulse into a second analog voltage quantity through low-pass filtering processing, as the second power control signal.

[0030] Optionally, when the switching frequency detection module comprises the first pulse shaping unit, the first pulse shaping unit and the second pulse shaping unit have the same structure.

[0031] Optionally, the comprehensive control module comprises a second operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; the non-inverting input of the second operational amplifier is connected to the ground through the eighth resistor, the inverting input is connected to the output of the switching frequency detection module through the ninth resistor, and the output is connected to the output of the peak-to-average ratio detection module through the tenth resistor; the output of the second operational amplifier is connected to the inverting input of the second operational amplifier through the eleventh resistor, and serves as the output of the comprehensive control module.

[0032] The application further provides a power supply circuit comprising the low-dropout linear regulator according to any one of the above.

[0033] The application further provides an electronic system comprising the power supply circuit according to the above.

[0034] As described above, the low-dropout linear regulator without off-chip capacitor, the power supply circuit and the electronic system according to the application can adjust the working current of the power consumption / response control module according to the switching frequency of the connected load and the number of times that the peak-to-average ratio of the multi-carrier modulation signal exceeds the set number; the working current of the power consumption / response control module is related to the response speed of the LDO, and the working current of the power consumption / response control module is adjusted to adjust the static power consumption of the LDO, so that the LDO has a lower average working energy consumption. When the switching frequency of the connected load is fast or the number of times that the peak-to-average ratio of the multi-carrier modulation signal exceeds the set number is large, the working current of the power consumption / response control module is large, and the loop bandwidth is increased to improve the response speed; when the switching frequency of the connected load is slow and the number of times that the peak-to-average ratio of the multi-carrier modulation signal exceeds the set number is small, the working current of the power consumption / response control module is small, and the overall energy efficiency is improved by reducing the power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 The structure schematic diagram of the low-dropout linear regulator in Example 1 is shown.

[0036] Figure 2A structure diagram of the switching frequency detection module in Embodiment 1 is shown.

[0037] Figure 3 A related signal waveform diagram of the first pulse shaping unit in Embodiment 1 is shown.

[0038] Figure 4 A structure diagram of the power consumption / response control module in Embodiment 1 is shown.

[0039] Figure 5 A structure diagram of the low dropout linear regulator in Embodiment 2 is shown.

[0040] Figure 6 A structure diagram of the peak-to-average ratio detection module in Embodiment 2 is shown.

[0041] Figure 7 A related signal waveform diagram of the peak-to-average ratio detection module in Embodiment 2 is shown.

[0042] Figure 8 A structure diagram of the comprehensive control module in Embodiment 2 is shown.

[0043] Element Number Explanation

[0044] 100 feedback resistor network

[0045] 200 error amplifier

[0046] 300 load switching module

[0047] 400 switching frequency detection module

[0048] 410 first pulse shaping unit

[0049] 411 first comparator

[0050] 412 second comparator

[0051] 413 RS flip-flop

[0052] 414 NAND gate

[0053] 415 inverter

[0054] 420 signal generation unit

[0055] 500 power consumption / response control module

[0056] 600 bandgap reference module

[0057] 700 peak-to-average ratio detection module

[0058] 710 comparison unit

[0059] 720 second pulse shaping unit

[0060] 730 low pass filter unit

[0061] 800 integrated control module DETAILED DESCRIPTION

[0062] The present application is herein described, by way of example only, with the comprehension that the advantages and utility thereof are not confined to such specific embodiments. Various modifications might be made by those skilled in the art, without departing from the spirit of the disclosure, and the general principles defined herein. The scope of the protection is thus indicated by the claims which follow.

[0063] Reference will now be made to the drawings, wherein Figures 1 to 8 It is to be understood that the above-mentioned arrangement is merely intended to illustrate the basic principles of the present application, and although only components related to the present application are shown, the actual implementation can include a larger number of components, and the shapes and dimensions of the components can vary. The actual implementation can also include a more complex arrangement of components.

[0064] Embodiment 1

[0065] As shown in Figure 1 , the present embodiment provides a low-dropout linear regulator (LDO) without off-chip capacitance, which includes a power transistor M0, a feedback resistor network 100, an error amplifier 200, a load switching module 300, a switching frequency detection module 400, and a power consumption / response control module 500. Further, it also includes a bandgap reference module 600 and a driving module (not shown in the figure). Wherein:

[0066] The control terminal of the power transistor M0 is connected to the output terminal of the power consumption / response control module 500, the first terminal is connected to the input power supply VIN, and the second terminal is connected to the ground through the feedback resistor network 100 and generates an output voltage VOUT. The feedback resistor network 100 divides the output voltage VOUT to generate a feedback voltage VFB.

[0067] Specifically, the power transistor M0 is an output adjustment transistor, and the output voltage VOUT is adjusted by controlling the conduction degree of the power transistor M0 through the output of the power consumption / response control module 500, so as to stabilize the output voltage VOUT. The power transistor M0 includes at least one of a PMOS transistor, an NMOS transistor, a PNP transistor, and an NPN transistor. During circuit design, the actual needs should be considered for selection; for different types of devices, the circuit should be appropriately adjusted to facilitate driving.

[0068] The figure shows the case where the power transistor M0 is an enhancement-mode PMOS transistor. The gate of the PMOS transistor is connected to the output of the power consumption / response control module 500, the source is connected to the input power supply VIN, and the drain is grounded through the feedback resistor network 100 to generate the output voltage VOUT. Correspondingly, the non-inverting input of the error amplifier 200 is connected to the reference voltage VREF, and the inverting input is connected to the feedback voltage VFB.

[0069] For a scheme without a driver module, if the power transistor M0 is replaced by an NMOS transistor instead of a PMOS transistor, the two input terminals of the error amplifier 200 should be adjusted in order to drive the power transistor. That is, the non-inverting input terminal of the error amplifier 200 is connected to the feedback voltage VFB, and the inverting input terminal is connected to the reference voltage VREF.

[0070] For the scheme of setting up the drive module, if the power transistor M0 is replaced by an NMOS transistor instead of a PMOS transistor, in addition to the adjustment method mentioned above, it can also be achieved by inverting the phase of the output of the drive module without adjusting the input of the error amplifier 200.

[0071] Of course, PNP transistors can be compared to PMOS transistors, and NPN transistors to NMOS transistors. However, when using transistors as power transistors, the input voltage VIN is lower than that of MOS transistors. In practical applications, transistors are current-controlled devices, while MOS transistors are voltage-controlled devices. Compared to MOS transistors, MOS transistors have lower quiescent current. NMOS transistors require a drive signal with a higher output voltage to operate, while PMOS transistors do not. Therefore, PMOS transistors are generally preferred as power transistors in applications.

[0072] Specifically, the feedback resistor network 100 includes a first feedback resistor RF1 and a second feedback resistor RF2; the first feedback resistor RF1 and the second feedback resistor RF2 are connected in series between the second terminal of the power transistor M0 and ground, and the connection node of the first feedback resistor RF1 and the second feedback resistor RF2 generates the feedback voltage VFB. It should be noted that the above example only shows the case of two resistors connected in series for voltage division; in fact, it is equally applicable to more resistors connected in series for voltage division.

[0073] The first input terminal of the error amplifier 200 is connected to the reference voltage VREF, and the second input terminal is connected to the feedback voltage VFB, which is used to amplify the error of the reference voltage VREF and the feedback voltage VFB.

[0074] As mentioned above, for different types of power transistors M0, the driving can be achieved by adjusting the input terminal of the error amplifier 200. In this embodiment, taking the power transistor M0 as an enhancement-type PMOS transistor as an example, the non-inverting input terminal of the error amplifier 200 is connected to the reference voltage VREF, and the inverting input terminal is connected to the feedback voltage VFB.

[0075] Specifically, the error amplifier 200 is implemented using a single-stage amplification structure or a two-stage amplification structure. Both single-stage and two-stage amplification structures can be implemented using existing known circuit structures, and this embodiment does not impose any restrictions on this. As an optional solution, the error amplifier 200 is implemented using a two-stage amplification structure, which gives the error amplifier 200 a higher signal gain, thus improving the power supply rejection ratio (PSRR).

[0076] The load switching module 300 is connected to the second end of the power transistor M0 and is used to control the switching of the connected load according to the switching control signal SW.

[0077] Specifically, the load switching module 300 includes a multiplexer K1 and at least two load units 310. The control terminal of the multiplexer K1 is connected to a switching control signal SW, the common terminal is connected to the second terminal of the power transistor M0, and each selection terminal is connected to the first terminal of each load unit 310. The second terminal of each load unit 310 is grounded. By controlling the connection between the common terminal of the multiplexer K1 and the corresponding selection terminal through the switching control signal SW, the corresponding load unit 310 is connected to the second terminal of the power transistor M0, thereby realizing the switching control of the connected load.

[0078] In one possible implementation, the switching control signal SW is a set of binary code values, and the multiplexer K1 is composed of at least two switching devices. The first terminals of each switching device are connected to each other as the common terminal of the multiplexer K1, and the second terminals of each switching device are the selection terminals of the multiplexer K1. The control terminals of each switching device correspond to different bits in the binary code value. When the corresponding bit in the binary code value is high, the corresponding switching device is closed; otherwise, the corresponding switching device is open.

[0079] The switching frequency detection module 400 receives the switching control signal SW and uses it to detect the switching frequency of the connected load based on the switching control signal SW, and generates a first power control signal based on the speed of the switching frequency.

[0080] Specifically, such as Figure 2 As shown, the switching frequency detection module 400 includes a first pulse shaping unit 410 and a signal generation unit 420. Wherein:

[0081] The first pulse shaping unit 410 is used to perform pulse widening processing on the pulse in the switching control signal SW to obtain a first rectangular pulse, so as to characterize the switching frequency of the access load according to the density of the first rectangular pulse; for example, if the first rectangular pulse is densely arranged, it indicates that the switching frequency of the access load is fast, and if the first rectangular pulse is sparsely arranged, it indicates that the switching frequency of the access load is slow.

[0082] As an example, the first pulse shaping unit 410 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, a discharge tube VT, a first comparator 411, a second comparator 412, an RS flip-flop 413, a NAND gate 414, and an inverter 415; the first resistor R1 and the first capacitor C1 are connected in series between the operating voltage VCC and ground; the second resistor R2, the third resistor R3, and the fourth resistor R4 are connected in series between the operating voltage VCC and ground; the non-inverting input terminal of the first comparator 411 is grounded via the second capacitor C2 and connected to the connection node of the second resistor R2 and the third resistor R3, and the inverting input terminal is connected to the connection node of the first resistor R1 and the first capacitor C1. The output terminal is connected to the reset terminal of RS flip-flop 413; the non-inverting input terminal of the second comparator 412 is connected to the switching control signal SW, the inverting input terminal is connected to the connection node of the third resistor R3 and the fourth resistor R4, and the output terminal is connected to the set terminal of RS flip-flop 413; the clear terminal of RS flip-flop 413 is connected to the inverted signal R of the clear signal, and the output terminal is connected to the first input terminal of NAND gate 414; the second input terminal of NAND gate 414 is connected to the inverted signal R of the clear signal, and the output terminal is connected to the input terminal of inverter 415 and connected to the gate of discharge tube VT through the fifth resistor R5; the output terminal of inverter 415 serves as the output terminal of the first pulse shaping unit 410; the drain of discharge tube VT is connected to the connection node of the first resistor R1 and the first capacitor C1, and the source is grounded.

[0083] When the inverted signal R of the reset signal is high: the working voltage VCC charges the first capacitor C1 through the first resistor R1. When the capacitor voltage rises to the first set threshold Vth1, the first comparator 411 outputs "0", sets the output of RS flip-flop 413 to 0, the NAND gate 414 outputs "1", and the inverter 415 outputs "0". At the same time, the discharge tube VT is turned on, the first capacitor C1 discharges through the discharge tube VT, and the circuit enters a steady state. When the pulse in the switching control signal SW arrives, since the potential of the pulse is less than the second set threshold Vth2 and the second set threshold Vth2 is less than the first set threshold Vth1, the second comparator 412 outputs "0", setting the output of RS flip-flop 413 to 1, the NAND gate 414 outputs "0", and the inverter 415 outputs "1", and the circuit enters a quasi-stable state. At the same time, the discharge tube VT is cut off, and the operating voltage VCC charges the first capacitor C1 through the first resistor R1. Even if the pulse in the switching control signal SW disappears and the second comparator 412 outputs "1", the charging continues until the capacitor voltage reaches the first set threshold Vth1, at which point the first comparator 411 outputs "0", and the circuit enters a steady state again. The relevant signal waveforms are as follows: Figure 3 As shown.

[0084] The signal generation unit 420 is connected to the output terminal of the first pulse shaping unit 410 and is used to convert the first rectangular pulse into a first analog voltage V1 as a first power control signal by capacitor charging.

[0085] As an example, the signal generation unit 420 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third capacitor C3; the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the first NMOS transistor NM1, and the second NMOS transistor NM2 are connected in series between the operating voltage VCC and ground; the gate terminals of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the second NMOS transistor NM2 are connected to their respective drain terminals; the gate terminal of the first NMOS transistor NM1 is connected to the output terminal of the first pulse shaping unit 410; and the source terminal of the first NMOS transistor NM1 is grounded through the third capacitor C3 and serves as the output terminal of the signal generation unit 420.

[0086] The first rectangular pulse CTL output by the first pulse shaping unit 410 controls the conduction time of the first NMOS transistor NM1, thereby controlling the charging time of the third capacitor C3 by the working voltage VCC, and thus controlling the magnitude of the first analog voltage V1. When the pulse arrangement in the switching control signal SW is relatively dense, the arrangement of the first rectangular pulse obtained after pulse broadening is also relatively dense, which increases the total charging time of the third capacitor C3 during this period and increases the first analog voltage V1.

[0087] The power consumption / response control module 500 is connected to the output of the error amplifier 200 and the switching frequency detection module 400. It is used to adjust the operating current of the power consumption / response control module 500 according to the first power control signal, and to adjust the output by controlling the power transistor M0 under different operating currents.

[0088] Specifically, such as Figure 4As shown, the power consumption / response control module 500 includes: a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first operational amplifier OP1, and a sixth resistor R6; the gate terminal of the fourth PMOS transistor PM4 is connected to the output terminal of the error amplifier 200, the source terminal is connected to the output voltage VOUT, and the drain terminal is connected to the drain terminal of the third NMOS transistor NM3 and the source terminal of the sixth NMOS transistor NM6; the gate terminals of the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 are connected to each other and connected to the inverting input terminal of the first operational amplifier OP1; the source terminals of the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 are grounded; the drain terminal of the fourth NMOS transistor NM4 is connected to its gate terminal; the fifth... The drain of NMOS transistor NM5 is connected to the drain of the fifth PMOS transistor PM5; the gate of the sixth NMOS transistor NM6 is connected to the bias voltage VB2, and its drain is connected to the drain of the sixth PMOS transistor PM6 and serves as the output of the power consumption / response control module 500; the gate of the fifth PMOS transistor PM5 is connected to its drain and then to the gate of the sixth PMOS transistor PM6; the sources of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected to the input power supply VIN; the non-inverting input of the first operational amplifier OP1 is connected to the output of the load switching module 400, and its output is connected to its inverting input via the sixth resistor R6; the substrates of the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 are connected to their respective sources, and the substrate of the sixth NMOS transistor NM6 is grounded.

[0089] The third NMOS transistor NM3, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 form a current mirror structure, and the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 form a current mirror structure. The ratio of the current flowing through the third NMOS transistor NM3 to the current flowing through the fifth NMOS transistor NM5 is P:1, and the ratio of the current flowing through the fifth PMOS transistor PM5 to the current flowing through the sixth PMOS transistor PM6 is 1:Q. P and Q are both arbitrary values ​​greater than 1.

[0090] By utilizing the virtual short and virtual open principle of the first operational amplifier OP1, the voltages at its two input terminals are made the same. The conduction level of the third NMOS transistor NM3 is controlled by the first analog voltage V1 to control the magnitude of the current flowing through it, thereby controlling the operating current of the power consumption / response control module 500. This ensures that the operating current of the power consumption / response control module 500 is positively correlated with the switching frequency of the connected load. When the switching frequency of the connected load is high, the power consumption / response control module 500 adjusts its output under a larger operating current to achieve a fast response. When the switching frequency of the connected load is low, the power consumption / response control module 500 adjusts its output under a smaller operating current to reduce power consumption.

[0091] During output regulation, the error amplifier 200, the fourth PMOS transistor PM4, the sixth NMOS transistor NM6, and the power transistor M0 constitute the main control loop, while the fourth PMOS transistor PM4, the sixth NMOS transistor NM6, and the power transistor M0 constitute the fast response loop. For the above two loops:

[0092] The narrow bandwidth of the main control loop results in poor transient response, but this defect can be compensated by the fast response loop. In the fast response loop, the fourth PMOS transistor PM4 forms a common gate structure, which makes the input impedance low and thus has a high response speed. The fast response loop monitors the output voltage VOUT and can quickly respond to the output voltage VOUT when the load current changes suddenly. The fast response loop also controls and reduces the overshoot and undershoot of the output voltage VOUT.

[0093] When the load switches from light to heavy, the output voltage VOUT experiences an undershoot. Because the source of the fourth PMOS transistor PM4 is connected to the output voltage VOUT, the drain voltage of PM4 decreases, consequently the drain voltage of the sixth NMOS transistor NM6, and consequently the control voltage of power transistor M0. This increases the |VOUT| of power transistor M0. GS This increases the conductivity of the output voltage VOUT, thereby maintaining stable output.

[0094] Similarly, when the load switches from heavy load to light load, the output voltage VOUT overshoots because the source of the fourth PMOS transistor PM4 is connected to the output voltage VOUT. This causes the drain voltage of the fourth PMOS transistor PM4 to rise, and the drain voltage of the sixth NMOS transistor NM6 to rise, which in turn causes the control terminal voltage of the power transistor M0 to rise. This reduces the |V... GS This reduces the conductivity of the circuit, pulling the output voltage VOUT down to maintain output stability.

[0095] Furthermore, the power consumption / response control module 500 also includes a fourth capacitor C4 and a seventh resistor R7; the fourth capacitor C4 and the seventh resistor R7 are connected in series between the gate and drain terminals of the fourth PMOS transistor PM4. Due to the presence of the parasitic gate capacitance of the power transistor M0, it will bypass the high-frequency signal. To avoid high-frequency signal oscillation, the fourth capacitor C4 and the seventh resistor R7 are used to compensate for the phase shift of the high-frequency signal in the amplification stage where the fourth PMOS transistor PM4 is located, so that the loop phase of the high-frequency signal is far from the oscillation condition.

[0096] The bandgap reference module 600 is used to provide a reference voltage VREF. The reference voltage VREF is a voltage that does not change with temperature. It is formed by adding a negative temperature coefficient voltage VBE and a positive temperature coefficient voltage ΔVBE to cancel out the temperature effect. It can be implemented using any existing bandgap reference circuit that can generate a zero temperature coefficient voltage, which has no substantial impact on this embodiment.

[0097] The driver module is connected between the output of the power consumption / response control module 500 and the control terminal of the power transistor M0 to enhance the drive. Of course, for different types of power transistors M0, the drive can also be achieved by inverting the phase of the driver module's output. In applications, this can be achieved by adding an inverter to the output of the driver module. The driver module can be implemented using a dedicated driver stage circuit or an inverter chain; this has no substantial impact on this embodiment.

[0098] Example 2

[0099] like Figure 5 As shown, the difference between this embodiment and Embodiment 1 is that the low-dropout linear regulator in this embodiment also includes a peak-to-average power ratio (PAPR) detection module 700 and a comprehensive control module 800. In this case, the power consumption / response control module 500 is no longer connected to the output of the switching frequency detection module 400, but instead connected to the output of the comprehensive control module 800. This module is used to adjust its operating current according to the total power control signal and to regulate the output through the control power transistor M0 under different operating currents. Wherein:

[0100] The peak-to-average power ratio (PAPR) detection module 700 is used to detect the PAPR of a multi-carrier modulated signal and generate a second power control signal based on the PAPR exceeding a set number of times.

[0101] Specifically, such as Figure 6 As shown, the peak-to-average power ratio (PAPR) detection module 700 includes a comparison unit 710, a second pulse shaping unit 720, and a low-pass filter unit 730. Wherein:

[0102] The comparison unit 710 is used to compare the peak voltage VP_S(t) of the multi-carrier modulated signal with the set voltage VS, and generates a comparison pulse when the peak voltage VP_S(t) is greater than the set voltage VS. The comparison unit 710 is implemented using a comparator, with the non-inverting input connected to the peak voltage VP_S(t), the inverting input connected to the set voltage VS, and the output generating the comparison pulse.

[0103] The second pulse shaping unit 720 is connected to the output terminal of the comparison unit 710 and is used to perform pulse broadening processing on the comparison pulse to generate a second rectangular pulse. The second pulse shaping unit 720 has the same structure as the first pulse shaping unit 410, as detailed in the relevant content of Embodiment 1, and will not be repeated here.

[0104] The low-pass filter unit 730 is connected to the output of the second pulse shaping unit 720 and is used to convert the second rectangular pulse into a second analog voltage quantity V2 as a second power control signal through low-pass filtering. The low-pass filter unit 730 is implemented using a low-pass filter.

[0105] The relevant signal waveforms involved in the comparison unit 710, the second pulse shaping unit 720, and the low-pass filter unit 730 are as follows: Figure 7 As shown in the diagram. This embodiment measures the peak-to-average power ratio (PAPR) of the multi-carrier modulation signal by the magnitude of the peak voltage VP_S(t). It determines whether the PAPR exceeds the set value by comparing the peak voltage VP_S(t) with the set voltage VS, and generates a comparison pulse when the PAPR exceeds the set value. In reality, if the PAPR of the multi-carrier modulation signal only occasionally exceeds the set value within a certain time period, the impact on the low-dropout linear regulator is minimal and negligible. To effectively regulate the low-dropout linear regulator, a second analog voltage V2 should be generated based on the number of times the PAPR of the multi-carrier modulation signal exceeds the set value. This ensures that the operating current of the power consumption / response control module 500 is positively correlated with the number of times the PAPR of the multi-carrier modulation signal exceeds the set value. When the number of times the PAPR of the multi-carrier modulation signal exceeds the set value is high, the power consumption / response control module 500 adjusts its output under a larger operating current to achieve a fast response. When the number of times the PAPR of the multi-carrier modulation signal exceeds the set value is low, the power consumption / response control module 500 adjusts its output under a smaller operating current to reduce power consumption.

[0106] The integrated control module 800 is connected to the output terminals of the switching frequency detection module 400 and the peak-to-average ratio detection module 700, and is used to generate a total power control signal based on the first power control signal and the second power control signal.

[0107] Specifically, such as Figure 8As shown, the integrated control module 800 includes: a second operational amplifier OP2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11; the non-inverting input terminal of the second operational amplifier OP2 is grounded through the eighth resistor R8, the inverting input terminal is connected to the output terminal of the switching frequency detection module 400 through the ninth resistor R9, and is connected to the output terminal of the peak-to-average power ratio detection module 700 through the tenth resistor R10, and the output terminal is connected to its inverting input terminal through the eleventh resistor R11 and serves as the output terminal of the integrated control module 800.

[0108] The second operational amplifier OP2, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11 constitute a circuit structure for adding analog voltages. The relationship between its output voltage and the two input voltages satisfies the following formula: (V1 / R9+V2 / R10)+VB1 / R11=0, where V1 is the first analog voltage output by the switching frequency detection module 400, V2 is the second analog voltage output by the peak-to-average power ratio detection module 700, VB1 is the analog voltage corresponding to the total power control signal, R9 is the resistance value of the ninth resistor, R10 is the resistance value of the tenth resistor, and R11 is the resistance value of the eleventh resistor.

[0109] Example 3

[0110] This embodiment provides a power supply circuit, including a low dropout linear regulator as described in Embodiment 1 or Embodiment 2; of course, in addition to the low dropout linear regulator, the power supply circuit may also include other functional circuits, such as a startup circuit, an overcurrent protection circuit, an overvoltage protection circuit, etc., and this embodiment does not limit this.

[0111] Example 4

[0112] This embodiment provides an electronic system including the power supply circuit described in Embodiment 3. Of course, in addition to the power supply circuit, the electronic system may also include other functional circuits, such as analog-to-digital conversion circuits, audio processing circuits, and radio frequency circuits; this embodiment does not impose any limitations on this. As an optional solution, the electronic system is a System-on-a-Chip (SOC). In fact, this SOC is suitable for various application scenarios, especially multi-carrier modulation applications.

[0113] In summary, the low-dropout linear regulator, power supply circuit, and electronic system of this invention, which features no external capacitors, adjusts the operating current of the power consumption / response control module by varying the switching frequency of the connected load and even the number of times the peak-to-average power ratio (PAPR) of the multi-carrier modulation signal exceeds a set value. Since the operating current of the power consumption / response control module is related to the response speed of the LDO, adjusting the operating current of the power consumption / response control module adjusts the static power consumption of the LDO, resulting in a lower average operating power consumption. When the switching frequency of the connected load is high or the PAPR exceeds a set value frequently, the operating current of the power consumption / response control module is higher, and the response speed is improved by increasing the loop bandwidth. Conversely, when the switching frequency of the connected load is low and the PAPR exceeds a set value less frequently, the operating current of the power consumption / response control module is lower, and the overall energy efficiency is improved by reducing power consumption. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A low-dropout linear regulator without external capacitors, characterized in that, The low-dropout linear regulator includes: The system comprises a power transistor, a feedback resistor network, an error amplifier, a load switching module, a switching frequency detection module, and a power consumption / response control module, among which: The control terminal of the power transistor is connected to the output terminal of the power consumption / response control module. The first terminal is connected to the input power supply, and the second terminal is grounded through the feedback resistor network to generate an output voltage. The feedback resistor network divides the output voltage to generate a feedback voltage. The first input terminal of the error amplifier is connected to the reference voltage, and the second input terminal is connected to the feedback voltage. The load switching module is connected to the second terminal of the power transistor and is used to control the switching of the connected load according to the switching control signal. The switching frequency detection module receives the switching control signal and is used to detect the switching frequency of the access load according to the switching control signal, and generate a first power control signal according to the speed of the switching frequency. The power consumption / response control module is connected to the output of the error amplifier and the switching frequency detection module. It is used to adjust the operating current of the power consumption / response control module according to the first power control signal, and to adjust the output by controlling the power transistor under different operating currents. The switching frequency detection module includes a first pulse shaping unit and a signal generation unit. The first pulse shaping unit is used to perform pulse widening processing on the pulse in the switching control signal to obtain a first rectangular pulse; The signal generation unit is connected to the output terminal of the first pulse shaping unit and is used to convert the first rectangular pulse into a first analog voltage quantity as the first power control signal by capacitor charging.

2. The low-dropout linear regulator without external capacitors according to claim 1, characterized in that, The load switching module includes: a multiplexer switch and at least two load units; the control terminal of the multiplexer switch is connected to the switching control signal, the common terminal is connected to the second terminal of the power transistor, and each selection terminal is connected to the first terminal of each load unit; the second terminal of each load unit is grounded.

3. The low-dropout linear regulator without external capacitors according to claim 1, characterized in that, The first pulse shaping unit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a discharge tube, a first comparator, a second comparator, an RS flip-flop, a NAND gate, and an inverter; the first resistor and the first capacitor are connected in series between the operating voltage and ground; the second resistor, the third resistor, and the fourth resistor are connected in series between the operating voltage and ground; the non-inverting input of the first comparator is grounded via the second capacitor and connected to the connection node of the second resistor and the third resistor, the inverting input is connected to the connection node of the first resistor and the first capacitor, and the output is connected to the reset terminal of the RS flip-flop; The non-inverting input of the second comparator is connected to the switching control signal, the inverting input is connected to the connection node of the third and fourth resistors, and the output is connected to the set input of the RS flip-flop. The clear input of the RS flip-flop is connected to the inverted signal of the clear signal, and the output is connected to the first input of the NAND gate. The second input of the NAND gate is connected to the inverted signal of the clear signal, and the output is connected to the input of the inverter and then connected to the gate of the discharge tube via the fifth resistor. The output of the inverter serves as the output of the first pulse shaping unit. The drain of the discharge tube is connected to the connection node of the first resistor and the first capacitor, and the source is grounded. And / or, the signal generation unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third capacitor; the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected in series between the operating voltage and ground; the gate terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the second NMOS transistor are connected to their respective drain terminals; the gate terminal of the first NMOS transistor is connected to the output terminal of the first pulse shaping unit; and the source terminal of the first NMOS transistor is grounded through the third capacitor and serves as the output terminal of the signal generation unit.

4. The low-dropout linear regulator without external capacitors according to claim 1, characterized in that, The power consumption / response control module includes: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first operational amplifier, and a sixth resistor; the gate terminal of the fourth PMOS transistor is connected to the output terminal of the error amplifier, the source terminal is connected to the output voltage, and the drain terminal is connected to the drain terminal of the third NMOS transistor and the source terminal of the sixth NMOS transistor; the gate terminals of the third, fourth, and fifth NMOS transistors are connected to each other and connected to the inverting input terminal of the first operational amplifier; the third NMOS transistor, the fourth NMOS transistor, and the... The source of the fifth NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected to its gate, and the drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor. The gate of the sixth NMOS transistor is connected to the bias voltage, and its drain is connected to the drain of the sixth PMOS transistor and serves as the output of the power consumption / response control module. The gate of the fifth PMOS transistor is connected to its drain and is also connected to the gate of the sixth PMOS transistor. The sources of the fifth and sixth PMOS transistors are connected to the input power supply. The non-inverting input of the first operational amplifier is connected to the output of the load switching module, and its output is connected to its inverting input via the sixth resistor.

5. The low-dropout linear regulator without external capacitors according to claim 4, characterized in that, The power consumption / response control module further includes a fourth capacitor and a seventh resistor; the fourth capacitor and the seventh resistor are connected in series between the gate and drain terminals of the fourth PMOS transistor.

6. The low-dropout linear regulator without external capacitors according to any one of claims 1-5, characterized in that, The low-dropout linear regulator further includes: a peak-to-average power ratio (PAPR) detection module and a comprehensive control module, wherein: The peak-to-average power ratio (PAPR) detection module is used to detect the PAPR of the multi-carrier modulated signal and generate a second power control signal based on the PAPR exceeding a set number of times. The integrated control module is connected to the output of the switching frequency detection module and the peak-to-average power ratio detection module, and is used to generate a total power control signal based on the first power control signal and the second power control signal. The power consumption / response control module adjusts its operating current according to the total power control signal, and adjusts the output by controlling the power transistor under different operating currents.

7. The low-dropout linear regulator without external capacitors according to claim 6, characterized in that, The peak-to-average power ratio (PAPR) detection module includes: a comparison unit, a second pulse shaping unit, and a low-pass filtering unit, wherein: The comparison unit is used to compare the peak voltage of the multi-carrier modulated signal with a set voltage, and to generate a comparison pulse when the peak voltage is greater than the set voltage; The second pulse shaping unit is connected to the output terminal of the comparison unit and is used to perform pulse widening processing on the comparison pulse to generate a second rectangular pulse; The low-pass filter unit is connected to the output of the second pulse shaping unit and is used to convert the second rectangular pulse into a second analog voltage quantity as the second power control signal through low-pass filtering.

8. The low-dropout linear regulator without external capacitors according to claim 7, characterized in that, When the switching frequency detection module includes the first pulse shaping unit, the first pulse shaping unit and the second pulse shaping unit have the same structure.

9. The low-dropout linear regulator without external capacitors according to claim 6, characterized in that, The integrated control module includes: a second operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor; the non-inverting input terminal of the second operational amplifier is grounded through the eighth resistor, the inverting input terminal is connected to the output terminal of the switching frequency detection module through the ninth resistor, and is connected to the output terminal of the peak-to-average power ratio detection module through the tenth resistor, and the output terminal is connected to its inverting input terminal through the eleventh resistor and serves as the output terminal of the integrated control module.

10. A power supply circuit, characterized in that, The power supply circuit includes a low dropout linear regulator as described in any one of claims 1-9.

11. An electronic system, characterized in that, The electronic system includes the power supply circuit as described in claim 10.

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