Control circuit, control device and processor

Abstract

This invention provides a control circuit, control device, and processor, applied in the field of computer technology. The control circuit includes: a loop module, used to obtain loop information corresponding to each layer of loop logic based on the currently executed nested loop instruction, execute the current layer of loop logic, and store the loop information corresponding to the current layer of loop logic; a cache module, used to store the loop information corresponding to the target layer of loop logic in each layer of loop logic, and write the loop information corresponding to the remaining layers of loop logic in each layer of loop logic into a memory module; a memory module, used to store the loop information corresponding to the remaining layers of loop logic; the area of ​​the memory module is smaller than the area of ​​the cache module, and the storage capacity of the memory module is larger than the storage capacity of the cache module; a control module, used to control the loop module, cache module, and memory module to perform their respective operations. Using this control circuit, arbitrary levels of nested loop logic can be implemented with relatively small hardware resources.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a control circuit, control device, and processor. Background Technology

[0002] Currently, processors are commonly used in autonomous driving chips, robotics chips, artificial intelligence (AI) chips, neural network processors (NPUs), neural network accelerators, central processing units (CPUs), graphics processing units (GPUs), and cloud computing chips. Taking autonomous driving chips as an example, the core of autonomous driving technology is perception, decision-making, and execution. The execution of perception and planning typically requires computation by neural networks, and the efficient computation of the relevant operators that make up the neural network determines perception latency and decision-making efficiency; these are important indicators for evaluating autonomous driving technology.

[0003] Loop instructions are among the most commonly used instructions in processors. Currently, there are two main ways to implement loop instructions in processors: one is the soft loop method, which uses a combination of multiple instructions, such as branch instructions, to achieve the loop function; the other is the hard loop method, which uses dedicated hardware structures to implement the loop function, specifically by setting up corresponding hardware structures for each loop level to achieve multiple loops.

[0004] However, neither of the above two methods of implementing loop instructions can simultaneously address both hardware resource constraints and the implementation of deeply nested loops. Summary of the Invention

[0005] This invention provides a control circuit, control device, and processor to address the shortcomings of existing methods for implementing loop functions, which cannot simultaneously consider hardware resources and the implementation of deeply nested loop functions. The invention aims to achieve arbitrary-level nested loop logic with a smaller area of ​​hardware resources.

[0006] In a first aspect, the present invention provides a control circuit, the control circuit comprising:

[0007] The loop module is used to obtain the loop information corresponding to each level of loop logic based on the currently executed nested loop instruction, execute the current level of loop logic, and store the loop information corresponding to the current level of loop logic; the loop information of the current level of loop logic includes at least one of the loop body start position, loop body end position, and current execution state of the current level of loop logic.

[0008] The cache module, connected to the loop module, is used to store the loop information corresponding to the target layer loop logic in each layer of loop logic, and to write the loop information corresponding to the remaining layer loop logic in each layer of loop logic into the memory module; the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer of loop logic, and the remaining layer loop logic is the loop logic remaining in each layer of loop logic except for the current layer loop logic and the target layer loop logic.

[0009] The memory module, connected to the cache module, is used to store the loop information corresponding to the remaining layer loop logic; the area of ​​the memory module is smaller than that of the cache module, and the storage capacity of the memory module is greater than that of the cache module.

[0010] The control module is connected to the loop module, cache module, and memory module respectively, and is used to control the loop module, cache module, and memory module to perform their respective operations.

[0011] According to a control circuit provided by the present invention, the above-mentioned loop module includes multiple loop sub-modules, each loop sub-module corresponding to execute a layer of loop logic, and the above-mentioned cache module includes a first data interface corresponding to each of the multiple loop sub-modules.

[0012] Each loop submodule is connected to the cache module through a corresponding first data interface, and is used to write the loop information corresponding to the target layer loop logic into the cache module through each first data interface, and / or read the loop information corresponding to the target layer loop logic from the cache module.

[0013] According to a control circuit provided by the present invention, the above-mentioned buffer module is specifically used for

[0014] The first push control signal is sent by the receiving control module; the first push control signal is sent by the control module when it determines that the number of loop logics at each layer is greater than the number of multiple loop submodules.

[0015] According to the first push control signal, the loop information corresponding to each layer of loop logic is obtained from the loop module, and multiple target layer loop logics located in the outer layer are determined from each layer of loop logic. The loop information of each target layer loop logic is pushed into the information stack of the cache module in a preset order.

[0016] When the number of target layer loop logics pushed into the information stack reaches the depth threshold, the receiving control module sends a first write data control signal, and according to the first write data control signal, the loop information of the target layer loop logic located at the bottom of the information stack is used as the loop information of the remaining layer loop logics and written into the memory module, until the loop information of multiple target layer loop logics is pushed into the information stack and / or written into the memory module.

[0017] According to a control circuit provided by the present invention, the above-mentioned control module is specifically used for

[0018] When the number of loop logics in each layer is greater than the number of multiple loop sub-modules, a second push control signal is sent to the loop module; the second push control signal is used to instruct the loop module to send the loop information corresponding to the target layer loop logic to the cache module, so that the cache module pushes the loop information of the target layer loop logic onto the stack.

[0019] When the number of target layer loop logics pushed into the information stack reaches the depth threshold, a second write data control signal is sent to the memory module; the second write data control signal is used to instruct the memory module to write the loop information of the remaining layer loop logics sent by the cache module into the memory area.

[0020] According to a control circuit provided by the present invention, the above-mentioned control module is further used for...

[0021] When a new nested loop instruction is obtained and multiple loop submodules are occupied, the new nested loop instruction is assigned to the loop submodule that executes the outermost loop logic among the multiple loop submodules.

[0022] When multiple loop submodules execute the inner nested loop logic of each loop logic, and it is determined that the new nested loop instruction is not the nested loop instruction corresponding to the inner nested loop logic of each loop logic, a pop control signal is sent to the cache module; the pop control signal is used to instruct the cache module to return the loop information of the target layer loop logic to the idle loop submodule among the multiple loop submodules.

[0023] If the number of target layer loop logics in the cache module is less than the depth threshold, a read data control signal is sent to the cache module. The read data control signal is used to instruct the cache module to read the loop information of the remaining layer loop logics in the memory module and push the loop information of the remaining layer loop logics onto the bottom of the information stack of the cache module.

[0024] According to a control circuit provided by the present invention, the target layer loop logic is specifically the loop logic of the layer or more closest to the current layer loop logic, and the remaining layer loop logic is specifically the loop logic of the layer or more furthest from the current layer loop logic.

[0025] According to a control circuit provided by the present invention, the read / write efficiency of the cache module is higher than that of the memory module.

[0026] According to a control circuit provided by the present invention, the memory module includes a second data interface;

[0027] The aforementioned cache module is connected to the memory module through a second data interface. Specifically, it is used to write the loop information corresponding to the remaining layer loop logic into the memory module through the second data interface, and / or to read the loop information corresponding to the remaining layer loop logic from the memory module.

[0028] In a second aspect, the present invention also provides a control device, the control device comprising:

[0029] The loop module is used to obtain the loop information corresponding to each level of loop logic based on the currently executed nested loop instruction, execute the current level of loop logic, and store the loop information corresponding to the current level of loop logic; the loop information of the current level of loop logic includes at least one of the loop body start position, loop body end position, and current execution state of the current level of loop logic.

[0030] The cache module is used to store the loop information corresponding to the target layer loop logic in each layer of loop logic, and to write the loop information corresponding to the remaining layer loop logic in each layer of loop logic into the memory module; the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer of loop logic, and the remaining layer loop logic is the loop logic remaining in each layer of loop logic except for the current layer loop logic and the target layer loop logic.

[0031] The memory module is used to store the loop information corresponding to the remaining layer loop logic; the area of ​​the memory module is smaller than that of the cache module, and the storage capacity of the memory module is greater than that of the cache module.

[0032] The control module is used to control the loop module, cache module, and memory module to perform their respective operations.

[0033] Thirdly, the present invention also provides a processor that includes the control circuit described in the first aspect.

[0034] The present invention provides a control circuit, a control device, and a processor. The control circuit includes a loop module, a cache module, a memory module, and a control module. The loop module obtains loop information corresponding to each layer of loop logic based on the currently executed nested loop instruction, executes the current layer of loop logic, and stores the loop information corresponding to the current layer of loop logic. The cache module is connected to the loop module and stores the loop information of the target layer of loop logic in each layer of loop logic and writes the loop information of the remaining layer of loop logic in each layer of loop logic into the memory module. The memory module is connected to the cache module and stores the loop information of the remaining layer of loop logic. The control module is connected to... The loop module, cache module, and memory module are connected to control the execution of corresponding operations by the loop module, cache module, and memory module. The loop information of the current-level loop logic includes at least one of the following: the start position of the loop body, the end position of the loop body, and the current execution state. The target-level loop logic is one or more loop logics located outside the current-level loop logic. The remaining loop logic refers to the loop logic remaining in each layer of loop logic besides the current-level and target-level loop logic. The area of ​​the memory module is smaller than that of the cache module, but the storage capacity of the memory module is larger than that of the cache module. This control circuit can store the loop information of all remaining loop logic in nested loop instructions in a memory module with a larger capacity and smaller area. This allows the loop information to be retrieved from the memory module whenever the loop module executes any level of loop logic, thus enabling the implementation of arbitrary nested loop functionality with relatively small hardware memory resources. Furthermore, while implementing arbitrary nested loop functionality, the loop information of the loop logic outside the current-level loop logic can be stored in a cache module with limited capacity and high read / write efficiency, thereby improving the loop efficiency when implementing arbitrary nested loop functionality. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is one of the schematic diagrams of the control circuit provided by the present invention.

[0037] Figure 2 This is the second schematic diagram of the control circuit provided by the present invention.

[0038] Figure label:

[0039] 10: Control circuit; 110: Loop module; 120: Buffer module; 130: Memory module; 140: Control module; 1100: Loop submodule; 1200: First data interface; 1300: Second data interface. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0041] Currently, there are two main ways to implement loop instructions in processors: soft loops and hard loops. Soft loops use a combination of branch instructions and other instructions to implement the loop function. The core loop body of this method only has two instructions, but each loop iteration requires five instructions, resulting in a significant decrease in instruction execution efficiency and thus low loop efficiency. Hard loops use dedicated hardware structures to implement the loop function. Specifically, each loop level requires a corresponding hardware structure to achieve multi-level loops. This method requires two instructions per loop iteration and has higher loop efficiency. However, each loop level requires a corresponding hardware structure, which, due to area resource limitations, prevents deep loop nesting and restricts support for scenarios such as multi-level loops and function calls. Therefore, neither of these methods can simultaneously address both hardware resource constraints and the implementation of deep nested loop functionality. Based on this, this invention provides a control circuit, control device, and processor to solve this technical problem.

[0042] The following is combined Figures 1-2 The control circuit of an embodiment of the present invention is described.

[0043] Figure 1 This is one of the schematic diagrams of the control circuit 10 provided by the present invention, see [link / reference]. Figure 1As shown, the control circuit 10 includes a loop module 110, a cache module 120, a memory module 130, and a control module 140. The loop module 110 is used to obtain loop information corresponding to each layer of loop logic based on the currently executed nested loop instruction, execute the current layer of loop logic, and store the loop information corresponding to the current layer of loop logic. The loop information of the current layer of loop logic includes at least one of the loop body start position, loop body end position, and current execution state. The cache module 120, connected to the loop module 110, is used to store the loop information corresponding to the target layer of loop logic in each layer of loop logic, and to write the loop information corresponding to the remaining layer of loop logic in each layer of loop logic into the memory module 130. The target layer loop logic is one or more loop logics located outside the current layer loop logic in each layer loop logic, and the remaining layer loop logic is the loop logic remaining in each layer loop logic excluding the current layer loop logic and the target layer loop logic; the memory module 130 is connected to the cache module 120 and is used to store the loop information corresponding to the remaining layer loop logic; the area of ​​the memory module 130 is smaller than the area of ​​the cache module 120, and the storage capacity of the memory module 130 is greater than the storage capacity of the cache module 120; the control module 140 is connected to the loop module 110, the cache module 120 and the memory module 130 respectively, and is used to control the loop module 110, the cache module 120 and the memory module 130 to perform their respective operations.

[0044] The loop module 110 (which can be referred to as the loop module) is connected to the cache module 120 and the control module 140. When the processor executes the current nested loop instruction, it can obtain the nested loop program corresponding to the nested loop instruction. The nested loop program can include multiple layers of loop logic (i.e., multiple loops), and it can also obtain the loop information corresponding to each layer of loop logic. The loop information of each layer of loop logic can include the start position of the loop body (i.e., the start pc, where pc refers to the program counter), the end position of the loop body (i.e., the end pc), and the current execution state. The current execution state refers to the current loop count of the loop logic, that is, which loop has been executed to.

[0045] The loop module 110 may include an execution unit and a storage unit. The execution unit can execute the loop logic of some layers in the multi-layered loop logic of the nested loop program described above. Here, the loop logic currently being executed by the execution unit of the loop module 110 can be denoted as the current layer loop logic. The number of layers of the current layer loop logic is the same as the number of hardware logic loops supported by the loop module 110. The storage unit in the loop module 110 may be, for example, an internal register, which can store the loop information required by the loop module 110 to execute the current layer loop logic, such as the loop information corresponding to the current layer loop logic.

[0046] For example, suppose the nested loop program above includes 5 levels of loop logic, that is, a 5-level nested loop program, which can be exemplified as follows:

[0047] {

[0048] loop1(0, 1, 2)

[0049] loop2(0, 1, 2)

[0050] loop3(0, 1, 2)

[0051] loop4(0, 1, 2)

[0052] loop5(0, 1, 2)

[0053] a = a + 1

[0054] }

[0055] The aforementioned cache module 120 can be a cache area composed of a stack, which has a large area but a small storage capacity. The aforementioned memory module 130 can be a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) or other types of memory, which has a small area and a large storage capacity, and can store more data or information.

[0056] The aforementioned cache module 120 is connected to the loop module 110. When the execution unit of the loop module 110 executes the current layer loop logic, it can store the loop information corresponding to the current layer loop logic in the corresponding storage unit. Generally, the number of layers of the current layer loop logic is the number of hardware logic loops supported by the loop module 110, which is less than the number of layers of multi-layer loop logic included in the nested loop program. That is to say, the hardware resources of the loop module 110 are limited, and it cannot execute all layers of loop logic at the moment. At this time, the loop information of one or more layers of loop logic outside the current layer loop logic (these are loop logics that have not been executed at the moment) can be sent to the cache module 120 so that the cache module 120 can store the loop information of one or more layers of loop logic outside the current layer loop logic in its own storage. Meanwhile, the cache module 120 is also connected to the memory module 130. Since the storage capacity of the cache module 120 is small, in order to avoid the cache module 120 overflowing, the cache module 120 can write a portion of the loop information of one or more layers of loop logic outside the current layer of loop logic obtained from the loop module 110 into the memory module 130 for storage.

[0057] The loop information of the layer loop logic stored in the cache module 120 can be recorded as the loop information of the target layer loop logic, and the loop information of the layer loop logic stored in the memory module 130 can be recorded as the loop information of the remaining layer loop logic. It can be understood that the memory module 130 stores all layer loop logic except for the current layer loop logic and the target layer loop logic. The area of ​​the memory module 130 is smaller than that of the cache module 120, and its storage capacity is larger. Therefore, it can store more layer loop logic information without occupying excessive hardware area and resources. When the loop module 110 needs to execute loop logic of any nested layer, the loop module 110 can obtain the required layer loop information from the memory module 130 through the cache module 120. Thus, the loop logic function of any nested layer can be implemented with a smaller memory module 130, balancing hardware resources and the implementation of deep nested loop functions.

[0058] Further, as an optional embodiment, the target layer loop logic is specifically the loop logic of the layer or more closest to the current layer loop logic, and the remaining layer loop logic is specifically the loop logic of the layer or more furthest from the current layer loop logic.

[0059] Continuing with the example of the 5-level nested loop program, assuming that the current loop logic being executed by loop module 110 is loop5 and loop4, then the target loop logic stored in cache module 120 is loop3 and loop2, and the memory module 130 stores loop1. Loop3 and loop2 are the loop logic layers closest to loop4 and loop5. After loop module 110 executes loop5 and loop4, it will generally execute loop3 and loop2 sequentially. Therefore, storing loop3 and loop2 in cache module 120 allows loop module 110 to quickly retrieve the required loop information during the loop process, improving memory access speed. Meanwhile, loop1 is the loop logic layer furthest from loop4 and loop5. Storing the loop information of these furthest loop logic layers in memory module 130 allows for quick retrieval of the corresponding loop information when these loop logic layers are executed, thus enabling arbitrary-level nested loop functionality.

[0060] In addition, as an optional embodiment, the read / write efficiency of the cache module 120 is higher than that of the memory module 130. This makes it easier for the loop module 110 to efficiently read or write data in the cache module 120, thereby improving memory access speed and efficiency, and thus improving the efficiency of the entire loop instruction execution.

[0061] Furthermore, the control module 140 (which can be referred to as the Ctrl module) is connected to the loop module 110, the cache module 120, and the memory module 130. The control module 140 can control the loop module 110, the cache module 120, and the memory module 130 to perform corresponding operations. These operations can include reading / acquiring data, writing / storing data, and other control operations. For example, the control module 140 can send nested loop instructions and loop information for each layer of loop logic to the loop module 110, control the execution unit of the loop module 110 to execute the current layer of loop logic and store the loop information of the current layer of loop logic, control the cache module 120 to store the loop information of the target layer of loop logic, and write the loop information of the remaining layers of loop logic to the memory module 130.

[0062] In this embodiment, the control circuit includes a loop module, a cache module, a memory module, and a control module. The loop module is used to obtain the loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, execute the current layer of loop logic, and store the loop information corresponding to the current layer of loop logic. The cache module is connected to the loop module and is used to store the loop information of the target layer loop logic in each layer of loop logic and write the loop information of the remaining layer loop logic in each layer of loop logic into the memory module. The memory module is connected to the cache module and is used to store the loop information of the remaining layer loop logic. The control module is connected to the loop module, the cache module, and the memory module respectively and is used to control the loop module, the cache module, and the memory module to perform corresponding operations. The loop information of the current layer loop logic includes at least one of the loop body start position, the loop body end position, and the current execution state of the current layer loop logic. The target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer of loop logic. The remaining loop logic is the loop logic remaining in each layer of loop logic excluding the current layer loop logic and the target layer loop logic. The area of ​​the memory module is smaller than that of the cache module, and the storage capacity of the memory module is larger than that of the cache module. This control circuit can store all the loop information of the remaining loop logic in the nested loop instruction in a memory module with a large capacity and a small area. This allows the corresponding loop information to be retrieved from the memory module when the loop module executes any level of loop logic, thus enabling the implementation of loop functions with arbitrary nesting levels with relatively small hardware memory resources. In addition, while implementing the loop function with arbitrary nesting levels, the loop information of the loop logic outside the current loop logic can be stored in a cache module with limited capacity and high read and write efficiency, which can improve the loop efficiency when implementing the loop function with arbitrary nesting levels.

[0063] Figure 2 This is a second schematic diagram of the control circuit 10 provided by the present invention, see [link / reference]. Figure 2As shown, the above-mentioned loop module 110 includes multiple loop sub-modules 1100, each loop sub-module 1100 corresponding to execute a layer of loop logic. The above-mentioned cache module 120 includes a first data interface 1200 corresponding to each of the multiple loop sub-modules 1100. Each loop sub-module 1100 is connected to the cache module 120 through the corresponding first data interface 1200, and is used to write the loop information corresponding to the target layer loop logic into the cache module 120 through each first data interface 1200, and / or read the loop information corresponding to the target layer loop logic in the cache module 120.

[0064] The aforementioned multiple loop submodules 1100 can be sequentially named loop submodule 0, loop submodule 1, loop submodule 2, ..., loop submodule ..., loop submodule n, where each of these n loop submodules can be denoted as loop submodule 1100, and n is greater than 1, representing the number of hardware logic loops supported by loop module 110, which is generally a finite number, meaning the resources of the hardware loop logic module are limited. The cache module 120 can be configured with a number of first data interfaces 1200 equal to (or greater than) the number of loop submodules 1100. Similarly, each loop submodule 1100 can also be configured with a data interface corresponding to the first data interface 1200. These first data interfaces 1200 are each connected to a data interface on a loop submodule 1100, allowing each loop submodule 1100 to directly access the cache module 120 through its corresponding first data interface 1200, thereby improving the memory access speed of the loop submodule 1100.

[0065] Alternatively, as an optional embodiment, each loop submodule 1100 includes a storage unit and an execution unit. The execution unit can execute a layer of loop logic, and the storage unit can be used to store the loop information required by the corresponding execution unit when executing the loop logic.

[0066] Optionally, see [link to relevant documentation] Figure 2 As shown, the memory module 130 includes a second data interface 1300; the cache module 120 is connected to the memory module 130 through the second data interface 1300, and is specifically used to write the loop information corresponding to the remaining layer loop logic into the memory module 130 through the second data interface 1300, and / or read the loop information corresponding to the remaining layer loop logic in the memory module 130.

[0067] The memory module 130 can be equipped with a second data interface 1300, and the corresponding cache module 120 can also be equipped with a data interface that connects to the second data interface 1300. This allows the cache module 120 to connect to the memory module 130 through the second data interface 1300 to perform read and write operations on the memory module 130. Providing this interface facilitates the cache module 120 in accurately reading data / information from or writing data / information to the memory module 130.

[0068] In this embodiment, the loop module includes multiple loop sub-modules, and the cache module is provided with data interfaces that correspond one-to-one with each of the loop sub-modules. This allows each loop sub-module to directly access the cache module through its corresponding data interface, improving the memory access speed of the loop sub-modules to the cache module and thus improving loop efficiency. Additionally, the memory module is provided with a data interface corresponding to the cache module, enabling the cache module to accurately read data / information from or write data / information to the memory module.

[0069] The following examples illustrate the case of pushing onto the stack in the cache module 120.

[0070] In some embodiments, the above-mentioned cache module 120 is specifically used for

[0071] The first push control signal is sent by the control module 140; the first push control signal is sent by the control module 140 when it is determined that the number of loop logics at each layer is greater than the number of multiple loop submodules 1100.

[0072] According to the first push control signal, the loop information corresponding to each layer of loop logic is obtained from the loop module 110, and multiple target layer loop logics located in the outer layer are determined from each layer of loop logic. The loop information of each target layer loop logic is pushed into the information stack of the cache module 120 in a preset order.

[0073] When the number of target layer loop logics pushed into the information stack reaches the depth threshold, the first write data control signal sent by the receiving control module 140 is used as the loop information of the remaining layer loop logics and written into the memory module 130 according to the first write data control signal, until the loop information of multiple target layer loop logics is pushed into the information stack and / or written into the memory module 130.

[0074] Optionally, the aforementioned control module 140 is specifically used for

[0075] When the number of loop logics at each layer is greater than the number of multiple loop sub-modules 1100, a second push control signal is sent to the loop module 110; the second push control signal is used to instruct the loop module 110 to send the loop information corresponding to the target layer loop logic to the cache module 120, so that the cache module 120 pushes the loop information of the target layer loop logic onto the stack.

[0076] When the number of target layer loop logics pushed into the information stack reaches the depth threshold, a second write data control signal is sent to the memory module 130; the second write data control signal is used to instruct the memory module 130 to write the loop information of the remaining layer loop logics sent by the cache module 120 into the memory area.

[0077] The cache module 120 may include an information stack for storing loop information of the target layer loop logic. The information stack is characterized by last-in-first-out (LIFO), meaning that the loop information that enters the information stack first is read out last.

[0078] When the control module 140 executes the nested loop instruction, it can determine whether the total number of loop logic layers is greater than the number of multiple loop sub-modules 1100. If it is not greater, it means that each loop sub-module 1100 can complete all the loop logic layers. If the total number of loop logic layers is greater than the number of multiple loop sub-modules 1100, it means that each loop sub-module 1100 cannot complete all the loop logic layers. In this case, the control module 140 can send a push instruction to the cache module 120 and the loop module 110, instructing the loop module 110 to push the loop information of the loop logic outside the current loop logic layer into the information stack of the cache module 120.

[0079] Specifically, during the stack push process, the loop information of the outermost loop logic can be pushed onto the information stack first, followed by the loop information of the inner loop logic adjacent to the outermost layer. During the stack push process, the control module 140 can continuously determine whether the number of target layer loop logics pushed into the information stack of the cache module 120 reaches the depth threshold. If the depth threshold is reached, the target layer loop logic at the bottom of the stack is used as the remaining layer loop logic and its loop information is written into the memory module 130. Then, the loop information of the target loop logic can continue to be pushed into the information stack of the cache module 120. When the number of target layer loop logics pushed into the stack reaches the depth threshold, the new target layer loop logic at the bottom of the stack is used as the remaining layer loop logic and its loop information is written into the memory module 130. This process is iterated until the information stack of the cache module 120 stores the same number of target layer loop logics as the depth threshold, and the loop information of all remaining layers of loop logic in each layer is written into the memory module 130. In addition, the aforementioned depth threshold refers to the depth of the information stack of the cache module 120, that is, the number of loop information of loop logic that can be pushed into it.

[0080] For example, continuing with the above 5-level nested loop program, assuming that the current loop logic being executed by loop module 110 is loop5 and loop4, and assuming that the depth threshold of the information stack of cache module 120 is 2, then loop module 110 can first push loop1 onto the information stack of cache module 120, then push loop2 onto the information stack, and after pushing loop2, write loop1, which is located at the bottom of the stack, into memory module 130, and then push loop3 onto the information stack. When actually executing the nested loop instructions, if loop5 has finished executing, loop3 can be read from the information stack and returned to loop module 110 for execution, and loop1 in memory module 130 can be read to the bottom of the information stack.

[0081] In this embodiment, the control module sends push instructions to the loop module and the cache module to control the loop module to push the loop information of the outermost loop logic into the information stack of the cache module in sequence. When the loop information of the target layer loop logic stored in the information stack reaches the depth threshold, the loop information of the target layer loop logic at the bottom of the stack is written into the memory module in sequence. This makes it easier to accurately store some loop information of the loop logic layer close to the current loop logic in the cache module, improving loop efficiency, and can accurately store the loop information of all remaining loop logic in the memory module, so as to accurately realize the loop function of any nested layer.

[0082] The following examples illustrate the case of popping data from the cache module 120.

[0083] In some embodiments, the control module 140 is further used for

[0084] When a new nested loop instruction is obtained and multiple loop submodules 1100 are occupied, the new nested loop instruction is assigned to the loop submodule 1100 that executes the outermost loop logic among the multiple loop submodules 1100.

[0085] When multiple loop submodules 1100 execute the inner nested loop logic of each loop logic layer, and determine that the new nested loop instruction is not the nested loop instruction corresponding to the inner nested loop logic of each loop logic layer, a pop control signal is sent to the cache module 120; the pop control signal is used to instruct the cache module 120 to return the loop information of the target layer loop logic to the idle loop submodule 1100 among the multiple loop submodules 1100.

[0086] If the number of target layer loop logics in cache module 120 is less than the depth threshold, a read data control signal is sent to cache module 120. The read data control signal is used to instruct cache module 120 to read the loop information of the remaining layer loop logics in memory module 130 and push the loop information of the remaining layer loop logics onto the bottom of the information stack of cache module 120.

[0087] After the control module 140 obtains a new nested loop instruction, it can first determine whether each loop sub-module 1100 of the loop module 110 is occupied. If they are all occupied, the new nested loop instruction is assigned to the loop sub-module 1100 that executes the outermost loop logic. At the same time, a push control signal can be sent to the loop sub-module 1100 to instruct it to push the loop information of the loop logic layer corresponding to the new nested loop instruction into the information stack of the cache module 120.

[0088] Meanwhile, after the outermost loop logic is executed, the aforementioned multiple loop submodules 1100 will continue to execute the corresponding inner nested loop logic. If a new nested loop instruction is obtained at this time, the control module 140 can determine whether the loop logic layer corresponding to the new nested loop instruction is the inner nested loop logic corresponding to the currently executed nested loop instruction. If not, the control module 140 can send a stack pop control signal to the cache module 120 to instruct the cache module 120 to return the loop information of the inner nested loop logic corresponding to the currently executed nested loop instruction to the loop submodules 1100 for execution. Specifically, it can be returned to the idle submodules in each loop submodule 1100.

[0089] After returning the loop information of the inner nested loop logic (i.e., the loop information of the target layer loop logic) in the information stack of cache module 120 to the idle loop submodule 1100, if control module 140 determines that the number of loop logic layers of the loop information stored in the information stack is less than the depth threshold, it can send a read data control signal and the address of memory module 130 to cache module 120. This allows cache module 120 to read the loop information of the outer nested loop logic corresponding to the currently executed nested loop instruction from memory module 130 at the address, for use by loop submodule 1100 next time. Here, after cache module 120 reads the loop information of the outer nested loop logic corresponding to the currently executed nested loop instruction from memory module 130, it can store the read loop information at the bottom of the information stack. This ensures that the loop logic layers from top to bottom of the stack are sequentially closer to the currently executed loop logic layer, improving memory access efficiency.

[0090] In this embodiment, when a new nested loop instruction is obtained and the current loop instruction has not yet been completed, a pop control signal is sent to the cache module to instruct the cache module to return the inner loop logic to the loop module for execution. When the loop information stored in the cache module is less than the depth threshold, part of the loop information is read from the memory module and stored at the bottom of the cache module's stack. This makes it easier for the loop module to obtain the loop information of the inner loop logic from the cache module for loop execution, thus improving loop efficiency. At the same time, part of the loop logic layer's loop information can be obtained from the memory module and sent to the cache module, thereby further improving loop efficiency while implementing loop functionality of arbitrary nested layers.

[0091] For example, assume the hardware loop logic of the loop module is 2 (i.e., it includes two loop sub-modules), the depth threshold of the cache module is 2 (i.e., the cache module can store loop information of up to two loop logic layers), and denot the cache module as stack and the memory module as ddr. Continuing with the above 5-level nested loop program as an example, the corresponding PC jumps of this nested loop program are as follows: 1->2->3->4->5->6->6->5->6->6->4->5->6->6->5->6->6->3->4->5->6->6->5->6->6->4->5->6->6->6->6->2->3->4->5->6->6->6->6->4->5->6->6->6->6->6->3->4->5->6->6->6->6->6->4->5->6->6->6->6, where 1 to 6 are the first to sixth lines of the above nested loop program, the first line is loop1(0, 1, 2), and the sixth line is a=a+1.

[0092] Based on the above nested loop program and the above PC jump order, some hardware behaviors of the processor are described as follows:

[0093] Execute the first line of the program: loop1 enters the loop hardware;

[0094] Execute line 2 of the program: loop2 enters the loop hardware;

[0095] Execute line 3: loop3 enters the loop hardware, and loop1 information is pushed onto the stack;

[0096] Execute line 4: loop4 enters the loop hardware, and loop2 information is pushed onto the stack;

[0097] Execute line 5: loop5 enters the loop hardware, loop3 information is pushed onto the stack, and loop1 information is entered into the DDR;

[0098] Execute line 6 of the program: a = a + 1 (loop1 = 0, loop2 = 0, loop3 = 0, loop4 = 0, loop5 = 0);

[0099] Execute line 6 of the program: a = a + 1, (loop1 = 0, loop2 = 0, loop3 = 0, loop4 = 0, loop5 = 1);

[0100] Execute line 5 of the program: loop5 enters the loop hardware;

[0101] Execute line 6 of the program: a = a + 1 (loop1 = 0, loop2 = 0, loop3 = 0, loop4 = 1, loop5 = 0);

[0102] Execute line 6 of the program: a = a + 1, (loop1 = 0, loop2 = 0, loop3 = 0, loop4 = 1, loop5 = 1); loop4 loop execution ends; loop3 loop information is popped from the stack and enters the hardware loop; the stack is in a pre-emptive state, loop1 loop information is read from the ddr and enters the bottom of the stack. ......

[0103] Execute line 4 of the program: loop4 enters the loop hardware;

[0104] Execute line 5: loop5 enters the loop hardware, and the loop information of loop3 is pushed onto the stack;

[0105] Execute line 6 of the program: a = a + 1 (loop1 = 1, loop2 = 1, loop3 = 1, loop4 = 0, loop5 = 0);

[0106] Execute line 6 of the program: a = a + 1 (loop1 = 1, loop2 = 1, loop3 = 1, loop4 = 0, loop5 = 1);

[0107] Execute line 5 of the program: loop5 enters the loop hardware;

[0108] Execute line 6 of the program: a = a + 1 (loop1 = 1, loop2 = 1, loop3 = 1, loop4 = 1, loop5 = 0);

[0109] Execute line 6 of the program: a = a + 1, (loop1 = 1, loop2 = 1, loop3 = 1, loop4 = 1, loop5 = 1); loop1 loop execution ends; loop3 loop information is popped from the stack, the stack is in a pre-emptive state, loop1 loop information is read from ddr and put into the bottom of the stack, loop2 loop information is popped from the stack, loop1 loop information is popped from the stack.

[0110] As can be seen from the above description, the technical solution of the present invention can use a memory module, which has a small area but a large storage capacity, to store the loop information of the remaining unstored loop logic layers in each layer of loop logic, so that arbitrary layer loop logic can be implemented with a small area cost.

[0111] The control device provided by the present invention will be described below. The control device described below can be referred to in correspondence with the control circuit described above.

[0112] In some embodiments, a control device is provided, the control device comprising:

[0113] The loop module is used to obtain the loop information corresponding to each level of loop logic based on the currently executed nested loop instruction, execute the current level of loop logic, and store the loop information corresponding to the current level of loop logic; the loop information of the current level of loop logic includes at least one of the loop body start position, loop body end position, and current execution state of the current level of loop logic.

[0114] The cache module is used to store the loop information corresponding to the target layer loop logic in each layer of loop logic, and to write the loop information corresponding to the remaining layer loop logic in each layer of loop logic into the memory module; the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer of loop logic, and the remaining layer loop logic is the loop logic remaining in each layer of loop logic except for the current layer loop logic and the target layer loop logic.

[0115] The memory module is used to store the loop information corresponding to the remaining layer loop logic; the area of ​​the memory module is smaller than that of the cache module, and the storage capacity of the memory module is greater than that of the cache module.

[0116] The control module is used to control the loop module, cache module, and memory module to perform their respective operations.

[0117] In this embodiment, the control device includes a loop module, a cache module, a memory module, and a control module. The loop module is used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, execute the current layer loop logic, and store the loop information corresponding to the current layer loop logic. It is also used to store the loop information of the target layer loop logic in each layer of loop logic and to write the loop information of the remaining layer loop logic in each layer of loop logic into the memory module. The control module is used to control the loop module, cache module, and memory module to perform corresponding operations. The loop information of the current layer loop logic includes at least one of the loop body start position, loop body end position, and current execution state. The target layer loop logic is one or more loop logics located outside the current layer loop logic in each layer of loop logic. The remaining loop logic is the loop logic remaining in each layer of loop logic excluding the current layer loop logic and the target layer loop logic. The area of ​​the memory module is smaller than that of the cache module, and the storage capacity of the memory module is larger than that of the cache module. This control device can store all the loop information of the remaining loop logic in the nested loop instructions in a memory module with a large capacity and a small area. This allows the corresponding loop information to be retrieved from the memory module when the loop module executes any level of loop logic, thus enabling the implementation of loop functions with arbitrary nesting levels with relatively small hardware memory resources. In addition, while implementing the loop function with arbitrary nesting levels, the loop information of the loop logic outside the current loop logic can be stored in a cache module with limited capacity and high read and write efficiency, which can improve the loop efficiency when implementing the loop function with arbitrary nesting levels.

[0118] It should be noted that the control device provided in this embodiment of the invention can realize all the functions implemented in the control circuit embodiment and achieve the same technical effect. Therefore, the parts that are the same as those in the control circuit embodiment and the beneficial effects will not be described in detail here.

[0119] In some embodiments, the present invention also provides a processor, which may include the control circuit 10 described above.

[0120] In this embodiment, the processor may include a control circuit, which includes a loop module, a cache module, a memory module, and a control module. The loop module is used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, execute the current layer loop logic, and store the loop information corresponding to the current layer loop logic. It is also used to store the loop information of the target layer loop logic in each layer of loop logic and to write the loop information of the remaining layer loop logic in each layer of loop logic into the memory module. The control module is used to control the loop module, cache module, and memory module to perform corresponding operations. The loop information of the current layer loop logic includes at least one of the loop body start position, loop body end position, and current execution state of the current layer loop logic. The target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer of loop logic. The remaining loop logic is the loop logic remaining in each layer of loop logic excluding the current layer loop logic and the target layer loop logic. The area of ​​the memory module is smaller than that of the cache module, and the storage capacity of the memory module is larger than that of the cache module. The processor's control circuit can store all the remaining loop information from nested loop instructions in a large-capacity, small-area memory module. This allows the loop module to retrieve the corresponding loop information from the memory module whenever it executes any level of loop logic, thus enabling the implementation of loop functionality with minimal hardware memory resources. Furthermore, while implementing loop functionality with arbitrary nesting levels, the loop information of the loop logic surrounding the current loop logic can be stored in a cache module with limited capacity and high read / write efficiency, thereby improving the loop efficiency when implementing loop functionality with arbitrary nesting levels.

[0121] It should be noted that the processor provided in the embodiments of the present invention can realize all the functions implemented in the control circuit embodiments and can achieve the same technical effects. Therefore, the parts that are the same as those in the control circuit embodiments and the beneficial effects will not be described in detail here.

[0122] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0123] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A control circuit, characterized in that, include: The loop module is used to obtain the loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, execute the current layer of loop logic, and store the loop information corresponding to the current layer of loop logic; the loop information of the current layer of loop logic includes at least one of the loop body start position, loop body end position, and current execution state of the current layer of loop logic; A cache module, connected to the loop module, is used to store loop information corresponding to the target layer loop logic in each layer of loop logic, and to write the loop information corresponding to the remaining layer loop logic in each layer of loop logic into the memory module; the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer of loop logic, and the remaining layer loop logic is the loop logic remaining in each layer of loop logic other than the current layer loop logic and the target layer loop logic; A memory module, connected to the cache module, is used to store the loop information corresponding to the remaining layer loop logic; The area of ​​the memory module is smaller than that of the cache module, and the storage capacity of the memory module is greater than that of the cache module. A control module is connected to the loop module, the cache module, and the memory module respectively, and is used to control the loop module, the cache module, and the memory module to perform their respective operations; The loop module includes multiple loop sub-modules, each loop sub-module corresponding to execute a layer of loop logic. The cache module is specifically used to receive a first push control signal sent by the control module. The first push control signal is sent by the control module when it determines that the number of loop logic layers is greater than the number of multiple loop sub-modules. Based on the first push control signal, the control module obtains the loop information corresponding to each layer of loop logic from the loop module, determines multiple target layer loop logics located in the outer layer from each layer of loop logic, and pushes the loop information of each target layer loop logic into the information stack of the cache module in a preset order. When the number of target layer loop logics pushed into the information stack reaches a depth threshold, the control module receives a first write data control signal sent by the control module, and writes the loop information of the target layer loop logic located at the bottom of the information stack as the loop information of the remaining layer loop logics into the memory module, until the loop information of the multiple target layer loop logics is pushed into the information stack and / or written into the memory module. The control module is specifically configured to send a second push control signal to the loop module when the number of loop logics in each layer is greater than the number of the plurality of loop sub-modules; the second push control signal is used to instruct the loop module to send the loop information corresponding to the target layer loop logic to the cache module, so that the cache module pushes the loop information of the target layer loop logic onto the stack; when the number of target layer loop logics pushed into the information stack reaches a depth threshold, the control module sends a second write data control signal to the memory module; the second write data control signal is used to instruct the memory module to write the loop information of the remaining layer loop logics sent by the cache module into the memory area; The control module is further configured to, when a new nested loop instruction is obtained and all of the multiple loop sub-modules are occupied, allocate the new nested loop instruction to the loop sub-module that executes the outermost loop logic among the multiple loop sub-modules. When the multiple loop submodules execute the inner nested loop logic of each layer of loop logic, and it is determined that the new nested loop instruction is not the nested loop instruction corresponding to the inner nested loop logic of each layer of loop logic, a stack pop control signal is sent to the cache module. The pop control signal is used to instruct the cache module to return the loop information of the target layer loop logic to the idle loop submodule among the plurality of loop submodules; when the number of target layer loop logics in the cache module is less than the depth threshold, a read data control signal is sent to the cache module; the read data control signal is used to instruct the cache module to read the loop information of the remaining layer loop logic in the memory module and push the loop information of the remaining layer loop logic onto the bottom of the information stack of the cache module.

2. The control circuit according to claim 1, characterized in that, The cache module includes a first data interface that corresponds one-to-one with each of the plurality of loop sub-modules; Each of the loop sub-modules is connected to the cache module through a corresponding first data interface, and is used to write the loop information corresponding to the target layer loop logic into the cache module through each of the first data interfaces, and / or read the loop information corresponding to the target layer loop logic in the cache module.

3. The control circuit according to any one of claims 1 to 2, characterized in that, The target layer loop logic is specifically the loop logic located in the layer or layer closest to the current layer loop logic, and the remaining layer loop logic is specifically the loop logic located in the layer or layer furthest from the current layer loop logic.

4. The control circuit according to any one of claims 1 to 2, characterized in that, The read / write efficiency of the cache module is higher than that of the memory module.

5. The control circuit according to any one of claims 1 to 2, characterized in that, The memory module includes a second data interface; The cache module is connected to the memory module through the second data interface, and is specifically used to write the loop information corresponding to the remaining layer loop logic into the memory module through the second data interface, and / or read the loop information corresponding to the remaining layer loop logic in the memory module.

6. A control device, characterized in that, include: The loop module is used to obtain the loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, execute the current layer of loop logic, and store the loop information corresponding to the current layer of loop logic; the loop information of the current layer of loop logic includes at least one of the loop body start position, loop body end position, and current execution state of the current layer of loop logic; A cache module is used to store the loop information corresponding to the target layer loop logic in each layer of loop logic, and to write the loop information corresponding to the remaining layer loop logic in each layer of loop logic into the memory module; the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer of loop logic, and the remaining layer loop logic is the loop logic remaining in each layer of loop logic other than the current layer loop logic and the target layer loop logic; The memory module is used to store the loop information corresponding to the remaining layer loop logic; The area of ​​the memory module is smaller than that of the cache module, and the storage capacity of the memory module is greater than that of the cache module. The control module is used to control the loop module, the cache module, and the memory module to perform their respective operations; The loop module includes multiple loop sub-modules, each loop sub-module corresponding to execute a layer of loop logic. The cache module is specifically used to receive a first push control signal sent by the control module. The first push control signal is sent by the control module when it determines that the number of loop logic layers is greater than the number of multiple loop sub-modules. Based on the first push control signal, the control module obtains the loop information corresponding to each layer of loop logic from the loop module, determines multiple target layer loop logics located in the outer layer from each layer of loop logic, and pushes the loop information of each target layer loop logic into the information stack of the cache module in a preset order. When the number of target layer loop logics pushed into the information stack reaches a depth threshold, the control module receives a first write data control signal sent by the control module, and writes the loop information of the target layer loop logic located at the bottom of the information stack as the loop information of the remaining layer loop logics into the memory module, until the loop information of the multiple target layer loop logics is pushed into the information stack and / or written into the memory module. The control module is specifically configured to send a second push control signal to the loop module when the number of loop logics in each layer is greater than the number of the plurality of loop sub-modules; the second push control signal is used to instruct the loop module to send the loop information corresponding to the target layer loop logic to the cache module, so that the cache module pushes the loop information of the target layer loop logic onto the stack; when the number of target layer loop logics pushed into the information stack reaches a depth threshold, the control module sends a second write data control signal to the memory module; the second write data control signal is used to instruct the memory module to write the loop information of the remaining layer loop logics sent by the cache module into the memory area; The control module is further configured to, when a new nested loop instruction is obtained and all of the multiple loop sub-modules are occupied, allocate the new nested loop instruction to the loop sub-module that executes the outermost loop logic among the multiple loop sub-modules. When the multiple loop submodules execute the inner nested loop logic of each layer of loop logic, and it is determined that the new nested loop instruction is not the nested loop instruction corresponding to the inner nested loop logic of each layer of loop logic, a stack pop control signal is sent to the cache module. The pop control signal is used to instruct the cache module to return the loop information of the target layer loop logic to the idle loop submodule among the plurality of loop submodules; when the number of target layer loop logics in the cache module is less than the depth threshold, a read data control signal is sent to the cache module; the read data control signal is used to instruct the cache module to read the loop information of the remaining layer loop logic in the memory module and push the loop information of the remaining layer loop logic onto the bottom of the information stack of the cache module.

7. A processor, characterized in that, Includes the control circuit as described in any one of claims 1 to 5.

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